Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	242486227	7811	0	0
host_fifo_config_rd_A	242486227	3700	0	0
host_nack_handler_timeout_rd_A	242486227	1422	0	0
host_timeout_ctrl_rd_A	242486227	1462	0	0
intr_enable_rd_A	242486227	2854	0	0
ovrd_rd_A	242486227	2167	0	0
target_fifo_config_rd_A	242486227	1549	0	0
target_id_rd_A	242486227	1689	0	0
target_timeout_ctrl_rd_A	242486227	1546	0	0
timeout_ctrl_rd_A	242486227	1519	0	0
timing0_rd_A	242486227	1517	0	0
timing1_rd_A	242486227	1640	0	0
timing2_rd_A	242486227	1456	0	0
timing3_rd_A	242486227	1388	0	0
timing4_rd_A	242486227	1635	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	7811	0	0
T94	8145	123	0	0
T95	15145	584	0	0
T114	2098	58	0	0
T115	11826	3	0	0
T117	1984	106	0	0
T118	9516	343	0	0
T124	11475	598	0	0
T126	9887	4	0	0
T127	3826	492	0	0
T130	2845	25	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	3700	0	0
T19	114148	0	0	0
T25	51075	0	0	0
T29	106727	0	0	0
T60	493064	0	0	0
T77	253898	0	0	0
T87	99499	0	0	0
T91	240440	129	0	0
T147	0	203	0	0
T148	0	122	0	0
T149	0	143	0	0
T150	0	198	0	0
T151	0	261	0	0
T152	0	164	0	0
T153	0	86	0	0
T154	0	226	0	0
T155	0	198	0	0
T156	578541	0	0	0
T157	26917	0	0	0
T158	1366	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1422	0	0
T70	1777	2	0	0
T94	8145	5	0	0
T95	15145	34	0	0
T118	9516	16	0	0
T124	11475	32	0	0
T132	2342	17	0	0
T135	2573	5	0	0
T144	3052	21	0	0
T159	5274	101	0	0
T160	2224	13	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1462	0	0
T70	1777	6	0	0
T94	8145	24	0	0
T95	15145	50	0	0
T118	9516	6	0	0
T124	11475	16	0	0
T132	2342	6	0	0
T144	3052	15	0	0
T159	5274	124	0	0
T160	2224	8	0	0
T161	5068	84	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	2854	0	0
T70	0	5	0	0
T94	0	14	0	0
T95	0	30	0	0
T102	6483	0	0	0
T159	0	94	0	0
T162	958324	19	0	0
T163	0	11	0	0
T164	0	35	0	0
T165	0	28	0	0
T166	0	17	0	0
T167	0	17	0	0
T168	9338	0	0	0
T169	112061	0	0	0
T170	59227	0	0	0
T171	1397	0	0	0
T172	178350	0	0	0
T173	89672	0	0	0
T174	1635	0	0	0
T175	1674	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	2167	0	0
T36	68532	0	0	0
T171	0	62	0	0
T176	2497	22	0	0
T177	0	69	0	0
T178	0	31	0	0
T179	0	45	0	0
T180	0	44	0	0
T181	0	41	0	0
T182	0	58	0	0
T183	0	49	0	0
T184	0	46	0	0
T185	2747	0	0	0
T186	44337	0	0	0
T187	120502	0	0	0
T188	990	0	0	0
T189	4799	0	0	0
T190	126556	0	0	0
T191	237846	0	0	0
T192	242722	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1549	0	0
T70	1777	8	0	0
T94	8145	36	0	0
T95	15145	51	0	0
T118	9516	4	0	0
T124	11475	3	0	0
T132	2342	17	0	0
T135	2573	19	0	0
T144	3052	25	0	0
T159	5274	81	0	0
T160	2224	16	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1689	0	0
T70	1777	10	0	0
T94	8145	4	0	0
T95	15145	45	0	0
T118	9516	12	0	0
T124	11475	14	0	0
T132	2342	38	0	0
T135	2573	20	0	0
T144	3052	29	0	0
T159	5274	96	0	0
T160	2224	33	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1546	0	0
T70	1777	8	0	0
T94	8145	11	0	0
T95	15145	44	0	0
T118	9516	23	0	0
T124	11475	12	0	0
T132	2342	15	0	0
T135	2573	4	0	0
T144	3052	19	0	0
T159	5274	87	0	0
T160	2224	10	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1519	0	0
T70	1777	4	0	0
T94	8145	31	0	0
T95	15145	26	0	0
T118	9516	16	0	0
T124	11475	14	0	0
T132	2342	13	0	0
T159	5274	98	0	0
T160	2224	5	0	0
T161	5068	61	0	0
T193	28581	171	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1517	0	0
T70	1777	3	0	0
T94	8145	8	0	0
T95	15145	49	0	0
T118	9516	25	0	0
T124	11475	13	0	0
T132	2342	2	0	0
T133	1391	7	0	0
T135	2573	8	0	0
T144	3052	25	0	0
T159	5274	90	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1640	0	0
T94	8145	23	0	0
T95	15145	42	0	0
T118	9516	26	0	0
T124	11475	20	0	0
T132	2342	17	0	0
T135	2573	13	0	0
T144	3052	7	0	0
T159	5274	105	0	0
T160	2224	3	0	0
T161	5068	43	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1456	0	0
T94	8145	1	0	0
T95	15145	22	0	0
T118	9516	5	0	0
T124	11475	6	0	0
T132	2342	9	0	0
T135	2573	9	0	0
T144	3052	19	0	0
T159	5274	135	0	0
T160	2224	26	0	0
T161	5068	35	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1388	0	0
T70	1777	7	0	0
T94	8145	23	0	0
T95	15145	6	0	0
T118	9516	7	0	0
T124	11475	6	0	0
T132	2342	8	0	0
T135	2573	16	0	0
T144	3052	12	0	0
T159	5274	103	0	0
T160	2224	7	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486227	1635	0	0
T70	1777	3	0	0
T94	8145	39	0	0
T95	15145	56	0	0
T118	9516	4	0	0
T124	11475	6	0	0
T132	2342	10	0	0
T133	1391	3	0	0
T135	2573	10	0	0
T144	3052	14	0	0
T159	5274	121	0	0