Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.01 97.51 91.32 97.65 45.51 94.97 98.23 90.86


Total test records in report: 1308
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T1256 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1064114812 Mar 28 12:35:54 PM PDT 24 Mar 28 12:35:55 PM PDT 24 14805863 ps
T1257 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3034545153 Mar 28 12:35:45 PM PDT 24 Mar 28 12:35:48 PM PDT 24 41297529 ps
T1258 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3895424592 Mar 28 12:35:43 PM PDT 24 Mar 28 12:35:48 PM PDT 24 347277786 ps
T125 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.384684883 Mar 28 12:35:45 PM PDT 24 Mar 28 12:35:48 PM PDT 24 141772887 ps
T140 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.800760855 Mar 28 12:35:41 PM PDT 24 Mar 28 12:35:44 PM PDT 24 46056702 ps
T1259 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3667491339 Mar 28 12:35:49 PM PDT 24 Mar 28 12:35:49 PM PDT 24 53894542 ps
T1260 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1034144601 Mar 28 12:35:36 PM PDT 24 Mar 28 12:35:38 PM PDT 24 95913801 ps
T1261 /workspace/coverage/cover_reg_top/2.i2c_intr_test.4190406912 Mar 28 12:35:45 PM PDT 24 Mar 28 12:35:48 PM PDT 24 207583271 ps
T1262 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2611856400 Mar 28 12:35:48 PM PDT 24 Mar 28 12:35:49 PM PDT 24 54754986 ps
T1263 /workspace/coverage/cover_reg_top/3.i2c_intr_test.55258896 Mar 28 12:36:00 PM PDT 24 Mar 28 12:36:00 PM PDT 24 16312957 ps
T1264 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2478205906 Mar 28 12:35:43 PM PDT 24 Mar 28 12:35:47 PM PDT 24 47392143 ps
T1265 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2470360116 Mar 28 12:36:03 PM PDT 24 Mar 28 12:36:04 PM PDT 24 57022745 ps
T1266 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1146059540 Mar 28 12:35:50 PM PDT 24 Mar 28 12:35:51 PM PDT 24 379848951 ps
T1267 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3881861178 Mar 28 12:36:01 PM PDT 24 Mar 28 12:36:07 PM PDT 24 3055414569 ps
T129 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.519419918 Mar 28 12:36:03 PM PDT 24 Mar 28 12:36:06 PM PDT 24 131941664 ps
T1268 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3801046012 Mar 28 12:36:01 PM PDT 24 Mar 28 12:36:02 PM PDT 24 175381631 ps
T1269 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3219152873 Mar 28 12:35:51 PM PDT 24 Mar 28 12:35:52 PM PDT 24 62738461 ps
T1270 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2890393513 Mar 28 12:36:01 PM PDT 24 Mar 28 12:36:02 PM PDT 24 64768925 ps
T1271 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1004806722 Mar 28 12:35:49 PM PDT 24 Mar 28 12:35:50 PM PDT 24 124921634 ps
T1272 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1349822229 Mar 28 12:35:51 PM PDT 24 Mar 28 12:35:52 PM PDT 24 27976809 ps
T1273 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1871546524 Mar 28 12:36:00 PM PDT 24 Mar 28 12:36:01 PM PDT 24 44893165 ps
T1274 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1775464806 Mar 28 12:36:01 PM PDT 24 Mar 28 12:36:02 PM PDT 24 65546074 ps
T1275 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.970710282 Mar 28 12:35:36 PM PDT 24 Mar 28 12:35:40 PM PDT 24 162567032 ps
T1276 /workspace/coverage/cover_reg_top/38.i2c_intr_test.785844573 Mar 28 12:36:00 PM PDT 24 Mar 28 12:36:01 PM PDT 24 20341154 ps
T1277 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2492957265 Mar 28 12:35:39 PM PDT 24 Mar 28 12:35:42 PM PDT 24 131608232 ps
T1278 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1515565880 Mar 28 12:35:44 PM PDT 24 Mar 28 12:35:48 PM PDT 24 47294598 ps
T1279 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1606657291 Mar 28 12:35:46 PM PDT 24 Mar 28 12:35:48 PM PDT 24 29939374 ps
T1280 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2531383809 Mar 28 12:35:46 PM PDT 24 Mar 28 12:35:48 PM PDT 24 39636249 ps
T1281 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3181219490 Mar 28 12:35:47 PM PDT 24 Mar 28 12:35:49 PM PDT 24 68336793 ps
T1282 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.813268335 Mar 28 12:35:44 PM PDT 24 Mar 28 12:35:48 PM PDT 24 234769113 ps
T1283 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.321777293 Mar 28 12:35:24 PM PDT 24 Mar 28 12:35:26 PM PDT 24 32770274 ps
T1284 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4150923104 Mar 28 12:35:42 PM PDT 24 Mar 28 12:35:48 PM PDT 24 695700690 ps
T1285 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2132568468 Mar 28 12:35:47 PM PDT 24 Mar 28 12:35:48 PM PDT 24 18561099 ps
T1286 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.230646402 Mar 28 12:35:56 PM PDT 24 Mar 28 12:35:59 PM PDT 24 189221657 ps
T1287 /workspace/coverage/cover_reg_top/42.i2c_intr_test.420579830 Mar 28 12:36:01 PM PDT 24 Mar 28 12:36:01 PM PDT 24 27352380 ps
T1288 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1271865088 Mar 28 12:35:48 PM PDT 24 Mar 28 12:35:50 PM PDT 24 49742236 ps
T1289 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.434665966 Mar 28 12:35:48 PM PDT 24 Mar 28 12:35:49 PM PDT 24 41044261 ps
T121 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1500020365 Mar 28 12:36:00 PM PDT 24 Mar 28 12:36:01 PM PDT 24 47746785 ps
T1290 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2630982796 Mar 28 12:35:41 PM PDT 24 Mar 28 12:35:45 PM PDT 24 21487200 ps
T1291 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.116381287 Mar 28 12:35:48 PM PDT 24 Mar 28 12:35:49 PM PDT 24 206220644 ps
T1292 /workspace/coverage/cover_reg_top/17.i2c_intr_test.219722973 Mar 28 12:35:39 PM PDT 24 Mar 28 12:35:42 PM PDT 24 35733044 ps
T1293 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2809735478 Mar 28 12:35:48 PM PDT 24 Mar 28 12:35:49 PM PDT 24 82229090 ps
T1294 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.780267564 Mar 28 12:35:44 PM PDT 24 Mar 28 12:35:47 PM PDT 24 62095320 ps
T1295 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1443221258 Mar 28 12:35:41 PM PDT 24 Mar 28 12:35:45 PM PDT 24 66178658 ps
T1296 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1080951561 Mar 28 12:35:40 PM PDT 24 Mar 28 12:35:44 PM PDT 24 409801472 ps
T1297 /workspace/coverage/cover_reg_top/27.i2c_intr_test.259753122 Mar 28 12:36:00 PM PDT 24 Mar 28 12:36:01 PM PDT 24 42755747 ps
T1298 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4192079557 Mar 28 12:35:55 PM PDT 24 Mar 28 12:35:58 PM PDT 24 184704750 ps
T1299 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3845410400 Mar 28 12:35:43 PM PDT 24 Mar 28 12:35:47 PM PDT 24 48428414 ps
T1300 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3006096276 Mar 28 12:36:02 PM PDT 24 Mar 28 12:36:04 PM PDT 24 252535465 ps
T1301 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.36713394 Mar 28 12:36:04 PM PDT 24 Mar 28 12:36:05 PM PDT 24 54807156 ps
T1302 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3318322265 Mar 28 12:35:52 PM PDT 24 Mar 28 12:35:53 PM PDT 24 31573213 ps
T1303 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.529724141 Mar 28 12:35:36 PM PDT 24 Mar 28 12:35:38 PM PDT 24 68284126 ps
T1304 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3154112703 Mar 28 12:35:59 PM PDT 24 Mar 28 12:36:01 PM PDT 24 75689415 ps
T1305 /workspace/coverage/cover_reg_top/22.i2c_intr_test.3691289091 Mar 28 12:35:42 PM PDT 24 Mar 28 12:35:47 PM PDT 24 224939608 ps
T1306 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2544173228 Mar 28 12:35:59 PM PDT 24 Mar 28 12:36:00 PM PDT 24 25330308 ps
T1307 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2483891979 Mar 28 12:35:42 PM PDT 24 Mar 28 12:35:47 PM PDT 24 26305724 ps
T231 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3737608062 Mar 28 12:35:43 PM PDT 24 Mar 28 12:35:48 PM PDT 24 419585916 ps
T1308 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3847263333 Mar 28 12:35:43 PM PDT 24 Mar 28 12:35:47 PM PDT 24 188596987 ps

Test location /workspace/coverage/default/36.i2c_host_stress_all.3570929301
Short name T6
Test name
Test status
Simulation time 34336617050 ps
CPU time 908.27 seconds
Started Mar 28 03:29:14 PM PDT 24
Finished Mar 28 03:44:23 PM PDT 24
Peak memory 1887964 kb
Host smart-67eda691-c5d4-4d61-975d-a276ef6f5f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570929301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.3570929301
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.4033820545
Short name T16
Test name
Test status
Simulation time 10077217455 ps
CPU time 30.67 seconds
Started Mar 28 03:29:29 PM PDT 24
Finished Mar 28 03:30:00 PM PDT 24
Peak memory 373952 kb
Host smart-ba0fe48b-21a2-45e2-93fb-abde7d2839a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033820545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.4033820545
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4196900715
Short name T95
Test name
Test status
Simulation time 229519310 ps
CPU time 2.84 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203568 kb
Host smart-cd9a3015-85f0-4ee9-a9d3-2b30aa94fe3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196900715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4196900715
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2683765123
Short name T28
Test name
Test status
Simulation time 34098208915 ps
CPU time 649.61 seconds
Started Mar 28 03:26:44 PM PDT 24
Finished Mar 28 03:37:34 PM PDT 24
Peak memory 933812 kb
Host smart-fe92b7c9-b6de-4072-ba9c-d74cc960d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683765123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2683765123
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_override.449732391
Short name T177
Test name
Test status
Simulation time 129993438 ps
CPU time 0.69 seconds
Started Mar 28 03:27:24 PM PDT 24
Finished Mar 28 03:27:25 PM PDT 24
Peak memory 203620 kb
Host smart-a3e84e41-901f-4635-885b-794ad3cb9218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449732391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.449732391
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1638110242
Short name T98
Test name
Test status
Simulation time 111011643 ps
CPU time 0.83 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:25:07 PM PDT 24
Peak memory 221196 kb
Host smart-ab8a35ac-a834-419d-a45b-f92f1bda0e1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638110242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1638110242
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.3373053489
Short name T52
Test name
Test status
Simulation time 19293938966 ps
CPU time 28.49 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:47 PM PDT 24
Peak memory 262668 kb
Host smart-6b3c269e-6bac-48bd-8e76-10cd84b3a16e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373053489 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.3373053489
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2023008028
Short name T70
Test name
Test status
Simulation time 222321004 ps
CPU time 0.76 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:42 PM PDT 24
Peak memory 203284 kb
Host smart-d1b13763-1868-40d1-bce0-a317dd167218
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023008028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2023008028
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1500195293
Short name T46
Test name
Test status
Simulation time 7436858251 ps
CPU time 18.75 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:27:51 PM PDT 24
Peak memory 295812 kb
Host smart-540e98ce-24ce-4306-a811-38ec01c5e5d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500195293 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1500195293
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.219694064
Short name T23
Test name
Test status
Simulation time 4447871774 ps
CPU time 14.31 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:25:31 PM PDT 24
Peak memory 203852 kb
Host smart-bd4a8824-90d1-43b0-a956-2062b6515885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219694064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.219694064
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1514287851
Short name T18
Test name
Test status
Simulation time 1197832026 ps
CPU time 22.8 seconds
Started Mar 28 03:25:07 PM PDT 24
Finished Mar 28 03:25:30 PM PDT 24
Peak memory 306732 kb
Host smart-4a10ef0b-73ad-4ad1-8a9d-486bc3c2973a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514287851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1514287851
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1102829695
Short name T43
Test name
Test status
Simulation time 25288287233 ps
CPU time 553.18 seconds
Started Mar 28 03:28:53 PM PDT 24
Finished Mar 28 03:38:06 PM PDT 24
Peak memory 1396152 kb
Host smart-26d5b7d5-eb35-4ec7-946a-d0da75e870b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102829695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1102829695
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.3331653209
Short name T32
Test name
Test status
Simulation time 3097368205 ps
CPU time 4.16 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:20 PM PDT 24
Peak memory 212116 kb
Host smart-4b4eb7d5-5814-4429-8048-2c03fe161796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331653209 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.3331653209
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2191570651
Short name T115
Test name
Test status
Simulation time 473088460 ps
CPU time 1.98 seconds
Started Mar 28 12:35:50 PM PDT 24
Finished Mar 28 12:35:53 PM PDT 24
Peak memory 203500 kb
Host smart-51717e4d-8a64-4129-911e-a9c24dbb5fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191570651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2191570651
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.1674317160
Short name T40
Test name
Test status
Simulation time 284774592 ps
CPU time 0.98 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 203692 kb
Host smart-77b95f09-e930-446b-adda-979842b56c2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674317160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.1674317160
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3844396094
Short name T47
Test name
Test status
Simulation time 4926180574 ps
CPU time 2.63 seconds
Started Mar 28 03:24:53 PM PDT 24
Finished Mar 28 03:24:56 PM PDT 24
Peak memory 203924 kb
Host smart-70df7735-98fc-453c-96b6-1f6d67689b9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844396094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3844396094
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2998126869
Short name T55
Test name
Test status
Simulation time 25761991 ps
CPU time 0.6 seconds
Started Mar 28 03:29:01 PM PDT 24
Finished Mar 28 03:29:02 PM PDT 24
Peak memory 203708 kb
Host smart-8c326a5a-5cb9-4a68-86a1-16e0eaf78183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998126869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2998126869
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2598554231
Short name T62
Test name
Test status
Simulation time 10118208201 ps
CPU time 106.59 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:32:04 PM PDT 24
Peak memory 667468 kb
Host smart-aad3929c-91f6-4873-9290-e6499a39b7e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598554231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2598554231
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.263334582
Short name T26
Test name
Test status
Simulation time 20254142713 ps
CPU time 1292.26 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:51:27 PM PDT 24
Peak memory 2274860 kb
Host smart-664ef4bb-9e36-444b-9a79-8c5818e6c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263334582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.263334582
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3927721983
Short name T152
Test name
Test status
Simulation time 3034372363 ps
CPU time 74.86 seconds
Started Mar 28 03:29:00 PM PDT 24
Finished Mar 28 03:30:15 PM PDT 24
Peak memory 958212 kb
Host smart-4ef42042-0880-45a4-9f5d-2ccf32ae0fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927721983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3927721983
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1917912316
Short name T233
Test name
Test status
Simulation time 18400607 ps
CPU time 0.68 seconds
Started Mar 28 12:35:56 PM PDT 24
Finished Mar 28 12:35:59 PM PDT 24
Peak memory 203244 kb
Host smart-d308c016-67be-4efd-b298-a0e5e2b758a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917912316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1917912316
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1417488796
Short name T483
Test name
Test status
Simulation time 115684345 ps
CPU time 6.81 seconds
Started Mar 28 03:26:15 PM PDT 24
Finished Mar 28 03:26:22 PM PDT 24
Peak memory 222156 kb
Host smart-508b1ae4-c2d5-4667-9ee0-7c1cf95874be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417488796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1417488796
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2045879071
Short name T239
Test name
Test status
Simulation time 10476482572 ps
CPU time 5.12 seconds
Started Mar 28 03:26:41 PM PDT 24
Finished Mar 28 03:26:47 PM PDT 24
Peak memory 233124 kb
Host smart-4e46a98f-8b70-40c5-b1d5-69484f3eb8f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045879071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2045879071
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.871758323
Short name T80
Test name
Test status
Simulation time 16657293989 ps
CPU time 114.45 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:31:47 PM PDT 24
Peak memory 1116968 kb
Host smart-7cb049c5-3514-4869-b9d5-039d3853f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871758323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.871758323
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.4224467278
Short name T195
Test name
Test status
Simulation time 34230397125 ps
CPU time 977.78 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:46:39 PM PDT 24
Peak memory 1894076 kb
Host smart-2954f53b-f646-4888-ac63-6ff88082bbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224467278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.4224467278
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3517368690
Short name T1238
Test name
Test status
Simulation time 130281516 ps
CPU time 2.46 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203576 kb
Host smart-1c233b12-8f92-4841-8bf3-6f283d1af075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517368690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3517368690
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3337518199
Short name T57
Test name
Test status
Simulation time 3729058287 ps
CPU time 57.74 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:27:54 PM PDT 24
Peak memory 565096 kb
Host smart-52022e06-9c47-44cf-8962-253493bf8302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337518199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3337518199
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.169572261
Short name T414
Test name
Test status
Simulation time 1268033382 ps
CPU time 6.49 seconds
Started Mar 28 03:26:15 PM PDT 24
Finished Mar 28 03:26:21 PM PDT 24
Peak memory 207412 kb
Host smart-ff8257d2-70e0-4227-b76b-e2be3e8c1c80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169572261 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.169572261
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1213789030
Short name T146
Test name
Test status
Simulation time 41970367 ps
CPU time 1 seconds
Started Mar 28 12:35:33 PM PDT 24
Finished Mar 28 12:35:34 PM PDT 24
Peak memory 203664 kb
Host smart-7f589178-b4d8-40c4-b749-f6d145b9a1bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213789030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1213789030
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.4075349134
Short name T224
Test name
Test status
Simulation time 1425116611 ps
CPU time 2.63 seconds
Started Mar 28 03:26:12 PM PDT 24
Finished Mar 28 03:26:15 PM PDT 24
Peak memory 203824 kb
Host smart-87df2979-4fb0-483e-a288-bd47077127a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075349134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.4075349134
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2938773107
Short name T205
Test name
Test status
Simulation time 341857062 ps
CPU time 0.83 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:26:55 PM PDT 24
Peak memory 203724 kb
Host smart-0c4d7c27-d865-451a-859a-ab809eba3e03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938773107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2938773107
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_override.2275880743
Short name T212
Test name
Test status
Simulation time 27682902 ps
CPU time 0.73 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:21 PM PDT 24
Peak memory 203624 kb
Host smart-bd440ffd-f061-4228-8fad-be538abc2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275880743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2275880743
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3082879928
Short name T199
Test name
Test status
Simulation time 12794346788 ps
CPU time 3.4 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:25:40 PM PDT 24
Peak memory 216268 kb
Host smart-5ea7e4ef-332d-44df-857d-d947b4fb2606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082879928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3082879928
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.274282404
Short name T900
Test name
Test status
Simulation time 2751868653 ps
CPU time 44.09 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:27:00 PM PDT 24
Peak memory 533412 kb
Host smart-7183e784-a7c5-4378-b71f-320dc4b64bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274282404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.274282404
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3662245488
Short name T79
Test name
Test status
Simulation time 10027890252 ps
CPU time 97.4 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:27:15 PM PDT 24
Peak memory 636704 kb
Host smart-2038a935-abc5-48b4-978f-86d5eb36da70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662245488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.3662245488
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3268662920
Short name T208
Test name
Test status
Simulation time 35274440657 ps
CPU time 1032.1 seconds
Started Mar 28 03:26:17 PM PDT 24
Finished Mar 28 03:43:30 PM PDT 24
Peak memory 2040280 kb
Host smart-3f98b843-b2df-424a-be9b-f816d79c461d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268662920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3268662920
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.526199246
Short name T215
Test name
Test status
Simulation time 987731762 ps
CPU time 43.33 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:27:22 PM PDT 24
Peak memory 204060 kb
Host smart-3d89de23-cef6-4fbb-a04d-1a6eb32f0bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526199246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.526199246
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2787577205
Short name T1167
Test name
Test status
Simulation time 10036427948 ps
CPU time 88.93 seconds
Started Mar 28 03:25:07 PM PDT 24
Finished Mar 28 03:26:37 PM PDT 24
Peak memory 764892 kb
Host smart-2c9460fa-237b-4874-bed6-614120d45abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787577205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2787577205
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1118973622
Short name T230
Test name
Test status
Simulation time 4308698590 ps
CPU time 135.27 seconds
Started Mar 28 03:30:45 PM PDT 24
Finished Mar 28 03:33:01 PM PDT 24
Peak memory 716512 kb
Host smart-42aea2ce-0abd-4a53-9533-7619ebdfbb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118973622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1118973622
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_perf.388177561
Short name T198
Test name
Test status
Simulation time 19428464558 ps
CPU time 26.04 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:26:18 PM PDT 24
Peak memory 212096 kb
Host smart-c7213b80-3ca8-4fa8-9b5b-97e34330bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388177561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.388177561
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3190188204
Short name T65
Test name
Test status
Simulation time 10127398832 ps
CPU time 36.12 seconds
Started Mar 28 03:28:13 PM PDT 24
Finished Mar 28 03:28:50 PM PDT 24
Peak memory 479164 kb
Host smart-dbbbe004-9746-471e-b3ce-f8c3e8d9140b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190188204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3190188204
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2242690255
Short name T128
Test name
Test status
Simulation time 95643841 ps
CPU time 2.01 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 203468 kb
Host smart-2fa43beb-afaa-4074-bb0f-1f0b6329187b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242690255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2242690255
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.47718345
Short name T122
Test name
Test status
Simulation time 462256338 ps
CPU time 1.39 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:43 PM PDT 24
Peak memory 203620 kb
Host smart-2ad9a6c0-ec37-4cde-9bab-cc3f0b980843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47718345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.47718345
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1916592391
Short name T120
Test name
Test status
Simulation time 189888865 ps
CPU time 1.32 seconds
Started Mar 28 12:36:05 PM PDT 24
Finished Mar 28 12:36:06 PM PDT 24
Peak memory 203604 kb
Host smart-e9abf34f-216e-4dae-a406-45f6553841f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916592391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1916592391
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1752445918
Short name T138
Test name
Test status
Simulation time 29099833 ps
CPU time 1.27 seconds
Started Mar 28 12:35:51 PM PDT 24
Finished Mar 28 12:35:53 PM PDT 24
Peak memory 203516 kb
Host smart-83cb3735-09d0-471e-93ce-c45ba0fcee43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752445918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1752445918
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.206197867
Short name T1233
Test name
Test status
Simulation time 762377198 ps
CPU time 3.14 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:06 PM PDT 24
Peak memory 203464 kb
Host smart-81409640-f1ed-4094-bf95-7e44d09349c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206197867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.206197867
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.4006293334
Short name T139
Test name
Test status
Simulation time 20705928 ps
CPU time 0.67 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 203044 kb
Host smart-c9af5ead-8900-4600-963d-ee3bdbd3fd99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006293334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.4006293334
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1577216956
Short name T1206
Test name
Test status
Simulation time 49835234 ps
CPU time 0.77 seconds
Started Mar 28 12:35:34 PM PDT 24
Finished Mar 28 12:35:36 PM PDT 24
Peak memory 203376 kb
Host smart-01029261-3ff8-4f84-8e2c-0d53f44a0f8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577216956 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1577216956
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.11997709
Short name T1247
Test name
Test status
Simulation time 53611821 ps
CPU time 0.67 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 203220 kb
Host smart-04592953-2ce3-45d1-906d-565247e2e837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11997709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.11997709
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.39117336
Short name T1240
Test name
Test status
Simulation time 51324402 ps
CPU time 0.68 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 203228 kb
Host smart-509e8b1e-5e96-4505-99a6-4449a48c5e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.39117336
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.321777293
Short name T1283
Test name
Test status
Simulation time 32770274 ps
CPU time 1.54 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 203480 kb
Host smart-a2016580-ddfb-4381-9e98-6c320af46fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321777293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.321777293
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2046872618
Short name T159
Test name
Test status
Simulation time 1055185230 ps
CPU time 1.14 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203480 kb
Host smart-55b0777d-10a2-4b3e-8586-f2e80ab8b923
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046872618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2046872618
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2621378138
Short name T193
Test name
Test status
Simulation time 297761254 ps
CPU time 3.3 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:50 PM PDT 24
Peak memory 203420 kb
Host smart-4f0ed768-34aa-4672-95a0-a11a6606bc84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621378138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2621378138
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3086562193
Short name T133
Test name
Test status
Simulation time 77399389 ps
CPU time 0.7 seconds
Started Mar 28 12:35:36 PM PDT 24
Finished Mar 28 12:35:37 PM PDT 24
Peak memory 203248 kb
Host smart-5d5f3398-9787-451c-942d-4c86df3440d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086562193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3086562193
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1035600909
Short name T1251
Test name
Test status
Simulation time 52270824 ps
CPU time 0.72 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:42 PM PDT 24
Peak memory 203396 kb
Host smart-4b9e108a-01c2-4706-bbeb-bf4e83b60e32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035600909 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1035600909
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.800760855
Short name T140
Test name
Test status
Simulation time 46056702 ps
CPU time 0.71 seconds
Started Mar 28 12:35:41 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203244 kb
Host smart-b0b76115-dc24-4290-82ec-494b0a44b14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800760855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.800760855
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2982695585
Short name T1203
Test name
Test status
Simulation time 65516741 ps
CPU time 0.65 seconds
Started Mar 28 12:35:46 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203248 kb
Host smart-e1fbd06f-a4fc-4b3d-b4c2-acd23900531a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982695585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2982695585
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1513168042
Short name T127
Test name
Test status
Simulation time 153136563 ps
CPU time 2.23 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:05 PM PDT 24
Peak memory 203524 kb
Host smart-da033cf1-3c05-428b-932c-160d3bb388cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513168042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1513168042
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.477824905
Short name T1243
Test name
Test status
Simulation time 67276971 ps
CPU time 1.33 seconds
Started Mar 28 12:35:38 PM PDT 24
Finished Mar 28 12:35:41 PM PDT 24
Peak memory 203484 kb
Host smart-c11990c0-3266-4edb-a392-e53e1e070e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477824905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.477824905
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1606657291
Short name T1279
Test name
Test status
Simulation time 29939374 ps
CPU time 0.8 seconds
Started Mar 28 12:35:46 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203344 kb
Host smart-64c17c05-3a54-4d69-afb9-bdbd4343b7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606657291 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1606657291
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3667491339
Short name T1259
Test name
Test status
Simulation time 53894542 ps
CPU time 0.66 seconds
Started Mar 28 12:35:49 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203252 kb
Host smart-143f44a7-1e62-4fa1-a3df-48a70373a92b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667491339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3667491339
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2890393513
Short name T1270
Test name
Test status
Simulation time 64768925 ps
CPU time 0.68 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:02 PM PDT 24
Peak memory 203268 kb
Host smart-c4cc6194-be5f-4c3e-b9d7-c75d144cb723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890393513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2890393513
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2186398928
Short name T1237
Test name
Test status
Simulation time 28858911 ps
CPU time 1.17 seconds
Started Mar 28 12:36:02 PM PDT 24
Finished Mar 28 12:36:03 PM PDT 24
Peak memory 203612 kb
Host smart-5b3fa1ea-8b85-4bb0-9838-ff046d878985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186398928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2186398928
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3318322265
Short name T1302
Test name
Test status
Simulation time 31573213 ps
CPU time 1.29 seconds
Started Mar 28 12:35:52 PM PDT 24
Finished Mar 28 12:35:53 PM PDT 24
Peak memory 203640 kb
Host smart-19132efb-0c0f-4bff-8d5c-6d9eb8b1dcd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318322265 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3318322265
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3219152873
Short name T1269
Test name
Test status
Simulation time 62738461 ps
CPU time 0.74 seconds
Started Mar 28 12:35:51 PM PDT 24
Finished Mar 28 12:35:52 PM PDT 24
Peak memory 203244 kb
Host smart-a9ff60aa-79ce-4d23-81eb-97d4c313b57d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219152873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3219152873
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.912992200
Short name T1230
Test name
Test status
Simulation time 49926438 ps
CPU time 0.7 seconds
Started Mar 28 12:35:37 PM PDT 24
Finished Mar 28 12:35:38 PM PDT 24
Peak memory 203312 kb
Host smart-45363232-42b5-4edc-8632-2edfa7eb8d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912992200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.912992200
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1869873459
Short name T1220
Test name
Test status
Simulation time 190077909 ps
CPU time 1.1 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203516 kb
Host smart-958ab4db-d26a-4559-859f-255f8fb2492f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869873459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1869873459
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.833380743
Short name T124
Test name
Test status
Simulation time 478205132 ps
CPU time 2.4 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:03 PM PDT 24
Peak memory 203272 kb
Host smart-3d5705b3-fcda-4cc3-a9d0-15bc64af2f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833380743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.833380743
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.384684883
Short name T125
Test name
Test status
Simulation time 141772887 ps
CPU time 1.31 seconds
Started Mar 28 12:35:45 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203500 kb
Host smart-851fb4ae-255c-4d6a-b2fd-9eb9ffcccd1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384684883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.384684883
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3376146375
Short name T1227
Test name
Test status
Simulation time 42527415 ps
CPU time 1 seconds
Started Mar 28 12:35:47 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203388 kb
Host smart-ca25c1c2-89ca-440b-96f8-69d8b5b46e76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376146375 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3376146375
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2757076727
Short name T142
Test name
Test status
Simulation time 18684775 ps
CPU time 0.68 seconds
Started Mar 28 12:35:47 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203196 kb
Host smart-e7109d3b-a261-475b-9573-59af1a5a5cee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757076727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2757076727
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.254028189
Short name T1213
Test name
Test status
Simulation time 31798914 ps
CPU time 0.73 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:04 PM PDT 24
Peak memory 203244 kb
Host smart-19932ce9-f704-431f-b19b-14893bacef45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254028189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.254028189
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3181219490
Short name T1281
Test name
Test status
Simulation time 68336793 ps
CPU time 1.28 seconds
Started Mar 28 12:35:47 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203432 kb
Host smart-64332220-150f-4543-8fc2-1dd0f6e25e61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181219490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3181219490
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3043332121
Short name T118
Test name
Test status
Simulation time 194229000 ps
CPU time 1.92 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203504 kb
Host smart-f1d64c18-af14-4d45-82b1-218c10883f60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043332121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3043332121
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.384270866
Short name T1253
Test name
Test status
Simulation time 254432159 ps
CPU time 1.37 seconds
Started Mar 28 12:35:45 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203548 kb
Host smart-dba6ba14-1aab-423f-9cb3-65b044682b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384270866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.384270866
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.434665966
Short name T1289
Test name
Test status
Simulation time 41044261 ps
CPU time 0.78 seconds
Started Mar 28 12:35:48 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203392 kb
Host smart-84e22cf9-cbb0-47b7-ad54-39a510c5fc6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434665966 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.434665966
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1704460978
Short name T136
Test name
Test status
Simulation time 40884394 ps
CPU time 0.66 seconds
Started Mar 28 12:35:41 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203148 kb
Host smart-9f9b2ece-c6eb-4d26-9438-33c984b717c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704460978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1704460978
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1775464806
Short name T1274
Test name
Test status
Simulation time 65546074 ps
CPU time 0.74 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:02 PM PDT 24
Peak memory 203264 kb
Host smart-519b4e36-3744-4d27-8e81-cae0c8e20ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775464806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1775464806
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.633730137
Short name T1254
Test name
Test status
Simulation time 90006472 ps
CPU time 1.09 seconds
Started Mar 28 12:35:47 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203560 kb
Host smart-b03ee54b-912d-4ce7-8937-a96fad9b3951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633730137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.633730137
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2047222884
Short name T1216
Test name
Test status
Simulation time 73579126 ps
CPU time 1.75 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:03 PM PDT 24
Peak memory 203572 kb
Host smart-9494a631-3a72-4b83-8f3c-9ab18d3e1886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047222884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2047222884
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.53122781
Short name T1250
Test name
Test status
Simulation time 238763477 ps
CPU time 1.39 seconds
Started Mar 28 12:36:04 PM PDT 24
Finished Mar 28 12:36:05 PM PDT 24
Peak memory 203604 kb
Host smart-1725a312-80f8-4de2-90d8-a2bd6da8f84b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53122781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.53122781
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.116381287
Short name T1291
Test name
Test status
Simulation time 206220644 ps
CPU time 0.76 seconds
Started Mar 28 12:35:48 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203348 kb
Host smart-7c095c0b-a704-4806-aada-e769162f260b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116381287 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.116381287
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3280500724
Short name T1255
Test name
Test status
Simulation time 18964824 ps
CPU time 0.75 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203300 kb
Host smart-2e24145c-5bb2-4ce1-911a-16b69ff1fc2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280500724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3280500724
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1064114812
Short name T1256
Test name
Test status
Simulation time 14805863 ps
CPU time 0.63 seconds
Started Mar 28 12:35:54 PM PDT 24
Finished Mar 28 12:35:55 PM PDT 24
Peak memory 203244 kb
Host smart-cb61eb79-9afa-4eb4-addb-64cdf1fcbd2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064114812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1064114812
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.851168897
Short name T1209
Test name
Test status
Simulation time 67714414 ps
CPU time 1.01 seconds
Started Mar 28 12:35:56 PM PDT 24
Finished Mar 28 12:35:59 PM PDT 24
Peak memory 203508 kb
Host smart-0de2654b-bc4c-489e-ad7b-eafd06e89e45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851168897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.851168897
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.653083747
Short name T1223
Test name
Test status
Simulation time 88535072 ps
CPU time 1.65 seconds
Started Mar 28 12:35:48 PM PDT 24
Finished Mar 28 12:35:50 PM PDT 24
Peak memory 203536 kb
Host smart-2b0f7fb2-a34c-4d7a-b1f4-92908f9f0ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653083747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.653083747
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2544173228
Short name T1306
Test name
Test status
Simulation time 25330308 ps
CPU time 1.04 seconds
Started Mar 28 12:35:59 PM PDT 24
Finished Mar 28 12:36:00 PM PDT 24
Peak memory 203360 kb
Host smart-b03a12db-01c0-4167-aa85-ab090c44daae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544173228 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2544173228
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3933591654
Short name T135
Test name
Test status
Simulation time 26009840 ps
CPU time 0.76 seconds
Started Mar 28 12:35:59 PM PDT 24
Finished Mar 28 12:36:00 PM PDT 24
Peak memory 203204 kb
Host smart-c53cf51f-839b-4c12-b16b-b366410325fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933591654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3933591654
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1473843014
Short name T1200
Test name
Test status
Simulation time 36676923 ps
CPU time 0.67 seconds
Started Mar 28 12:35:57 PM PDT 24
Finished Mar 28 12:35:59 PM PDT 24
Peak memory 203240 kb
Host smart-d5c68ede-a40f-457c-9421-70bf0f193f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473843014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1473843014
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.36713394
Short name T1301
Test name
Test status
Simulation time 54807156 ps
CPU time 0.94 seconds
Started Mar 28 12:36:04 PM PDT 24
Finished Mar 28 12:36:05 PM PDT 24
Peak memory 203316 kb
Host smart-79da0072-5be6-4367-bb97-44fdb5b21ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_out
standing.36713394
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3006096276
Short name T1300
Test name
Test status
Simulation time 252535465 ps
CPU time 1.44 seconds
Started Mar 28 12:36:02 PM PDT 24
Finished Mar 28 12:36:04 PM PDT 24
Peak memory 203588 kb
Host smart-aa947ff4-ab12-48b7-88fb-d080daa94247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006096276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3006096276
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2131073917
Short name T114
Test name
Test status
Simulation time 84007254 ps
CPU time 1.21 seconds
Started Mar 28 12:35:40 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203612 kb
Host smart-aeb96e97-4a7f-42ad-8559-9affdacf4010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131073917 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2131073917
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2840770076
Short name T1229
Test name
Test status
Simulation time 21472345 ps
CPU time 0.65 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203256 kb
Host smart-a598c818-55f4-4754-9dde-ff3a57418201
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840770076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2840770076
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3948113971
Short name T1195
Test name
Test status
Simulation time 62362553 ps
CPU time 0.67 seconds
Started Mar 28 12:35:56 PM PDT 24
Finished Mar 28 12:35:57 PM PDT 24
Peak memory 203236 kb
Host smart-a987abe1-2264-4bca-977a-2bb23edf3c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948113971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3948113971
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1230278634
Short name T145
Test name
Test status
Simulation time 32388558 ps
CPU time 1.06 seconds
Started Mar 28 12:35:40 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203728 kb
Host smart-ba332f0d-6943-4494-bb69-0d05ee7f2c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230278634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1230278634
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3801046012
Short name T1268
Test name
Test status
Simulation time 175381631 ps
CPU time 1.32 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:02 PM PDT 24
Peak memory 203488 kb
Host smart-59317677-854a-45c0-aca3-913ee406effe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801046012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3801046012
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2638327558
Short name T126
Test name
Test status
Simulation time 100911112 ps
CPU time 2.07 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203552 kb
Host smart-b9ef2c11-61a5-4502-92b1-91173eff9f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638327558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2638327558
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3260444503
Short name T1219
Test name
Test status
Simulation time 70667232 ps
CPU time 0.76 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203384 kb
Host smart-c73cb697-863f-4c70-873e-488a15a8be30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260444503 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3260444503
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.723767583
Short name T134
Test name
Test status
Simulation time 17292597 ps
CPU time 0.69 seconds
Started Mar 28 12:35:59 PM PDT 24
Finished Mar 28 12:36:00 PM PDT 24
Peak memory 203160 kb
Host smart-f90b9c54-05f6-4afb-a9fa-6ec531679947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723767583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.723767583
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.219722973
Short name T1292
Test name
Test status
Simulation time 35733044 ps
CPU time 0.71 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:42 PM PDT 24
Peak memory 203384 kb
Host smart-786a4ab8-888d-4037-a6d2-260eb2e4a698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219722973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.219722973
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2439404291
Short name T1212
Test name
Test status
Simulation time 38943730 ps
CPU time 0.85 seconds
Started Mar 28 12:35:57 PM PDT 24
Finished Mar 28 12:35:59 PM PDT 24
Peak memory 203300 kb
Host smart-7b1d18cc-f345-4c25-9906-780f9700406d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439404291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2439404291
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4192079557
Short name T1298
Test name
Test status
Simulation time 184704750 ps
CPU time 2.04 seconds
Started Mar 28 12:35:55 PM PDT 24
Finished Mar 28 12:35:58 PM PDT 24
Peak memory 203488 kb
Host smart-dd28725f-2889-4457-a3f7-eca6a87fcf11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192079557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.4192079557
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3737608062
Short name T231
Test name
Test status
Simulation time 419585916 ps
CPU time 2.06 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203392 kb
Host smart-0ebc88c8-ee9c-4b25-a178-70df5c93edf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737608062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3737608062
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1323162659
Short name T130
Test name
Test status
Simulation time 129439497 ps
CPU time 0.99 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203320 kb
Host smart-80ccecce-6fcd-4553-a377-56ed198d299f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323162659 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1323162659
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1100605041
Short name T69
Test name
Test status
Simulation time 118191063 ps
CPU time 0.75 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:42 PM PDT 24
Peak memory 203372 kb
Host smart-64634152-7f2a-44ad-a457-19b5dac8c0e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100605041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1100605041
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2531383809
Short name T1280
Test name
Test status
Simulation time 39636249 ps
CPU time 0.67 seconds
Started Mar 28 12:35:46 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203224 kb
Host smart-df674dda-d0dd-42a7-8284-53cfb1bbda96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531383809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2531383809
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3727309634
Short name T143
Test name
Test status
Simulation time 48707598 ps
CPU time 1.18 seconds
Started Mar 28 12:36:02 PM PDT 24
Finished Mar 28 12:36:03 PM PDT 24
Peak memory 203600 kb
Host smart-bbca5d78-db0d-4e04-a7cd-46ca34a2b814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727309634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3727309634
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3847263333
Short name T1308
Test name
Test status
Simulation time 188596987 ps
CPU time 1.42 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203416 kb
Host smart-ed5c23af-54cb-42da-8475-ed74e3c3687b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847263333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3847263333
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3895424592
Short name T1258
Test name
Test status
Simulation time 347277786 ps
CPU time 1.48 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203368 kb
Host smart-a969f2c2-ff41-4c51-bf87-8f621c942090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895424592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3895424592
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1271865088
Short name T1288
Test name
Test status
Simulation time 49742236 ps
CPU time 1.3 seconds
Started Mar 28 12:35:48 PM PDT 24
Finished Mar 28 12:35:50 PM PDT 24
Peak memory 203616 kb
Host smart-d1528eb3-ad3f-4c8c-9e78-a05a197fd5c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271865088 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1271865088
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.400094517
Short name T132
Test name
Test status
Simulation time 54516447 ps
CPU time 0.77 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203196 kb
Host smart-67622eca-2c44-49d2-b5e2-317711f6b235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400094517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.400094517
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2642121372
Short name T1210
Test name
Test status
Simulation time 14995545 ps
CPU time 0.64 seconds
Started Mar 28 12:35:37 PM PDT 24
Finished Mar 28 12:35:38 PM PDT 24
Peak memory 203196 kb
Host smart-92564b57-d214-4cd9-a4f2-1bd82782b218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642121372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2642121372
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.230646402
Short name T1286
Test name
Test status
Simulation time 189221657 ps
CPU time 1.09 seconds
Started Mar 28 12:35:56 PM PDT 24
Finished Mar 28 12:35:59 PM PDT 24
Peak memory 203556 kb
Host smart-77a2dc46-5c0c-4a8a-ac76-de10dd355ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230646402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.230646402
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1062930528
Short name T116
Test name
Test status
Simulation time 125370166 ps
CPU time 1.28 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:43 PM PDT 24
Peak memory 203420 kb
Host smart-566cd402-2073-4f61-bdd3-c3f75cd02381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062930528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1062930528
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3361019861
Short name T201
Test name
Test status
Simulation time 150356785 ps
CPU time 1.7 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203424 kb
Host smart-cd187a38-eb07-4da9-8be2-82b01f4141e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361019861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3361019861
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3441638365
Short name T1231
Test name
Test status
Simulation time 1457044111 ps
CPU time 5.35 seconds
Started Mar 28 12:35:58 PM PDT 24
Finished Mar 28 12:36:03 PM PDT 24
Peak memory 203468 kb
Host smart-b1531c99-45d9-420c-8dea-2d8e0213f1d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441638365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3441638365
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.873191583
Short name T1236
Test name
Test status
Simulation time 48716077 ps
CPU time 0.69 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:04 PM PDT 24
Peak memory 203232 kb
Host smart-d2362e78-2e53-4e1f-ba35-20b27487292b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873191583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.873191583
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2298664280
Short name T117
Test name
Test status
Simulation time 79459254 ps
CPU time 1.12 seconds
Started Mar 28 12:35:54 PM PDT 24
Finished Mar 28 12:35:55 PM PDT 24
Peak memory 203012 kb
Host smart-c6d63b42-a953-48bb-8d5b-94d81cf9799a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298664280 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2298664280
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3149742885
Short name T141
Test name
Test status
Simulation time 33391457 ps
CPU time 0.69 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203056 kb
Host smart-701d1e4d-9733-4921-9668-d192f85ef2f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149742885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3149742885
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.4190406912
Short name T1261
Test name
Test status
Simulation time 207583271 ps
CPU time 0.58 seconds
Started Mar 28 12:35:45 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 202892 kb
Host smart-868eb431-63aa-48c1-8ff1-36f34cb5cc38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190406912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.4190406912
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1349822229
Short name T1272
Test name
Test status
Simulation time 27976809 ps
CPU time 1.14 seconds
Started Mar 28 12:35:51 PM PDT 24
Finished Mar 28 12:35:52 PM PDT 24
Peak memory 203608 kb
Host smart-22205a10-81cd-4e76-b377-8f78d9f53986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349822229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1349822229
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3832919115
Short name T1208
Test name
Test status
Simulation time 49024556 ps
CPU time 2.24 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203564 kb
Host smart-129e45ff-3cea-4861-a7f1-2428f1bfbde7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832919115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3832919115
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2333888012
Short name T123
Test name
Test status
Simulation time 135811328 ps
CPU time 1.48 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203560 kb
Host smart-d2dd4a0e-980b-4bd4-9329-d72407c6bc7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333888012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2333888012
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3034545153
Short name T1257
Test name
Test status
Simulation time 41297529 ps
CPU time 0.68 seconds
Started Mar 28 12:35:45 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203220 kb
Host smart-eb0ffc8e-d873-4d2d-9097-cead9bbe59c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034545153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3034545153
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.92115019
Short name T1228
Test name
Test status
Simulation time 55867551 ps
CPU time 0.66 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203056 kb
Host smart-f7163c11-1064-4f05-b218-ead6a3271124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92115019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.92115019
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3691289091
Short name T1305
Test name
Test status
Simulation time 224939608 ps
CPU time 0.67 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203268 kb
Host smart-e52cdcf2-270f-42a5-8e9a-f3ba6f7dbe30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691289091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3691289091
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3636510259
Short name T1248
Test name
Test status
Simulation time 46884223 ps
CPU time 0.64 seconds
Started Mar 28 12:35:46 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203224 kb
Host smart-9f220824-0dd4-45aa-a5e6-34d74f9fb225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636510259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3636510259
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1748151559
Short name T1218
Test name
Test status
Simulation time 23453707 ps
CPU time 0.66 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:04 PM PDT 24
Peak memory 203244 kb
Host smart-04e0a41c-01a3-4eca-adaa-389791f29c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748151559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1748151559
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.4287956431
Short name T166
Test name
Test status
Simulation time 16978964 ps
CPU time 0.67 seconds
Started Mar 28 12:35:47 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203120 kb
Host smart-5ee7198f-cd9c-4a52-ac50-5bab7d86d51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287956431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.4287956431
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2438062266
Short name T1225
Test name
Test status
Simulation time 46629765 ps
CPU time 0.65 seconds
Started Mar 28 12:35:54 PM PDT 24
Finished Mar 28 12:35:55 PM PDT 24
Peak memory 203232 kb
Host smart-0b238ab9-3802-4b6c-9e1b-4e09022f5a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438062266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2438062266
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.259753122
Short name T1297
Test name
Test status
Simulation time 42755747 ps
CPU time 0.68 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203236 kb
Host smart-1db92b3b-e5bc-4443-8b16-321eff6ed3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259753122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.259753122
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2278916806
Short name T1201
Test name
Test status
Simulation time 34164547 ps
CPU time 0.66 seconds
Started Mar 28 12:36:02 PM PDT 24
Finished Mar 28 12:36:02 PM PDT 24
Peak memory 203264 kb
Host smart-4ca8915c-523b-4a4d-b48e-8af87dafff74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278916806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2278916806
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.4176146657
Short name T1224
Test name
Test status
Simulation time 76468982 ps
CPU time 0.7 seconds
Started Mar 28 12:36:02 PM PDT 24
Finished Mar 28 12:36:02 PM PDT 24
Peak memory 203264 kb
Host smart-1e65cffb-7ccc-4a45-905b-7c9257a0bff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176146657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4176146657
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4083018662
Short name T161
Test name
Test status
Simulation time 230447798 ps
CPU time 1.25 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203296 kb
Host smart-7c516c28-bc4e-41aa-b3fb-3aaa9a0b1992
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083018662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.4083018662
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3881861178
Short name T1267
Test name
Test status
Simulation time 3055414569 ps
CPU time 5.6 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:07 PM PDT 24
Peak memory 203556 kb
Host smart-7361b290-ebfe-42dc-b047-a1f82c1d9eb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881861178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3881861178
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2470360116
Short name T1265
Test name
Test status
Simulation time 57022745 ps
CPU time 1 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:04 PM PDT 24
Peak memory 203396 kb
Host smart-c388d086-0331-4d60-8e42-f6734cfb3c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470360116 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2470360116
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1454813867
Short name T1211
Test name
Test status
Simulation time 17475915 ps
CPU time 0.66 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203064 kb
Host smart-87c9e809-6e5d-4d8a-9b18-8600b8afdc6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454813867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1454813867
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.55258896
Short name T1263
Test name
Test status
Simulation time 16312957 ps
CPU time 0.68 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:00 PM PDT 24
Peak memory 203316 kb
Host smart-e8b193f5-64c2-4c5c-956a-382ac0e54fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55258896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.55258896
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.813268335
Short name T1282
Test name
Test status
Simulation time 234769113 ps
CPU time 0.88 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203308 kb
Host smart-7b505e65-38d7-4da8-bead-0ebab989f3f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813268335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.813268335
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.970710282
Short name T1275
Test name
Test status
Simulation time 162567032 ps
CPU time 2.31 seconds
Started Mar 28 12:35:36 PM PDT 24
Finished Mar 28 12:35:40 PM PDT 24
Peak memory 203500 kb
Host smart-8da2d452-ab3a-4429-855c-09050e9a91db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970710282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.970710282
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1500020365
Short name T121
Test name
Test status
Simulation time 47746785 ps
CPU time 1.36 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203540 kb
Host smart-47aa6853-0d2a-40e6-91b5-68a73cd35d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500020365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1500020365
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2630982796
Short name T1290
Test name
Test status
Simulation time 21487200 ps
CPU time 0.68 seconds
Started Mar 28 12:35:41 PM PDT 24
Finished Mar 28 12:35:45 PM PDT 24
Peak memory 203312 kb
Host smart-72120c46-46e3-442f-a4bb-98621499e9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630982796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2630982796
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2132568468
Short name T1285
Test name
Test status
Simulation time 18561099 ps
CPU time 0.68 seconds
Started Mar 28 12:35:47 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203228 kb
Host smart-b97382f2-890f-40f6-b9ea-350f3415c96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132568468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2132568468
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3369470841
Short name T1245
Test name
Test status
Simulation time 34576702 ps
CPU time 0.66 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:04 PM PDT 24
Peak memory 203304 kb
Host smart-c6a07b02-77a2-4b40-91e1-c0a60234d73b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369470841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3369470841
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2658906599
Short name T1214
Test name
Test status
Simulation time 56172371 ps
CPU time 0.68 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203268 kb
Host smart-0bfd9eaf-5b0f-413e-a54d-1f320c22739b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658906599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2658906599
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.844766800
Short name T1217
Test name
Test status
Simulation time 16767860 ps
CPU time 0.67 seconds
Started Mar 28 12:36:02 PM PDT 24
Finished Mar 28 12:36:03 PM PDT 24
Peak memory 203264 kb
Host smart-ea5eb8f5-78d6-4aab-8264-0242a8699cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844766800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.844766800
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1805515000
Short name T1198
Test name
Test status
Simulation time 93428244 ps
CPU time 0.63 seconds
Started Mar 28 12:35:41 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203172 kb
Host smart-da3e3e52-660b-44fe-a33a-06ddbbf094a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805515000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1805515000
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2553572094
Short name T1196
Test name
Test status
Simulation time 17078735 ps
CPU time 0.66 seconds
Started Mar 28 12:36:05 PM PDT 24
Finished Mar 28 12:36:06 PM PDT 24
Peak memory 203304 kb
Host smart-a1cc6221-13f6-4c10-be9d-136e9d528d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553572094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2553572094
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2512201869
Short name T235
Test name
Test status
Simulation time 52997186 ps
CPU time 0.66 seconds
Started Mar 28 12:35:41 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203172 kb
Host smart-324c52f0-327e-4168-8bf5-139e710f5815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512201869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2512201869
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.785844573
Short name T1276
Test name
Test status
Simulation time 20341154 ps
CPU time 0.73 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203264 kb
Host smart-dafa264f-418b-466c-92f4-4ff6ba5749cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785844573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.785844573
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2796613559
Short name T1249
Test name
Test status
Simulation time 18220229 ps
CPU time 0.67 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:04 PM PDT 24
Peak memory 203304 kb
Host smart-639f00f0-2514-413f-91e7-a24f2d516ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796613559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2796613559
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.4074623614
Short name T137
Test name
Test status
Simulation time 139933461 ps
CPU time 1.62 seconds
Started Mar 28 12:35:40 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203468 kb
Host smart-ba5754d3-81c5-492f-8ed8-d91dcc3f6e1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074623614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.4074623614
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.210919089
Short name T1205
Test name
Test status
Simulation time 354752100 ps
CPU time 2.89 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203440 kb
Host smart-86d82b60-82e5-41f0-80a4-f8553e4de21b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210919089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.210919089
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3107755734
Short name T1197
Test name
Test status
Simulation time 16282545 ps
CPU time 0.73 seconds
Started Mar 28 12:35:54 PM PDT 24
Finished Mar 28 12:35:55 PM PDT 24
Peak memory 202688 kb
Host smart-b3f7a418-cd8d-45b5-913f-68965de1a333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107755734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3107755734
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.529724141
Short name T1303
Test name
Test status
Simulation time 68284126 ps
CPU time 0.96 seconds
Started Mar 28 12:35:36 PM PDT 24
Finished Mar 28 12:35:38 PM PDT 24
Peak memory 203404 kb
Host smart-02b59313-e789-434c-a813-27617c7cc470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529724141 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.529724141
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.4150676317
Short name T160
Test name
Test status
Simulation time 48375681 ps
CPU time 0.74 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203244 kb
Host smart-ef9582c2-5f3a-4449-8c62-f9db78ee80cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150676317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.4150676317
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.206854556
Short name T1242
Test name
Test status
Simulation time 18808213 ps
CPU time 0.64 seconds
Started Mar 28 12:35:41 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203288 kb
Host smart-b38c601b-fd07-4813-aaaa-07032837bee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206854556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.206854556
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1080951561
Short name T1296
Test name
Test status
Simulation time 409801472 ps
CPU time 1.06 seconds
Started Mar 28 12:35:40 PM PDT 24
Finished Mar 28 12:35:44 PM PDT 24
Peak memory 203528 kb
Host smart-06861afb-f782-4800-91c2-f12f74b4b3f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080951561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1080951561
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2809735478
Short name T1293
Test name
Test status
Simulation time 82229090 ps
CPU time 1.1 seconds
Started Mar 28 12:35:48 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203596 kb
Host smart-1e9bc8bd-6987-4947-b914-653512d64ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809735478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2809735478
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.622308280
Short name T1244
Test name
Test status
Simulation time 300902099 ps
CPU time 1.45 seconds
Started Mar 28 12:35:38 PM PDT 24
Finished Mar 28 12:35:41 PM PDT 24
Peak memory 203524 kb
Host smart-ce7c1903-d7cd-401c-a479-cb14da54dc10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622308280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.622308280
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.1613768892
Short name T1241
Test name
Test status
Simulation time 21112713 ps
CPU time 0.74 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:02 PM PDT 24
Peak memory 203248 kb
Host smart-de50b8b4-df67-47fe-b67f-cf47aaab8357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613768892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1613768892
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2611856400
Short name T1262
Test name
Test status
Simulation time 54754986 ps
CPU time 0.68 seconds
Started Mar 28 12:35:48 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203248 kb
Host smart-8254ba85-30fb-4c7e-be51-6412bfa1a315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611856400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2611856400
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.420579830
Short name T1287
Test name
Test status
Simulation time 27352380 ps
CPU time 0.68 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203248 kb
Host smart-a27ce772-1552-4613-845f-1c077e54a5b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420579830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.420579830
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.302327710
Short name T1246
Test name
Test status
Simulation time 44432810 ps
CPU time 0.71 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203248 kb
Host smart-f6c0090f-51e0-4e64-8777-bf5411c5d57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302327710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.302327710
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1004806722
Short name T1271
Test name
Test status
Simulation time 124921634 ps
CPU time 0.72 seconds
Started Mar 28 12:35:49 PM PDT 24
Finished Mar 28 12:35:50 PM PDT 24
Peak memory 203232 kb
Host smart-7fc26bda-6385-4db6-91c0-818ccda8acf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004806722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1004806722
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2478205906
Short name T1264
Test name
Test status
Simulation time 47392143 ps
CPU time 0.66 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203192 kb
Host smart-e356c132-94ee-4b6d-bd06-ea3855654dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478205906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2478205906
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3657127974
Short name T167
Test name
Test status
Simulation time 18207152 ps
CPU time 0.74 seconds
Started Mar 28 12:36:02 PM PDT 24
Finished Mar 28 12:36:03 PM PDT 24
Peak memory 203244 kb
Host smart-0fd1f1b9-cebd-4797-bbb5-8f50b9859142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657127974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3657127974
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3845410400
Short name T1299
Test name
Test status
Simulation time 48428414 ps
CPU time 0.65 seconds
Started Mar 28 12:35:43 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203328 kb
Host smart-6ca57a63-5999-4b1d-bef6-cf53904aef22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845410400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3845410400
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.961087463
Short name T1199
Test name
Test status
Simulation time 16422218 ps
CPU time 0.66 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:00 PM PDT 24
Peak memory 203244 kb
Host smart-3ac5139a-67e4-4d56-94e6-bb102231a883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961087463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.961087463
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2492957265
Short name T1277
Test name
Test status
Simulation time 131608232 ps
CPU time 0.9 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:42 PM PDT 24
Peak memory 203360 kb
Host smart-b171b948-b56d-4d47-9e7e-39cfa3d567bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492957265 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2492957265
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1532526163
Short name T1207
Test name
Test status
Simulation time 20224612 ps
CPU time 0.68 seconds
Started Mar 28 12:36:01 PM PDT 24
Finished Mar 28 12:36:02 PM PDT 24
Peak memory 203032 kb
Host smart-594fa89c-bf7c-4df8-9e9f-e45800c8a64f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532526163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1532526163
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1967919405
Short name T234
Test name
Test status
Simulation time 51785942 ps
CPU time 0.65 seconds
Started Mar 28 12:35:59 PM PDT 24
Finished Mar 28 12:36:00 PM PDT 24
Peak memory 203240 kb
Host smart-895c5b4c-2bc5-46e8-81db-89555f938bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967919405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1967919405
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2927163345
Short name T1234
Test name
Test status
Simulation time 27859696 ps
CPU time 1.09 seconds
Started Mar 28 12:35:36 PM PDT 24
Finished Mar 28 12:35:38 PM PDT 24
Peak memory 203600 kb
Host smart-25655a95-9971-4768-a692-3c5252ad731f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927163345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2927163345
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1146059540
Short name T1266
Test name
Test status
Simulation time 379848951 ps
CPU time 1.74 seconds
Started Mar 28 12:35:50 PM PDT 24
Finished Mar 28 12:35:51 PM PDT 24
Peak memory 203516 kb
Host smart-a4a171aa-2ce3-4664-905b-fcf1491c9b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146059540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1146059540
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.519419918
Short name T129
Test name
Test status
Simulation time 131941664 ps
CPU time 2.12 seconds
Started Mar 28 12:36:03 PM PDT 24
Finished Mar 28 12:36:06 PM PDT 24
Peak memory 203652 kb
Host smart-347e4547-c8ce-4869-abb1-cfac99852b6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519419918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.519419918
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2483891979
Short name T1307
Test name
Test status
Simulation time 26305724 ps
CPU time 1.07 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203388 kb
Host smart-c80eafe5-857c-41a4-b3ad-8d80a09fac23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483891979 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2483891979
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1026006791
Short name T1221
Test name
Test status
Simulation time 19713197 ps
CPU time 0.67 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203224 kb
Host smart-fa5976b2-0066-49d8-b38d-9bd18cc413d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026006791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1026006791
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1871546524
Short name T1273
Test name
Test status
Simulation time 44893165 ps
CPU time 0.65 seconds
Started Mar 28 12:36:00 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203312 kb
Host smart-23ecbb22-7310-4e80-8870-9edc405fe110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871546524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1871546524
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1443221258
Short name T1295
Test name
Test status
Simulation time 66178658 ps
CPU time 0.85 seconds
Started Mar 28 12:35:41 PM PDT 24
Finished Mar 28 12:35:45 PM PDT 24
Peak memory 203352 kb
Host smart-9272b2d3-3ca5-4f9a-ac5f-e1255a8f71f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443221258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1443221258
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1034144601
Short name T1260
Test name
Test status
Simulation time 95913801 ps
CPU time 1.4 seconds
Started Mar 28 12:35:36 PM PDT 24
Finished Mar 28 12:35:38 PM PDT 24
Peak memory 203544 kb
Host smart-27fe0b1c-7b0e-4766-a2b6-9347b8fb2dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034144601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1034144601
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4150923104
Short name T1284
Test name
Test status
Simulation time 695700690 ps
CPU time 2.14 seconds
Started Mar 28 12:35:42 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203572 kb
Host smart-34cc9bfc-b039-4f21-bdc6-bbb2e53456d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150923104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4150923104
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3202061922
Short name T1235
Test name
Test status
Simulation time 32782690 ps
CPU time 1.02 seconds
Started Mar 28 12:35:46 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203388 kb
Host smart-1b9be3be-7e2e-4842-a63f-833ab95e6f57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202061922 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3202061922
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.780267564
Short name T1294
Test name
Test status
Simulation time 62095320 ps
CPU time 0.71 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:47 PM PDT 24
Peak memory 203220 kb
Host smart-f21804f4-eb62-4f3f-a864-083bd185c675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780267564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.780267564
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1515565880
Short name T1278
Test name
Test status
Simulation time 47294598 ps
CPU time 0.67 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203228 kb
Host smart-2d2a39a4-0c88-42ad-96f4-2b6dca9f7d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515565880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1515565880
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2945195163
Short name T1232
Test name
Test status
Simulation time 101838874 ps
CPU time 0.89 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203424 kb
Host smart-d051c632-1ebb-4e07-a2b8-ff39f955c7aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945195163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.2945195163
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1465214671
Short name T94
Test name
Test status
Simulation time 81477077 ps
CPU time 1.81 seconds
Started Mar 28 12:35:46 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203436 kb
Host smart-de864543-8c06-46d4-ac50-d5d87344111b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465214671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1465214671
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.210340063
Short name T119
Test name
Test status
Simulation time 277335577 ps
CPU time 2.12 seconds
Started Mar 28 12:35:39 PM PDT 24
Finished Mar 28 12:35:43 PM PDT 24
Peak memory 203524 kb
Host smart-ce2aaa8f-e8a1-4e37-a696-fce95ac353bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210340063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.210340063
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2428079006
Short name T131
Test name
Test status
Simulation time 79797704 ps
CPU time 1 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203348 kb
Host smart-030aa80d-ce23-4440-a416-426465fab785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428079006 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2428079006
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3838513617
Short name T1226
Test name
Test status
Simulation time 37495249 ps
CPU time 0.66 seconds
Started Mar 28 12:35:52 PM PDT 24
Finished Mar 28 12:35:53 PM PDT 24
Peak memory 203220 kb
Host smart-ab7afae5-2d72-4f6f-b1b2-ec9d05c68834
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838513617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3838513617
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3724640805
Short name T1204
Test name
Test status
Simulation time 29161424 ps
CPU time 0.73 seconds
Started Mar 28 12:35:54 PM PDT 24
Finished Mar 28 12:35:55 PM PDT 24
Peak memory 203240 kb
Host smart-4fee7e46-f993-473e-a934-87b0a6e643b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724640805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3724640805
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1229501971
Short name T1215
Test name
Test status
Simulation time 55147995 ps
CPU time 1.09 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203556 kb
Host smart-9ab495e8-ff81-474d-a155-f37f2d4b5f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229501971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1229501971
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1951108841
Short name T1222
Test name
Test status
Simulation time 53391889 ps
CPU time 2.33 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:49 PM PDT 24
Peak memory 203624 kb
Host smart-07d88154-06a7-4bf9-ba6e-98a1ac7cac6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951108841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1951108841
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3154112703
Short name T1304
Test name
Test status
Simulation time 75689415 ps
CPU time 1.44 seconds
Started Mar 28 12:35:59 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 203592 kb
Host smart-32e5dccf-6e45-4321-9d48-c2923a344c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154112703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3154112703
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2961092831
Short name T1252
Test name
Test status
Simulation time 24469847 ps
CPU time 0.82 seconds
Started Mar 28 12:35:45 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203384 kb
Host smart-2aca19ea-cfaf-4682-8921-6eeb701cfd17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961092831 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2961092831
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.722773579
Short name T71
Test name
Test status
Simulation time 25452090 ps
CPU time 0.77 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203100 kb
Host smart-d318a3aa-8416-496a-99ba-573c54e15bc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722773579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.722773579
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.702724270
Short name T1202
Test name
Test status
Simulation time 128456070 ps
CPU time 0.66 seconds
Started Mar 28 12:35:44 PM PDT 24
Finished Mar 28 12:35:48 PM PDT 24
Peak memory 203268 kb
Host smart-78a22334-914a-4710-8b09-b317ff0ec6c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702724270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.702724270
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2958054249
Short name T144
Test name
Test status
Simulation time 145362167 ps
CPU time 0.83 seconds
Started Mar 28 12:35:34 PM PDT 24
Finished Mar 28 12:35:35 PM PDT 24
Peak memory 203280 kb
Host smart-ca498d58-9078-463c-ae20-64de24a8cb63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958054249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2958054249
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3423921585
Short name T1239
Test name
Test status
Simulation time 98338282 ps
CPU time 1.29 seconds
Started Mar 28 12:35:38 PM PDT 24
Finished Mar 28 12:35:39 PM PDT 24
Peak memory 203556 kb
Host smart-d30f517b-3751-4cab-a5ad-17ef4c0fcef2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423921585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3423921585
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1491416934
Short name T96
Test name
Test status
Simulation time 472725080 ps
CPU time 2.29 seconds
Started Mar 28 12:35:53 PM PDT 24
Finished Mar 28 12:35:56 PM PDT 24
Peak memory 203580 kb
Host smart-20a7a551-70ad-4749-8e8c-45a38b42db5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491416934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1491416934
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2452187031
Short name T826
Test name
Test status
Simulation time 17351239 ps
CPU time 0.62 seconds
Started Mar 28 03:24:48 PM PDT 24
Finished Mar 28 03:24:48 PM PDT 24
Peak memory 203620 kb
Host smart-d8f38c81-23c9-4245-902f-80b508d8b7de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452187031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2452187031
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.26801427
Short name T368
Test name
Test status
Simulation time 219513800 ps
CPU time 1.52 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 212128 kb
Host smart-2934025c-8850-4d3f-8708-944bbfea7665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26801427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.26801427
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2540286155
Short name T393
Test name
Test status
Simulation time 261671746 ps
CPU time 5.01 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:24:57 PM PDT 24
Peak memory 254376 kb
Host smart-1d12af3c-06fa-4c07-aece-252ec544cd4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540286155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2540286155
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1674721218
Short name T597
Test name
Test status
Simulation time 4422484901 ps
CPU time 65.19 seconds
Started Mar 28 03:24:57 PM PDT 24
Finished Mar 28 03:26:02 PM PDT 24
Peak memory 698604 kb
Host smart-bf66e047-efec-4c97-81ba-c37f3fb3af47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674721218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1674721218
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2764397193
Short name T699
Test name
Test status
Simulation time 6759913479 ps
CPU time 103.83 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:26:35 PM PDT 24
Peak memory 543460 kb
Host smart-772fcb18-5c52-49ba-b6c3-251059983224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764397193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2764397193
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.794754239
Short name T750
Test name
Test status
Simulation time 490137666 ps
CPU time 6.85 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:58 PM PDT 24
Peak memory 222216 kb
Host smart-1cbad2d4-a00f-44aa-8793-80123dc02a02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794754239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.794754239
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1631667111
Short name T764
Test name
Test status
Simulation time 28323833905 ps
CPU time 63.33 seconds
Started Mar 28 03:24:53 PM PDT 24
Finished Mar 28 03:25:57 PM PDT 24
Peak memory 769004 kb
Host smart-e4ebcc76-98cc-4f06-9473-ac545ddc0872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631667111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1631667111
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3763955595
Short name T24
Test name
Test status
Simulation time 553299265 ps
CPU time 3.66 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:55 PM PDT 24
Peak memory 203852 kb
Host smart-7ddc18b6-6270-4170-af8d-2aa71643f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763955595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3763955595
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1802236843
Short name T361
Test name
Test status
Simulation time 15353949536 ps
CPU time 107.4 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:26:38 PM PDT 24
Peak memory 544020 kb
Host smart-14dfddcc-3f95-46f0-9bf5-a58e68a6152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802236843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1802236843
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.4192896213
Short name T1174
Test name
Test status
Simulation time 16668551 ps
CPU time 0.64 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 203596 kb
Host smart-b3966e7d-d382-41b0-a58a-242a7106ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192896213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4192896213
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.272076928
Short name T965
Test name
Test status
Simulation time 7582646775 ps
CPU time 381.2 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:31:13 PM PDT 24
Peak memory 1821344 kb
Host smart-468154d5-b004-4d81-8b02-53640e06cbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272076928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.272076928
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2269169876
Short name T1185
Test name
Test status
Simulation time 3170091697 ps
CPU time 82.51 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:26:13 PM PDT 24
Peak memory 397220 kb
Host smart-ed8e9d6d-6982-490a-908c-def41c07fb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269169876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2269169876
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.4007569290
Short name T102
Test name
Test status
Simulation time 67558984 ps
CPU time 1.03 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 222360 kb
Host smart-8ad2e976-4e45-46d2-b056-7c6c6078257f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007569290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.4007569290
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1642178411
Short name T526
Test name
Test status
Simulation time 650881221 ps
CPU time 3.58 seconds
Started Mar 28 03:24:53 PM PDT 24
Finished Mar 28 03:24:57 PM PDT 24
Peak memory 203772 kb
Host smart-a8732903-24fb-4acf-9c4d-57468b6baaf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642178411 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1642178411
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3389854179
Short name T622
Test name
Test status
Simulation time 10166068706 ps
CPU time 52.25 seconds
Started Mar 28 03:24:53 PM PDT 24
Finished Mar 28 03:25:45 PM PDT 24
Peak memory 471148 kb
Host smart-4f581937-a53b-4a80-a213-bdfc9d95b574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389854179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3389854179
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1523396414
Short name T930
Test name
Test status
Simulation time 10406049241 ps
CPU time 16.73 seconds
Started Mar 28 03:24:53 PM PDT 24
Finished Mar 28 03:25:10 PM PDT 24
Peak memory 322424 kb
Host smart-2cea3bf7-48d1-47c1-aaed-310b977d8f3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523396414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1523396414
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.4116778130
Short name T363
Test name
Test status
Simulation time 692396737 ps
CPU time 3.7 seconds
Started Mar 28 03:24:53 PM PDT 24
Finished Mar 28 03:24:56 PM PDT 24
Peak memory 204256 kb
Host smart-098561cb-d33b-4b78-a7d6-2a1a3131b36b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116778130 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.4116778130
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1341578357
Short name T586
Test name
Test status
Simulation time 1030605082 ps
CPU time 14.24 seconds
Started Mar 28 03:24:53 PM PDT 24
Finished Mar 28 03:25:07 PM PDT 24
Peak memory 203772 kb
Host smart-b745f5de-df95-43a4-840a-02cc0548b791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341578357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1341578357
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.92272515
Short name T716
Test name
Test status
Simulation time 1292969023 ps
CPU time 19.58 seconds
Started Mar 28 03:24:54 PM PDT 24
Finished Mar 28 03:25:14 PM PDT 24
Peak memory 221772 kb
Host smart-c4447013-f8ff-4c8e-aa54-14d078393c52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92272515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stress_rd.92272515
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.101553736
Short name T54
Test name
Test status
Simulation time 25883851565 ps
CPU time 265.86 seconds
Started Mar 28 03:24:54 PM PDT 24
Finished Mar 28 03:29:20 PM PDT 24
Peak memory 988096 kb
Host smart-fe2c141d-9225-4d03-8a4f-70eeb3ca2ca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101553736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.101553736
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.4233187001
Short name T1078
Test name
Test status
Simulation time 1251660256 ps
CPU time 7.27 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:57 PM PDT 24
Peak memory 215724 kb
Host smart-eb543b24-0b26-4bab-a699-f596f175f7bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233187001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.4233187001
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2138282293
Short name T689
Test name
Test status
Simulation time 59912797 ps
CPU time 0.63 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:25:05 PM PDT 24
Peak memory 203704 kb
Host smart-c8d23bad-00e8-4fda-97e5-60afe2b81afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138282293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2138282293
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3754505495
Short name T751
Test name
Test status
Simulation time 186311736 ps
CPU time 1.46 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 212092 kb
Host smart-fec59a74-484c-4238-9fd8-8cbfa7b9ac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754505495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3754505495
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.920581482
Short name T980
Test name
Test status
Simulation time 274780478 ps
CPU time 14.08 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:25:06 PM PDT 24
Peak memory 260740 kb
Host smart-8f178d51-6894-43f6-a642-2c0e04807fe3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920581482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.920581482
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.412535298
Short name T485
Test name
Test status
Simulation time 30130360829 ps
CPU time 190.31 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:28:00 PM PDT 24
Peak memory 805900 kb
Host smart-26cf0dc4-b1b9-4c89-854b-f32bef4411be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412535298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.412535298
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.285830400
Short name T510
Test name
Test status
Simulation time 2373544047 ps
CPU time 38.31 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:25:28 PM PDT 24
Peak memory 514244 kb
Host smart-c961cb20-fc58-4051-8ffe-061383b1ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285830400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.285830400
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2874373716
Short name T553
Test name
Test status
Simulation time 209948674 ps
CPU time 0.93 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 203400 kb
Host smart-6f4f504f-7454-4e6b-b226-8229ba658582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874373716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2874373716
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2797923724
Short name T405
Test name
Test status
Simulation time 752242763 ps
CPU time 4.8 seconds
Started Mar 28 03:24:48 PM PDT 24
Finished Mar 28 03:24:53 PM PDT 24
Peak memory 203732 kb
Host smart-3d43d021-d255-409b-a277-2ce93f1a6e80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797923724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2797923724
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3551099757
Short name T997
Test name
Test status
Simulation time 14653349827 ps
CPU time 217 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:28:30 PM PDT 24
Peak memory 945044 kb
Host smart-3bb4997e-261b-4a7c-932e-d107955a23f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551099757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3551099757
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.4117295106
Short name T251
Test name
Test status
Simulation time 515769890 ps
CPU time 20.65 seconds
Started Mar 28 03:25:02 PM PDT 24
Finished Mar 28 03:25:23 PM PDT 24
Peak memory 203840 kb
Host smart-c956a310-d650-4d8c-a672-8dc63bc6f105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117295106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4117295106
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.1325243540
Short name T882
Test name
Test status
Simulation time 18736082 ps
CPU time 0.67 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:24:50 PM PDT 24
Peak memory 203608 kb
Host smart-2e43bd07-eb00-453e-b6a0-ef94d890ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325243540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1325243540
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1803020124
Short name T45
Test name
Test status
Simulation time 7827370585 ps
CPU time 92.48 seconds
Started Mar 28 03:24:49 PM PDT 24
Finished Mar 28 03:26:22 PM PDT 24
Peak memory 244644 kb
Host smart-5c9d90e0-56da-437f-bfe3-d84b6de8165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803020124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1803020124
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.131440870
Short name T584
Test name
Test status
Simulation time 6310806664 ps
CPU time 89.36 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:26:14 PM PDT 24
Peak memory 439988 kb
Host smart-e03fdb1f-0017-470f-bba5-230a43ce64af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131440870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.131440870
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1158692237
Short name T782
Test name
Test status
Simulation time 39774449785 ps
CPU time 1940.43 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:57:12 PM PDT 24
Peak memory 3868368 kb
Host smart-86f9721c-718e-4bc0-bb3f-f0d38c04cee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158692237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1158692237
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2071462802
Short name T101
Test name
Test status
Simulation time 40920983 ps
CPU time 0.83 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:25:06 PM PDT 24
Peak memory 221280 kb
Host smart-60743d92-9f1d-45bf-a43d-7901962c05cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071462802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2071462802
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3308223345
Short name T588
Test name
Test status
Simulation time 2210205545 ps
CPU time 2.88 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:25:08 PM PDT 24
Peak memory 203860 kb
Host smart-cd6b9278-af17-4938-96fe-17516ae63edb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308223345 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3308223345
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3555957995
Short name T240
Test name
Test status
Simulation time 10230309313 ps
CPU time 38.92 seconds
Started Mar 28 03:25:01 PM PDT 24
Finished Mar 28 03:25:40 PM PDT 24
Peak memory 379172 kb
Host smart-41e683ed-cee1-42ad-a806-cbc4e2dd63a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555957995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3555957995
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3197957247
Short name T458
Test name
Test status
Simulation time 10120214414 ps
CPU time 81.48 seconds
Started Mar 28 03:25:11 PM PDT 24
Finished Mar 28 03:26:33 PM PDT 24
Peak memory 686744 kb
Host smart-0dd2cd5b-a63c-448c-bd04-b46032450a53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197957247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3197957247
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2865970233
Short name T840
Test name
Test status
Simulation time 1247552240 ps
CPU time 2.24 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:25:07 PM PDT 24
Peak memory 203796 kb
Host smart-130beb58-d3a3-42b6-b289-b953ee19695a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865970233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2865970233
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2448561415
Short name T1049
Test name
Test status
Simulation time 889403512 ps
CPU time 5.19 seconds
Started Mar 28 03:24:48 PM PDT 24
Finished Mar 28 03:24:54 PM PDT 24
Peak memory 206484 kb
Host smart-9cfd6cdd-720c-4a78-ab83-5cfd3babdfeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448561415 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2448561415
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.773321408
Short name T303
Test name
Test status
Simulation time 4662056808 ps
CPU time 9.31 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:25:02 PM PDT 24
Peak memory 203932 kb
Host smart-58713f5b-33c3-4e7d-89b7-c41c52b00fc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773321408 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.773321408
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.675503845
Short name T896
Test name
Test status
Simulation time 2898337040 ps
CPU time 20.08 seconds
Started Mar 28 03:24:52 PM PDT 24
Finished Mar 28 03:25:12 PM PDT 24
Peak memory 203900 kb
Host smart-e2d8b710-6ea3-4f3e-893d-20394dad9dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675503845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.675503845
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3679885377
Short name T876
Test name
Test status
Simulation time 742236711 ps
CPU time 31.47 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:25:23 PM PDT 24
Peak memory 203756 kb
Host smart-c0f85cd0-ae0a-491f-9c0f-5eee51465fbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679885377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3679885377
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3700758212
Short name T400
Test name
Test status
Simulation time 10845483542 ps
CPU time 22.12 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:25:13 PM PDT 24
Peak memory 203816 kb
Host smart-cc14e89e-7049-44d8-a738-01fe6f3a37a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700758212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3700758212
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.772758843
Short name T362
Test name
Test status
Simulation time 47699119395 ps
CPU time 1417.97 seconds
Started Mar 28 03:24:45 PM PDT 24
Finished Mar 28 03:48:24 PM PDT 24
Peak memory 5830364 kb
Host smart-9f09893b-2035-45ea-8921-497680696730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772758843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.772758843
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.228918446
Short name T676
Test name
Test status
Simulation time 2319212880 ps
CPU time 6.71 seconds
Started Mar 28 03:24:51 PM PDT 24
Finished Mar 28 03:24:58 PM PDT 24
Peak memory 203936 kb
Host smart-2ff16caf-a003-43b6-85eb-a3aeee41373d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228918446 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.228918446
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3815063508
Short name T1190
Test name
Test status
Simulation time 22175965 ps
CPU time 0.63 seconds
Started Mar 28 03:26:14 PM PDT 24
Finished Mar 28 03:26:14 PM PDT 24
Peak memory 203596 kb
Host smart-63626113-7f56-43b1-86ac-08156bf288c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815063508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3815063508
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2857989282
Short name T1139
Test name
Test status
Simulation time 46478765 ps
CPU time 1.29 seconds
Started Mar 28 03:26:02 PM PDT 24
Finished Mar 28 03:26:03 PM PDT 24
Peak memory 212024 kb
Host smart-f84e3d8a-42a0-4647-937c-7b371dda03c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857989282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2857989282
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.681878237
Short name T696
Test name
Test status
Simulation time 5003328037 ps
CPU time 4.97 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:25:59 PM PDT 24
Peak memory 258588 kb
Host smart-b68375d6-2324-4959-9334-743296896c61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681878237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.681878237
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1560538668
Short name T1091
Test name
Test status
Simulation time 1308027303 ps
CPU time 42.48 seconds
Started Mar 28 03:25:59 PM PDT 24
Finished Mar 28 03:26:41 PM PDT 24
Peak memory 491144 kb
Host smart-0f807dcf-7ca7-49a9-b592-ad5218b48ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560538668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1560538668
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1671785772
Short name T442
Test name
Test status
Simulation time 2197291698 ps
CPU time 144.41 seconds
Started Mar 28 03:25:59 PM PDT 24
Finished Mar 28 03:28:23 PM PDT 24
Peak memory 596748 kb
Host smart-5620d0fc-0227-42b7-b1e2-d98fad83d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671785772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1671785772
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2930077060
Short name T331
Test name
Test status
Simulation time 134592775 ps
CPU time 1 seconds
Started Mar 28 03:26:02 PM PDT 24
Finished Mar 28 03:26:03 PM PDT 24
Peak memory 203724 kb
Host smart-4effedb4-abf7-41d8-b235-2a4af5bc8487
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930077060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2930077060
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.755797014
Short name T455
Test name
Test status
Simulation time 355804518 ps
CPU time 5.52 seconds
Started Mar 28 03:25:58 PM PDT 24
Finished Mar 28 03:26:03 PM PDT 24
Peak memory 236928 kb
Host smart-a5225c15-d24c-4749-8a39-c81a65807332
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755797014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
755797014
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.4002061538
Short name T153
Test name
Test status
Simulation time 3018438868 ps
CPU time 68.45 seconds
Started Mar 28 03:26:02 PM PDT 24
Finished Mar 28 03:27:10 PM PDT 24
Peak memory 864124 kb
Host smart-bc1bb2ba-0d9a-458f-abe9-5e6ea39b75c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002061538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.4002061538
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.140803336
Short name T186
Test name
Test status
Simulation time 466713097 ps
CPU time 17.54 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:26:33 PM PDT 24
Peak memory 203892 kb
Host smart-d5c0661d-5175-48dd-807f-e66385f7fd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140803336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.140803336
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.251254561
Short name T806
Test name
Test status
Simulation time 6863572817 ps
CPU time 93.65 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:27:54 PM PDT 24
Peak memory 464428 kb
Host smart-e6002f42-d6d5-4687-a3c6-65121d60ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251254561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.251254561
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2772102619
Short name T184
Test name
Test status
Simulation time 29580351 ps
CPU time 0.66 seconds
Started Mar 28 03:25:55 PM PDT 24
Finished Mar 28 03:25:55 PM PDT 24
Peak memory 203556 kb
Host smart-85ed0ffc-32f7-4fe4-bd89-213c82c1677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772102619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2772102619
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2054801635
Short name T1160
Test name
Test status
Simulation time 1195675195 ps
CPU time 28.42 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:26:21 PM PDT 24
Peak memory 375532 kb
Host smart-45c14dd1-f51a-45f9-a98c-9dcd86fa9537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054801635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2054801635
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1608556825
Short name T164
Test name
Test status
Simulation time 61373246803 ps
CPU time 863.53 seconds
Started Mar 28 03:26:03 PM PDT 24
Finished Mar 28 03:40:27 PM PDT 24
Peak memory 3030184 kb
Host smart-f803124b-5d5f-4cff-baf1-138283246f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608556825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1608556825
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.655738414
Short name T1158
Test name
Test status
Simulation time 2895303587 ps
CPU time 2.82 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:26:23 PM PDT 24
Peak memory 203836 kb
Host smart-dd34dbe3-af37-4109-9a08-773b8d55c0b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655738414 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.655738414
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3610214290
Short name T1179
Test name
Test status
Simulation time 10038312002 ps
CPU time 75.21 seconds
Started Mar 28 03:26:02 PM PDT 24
Finished Mar 28 03:27:18 PM PDT 24
Peak memory 557076 kb
Host smart-4b35d04e-10b6-4405-8134-cac5bc642934
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610214290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3610214290
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.668529868
Short name T487
Test name
Test status
Simulation time 10176047505 ps
CPU time 18.31 seconds
Started Mar 28 03:26:03 PM PDT 24
Finished Mar 28 03:26:22 PM PDT 24
Peak memory 360920 kb
Host smart-035340e7-cedd-4019-97a9-fad94f91af56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668529868 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.668529868
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2460706652
Short name T1022
Test name
Test status
Simulation time 364603374 ps
CPU time 2.21 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:26:18 PM PDT 24
Peak memory 203808 kb
Host smart-c1d16e9e-6aa5-49e6-824a-bb8ce54ae982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460706652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2460706652
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2429985437
Short name T645
Test name
Test status
Simulation time 1774824867 ps
CPU time 4.76 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:25:57 PM PDT 24
Peak memory 203824 kb
Host smart-170bb386-fc04-40bf-be7c-9d2ce0a4e2c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429985437 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2429985437
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.4009046588
Short name T1135
Test name
Test status
Simulation time 5844721341 ps
CPU time 7.39 seconds
Started Mar 28 03:26:03 PM PDT 24
Finished Mar 28 03:26:11 PM PDT 24
Peak memory 203804 kb
Host smart-c2d42c25-3813-4175-b53c-50e25e54fc27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009046588 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.4009046588
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1086616271
Short name T283
Test name
Test status
Simulation time 1025577741 ps
CPU time 39.26 seconds
Started Mar 28 03:26:01 PM PDT 24
Finished Mar 28 03:26:41 PM PDT 24
Peak memory 203788 kb
Host smart-1e3b9224-f5f2-4589-abcc-370cb18be62f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086616271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1086616271
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3662425390
Short name T157
Test name
Test status
Simulation time 2990952783 ps
CPU time 4.47 seconds
Started Mar 28 03:26:03 PM PDT 24
Finished Mar 28 03:26:08 PM PDT 24
Peak memory 203880 kb
Host smart-a2e8059c-53cf-42af-a905-3167e883d1cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662425390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3662425390
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.653079699
Short name T1080
Test name
Test status
Simulation time 39254318040 ps
CPU time 588.08 seconds
Started Mar 28 03:25:57 PM PDT 24
Finished Mar 28 03:35:46 PM PDT 24
Peak memory 1732592 kb
Host smart-8f46a0ff-893b-465c-bfef-7be141134b71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653079699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.653079699
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.588833854
Short name T576
Test name
Test status
Simulation time 1494405200 ps
CPU time 7.87 seconds
Started Mar 28 03:26:02 PM PDT 24
Finished Mar 28 03:26:11 PM PDT 24
Peak memory 216084 kb
Host smart-ba193fcd-c974-40ef-8dda-7937eb7a066d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588833854 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.588833854
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2921217372
Short name T633
Test name
Test status
Simulation time 46356275 ps
CPU time 0.61 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:26:20 PM PDT 24
Peak memory 203668 kb
Host smart-41730e06-3f2d-4783-b465-926ea946f6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921217372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2921217372
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1804242376
Short name T407
Test name
Test status
Simulation time 32945552 ps
CPU time 1.06 seconds
Started Mar 28 03:26:15 PM PDT 24
Finished Mar 28 03:26:16 PM PDT 24
Peak memory 211992 kb
Host smart-e01bc4f4-77d6-4ace-9a87-0a208c5ceec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804242376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1804242376
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1507284828
Short name T295
Test name
Test status
Simulation time 3606702344 ps
CPU time 19.75 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:26:35 PM PDT 24
Peak memory 286068 kb
Host smart-b13eaf8d-129e-4052-a917-be61bddfd06b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507284828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1507284828
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1985201098
Short name T291
Test name
Test status
Simulation time 2506746073 ps
CPU time 76.17 seconds
Started Mar 28 03:26:13 PM PDT 24
Finished Mar 28 03:27:30 PM PDT 24
Peak memory 734128 kb
Host smart-8c884951-a27d-426d-a40f-74093ce16b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985201098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1985201098
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3739508808
Short name T298
Test name
Test status
Simulation time 2971275789 ps
CPU time 36.35 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:26:57 PM PDT 24
Peak memory 512244 kb
Host smart-4faa3842-b674-4b25-9332-47d3cf0888ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739508808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3739508808
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3791990055
Short name T499
Test name
Test status
Simulation time 153020461 ps
CPU time 1.04 seconds
Started Mar 28 03:26:15 PM PDT 24
Finished Mar 28 03:26:17 PM PDT 24
Peak memory 203736 kb
Host smart-17280eb8-e7e2-4f35-9eb7-5a3ac9b0ebd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791990055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3791990055
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.964152669
Short name T1126
Test name
Test status
Simulation time 34944594686 ps
CPU time 157.95 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:28:54 PM PDT 24
Peak memory 786732 kb
Host smart-9ff28802-7b24-47b9-a118-fc6c063d2b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964152669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.964152669
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.1835363486
Short name T413
Test name
Test status
Simulation time 510090680 ps
CPU time 10.36 seconds
Started Mar 28 03:26:14 PM PDT 24
Finished Mar 28 03:26:24 PM PDT 24
Peak memory 203840 kb
Host smart-72044a28-e9e7-4c13-9661-1a21ef970be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835363486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.1835363486
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3787639835
Short name T254
Test name
Test status
Simulation time 1387071006 ps
CPU time 74.36 seconds
Started Mar 28 03:26:17 PM PDT 24
Finished Mar 28 03:27:32 PM PDT 24
Peak memory 396696 kb
Host smart-9c02c6f9-2375-4b2e-a7f0-2cce29546fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787639835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3787639835
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.440038776
Short name T185
Test name
Test status
Simulation time 27504369 ps
CPU time 0.7 seconds
Started Mar 28 03:26:23 PM PDT 24
Finished Mar 28 03:26:24 PM PDT 24
Peak memory 203576 kb
Host smart-da4c057d-053f-4be2-a560-401be1e88d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440038776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.440038776
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1899078178
Short name T285
Test name
Test status
Simulation time 7300871011 ps
CPU time 113.89 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:28:10 PM PDT 24
Peak memory 597204 kb
Host smart-55feeadf-447b-4f0d-9629-9fa081929409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899078178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1899078178
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2688794408
Short name T693
Test name
Test status
Simulation time 4104118376 ps
CPU time 28.67 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:26:47 PM PDT 24
Peak memory 366088 kb
Host smart-3f0d819a-6264-4585-9e1d-136d2b63f8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688794408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2688794408
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.4072674590
Short name T106
Test name
Test status
Simulation time 2146551649 ps
CPU time 5.09 seconds
Started Mar 28 03:26:23 PM PDT 24
Finished Mar 28 03:26:28 PM PDT 24
Peak memory 212044 kb
Host smart-2e03978d-ba09-4d9f-8ca4-4e2061b2be1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072674590 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.4072674590
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.218516174
Short name T366
Test name
Test status
Simulation time 10086462408 ps
CPU time 68.99 seconds
Started Mar 28 03:26:13 PM PDT 24
Finished Mar 28 03:27:22 PM PDT 24
Peak memory 601112 kb
Host smart-c8b28f8b-68f7-4c37-ae70-3bacb5cf6aed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218516174 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.218516174
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4100000527
Short name T1038
Test name
Test status
Simulation time 10487953579 ps
CPU time 15.16 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:26:36 PM PDT 24
Peak memory 328944 kb
Host smart-a672213b-49e7-4786-8ae8-d7c8af35e1b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100000527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.4100000527
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2924558758
Short name T839
Test name
Test status
Simulation time 1035214784 ps
CPU time 5.83 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:26:22 PM PDT 24
Peak memory 212012 kb
Host smart-9f2dc3d9-5c7f-441e-b663-43d60a13f903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924558758 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2924558758
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1555963429
Short name T1012
Test name
Test status
Simulation time 1308895477 ps
CPU time 9.35 seconds
Started Mar 28 03:26:14 PM PDT 24
Finished Mar 28 03:26:23 PM PDT 24
Peak memory 203872 kb
Host smart-f7e82841-6020-40eb-b4e0-27090c891a59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555963429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1555963429
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3517389324
Short name T408
Test name
Test status
Simulation time 1404562862 ps
CPU time 26.72 seconds
Started Mar 28 03:26:24 PM PDT 24
Finished Mar 28 03:26:51 PM PDT 24
Peak memory 219588 kb
Host smart-d10bbec8-d6e5-4df1-8743-1f4281604645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517389324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3517389324
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.375656686
Short name T548
Test name
Test status
Simulation time 13513225963 ps
CPU time 89.41 seconds
Started Mar 28 03:26:14 PM PDT 24
Finished Mar 28 03:27:44 PM PDT 24
Peak memory 804620 kb
Host smart-8d326d2b-f924-4f21-ba85-432773b867ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375656686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.375656686
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_alert_test.1144142202
Short name T174
Test name
Test status
Simulation time 16538560 ps
CPU time 0.65 seconds
Started Mar 28 03:26:22 PM PDT 24
Finished Mar 28 03:26:23 PM PDT 24
Peak memory 203708 kb
Host smart-7e6ce267-5149-4796-9fbd-333aa57dcc18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144142202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1144142202
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3180556788
Short name T794
Test name
Test status
Simulation time 94324795 ps
CPU time 1.57 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:26:20 PM PDT 24
Peak memory 212004 kb
Host smart-effcefce-1dbf-4807-a0fb-61f2d4732d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180556788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3180556788
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2733822005
Short name T329
Test name
Test status
Simulation time 318176169 ps
CPU time 5.66 seconds
Started Mar 28 03:26:23 PM PDT 24
Finished Mar 28 03:26:29 PM PDT 24
Peak memory 256536 kb
Host smart-f14cd81e-b590-4233-b14b-2718236fecc1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733822005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2733822005
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3629896840
Short name T545
Test name
Test status
Simulation time 8266739244 ps
CPU time 68.27 seconds
Started Mar 28 03:26:22 PM PDT 24
Finished Mar 28 03:27:30 PM PDT 24
Peak memory 718008 kb
Host smart-a5ae5873-cce7-479c-8d0f-db8e57c1f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629896840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3629896840
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3308197447
Short name T838
Test name
Test status
Simulation time 290399249 ps
CPU time 0.81 seconds
Started Mar 28 03:26:13 PM PDT 24
Finished Mar 28 03:26:14 PM PDT 24
Peak memory 203652 kb
Host smart-aba39d40-c818-4aa2-8c8a-b6c4fba2aa9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308197447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3308197447
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3358544564
Short name T652
Test name
Test status
Simulation time 790640638 ps
CPU time 3.72 seconds
Started Mar 28 03:26:25 PM PDT 24
Finished Mar 28 03:26:29 PM PDT 24
Peak memory 203852 kb
Host smart-e1f99ccf-b861-4d9b-b7bd-1ca61c62df83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358544564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3358544564
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1207930130
Short name T761
Test name
Test status
Simulation time 12420022296 ps
CPU time 138.14 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:28:38 PM PDT 24
Peak memory 1233176 kb
Host smart-906b1eba-c47d-4c8e-8e27-6cbdfb4a660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207930130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1207930130
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.291135772
Short name T515
Test name
Test status
Simulation time 409970822 ps
CPU time 5.28 seconds
Started Mar 28 03:26:17 PM PDT 24
Finished Mar 28 03:26:22 PM PDT 24
Peak memory 203888 kb
Host smart-7cf13a5f-1fa2-445d-ae42-b365480eb0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291135772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.291135772
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2817296411
Short name T381
Test name
Test status
Simulation time 6001811723 ps
CPU time 26.8 seconds
Started Mar 28 03:26:12 PM PDT 24
Finished Mar 28 03:26:39 PM PDT 24
Peak memory 338656 kb
Host smart-d196a949-4f49-4606-9a17-4555b08ae17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817296411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2817296411
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3769885859
Short name T1071
Test name
Test status
Simulation time 43212481 ps
CPU time 0.65 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:26:20 PM PDT 24
Peak memory 203584 kb
Host smart-8ddeee8a-13c8-42ae-aa57-eb46eaecdd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769885859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3769885859
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2599068907
Short name T44
Test name
Test status
Simulation time 6327030304 ps
CPU time 98.6 seconds
Started Mar 28 03:26:14 PM PDT 24
Finished Mar 28 03:27:53 PM PDT 24
Peak memory 574652 kb
Host smart-b438d25c-111f-4dd9-8331-f566a78990c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599068907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2599068907
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2838384289
Short name T237
Test name
Test status
Simulation time 5765457330 ps
CPU time 73.07 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:27:32 PM PDT 24
Peak memory 387400 kb
Host smart-dcc1abbc-3f19-4875-80a3-d8975a3e5dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838384289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2838384289
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2348308348
Short name T33
Test name
Test status
Simulation time 12079949183 ps
CPU time 4.07 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:26:24 PM PDT 24
Peak memory 203896 kb
Host smart-50af1646-6c7e-4d0b-8d54-b3cf79baaaa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348308348 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2348308348
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.364740117
Short name T729
Test name
Test status
Simulation time 11162922865 ps
CPU time 6.72 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:26:22 PM PDT 24
Peak memory 240032 kb
Host smart-9bb466d2-7e61-41ec-a4b5-e5416a084e1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364740117 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.364740117
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.7123652
Short name T1001
Test name
Test status
Simulation time 10176111532 ps
CPU time 61.29 seconds
Started Mar 28 03:26:23 PM PDT 24
Finished Mar 28 03:27:24 PM PDT 24
Peak memory 560020 kb
Host smart-5ae6ac5c-a0a8-440c-ac63-8d943ca8f18a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7123652 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.i2c_target_fifo_reset_tx.7123652
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1499610080
Short name T1183
Test name
Test status
Simulation time 364069052 ps
CPU time 2.3 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:26:21 PM PDT 24
Peak memory 203752 kb
Host smart-3f0698e1-bb7d-4372-8c4f-1b98cb687386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499610080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1499610080
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.771536062
Short name T169
Test name
Test status
Simulation time 5603170212 ps
CPU time 5.65 seconds
Started Mar 28 03:26:15 PM PDT 24
Finished Mar 28 03:26:20 PM PDT 24
Peak memory 212060 kb
Host smart-f54a1221-2304-4950-8054-d6e51dde401b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771536062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.771536062
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1490174158
Short name T481
Test name
Test status
Simulation time 1937369674 ps
CPU time 16.84 seconds
Started Mar 28 03:26:14 PM PDT 24
Finished Mar 28 03:26:31 PM PDT 24
Peak memory 203788 kb
Host smart-59861f00-28ec-46e2-92db-38aa2f1967e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490174158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1490174158
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2368531949
Short name T857
Test name
Test status
Simulation time 818004442 ps
CPU time 14.97 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:26:34 PM PDT 24
Peak memory 210088 kb
Host smart-9c7382a0-89f2-456a-895b-719832da30e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368531949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2368531949
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.4100231679
Short name T250
Test name
Test status
Simulation time 10269464990 ps
CPU time 274.04 seconds
Started Mar 28 03:26:18 PM PDT 24
Finished Mar 28 03:30:52 PM PDT 24
Peak memory 1198372 kb
Host smart-a7a7eac1-bc2a-4d66-8521-0a3dfc9334ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100231679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.4100231679
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.911118247
Short name T564
Test name
Test status
Simulation time 5325152021 ps
CPU time 7.37 seconds
Started Mar 28 03:26:19 PM PDT 24
Finished Mar 28 03:26:26 PM PDT 24
Peak memory 220036 kb
Host smart-de7954b0-cc75-4c57-8356-438129252f4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911118247 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_timeout.911118247
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3148924619
Short name T523
Test name
Test status
Simulation time 17365877 ps
CPU time 0.64 seconds
Started Mar 28 03:26:42 PM PDT 24
Finished Mar 28 03:26:43 PM PDT 24
Peak memory 203588 kb
Host smart-65e5451e-be24-4081-8d3b-0badb80638e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148924619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3148924619
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2905227046
Short name T278
Test name
Test status
Simulation time 79806425 ps
CPU time 1.4 seconds
Started Mar 28 03:26:22 PM PDT 24
Finished Mar 28 03:26:24 PM PDT 24
Peak memory 212044 kb
Host smart-27ba6d36-8a16-4aff-b6a7-fb71f1779636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905227046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2905227046
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2936822875
Short name T763
Test name
Test status
Simulation time 460948272 ps
CPU time 23.42 seconds
Started Mar 28 03:26:13 PM PDT 24
Finished Mar 28 03:26:37 PM PDT 24
Peak memory 288916 kb
Host smart-be4de3cf-d853-44dc-b654-586af46a93ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936822875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2936822875
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.2176649903
Short name T112
Test name
Test status
Simulation time 4125351680 ps
CPU time 72.81 seconds
Started Mar 28 03:26:15 PM PDT 24
Finished Mar 28 03:27:28 PM PDT 24
Peak memory 698452 kb
Host smart-86b30308-c828-469f-8784-58ed5660bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176649903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2176649903
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2549616035
Short name T769
Test name
Test status
Simulation time 3147551885 ps
CPU time 50.88 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:27:11 PM PDT 24
Peak memory 551420 kb
Host smart-e111f4f3-040e-4b66-be9d-ee3bdd54661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549616035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2549616035
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3485526919
Short name T473
Test name
Test status
Simulation time 668034496 ps
CPU time 1.14 seconds
Started Mar 28 03:26:16 PM PDT 24
Finished Mar 28 03:26:17 PM PDT 24
Peak memory 203692 kb
Host smart-0a0c9047-d791-4a86-81de-49142dea0c3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485526919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3485526919
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3896067529
Short name T1163
Test name
Test status
Simulation time 164876095 ps
CPU time 3.31 seconds
Started Mar 28 03:26:13 PM PDT 24
Finished Mar 28 03:26:16 PM PDT 24
Peak memory 203804 kb
Host smart-7a1f805a-83d2-421d-b808-8d7705e5ec2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896067529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3896067529
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3742403525
Short name T282
Test name
Test status
Simulation time 26184774676 ps
CPU time 63.55 seconds
Started Mar 28 03:26:17 PM PDT 24
Finished Mar 28 03:27:21 PM PDT 24
Peak memory 760932 kb
Host smart-474ed5d4-6cdd-41e8-aed2-b64212f446eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742403525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3742403525
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.2256503546
Short name T1180
Test name
Test status
Simulation time 2916453733 ps
CPU time 4.51 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:44 PM PDT 24
Peak memory 203872 kb
Host smart-2d8c2fb7-f44c-4f44-86d4-fb73bb838efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256503546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2256503546
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3915872935
Short name T475
Test name
Test status
Simulation time 7084954282 ps
CPU time 87.58 seconds
Started Mar 28 03:26:36 PM PDT 24
Finished Mar 28 03:28:04 PM PDT 24
Peak memory 398792 kb
Host smart-6939df0e-ecca-4bb2-9c8f-e75905d1695d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915872935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3915872935
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3376593725
Short name T684
Test name
Test status
Simulation time 85215279 ps
CPU time 0.68 seconds
Started Mar 28 03:26:15 PM PDT 24
Finished Mar 28 03:26:16 PM PDT 24
Peak memory 203632 kb
Host smart-9457b63c-5d3d-41d6-9b52-ca0ce105f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376593725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3376593725
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3721184957
Short name T987
Test name
Test status
Simulation time 5073491560 ps
CPU time 65.81 seconds
Started Mar 28 03:26:17 PM PDT 24
Finished Mar 28 03:27:23 PM PDT 24
Peak memory 228540 kb
Host smart-36f59310-b170-4315-adbf-080eded3ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721184957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3721184957
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.4144909307
Short name T307
Test name
Test status
Simulation time 3583523731 ps
CPU time 41.53 seconds
Started Mar 28 03:26:20 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 270588 kb
Host smart-ab73b06d-1f74-4b4b-9552-7b8e46e9a7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144909307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.4144909307
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1661590714
Short name T1175
Test name
Test status
Simulation time 5679419173 ps
CPU time 5.36 seconds
Started Mar 28 03:26:36 PM PDT 24
Finished Mar 28 03:26:42 PM PDT 24
Peak memory 205044 kb
Host smart-1f6d0bfc-fde8-4781-b146-e8c08a2e1c19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661590714 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1661590714
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.976967919
Short name T296
Test name
Test status
Simulation time 10404818377 ps
CPU time 9.84 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:26:50 PM PDT 24
Peak memory 289548 kb
Host smart-8bd8af2d-e481-4c84-9580-d9ac962135c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976967919 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.976967919
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1194302528
Short name T345
Test name
Test status
Simulation time 10083238567 ps
CPU time 120.2 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:28:40 PM PDT 24
Peak memory 741144 kb
Host smart-1efeb23e-967f-4c0a-a2db-2c8617c56e60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194302528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1194302528
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.871543077
Short name T1054
Test name
Test status
Simulation time 860719638 ps
CPU time 2.55 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:42 PM PDT 24
Peak memory 203760 kb
Host smart-842f94b7-6afb-4f7f-b575-c44dfc3a4bc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871543077 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_hrst.871543077
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1846651756
Short name T885
Test name
Test status
Simulation time 1042186774 ps
CPU time 5.43 seconds
Started Mar 28 03:26:38 PM PDT 24
Finished Mar 28 03:26:44 PM PDT 24
Peak memory 206296 kb
Host smart-37e9f395-23a3-4a2e-ab33-46794f92cdfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846651756 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1846651756
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3798633971
Short name T1137
Test name
Test status
Simulation time 5387275740 ps
CPU time 14.35 seconds
Started Mar 28 03:26:17 PM PDT 24
Finished Mar 28 03:26:31 PM PDT 24
Peak memory 203936 kb
Host smart-4c494555-a6a9-4ac3-8b1b-483bbac13c3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798633971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3798633971
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.350038265
Short name T342
Test name
Test status
Simulation time 1508324156 ps
CPU time 23.43 seconds
Started Mar 28 03:26:22 PM PDT 24
Finished Mar 28 03:26:45 PM PDT 24
Peak memory 224408 kb
Host smart-53a8eb9a-2c84-4913-ad6d-8e0f8301c03a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350038265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.350038265
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1179839136
Short name T554
Test name
Test status
Simulation time 28800896213 ps
CPU time 2258.76 seconds
Started Mar 28 03:26:17 PM PDT 24
Finished Mar 28 04:03:57 PM PDT 24
Peak memory 3554140 kb
Host smart-9a564713-cb22-4526-a25b-a352ec42cf52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179839136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1179839136
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3363791350
Short name T954
Test name
Test status
Simulation time 5217518749 ps
CPU time 7.09 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:46 PM PDT 24
Peak memory 220096 kb
Host smart-ad4165dd-05c4-4fe2-9954-7cf74d991c73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363791350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3363791350
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3945671594
Short name T1002
Test name
Test status
Simulation time 41296793 ps
CPU time 0.62 seconds
Started Mar 28 03:27:07 PM PDT 24
Finished Mar 28 03:27:09 PM PDT 24
Peak memory 203620 kb
Host smart-9ea0f2cf-b38d-4e7f-9541-44da9b3f99ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945671594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3945671594
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3262765789
Short name T803
Test name
Test status
Simulation time 285653578 ps
CPU time 1.26 seconds
Started Mar 28 03:26:41 PM PDT 24
Finished Mar 28 03:26:43 PM PDT 24
Peak memory 220172 kb
Host smart-f420fd05-1e90-4e46-a8dd-586a8e1a3f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262765789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3262765789
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3319995625
Short name T256
Test name
Test status
Simulation time 855869180 ps
CPU time 9.32 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:49 PM PDT 24
Peak memory 294704 kb
Host smart-e9c1840a-9ed4-4927-8fa4-f9a2c70ca4b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319995625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3319995625
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2387628537
Short name T1027
Test name
Test status
Simulation time 1335088172 ps
CPU time 47.12 seconds
Started Mar 28 03:26:42 PM PDT 24
Finished Mar 28 03:27:29 PM PDT 24
Peak memory 513044 kb
Host smart-eb73aa29-1130-4f11-abfd-feeab8ac8008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387628537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2387628537
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.890470456
Short name T731
Test name
Test status
Simulation time 3856281268 ps
CPU time 68.23 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:27:48 PM PDT 24
Peak memory 684964 kb
Host smart-167ae5ea-1830-4c37-82bd-8ce9dfd80dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890470456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.890470456
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.453689231
Short name T639
Test name
Test status
Simulation time 368062023 ps
CPU time 0.95 seconds
Started Mar 28 03:26:38 PM PDT 24
Finished Mar 28 03:26:40 PM PDT 24
Peak memory 203692 kb
Host smart-b2cffbc8-89e1-41ca-a11e-4585783a1d72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453689231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fm
t.453689231
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3352544320
Short name T1005
Test name
Test status
Simulation time 145921486 ps
CPU time 7.35 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:47 PM PDT 24
Peak memory 203812 kb
Host smart-32a1dbd2-5505-4c38-aef4-967b91ddb3bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352544320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3352544320
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1745291640
Short name T1036
Test name
Test status
Simulation time 8460388431 ps
CPU time 134.13 seconds
Started Mar 28 03:26:37 PM PDT 24
Finished Mar 28 03:28:52 PM PDT 24
Peak memory 731148 kb
Host smart-1aa9b7c2-2c8b-4759-8057-df766f070749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745291640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1745291640
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.1585247465
Short name T222
Test name
Test status
Simulation time 2461572729 ps
CPU time 6.96 seconds
Started Mar 28 03:26:38 PM PDT 24
Finished Mar 28 03:26:46 PM PDT 24
Peak memory 203892 kb
Host smart-7a53a851-617b-413d-aa95-00ce8c159c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585247465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1585247465
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_override.1802136941
Short name T895
Test name
Test status
Simulation time 30053780 ps
CPU time 0.66 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:40 PM PDT 24
Peak memory 203612 kb
Host smart-84ac4152-bb21-407f-b68b-508104657ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802136941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1802136941
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3729251268
Short name T1014
Test name
Test status
Simulation time 7883070646 ps
CPU time 73.8 seconds
Started Mar 28 03:26:36 PM PDT 24
Finished Mar 28 03:27:50 PM PDT 24
Peak memory 220556 kb
Host smart-8a414919-f4cf-477f-916d-3ba11440cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729251268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3729251268
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.1181967060
Short name T255
Test name
Test status
Simulation time 5100945000 ps
CPU time 78.47 seconds
Started Mar 28 03:26:35 PM PDT 24
Finished Mar 28 03:27:55 PM PDT 24
Peak memory 404120 kb
Host smart-709cc9b7-f871-4ac9-bb75-c50fa56bc9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181967060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.1181967060
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.158669548
Short name T1025
Test name
Test status
Simulation time 4181126161 ps
CPU time 4.54 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:26:44 PM PDT 24
Peak memory 212044 kb
Host smart-edb1f211-170c-450a-86ad-ae3b977cc083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158669548 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.158669548
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2971949482
Short name T1155
Test name
Test status
Simulation time 10226491507 ps
CPU time 14.87 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:26:55 PM PDT 24
Peak memory 285548 kb
Host smart-1a7b22f9-6683-4735-9fa7-526b790f79c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971949482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2971949482
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1137877132
Short name T1039
Test name
Test status
Simulation time 10045265069 ps
CPU time 111.5 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:28:31 PM PDT 24
Peak memory 731732 kb
Host smart-1b54ffbf-740c-4fdf-b41f-e5fe5588d40e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137877132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1137877132
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.522479445
Short name T626
Test name
Test status
Simulation time 336988876 ps
CPU time 2.19 seconds
Started Mar 28 03:26:38 PM PDT 24
Finished Mar 28 03:26:41 PM PDT 24
Peak memory 203692 kb
Host smart-c1eddb10-2788-4937-91ca-010a5eb390c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522479445 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.522479445
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2237231466
Short name T560
Test name
Test status
Simulation time 809185114 ps
CPU time 4.47 seconds
Started Mar 28 03:26:37 PM PDT 24
Finished Mar 28 03:26:42 PM PDT 24
Peak memory 206420 kb
Host smart-97eebebf-4799-4881-80b4-b9f344a11a80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237231466 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2237231466
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.509067969
Short name T436
Test name
Test status
Simulation time 5893163018 ps
CPU time 4.46 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:26:45 PM PDT 24
Peak memory 203852 kb
Host smart-0c6eb256-95ef-4024-88a4-c01122b9ba05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509067969 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.509067969
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2135217522
Short name T858
Test name
Test status
Simulation time 1414896007 ps
CPU time 19.64 seconds
Started Mar 28 03:26:38 PM PDT 24
Finished Mar 28 03:26:59 PM PDT 24
Peak memory 203868 kb
Host smart-98be957e-2fbf-4960-bce5-ce309a6fe82a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135217522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2135217522
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1562607216
Short name T587
Test name
Test status
Simulation time 1951243924 ps
CPU time 42.66 seconds
Started Mar 28 03:26:37 PM PDT 24
Finished Mar 28 03:27:20 PM PDT 24
Peak memory 203852 kb
Host smart-4078aac1-6531-4657-84b3-ea0f5a0ecbfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562607216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1562607216
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3510326670
Short name T1140
Test name
Test status
Simulation time 5728153712 ps
CPU time 88.6 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:28:08 PM PDT 24
Peak memory 932368 kb
Host smart-e94853d7-8d64-46d1-a5a2-a6090745d1cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510326670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3510326670
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3889358431
Short name T507
Test name
Test status
Simulation time 1167548607 ps
CPU time 6.34 seconds
Started Mar 28 03:26:38 PM PDT 24
Finished Mar 28 03:26:44 PM PDT 24
Peak memory 210220 kb
Host smart-21851cc4-a88f-4c76-a4be-4ca2a3c566b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889358431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3889358431
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.97883083
Short name T744
Test name
Test status
Simulation time 15590846 ps
CPU time 0.62 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:26:54 PM PDT 24
Peak memory 203700 kb
Host smart-ad4d834a-0017-4d78-8660-57116f48191b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97883083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.97883083
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.269660275
Short name T737
Test name
Test status
Simulation time 144314431 ps
CPU time 1.19 seconds
Started Mar 28 03:26:41 PM PDT 24
Finished Mar 28 03:26:42 PM PDT 24
Peak memory 203836 kb
Host smart-3575c5ef-b074-45ed-a202-3e2257905d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269660275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.269660275
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3771534122
Short name T706
Test name
Test status
Simulation time 316957024 ps
CPU time 7.05 seconds
Started Mar 28 03:26:36 PM PDT 24
Finished Mar 28 03:26:43 PM PDT 24
Peak memory 269264 kb
Host smart-408bd921-925a-496f-a429-53b4f424a3ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771534122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3771534122
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.2378005236
Short name T667
Test name
Test status
Simulation time 1308450278 ps
CPU time 30.04 seconds
Started Mar 28 03:26:43 PM PDT 24
Finished Mar 28 03:27:14 PM PDT 24
Peak memory 409200 kb
Host smart-0f3e5cf2-1a0c-486e-9492-398c271b15c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378005236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2378005236
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3658011913
Short name T10
Test name
Test status
Simulation time 2367936264 ps
CPU time 86.97 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:28:06 PM PDT 24
Peak memory 770056 kb
Host smart-fd41ce47-227c-4aab-8f1f-a835c4066220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658011913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3658011913
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1563366957
Short name T484
Test name
Test status
Simulation time 297678191 ps
CPU time 0.84 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:26:41 PM PDT 24
Peak memory 203720 kb
Host smart-97166ca0-ba48-410e-8c0e-ca3d9d1c653b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563366957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1563366957
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1082767710
Short name T713
Test name
Test status
Simulation time 582518779 ps
CPU time 4.68 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:44 PM PDT 24
Peak memory 231312 kb
Host smart-60017ab0-6d47-474b-ab0c-95c3aa6ccfea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082767710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1082767710
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.262630436
Short name T609
Test name
Test status
Simulation time 16244470900 ps
CPU time 168.7 seconds
Started Mar 28 03:26:43 PM PDT 24
Finished Mar 28 03:29:33 PM PDT 24
Peak memory 770212 kb
Host smart-29663915-f946-4197-9520-6f0c2b7aa329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262630436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.262630436
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.468898687
Short name T509
Test name
Test status
Simulation time 1273945411 ps
CPU time 4.79 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 203828 kb
Host smart-2061ed8e-84de-44b0-98fc-ab164cc40a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468898687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.468898687
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2647342758
Short name T724
Test name
Test status
Simulation time 4536123285 ps
CPU time 26.62 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:27:21 PM PDT 24
Peak memory 361152 kb
Host smart-17f2c013-71aa-4a49-85ba-57514e1cb8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647342758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2647342758
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1355505851
Short name T908
Test name
Test status
Simulation time 30160582 ps
CPU time 0.68 seconds
Started Mar 28 03:26:42 PM PDT 24
Finished Mar 28 03:26:44 PM PDT 24
Peak memory 203612 kb
Host smart-7dc4ec0c-0024-4544-adec-a6a7c9c3c858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355505851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1355505851
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1783861812
Short name T30
Test name
Test status
Simulation time 7137790279 ps
CPU time 322.45 seconds
Started Mar 28 03:26:37 PM PDT 24
Finished Mar 28 03:32:00 PM PDT 24
Peak memory 248408 kb
Host smart-2f0d7354-d425-452e-bc39-b2e725cdd935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783861812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1783861812
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3099661246
Short name T1169
Test name
Test status
Simulation time 6719512346 ps
CPU time 30.51 seconds
Started Mar 28 03:26:38 PM PDT 24
Finished Mar 28 03:27:10 PM PDT 24
Peak memory 380748 kb
Host smart-d792ef94-cd5b-419b-a35a-f569503243f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099661246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3099661246
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.2082983323
Short name T29
Test name
Test status
Simulation time 34428069697 ps
CPU time 673.41 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:37:53 PM PDT 24
Peak memory 2195676 kb
Host smart-ee3467e7-5fa6-4358-90bb-b40857514220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082983323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.2082983323
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1263328472
Short name T494
Test name
Test status
Simulation time 1684849215 ps
CPU time 2.53 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:26:42 PM PDT 24
Peak memory 203816 kb
Host smart-31142d32-555e-4d95-a61e-e2e8725d8931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263328472 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1263328472
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3988836692
Short name T1164
Test name
Test status
Simulation time 10312856106 ps
CPU time 15.5 seconds
Started Mar 28 03:26:41 PM PDT 24
Finished Mar 28 03:26:58 PM PDT 24
Peak memory 310604 kb
Host smart-1738b68b-8069-42c5-99f0-ab9ac28d5449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988836692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3988836692
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.3593740414
Short name T1037
Test name
Test status
Simulation time 1080205760 ps
CPU time 2.82 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:42 PM PDT 24
Peak memory 203736 kb
Host smart-3fc14ef8-baaf-489e-afa9-1df99bc2ac8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593740414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.3593740414
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3003256456
Short name T757
Test name
Test status
Simulation time 1403833616 ps
CPU time 4.92 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:26:44 PM PDT 24
Peak memory 206436 kb
Host smart-59692f3d-e15e-4661-b342-4f65ef46b5cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003256456 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3003256456
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3407251493
Short name T334
Test name
Test status
Simulation time 13408429276 ps
CPU time 43.41 seconds
Started Mar 28 03:26:40 PM PDT 24
Finished Mar 28 03:27:24 PM PDT 24
Peak memory 203776 kb
Host smart-c01be18b-e0f8-4d5d-8b5c-e8a2f2115092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407251493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3407251493
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1469086313
Short name T562
Test name
Test status
Simulation time 39738516424 ps
CPU time 921.99 seconds
Started Mar 28 03:26:39 PM PDT 24
Finished Mar 28 03:42:02 PM PDT 24
Peak memory 4334792 kb
Host smart-61fea100-59f1-4c81-a67f-361a4578f32c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469086313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1469086313
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3194594816
Short name T860
Test name
Test status
Simulation time 3946683428 ps
CPU time 6.79 seconds
Started Mar 28 03:26:43 PM PDT 24
Finished Mar 28 03:26:51 PM PDT 24
Peak memory 220056 kb
Host smart-da18743b-e78d-4bc3-96e8-58e75ea3f034
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194594816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3194594816
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2895938575
Short name T1151
Test name
Test status
Simulation time 17632800 ps
CPU time 0.64 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 203600 kb
Host smart-1252bff6-a52c-4f41-b1bf-d38bfea9c7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895938575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2895938575
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2958488357
Short name T650
Test name
Test status
Simulation time 65981639 ps
CPU time 1.37 seconds
Started Mar 28 03:26:53 PM PDT 24
Finished Mar 28 03:26:55 PM PDT 24
Peak memory 212064 kb
Host smart-20821399-a221-40b2-9a10-b932a4f8c90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958488357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2958488357
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2291688580
Short name T1024
Test name
Test status
Simulation time 1392136588 ps
CPU time 6.48 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 279416 kb
Host smart-8a644598-c41b-41fc-b530-686e32b8ca6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291688580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2291688580
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2787391814
Short name T90
Test name
Test status
Simulation time 2898770863 ps
CPU time 33.39 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:27:33 PM PDT 24
Peak memory 403848 kb
Host smart-d020e193-2df5-467f-b454-396a40dcd7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787391814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2787391814
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.975932195
Short name T736
Test name
Test status
Simulation time 2123286476 ps
CPU time 75.07 seconds
Started Mar 28 03:26:55 PM PDT 24
Finished Mar 28 03:28:11 PM PDT 24
Peak memory 708612 kb
Host smart-f45cc0f6-cfb4-4960-88ba-9e10cab5f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975932195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.975932195
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.510768694
Short name T432
Test name
Test status
Simulation time 248399467 ps
CPU time 3.53 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 223916 kb
Host smart-28802c32-7daf-4cc4-b7ac-9f3ea7fbdbe1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510768694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
510768694
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2280432335
Short name T1157
Test name
Test status
Simulation time 2297412900 ps
CPU time 137.01 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:29:12 PM PDT 24
Peak memory 671792 kb
Host smart-80fb75a3-b9ba-4eb2-8b39-9638f0434d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280432335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2280432335
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1333186979
Short name T365
Test name
Test status
Simulation time 291640369 ps
CPU time 12.74 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:10 PM PDT 24
Peak memory 203844 kb
Host smart-77b0fe67-7711-41e7-8521-15bdf6ec9115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333186979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1333186979
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1059594571
Short name T15
Test name
Test status
Simulation time 1766094381 ps
CPU time 33.01 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:27:32 PM PDT 24
Peak memory 325604 kb
Host smart-231db27b-6f2d-4460-a2b7-78d17a3e486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059594571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1059594571
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.2947818614
Short name T462
Test name
Test status
Simulation time 25345711 ps
CPU time 0.64 seconds
Started Mar 28 03:26:53 PM PDT 24
Finished Mar 28 03:26:54 PM PDT 24
Peak memory 203624 kb
Host smart-a311efd1-fbe5-48dc-8363-71f68d70d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947818614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2947818614
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1933360967
Short name T196
Test name
Test status
Simulation time 23979180413 ps
CPU time 85.63 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:28:20 PM PDT 24
Peak memory 203936 kb
Host smart-e92ed44c-00a9-4612-bcba-113df31f1808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933360967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1933360967
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2954132205
Short name T265
Test name
Test status
Simulation time 8642173271 ps
CPU time 28.51 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:27:23 PM PDT 24
Peak memory 366076 kb
Host smart-31aa1524-2648-4ae9-b7d7-67ea1ac26452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954132205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2954132205
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2175158114
Short name T449
Test name
Test status
Simulation time 822477503 ps
CPU time 2.39 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:26:59 PM PDT 24
Peak memory 203804 kb
Host smart-1a48532c-1c7b-44ca-b743-1168158c33b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175158114 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2175158114
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.872460365
Short name T877
Test name
Test status
Simulation time 10144427836 ps
CPU time 33.99 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:34 PM PDT 24
Peak memory 378644 kb
Host smart-71453fb1-c1e6-430a-beb5-4d3ccb8e01a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872460365 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.872460365
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.717447130
Short name T682
Test name
Test status
Simulation time 10065894712 ps
CPU time 98.08 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:28:38 PM PDT 24
Peak memory 723148 kb
Host smart-9845989b-c41f-4c7d-9969-255e42766e06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717447130 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.717447130
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.1248342527
Short name T1066
Test name
Test status
Simulation time 261727119 ps
CPU time 1.95 seconds
Started Mar 28 03:26:53 PM PDT 24
Finished Mar 28 03:26:55 PM PDT 24
Peak memory 203844 kb
Host smart-a618d525-4639-4a05-a78e-a39d0c80e29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248342527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.1248342527
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3824981260
Short name T353
Test name
Test status
Simulation time 2917931912 ps
CPU time 4.04 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 203900 kb
Host smart-08e31b69-9f42-4339-b665-ad5ec3007059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824981260 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3824981260
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.477618487
Short name T524
Test name
Test status
Simulation time 5663062144 ps
CPU time 12.25 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:27:11 PM PDT 24
Peak memory 203892 kb
Host smart-7469c4cf-e07b-42fc-a832-59371d594224
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477618487 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.477618487
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3003705318
Short name T370
Test name
Test status
Simulation time 8859452955 ps
CPU time 14.5 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:12 PM PDT 24
Peak memory 203876 kb
Host smart-2dba6bcd-4d7b-4450-9155-e0a9eba9d129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003705318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3003705318
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1502545576
Short name T986
Test name
Test status
Simulation time 1940394998 ps
CPU time 31.84 seconds
Started Mar 28 03:26:55 PM PDT 24
Finished Mar 28 03:27:27 PM PDT 24
Peak memory 235068 kb
Host smart-9edaf970-4832-4208-b237-cc6e6a2d2d21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502545576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1502545576
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3816289939
Short name T156
Test name
Test status
Simulation time 12052755270 ps
CPU time 103.62 seconds
Started Mar 28 03:26:53 PM PDT 24
Finished Mar 28 03:28:37 PM PDT 24
Peak memory 1224656 kb
Host smart-b8dd5015-32dd-4d6b-9fd3-99cb9c4c2d2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816289939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3816289939
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2370114751
Short name T657
Test name
Test status
Simulation time 5748613385 ps
CPU time 7.66 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:27:04 PM PDT 24
Peak memory 220120 kb
Host smart-3902ddbc-3daf-44c5-83a3-fd12470c9c91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370114751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2370114751
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.2781690964
Short name T1193
Test name
Test status
Simulation time 10940588513 ps
CPU time 3.4 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 204972 kb
Host smart-313038dd-350d-448e-9979-718e6a5d2d43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781690964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.i2c_target_unexp_stop.2781690964
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3704606095
Short name T849
Test name
Test status
Simulation time 108635275 ps
CPU time 0.62 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:26:59 PM PDT 24
Peak memory 203720 kb
Host smart-a08b836c-d540-4f2b-a61c-ba4057a63ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704606095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3704606095
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3168200915
Short name T755
Test name
Test status
Simulation time 788847015 ps
CPU time 1.19 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:26:59 PM PDT 24
Peak memory 215276 kb
Host smart-b20a7224-2cac-44a0-84b5-798d3d585f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168200915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3168200915
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.167238171
Short name T571
Test name
Test status
Simulation time 2419831134 ps
CPU time 4.38 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 246304 kb
Host smart-c66e0f1e-a454-4da3-889e-3d8036e8d223
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167238171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.167238171
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2783093788
Short name T472
Test name
Test status
Simulation time 6328752968 ps
CPU time 83.18 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:28:22 PM PDT 24
Peak memory 488236 kb
Host smart-a2129a09-addc-48d5-b86b-cdce2e07c0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783093788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2783093788
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.4015322281
Short name T1125
Test name
Test status
Simulation time 477181134 ps
CPU time 1.06 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:27:00 PM PDT 24
Peak memory 203812 kb
Host smart-cdab1c70-5058-4c95-b92d-d7caf4807df1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015322281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.4015322281
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2127309821
Short name T593
Test name
Test status
Simulation time 1333457332 ps
CPU time 4.26 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 203732 kb
Host smart-5f76fbeb-d587-4d27-83e9-6e13f514ea8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127309821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2127309821
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2519411908
Short name T791
Test name
Test status
Simulation time 3058605136 ps
CPU time 88.35 seconds
Started Mar 28 03:26:55 PM PDT 24
Finished Mar 28 03:28:23 PM PDT 24
Peak memory 931596 kb
Host smart-a368da51-5408-4ed3-a8f0-c5634519efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519411908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2519411908
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.357173203
Short name T901
Test name
Test status
Simulation time 873649542 ps
CPU time 18.28 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:27:17 PM PDT 24
Peak memory 203796 kb
Host smart-c50820aa-4ebc-4c24-9033-05d2d0580eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357173203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.357173203
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.1575686082
Short name T468
Test name
Test status
Simulation time 6132130350 ps
CPU time 30.23 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:27:29 PM PDT 24
Peak memory 411368 kb
Host smart-696796ad-7e6d-4223-acdb-acc41b30903b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575686082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.1575686082
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2740296927
Short name T1085
Test name
Test status
Simulation time 18411071 ps
CPU time 0.65 seconds
Started Mar 28 03:26:55 PM PDT 24
Finished Mar 28 03:26:56 PM PDT 24
Peak memory 203544 kb
Host smart-388b7ace-631f-4e79-933b-57102b719736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740296927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2740296927
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2340984716
Short name T1042
Test name
Test status
Simulation time 4819872825 ps
CPU time 70.79 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:28:07 PM PDT 24
Peak memory 226584 kb
Host smart-5fb16763-ec0c-4685-9f89-3f89032de821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340984716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2340984716
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.106354810
Short name T349
Test name
Test status
Simulation time 1461835326 ps
CPU time 33.84 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:27:32 PM PDT 24
Peak memory 361756 kb
Host smart-920b9e90-ee5f-4441-922f-0486ff88bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106354810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.106354810
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2581515717
Short name T880
Test name
Test status
Simulation time 630921996 ps
CPU time 2.14 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:27:01 PM PDT 24
Peak memory 203784 kb
Host smart-78d64d7f-ecf7-4698-85cc-0c11b6572cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581515717 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2581515717
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.4043626201
Short name T601
Test name
Test status
Simulation time 10093198501 ps
CPU time 36.37 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:37 PM PDT 24
Peak memory 412324 kb
Host smart-06915d28-2700-4482-a267-ab501c0f30cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043626201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.4043626201
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.4202658321
Short name T671
Test name
Test status
Simulation time 10055046241 ps
CPU time 86.74 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:28:25 PM PDT 24
Peak memory 697576 kb
Host smart-5d178726-b78d-42d9-a923-cec44a6b001f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202658321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.4202658321
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.3818263454
Short name T815
Test name
Test status
Simulation time 315486907 ps
CPU time 2.18 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 203840 kb
Host smart-6ffe7e35-0e88-4049-8f1c-76137726231a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818263454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.3818263454
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3537149441
Short name T358
Test name
Test status
Simulation time 2216657906 ps
CPU time 5.6 seconds
Started Mar 28 03:27:02 PM PDT 24
Finished Mar 28 03:27:08 PM PDT 24
Peak memory 208816 kb
Host smart-bb596906-58ec-49bd-acdf-52046f76afa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537149441 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3537149441
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2756120344
Short name T1087
Test name
Test status
Simulation time 2053639501 ps
CPU time 16.11 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:14 PM PDT 24
Peak memory 203748 kb
Host smart-9840a53f-7496-43ae-b8ac-e0bc66d7c7cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756120344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2756120344
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2709921631
Short name T977
Test name
Test status
Simulation time 5635784469 ps
CPU time 28.36 seconds
Started Mar 28 03:26:54 PM PDT 24
Finished Mar 28 03:27:22 PM PDT 24
Peak memory 223700 kb
Host smart-97d2469c-561c-46f6-8257-291f851f7bd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709921631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2709921631
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3003986148
Short name T306
Test name
Test status
Simulation time 29276813212 ps
CPU time 611.82 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:37:11 PM PDT 24
Peak memory 1654872 kb
Host smart-63473421-62ec-4879-8df1-566b11d9a279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003986148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3003986148
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2684920127
Short name T674
Test name
Test status
Simulation time 4615592553 ps
CPU time 6.13 seconds
Started Mar 28 03:27:02 PM PDT 24
Finished Mar 28 03:27:08 PM PDT 24
Peak memory 203932 kb
Host smart-8d43c846-3b35-4296-b4b3-44a5dcac460b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684920127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2684920127
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.1463585905
Short name T950
Test name
Test status
Simulation time 2426928050 ps
CPU time 5.09 seconds
Started Mar 28 03:26:55 PM PDT 24
Finished Mar 28 03:27:00 PM PDT 24
Peak memory 210388 kb
Host smart-817fd24e-9f40-4a18-90ef-69c7776d33ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463585905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.1463585905
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.4179232680
Short name T892
Test name
Test status
Simulation time 26382648 ps
CPU time 0.66 seconds
Started Mar 28 03:27:01 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 203664 kb
Host smart-7f01c170-b74c-4a5d-9aee-20b8894b842b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179232680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.4179232680
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.757210915
Short name T707
Test name
Test status
Simulation time 213948205 ps
CPU time 1.26 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 212008 kb
Host smart-66721768-971f-47fb-818d-acc5ff59acec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757210915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.757210915
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.876820583
Short name T1110
Test name
Test status
Simulation time 1226817080 ps
CPU time 16.09 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:16 PM PDT 24
Peak memory 266308 kb
Host smart-dd8efbe5-fb0c-40b7-b86e-8ee59a57c448
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876820583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.876820583
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3320537926
Short name T568
Test name
Test status
Simulation time 5185779353 ps
CPU time 52.59 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:27:50 PM PDT 24
Peak memory 618260 kb
Host smart-369637d6-cfa8-4fd0-9317-c41389ea342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320537926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3320537926
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2797339040
Short name T521
Test name
Test status
Simulation time 2837365814 ps
CPU time 95.98 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:28:32 PM PDT 24
Peak memory 450792 kb
Host smart-86608105-6143-4d50-8e4b-931c2d36b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797339040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2797339040
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.4118896787
Short name T447
Test name
Test status
Simulation time 98863889 ps
CPU time 0.97 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:26:58 PM PDT 24
Peak memory 203640 kb
Host smart-9e6f5387-88a8-40b0-af4a-ebd5b47475d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118896787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.4118896787
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2403858597
Short name T290
Test name
Test status
Simulation time 535498228 ps
CPU time 6.06 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:27:04 PM PDT 24
Peak memory 218568 kb
Host smart-7161883a-db08-4dd3-b5d4-bb1f05566cfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403858597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2403858597
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1614337550
Short name T932
Test name
Test status
Simulation time 8019874184 ps
CPU time 272.2 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:31:28 PM PDT 24
Peak memory 1053748 kb
Host smart-f4fe2eb3-7044-4e0f-9d40-7222a1744a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614337550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1614337550
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.901820635
Short name T318
Test name
Test status
Simulation time 1887341670 ps
CPU time 7.96 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:27:06 PM PDT 24
Peak memory 203876 kb
Host smart-210d117f-05d5-4aa9-aad9-ab61d93d4165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901820635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.901820635
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1951633689
Short name T422
Test name
Test status
Simulation time 1488474355 ps
CPU time 82.91 seconds
Started Mar 28 03:27:01 PM PDT 24
Finished Mar 28 03:28:25 PM PDT 24
Peak memory 478352 kb
Host smart-0c455c00-5ce1-42b6-adf0-fd40ba54fc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951633689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1951633689
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1987036066
Short name T1083
Test name
Test status
Simulation time 27131742 ps
CPU time 0.65 seconds
Started Mar 28 03:26:56 PM PDT 24
Finished Mar 28 03:26:57 PM PDT 24
Peak memory 203616 kb
Host smart-bcbed944-1886-4504-b5b2-948ca44506ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987036066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1987036066
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2937389614
Short name T273
Test name
Test status
Simulation time 12703315991 ps
CPU time 387.87 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:33:27 PM PDT 24
Peak memory 1862164 kb
Host smart-dc2d3240-f3c1-42ae-ae91-5e1a32125c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937389614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2937389614
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3060524346
Short name T1081
Test name
Test status
Simulation time 2229347162 ps
CPU time 54.95 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:27:54 PM PDT 24
Peak memory 311672 kb
Host smart-e8dc5690-9b71-4231-89a1-8183e2c85609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060524346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3060524346
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3786767563
Short name T498
Test name
Test status
Simulation time 7489610203 ps
CPU time 5.7 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:06 PM PDT 24
Peak memory 203908 kb
Host smart-cd714b10-b6f4-4266-a0dc-883950a5657c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786767563 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3786767563
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.154551151
Short name T675
Test name
Test status
Simulation time 10162666246 ps
CPU time 13.07 seconds
Started Mar 28 03:26:57 PM PDT 24
Finished Mar 28 03:27:11 PM PDT 24
Peak memory 297052 kb
Host smart-d395d25f-fcbf-4ad3-ac08-3fa6aae66648
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154551151 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.154551151
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2804306060
Short name T589
Test name
Test status
Simulation time 10062755295 ps
CPU time 116.11 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:28:54 PM PDT 24
Peak memory 737188 kb
Host smart-b3cb72ee-9fa6-416b-a8ac-13c2a8237bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804306060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2804306060
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.3010268641
Short name T1010
Test name
Test status
Simulation time 276026480 ps
CPU time 1.95 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:03 PM PDT 24
Peak memory 203856 kb
Host smart-53c6cb29-74e3-4b15-badc-ffa77e8535ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010268641 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.3010268641
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.426720781
Short name T607
Test name
Test status
Simulation time 768388483 ps
CPU time 4.92 seconds
Started Mar 28 03:26:58 PM PDT 24
Finished Mar 28 03:27:03 PM PDT 24
Peak memory 206696 kb
Host smart-a491fc21-d388-4a97-90a4-fcf66219be43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426720781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.426720781
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1653036571
Short name T320
Test name
Test status
Simulation time 3434823110 ps
CPU time 12.84 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:27:12 PM PDT 24
Peak memory 203968 kb
Host smart-25888e04-df62-49e1-9f9f-2f1255bef571
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653036571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1653036571
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.4203280071
Short name T376
Test name
Test status
Simulation time 1183041154 ps
CPU time 10.85 seconds
Started Mar 28 03:27:00 PM PDT 24
Finished Mar 28 03:27:11 PM PDT 24
Peak memory 203776 kb
Host smart-7f64aa32-5daa-42cf-b681-1073bba880f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203280071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.4203280071
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2533598627
Short name T241
Test name
Test status
Simulation time 8801623240 ps
CPU time 561.85 seconds
Started Mar 28 03:27:02 PM PDT 24
Finished Mar 28 03:36:24 PM PDT 24
Peak memory 1731644 kb
Host smart-c4eb3396-e3bb-4486-bcc3-598edb269198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533598627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2533598627
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.4287870842
Short name T865
Test name
Test status
Simulation time 5314369124 ps
CPU time 6.72 seconds
Started Mar 28 03:27:03 PM PDT 24
Finished Mar 28 03:27:10 PM PDT 24
Peak memory 203876 kb
Host smart-abe8c89d-c86d-4195-8f92-eef4f9cca3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287870842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.4287870842
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2926771723
Short name T1177
Test name
Test status
Simulation time 19292436 ps
CPU time 0.63 seconds
Started Mar 28 03:27:17 PM PDT 24
Finished Mar 28 03:27:18 PM PDT 24
Peak memory 203696 kb
Host smart-24f4af2c-510f-43fd-ab35-ecebac03cd40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926771723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2926771723
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3074903221
Short name T210
Test name
Test status
Simulation time 119551174 ps
CPU time 1.22 seconds
Started Mar 28 03:27:13 PM PDT 24
Finished Mar 28 03:27:15 PM PDT 24
Peak memory 212036 kb
Host smart-afe9db87-1d93-463a-b135-c3729a892ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074903221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3074903221
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1557659700
Short name T549
Test name
Test status
Simulation time 260468141 ps
CPU time 13.45 seconds
Started Mar 28 03:27:11 PM PDT 24
Finished Mar 28 03:27:25 PM PDT 24
Peak memory 255980 kb
Host smart-029ab22a-bf32-4188-85d8-1ec8e10b37f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557659700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1557659700
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2525735222
Short name T1044
Test name
Test status
Simulation time 7129501894 ps
CPU time 98.06 seconds
Started Mar 28 03:27:10 PM PDT 24
Finished Mar 28 03:28:49 PM PDT 24
Peak memory 294504 kb
Host smart-c6158a6f-72c3-4fa0-9252-2c0b59c053e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525735222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2525735222
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2447872901
Short name T829
Test name
Test status
Simulation time 1568925061 ps
CPU time 38.53 seconds
Started Mar 28 03:27:14 PM PDT 24
Finished Mar 28 03:27:53 PM PDT 24
Peak memory 486680 kb
Host smart-2c0a80bd-57f3-4589-9995-670d694880d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447872901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2447872901
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.4168116862
Short name T1132
Test name
Test status
Simulation time 262783445 ps
CPU time 0.8 seconds
Started Mar 28 03:27:15 PM PDT 24
Finished Mar 28 03:27:16 PM PDT 24
Peak memory 203540 kb
Host smart-78ed4d62-994d-4686-a3a0-183409cc3818
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168116862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.4168116862
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4251350688
Short name T471
Test name
Test status
Simulation time 487641938 ps
CPU time 8.55 seconds
Started Mar 28 03:27:16 PM PDT 24
Finished Mar 28 03:27:24 PM PDT 24
Peak memory 230472 kb
Host smart-a6ad5d8a-933d-4bde-99ae-4f2e5cfd6a09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251350688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4251350688
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3388463524
Short name T915
Test name
Test status
Simulation time 8020050942 ps
CPU time 106.64 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:28:45 PM PDT 24
Peak memory 1182512 kb
Host smart-22a2a3fa-85d7-4515-a00f-a114446052e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388463524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3388463524
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2992845746
Short name T789
Test name
Test status
Simulation time 510086351 ps
CPU time 6.24 seconds
Started Mar 28 03:27:16 PM PDT 24
Finished Mar 28 03:27:22 PM PDT 24
Peak memory 203848 kb
Host smart-a5bbf632-57dc-4986-af8d-09afe9d7b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992845746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2992845746
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3506435757
Short name T975
Test name
Test status
Simulation time 4763035650 ps
CPU time 26.32 seconds
Started Mar 28 03:27:14 PM PDT 24
Finished Mar 28 03:27:40 PM PDT 24
Peak memory 372276 kb
Host smart-a5abb5dd-7e27-419c-894b-e29b88778c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506435757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3506435757
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2054502832
Short name T11
Test name
Test status
Simulation time 16229126 ps
CPU time 0.7 seconds
Started Mar 28 03:27:01 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 203652 kb
Host smart-674bb371-43f1-4f54-8028-1eba15290b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054502832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2054502832
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2994702950
Short name T454
Test name
Test status
Simulation time 7010924133 ps
CPU time 125.59 seconds
Started Mar 28 03:27:18 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 979596 kb
Host smart-8829d284-857f-4c25-8dc4-a72eafc5a0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994702950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2994702950
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.311784736
Short name T897
Test name
Test status
Simulation time 6718496285 ps
CPU time 92.37 seconds
Started Mar 28 03:26:59 PM PDT 24
Finished Mar 28 03:28:31 PM PDT 24
Peak memory 411268 kb
Host smart-b237cd8d-7564-414d-be01-b72ec80e8ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311784736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.311784736
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3908702839
Short name T27
Test name
Test status
Simulation time 12017796779 ps
CPU time 499.4 seconds
Started Mar 28 03:27:11 PM PDT 24
Finished Mar 28 03:35:31 PM PDT 24
Peak memory 1560544 kb
Host smart-0611b116-917a-4ae1-8172-6dc252b384f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908702839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3908702839
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3543350222
Short name T1176
Test name
Test status
Simulation time 1289424316 ps
CPU time 3.37 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:15 PM PDT 24
Peak memory 203840 kb
Host smart-4c640250-129e-4918-b0b7-930ddaaaf119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543350222 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3543350222
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.4112078366
Short name T942
Test name
Test status
Simulation time 10246166528 ps
CPU time 15.9 seconds
Started Mar 28 03:27:14 PM PDT 24
Finished Mar 28 03:27:30 PM PDT 24
Peak memory 315504 kb
Host smart-9024810e-b8a6-4ca9-a7e4-e9bbdc69fc36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112078366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.4112078366
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3366346220
Short name T925
Test name
Test status
Simulation time 10158252862 ps
CPU time 104.02 seconds
Started Mar 28 03:27:18 PM PDT 24
Finished Mar 28 03:29:02 PM PDT 24
Peak memory 717476 kb
Host smart-cb57a81d-6099-4c1e-8b73-56a2452e3916
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366346220 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3366346220
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.778336193
Short name T49
Test name
Test status
Simulation time 1795423923 ps
CPU time 2.67 seconds
Started Mar 28 03:27:18 PM PDT 24
Finished Mar 28 03:27:21 PM PDT 24
Peak memory 203456 kb
Host smart-5ec96f08-f450-497d-bbd9-6c449ef2fdd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778336193 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_hrst.778336193
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.968287194
Short name T856
Test name
Test status
Simulation time 1405827534 ps
CPU time 3.59 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:16 PM PDT 24
Peak memory 203752 kb
Host smart-408db7be-7f15-4344-ada2-e9bb1250b027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968287194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.968287194
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1426690660
Short name T466
Test name
Test status
Simulation time 2823917320 ps
CPU time 52.02 seconds
Started Mar 28 03:27:11 PM PDT 24
Finished Mar 28 03:28:04 PM PDT 24
Peak memory 203828 kb
Host smart-0eaf5542-18fe-4e53-8257-bfdd77a20a52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426690660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1426690660
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.495617740
Short name T503
Test name
Test status
Simulation time 1425926628 ps
CPU time 27.54 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:40 PM PDT 24
Peak memory 219192 kb
Host smart-23730027-f627-4501-8741-db7b685a15fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495617740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.495617740
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1137695061
Short name T971
Test name
Test status
Simulation time 5544590726 ps
CPU time 7.03 seconds
Started Mar 28 03:27:13 PM PDT 24
Finished Mar 28 03:27:20 PM PDT 24
Peak memory 212132 kb
Host smart-eec8d248-348b-4a7e-987c-5820012adb95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137695061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1137695061
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3197523378
Short name T1032
Test name
Test status
Simulation time 17336098 ps
CPU time 0.62 seconds
Started Mar 28 03:25:12 PM PDT 24
Finished Mar 28 03:25:13 PM PDT 24
Peak memory 203668 kb
Host smart-aeaac31f-32bf-428b-ad33-c8db91218534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197523378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3197523378
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.328915408
Short name T355
Test name
Test status
Simulation time 608185757 ps
CPU time 1.37 seconds
Started Mar 28 03:25:01 PM PDT 24
Finished Mar 28 03:25:03 PM PDT 24
Peak memory 212016 kb
Host smart-d9c5411c-995c-4f3f-9ee6-f9a32e60377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328915408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.328915408
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1455966675
Short name T470
Test name
Test status
Simulation time 369881338 ps
CPU time 3.96 seconds
Started Mar 28 03:25:11 PM PDT 24
Finished Mar 28 03:25:15 PM PDT 24
Peak memory 228116 kb
Host smart-b6ebf1ff-485c-4dba-8535-413e47cf1b03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455966675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1455966675
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3060421660
Short name T1016
Test name
Test status
Simulation time 1351719008 ps
CPU time 45.64 seconds
Started Mar 28 03:25:01 PM PDT 24
Finished Mar 28 03:25:47 PM PDT 24
Peak memory 538740 kb
Host smart-1233dcc1-3b9c-4636-8046-e9168cabb1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060421660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3060421660
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.4171797560
Short name T39
Test name
Test status
Simulation time 160727089 ps
CPU time 0.97 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:25:07 PM PDT 24
Peak memory 203592 kb
Host smart-b8579201-7501-454f-a5c0-50782e45a44b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171797560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.4171797560
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.38494481
Short name T760
Test name
Test status
Simulation time 421158950 ps
CPU time 3.08 seconds
Started Mar 28 03:25:06 PM PDT 24
Finished Mar 28 03:25:09 PM PDT 24
Peak memory 220948 kb
Host smart-0f35fb4b-02f3-4745-8803-89dcff661601
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.38494481
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3210565321
Short name T151
Test name
Test status
Simulation time 25155402682 ps
CPU time 117.55 seconds
Started Mar 28 03:25:11 PM PDT 24
Finished Mar 28 03:27:09 PM PDT 24
Peak memory 1330296 kb
Host smart-a23b5c53-0b58-4690-8e17-4b11b91fac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210565321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3210565321
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1778117942
Short name T392
Test name
Test status
Simulation time 2607048139 ps
CPU time 17.44 seconds
Started Mar 28 03:25:13 PM PDT 24
Finished Mar 28 03:25:30 PM PDT 24
Peak memory 203900 kb
Host smart-2e5e4f7f-b56a-4182-96ed-9cc70052c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778117942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1778117942
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2464997782
Short name T1109
Test name
Test status
Simulation time 11134654354 ps
CPU time 83.17 seconds
Started Mar 28 03:25:03 PM PDT 24
Finished Mar 28 03:26:27 PM PDT 24
Peak memory 358492 kb
Host smart-3aeba93e-2538-4008-822d-08a51fb620b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464997782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2464997782
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.343904696
Short name T718
Test name
Test status
Simulation time 26197548 ps
CPU time 0.67 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:25:06 PM PDT 24
Peak memory 203684 kb
Host smart-03c508aa-09b2-490d-a5a6-c1b76d54a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343904696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.343904696
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2809227338
Short name T819
Test name
Test status
Simulation time 3072158046 ps
CPU time 91.38 seconds
Started Mar 28 03:25:15 PM PDT 24
Finished Mar 28 03:26:46 PM PDT 24
Peak memory 446124 kb
Host smart-a8473abe-22f6-4ae8-a164-c9b3b8011178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809227338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2809227338
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.4246063511
Short name T232
Test name
Test status
Simulation time 9770524211 ps
CPU time 135.64 seconds
Started Mar 28 03:25:03 PM PDT 24
Finished Mar 28 03:27:19 PM PDT 24
Peak memory 549528 kb
Host smart-ba321469-05d7-4051-b3db-06b2ff21b757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246063511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.4246063511
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.150896157
Short name T778
Test name
Test status
Simulation time 1947032222 ps
CPU time 2.48 seconds
Started Mar 28 03:25:03 PM PDT 24
Finished Mar 28 03:25:05 PM PDT 24
Peak memory 203788 kb
Host smart-d8f1c63d-ce27-4fb4-9996-47d4b0f14309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150896157 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.150896157
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.189352423
Short name T1142
Test name
Test status
Simulation time 10044687385 ps
CPU time 74.75 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:26:21 PM PDT 24
Peak memory 513004 kb
Host smart-945247a6-b9c1-4e5d-aa83-95b886898a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189352423 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.189352423
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3204645677
Short name T943
Test name
Test status
Simulation time 10101042467 ps
CPU time 82.42 seconds
Started Mar 28 03:25:01 PM PDT 24
Finished Mar 28 03:26:24 PM PDT 24
Peak memory 664008 kb
Host smart-393416a7-be33-4dfe-bb3e-d5a58afe4e83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204645677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3204645677
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.299710544
Short name T219
Test name
Test status
Simulation time 344820825 ps
CPU time 2.26 seconds
Started Mar 28 03:25:02 PM PDT 24
Finished Mar 28 03:25:04 PM PDT 24
Peak memory 203780 kb
Host smart-bcea070b-d0ff-417f-af54-5597ba62520f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299710544 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.299710544
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1276293900
Short name T246
Test name
Test status
Simulation time 4714049719 ps
CPU time 5.06 seconds
Started Mar 28 03:25:06 PM PDT 24
Finished Mar 28 03:25:11 PM PDT 24
Peak memory 203884 kb
Host smart-a29a4725-f91f-4f3e-b1e4-68901d92e247
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276293900 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1276293900
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3045471606
Short name T649
Test name
Test status
Simulation time 1757764409 ps
CPU time 15.72 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:25:22 PM PDT 24
Peak memory 203836 kb
Host smart-846d52c4-75c9-4f5b-a99a-a5b98e576c97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045471606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3045471606
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1654019406
Short name T1144
Test name
Test status
Simulation time 3462316681 ps
CPU time 24.16 seconds
Started Mar 28 03:25:00 PM PDT 24
Finished Mar 28 03:25:24 PM PDT 24
Peak memory 228548 kb
Host smart-90a27ae8-f18f-4157-8aa9-09a1216c3762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654019406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1654019406
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.383258557
Short name T920
Test name
Test status
Simulation time 8385846643 ps
CPU time 17.14 seconds
Started Mar 28 03:25:12 PM PDT 24
Finished Mar 28 03:25:30 PM PDT 24
Peak memory 203828 kb
Host smart-9c2d660c-e65c-4225-b5fe-15a287e29a5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383258557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.383258557
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1809254305
Short name T491
Test name
Test status
Simulation time 29811239106 ps
CPU time 586.24 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:34:52 PM PDT 24
Peak memory 1678268 kb
Host smart-5a964b3e-ad5e-46da-a048-9ba8900f60ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809254305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1809254305
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.350168480
Short name T1034
Test name
Test status
Simulation time 1518261334 ps
CPU time 7.66 seconds
Started Mar 28 03:25:08 PM PDT 24
Finished Mar 28 03:25:16 PM PDT 24
Peak memory 216880 kb
Host smart-bc58938c-a84e-42a7-8aba-69d8f6e9d0f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350168480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.350168480
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.877769590
Short name T773
Test name
Test status
Simulation time 44827670 ps
CPU time 0.61 seconds
Started Mar 28 03:27:18 PM PDT 24
Finished Mar 28 03:27:18 PM PDT 24
Peak memory 203184 kb
Host smart-cb9f4a92-b972-4da6-a9af-b193f57f4525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877769590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.877769590
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3996540804
Short name T111
Test name
Test status
Simulation time 161952855 ps
CPU time 1.37 seconds
Started Mar 28 03:27:14 PM PDT 24
Finished Mar 28 03:27:16 PM PDT 24
Peak memory 211984 kb
Host smart-b8beba6e-a53e-4cbe-b63d-1a767fec6418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996540804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3996540804
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.924537793
Short name T259
Test name
Test status
Simulation time 527243020 ps
CPU time 13.29 seconds
Started Mar 28 03:27:17 PM PDT 24
Finished Mar 28 03:27:31 PM PDT 24
Peak memory 249456 kb
Host smart-5592f018-52e9-4c79-84f9-21a7786154d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924537793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.924537793
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1471763722
Short name T84
Test name
Test status
Simulation time 7503052606 ps
CPU time 175.07 seconds
Started Mar 28 03:27:21 PM PDT 24
Finished Mar 28 03:30:16 PM PDT 24
Peak memory 763736 kb
Host smart-a07b853c-ed5d-4ed3-98eb-c602af7e1029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471763722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1471763722
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.513494717
Short name T634
Test name
Test status
Simulation time 12318100229 ps
CPU time 68.53 seconds
Started Mar 28 03:27:15 PM PDT 24
Finished Mar 28 03:28:24 PM PDT 24
Peak memory 727836 kb
Host smart-efe21774-27a4-43d3-9e4e-a28a11f49570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513494717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.513494717
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1471121873
Short name T452
Test name
Test status
Simulation time 577466624 ps
CPU time 1.14 seconds
Started Mar 28 03:27:13 PM PDT 24
Finished Mar 28 03:27:15 PM PDT 24
Peak memory 203472 kb
Host smart-49bd9273-5c0f-4362-8679-3a64a936b771
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471121873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1471121873
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2163875259
Short name T297
Test name
Test status
Simulation time 655729643 ps
CPU time 4.32 seconds
Started Mar 28 03:27:16 PM PDT 24
Finished Mar 28 03:27:21 PM PDT 24
Peak memory 203744 kb
Host smart-4b4eb0d6-c1bc-47b4-b2b4-3cae0edbb73f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163875259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2163875259
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2456798063
Short name T226
Test name
Test status
Simulation time 20702354113 ps
CPU time 141.19 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:29:34 PM PDT 24
Peak memory 1284540 kb
Host smart-808629cb-e8f8-468c-a5d6-64adeed47118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456798063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2456798063
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.1842711432
Short name T1141
Test name
Test status
Simulation time 391395074 ps
CPU time 16.4 seconds
Started Mar 28 03:27:25 PM PDT 24
Finished Mar 28 03:27:41 PM PDT 24
Peak memory 203868 kb
Host smart-cbf79fe4-05e0-42cc-9e52-efdb3d87d11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842711432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1842711432
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.1984747787
Short name T467
Test name
Test status
Simulation time 5755762444 ps
CPU time 66.9 seconds
Started Mar 28 03:27:17 PM PDT 24
Finished Mar 28 03:28:25 PM PDT 24
Peak memory 404388 kb
Host smart-585f9dfe-9cdc-46db-b726-0c0a26a9201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984747787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.1984747787
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2791655280
Short name T182
Test name
Test status
Simulation time 29629624 ps
CPU time 0.67 seconds
Started Mar 28 03:27:13 PM PDT 24
Finished Mar 28 03:27:14 PM PDT 24
Peak memory 203388 kb
Host smart-d5028e45-aeda-4a8c-980e-5bdb4e525d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791655280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2791655280
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1956977253
Short name T550
Test name
Test status
Simulation time 29972985271 ps
CPU time 183.66 seconds
Started Mar 28 03:27:10 PM PDT 24
Finished Mar 28 03:30:14 PM PDT 24
Peak memory 203856 kb
Host smart-d52d2c9e-74d1-4c33-bf8e-62a31fed34f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956977253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1956977253
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.868796371
Short name T968
Test name
Test status
Simulation time 2958687211 ps
CPU time 36.59 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:49 PM PDT 24
Peak memory 430404 kb
Host smart-6cf4b3a1-4dee-4ebe-808e-d1d40464d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868796371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.868796371
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1225768375
Short name T274
Test name
Test status
Simulation time 671609649 ps
CPU time 3.77 seconds
Started Mar 28 03:27:21 PM PDT 24
Finished Mar 28 03:27:25 PM PDT 24
Peak memory 203772 kb
Host smart-b202ebd5-e989-48bc-af59-f0f0cc662c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225768375 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1225768375
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.4133737223
Short name T1082
Test name
Test status
Simulation time 10089129481 ps
CPU time 16.77 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:30 PM PDT 24
Peak memory 307544 kb
Host smart-2c314a5a-88e9-4db8-b899-785e846021c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133737223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.4133737223
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.723684934
Short name T654
Test name
Test status
Simulation time 10293713872 ps
CPU time 15.4 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:28 PM PDT 24
Peak memory 324172 kb
Host smart-ac6a47e3-8593-4327-92b1-47bf91349c2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723684934 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.723684934
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2039644202
Short name T834
Test name
Test status
Simulation time 400651514 ps
CPU time 2.45 seconds
Started Mar 28 03:27:17 PM PDT 24
Finished Mar 28 03:27:20 PM PDT 24
Peak memory 203828 kb
Host smart-e3075453-7e25-4c36-a682-d6b1cd6627de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039644202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2039644202
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.4289791169
Short name T680
Test name
Test status
Simulation time 621652826 ps
CPU time 3.67 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:16 PM PDT 24
Peak memory 203832 kb
Host smart-4ff8a2c9-289e-4bd6-91f9-2a61577bcd3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289791169 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.4289791169
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2028672469
Short name T319
Test name
Test status
Simulation time 696976442 ps
CPU time 25.58 seconds
Started Mar 28 03:27:13 PM PDT 24
Finished Mar 28 03:27:39 PM PDT 24
Peak memory 203804 kb
Host smart-f9af1259-28b3-4a3a-9c5c-e21aa6abff1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028672469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2028672469
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2996543662
Short name T623
Test name
Test status
Simulation time 291245441 ps
CPU time 12.2 seconds
Started Mar 28 03:27:17 PM PDT 24
Finished Mar 28 03:27:30 PM PDT 24
Peak memory 203804 kb
Host smart-1ff714b5-c496-4c70-9a66-b578870e5a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996543662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2996543662
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.910313533
Short name T538
Test name
Test status
Simulation time 12839203120 ps
CPU time 154.47 seconds
Started Mar 28 03:27:10 PM PDT 24
Finished Mar 28 03:29:45 PM PDT 24
Peak memory 800420 kb
Host smart-dc465c2d-2e77-4110-9d87-bb7e3e2fabe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910313533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.910313533
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.389383367
Short name T508
Test name
Test status
Simulation time 8808203464 ps
CPU time 6.13 seconds
Started Mar 28 03:27:13 PM PDT 24
Finished Mar 28 03:27:20 PM PDT 24
Peak memory 211248 kb
Host smart-fc29f324-268f-4271-88bb-6f8467fe0835
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389383367 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.389383367
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2028459576
Short name T959
Test name
Test status
Simulation time 52778192 ps
CPU time 0.63 seconds
Started Mar 28 03:27:35 PM PDT 24
Finished Mar 28 03:27:36 PM PDT 24
Peak memory 203596 kb
Host smart-81184ecb-e961-4202-9bb4-de14a6e00b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028459576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2028459576
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3411269840
Short name T961
Test name
Test status
Simulation time 467748267 ps
CPU time 1.39 seconds
Started Mar 28 03:27:25 PM PDT 24
Finished Mar 28 03:27:26 PM PDT 24
Peak memory 203852 kb
Host smart-4a86d82e-c973-4936-a129-342ce783b368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411269840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3411269840
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.49993020
Short name T575
Test name
Test status
Simulation time 1730513115 ps
CPU time 15.95 seconds
Started Mar 28 03:27:12 PM PDT 24
Finished Mar 28 03:27:28 PM PDT 24
Peak memory 268812 kb
Host smart-b6d4332a-8e2c-4d5d-bebe-5b7b44c1db8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49993020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty
.49993020
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2973159744
Short name T1094
Test name
Test status
Simulation time 3622942725 ps
CPU time 52.11 seconds
Started Mar 28 03:27:26 PM PDT 24
Finished Mar 28 03:28:19 PM PDT 24
Peak memory 583680 kb
Host smart-b6d6960e-120e-4dde-9123-b9a746d31feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973159744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2973159744
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2511968791
Short name T963
Test name
Test status
Simulation time 8873908349 ps
CPU time 80.62 seconds
Started Mar 28 03:27:13 PM PDT 24
Finished Mar 28 03:28:34 PM PDT 24
Peak memory 755936 kb
Host smart-3b089d27-1124-489f-8d1b-48e0f9e48457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511968791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2511968791
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.4184942067
Short name T827
Test name
Test status
Simulation time 151976761 ps
CPU time 1.17 seconds
Started Mar 28 03:27:25 PM PDT 24
Finished Mar 28 03:27:26 PM PDT 24
Peak memory 203816 kb
Host smart-633354b3-4d80-4eb6-93ae-05d9de08d23e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184942067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.4184942067
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3641560878
Short name T107
Test name
Test status
Simulation time 165142841 ps
CPU time 9.18 seconds
Started Mar 28 03:27:15 PM PDT 24
Finished Mar 28 03:27:24 PM PDT 24
Peak memory 233668 kb
Host smart-528bd79a-fb4c-42d6-97f3-7ae13ae04b9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641560878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3641560878
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.4289990658
Short name T225
Test name
Test status
Simulation time 25774618313 ps
CPU time 300.07 seconds
Started Mar 28 03:27:17 PM PDT 24
Finished Mar 28 03:32:18 PM PDT 24
Peak memory 1138168 kb
Host smart-a5dcf171-b71e-4df5-af8e-442029627cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289990658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.4289990658
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2117686262
Short name T709
Test name
Test status
Simulation time 734288971 ps
CPU time 4.74 seconds
Started Mar 28 03:27:28 PM PDT 24
Finished Mar 28 03:27:33 PM PDT 24
Peak memory 203828 kb
Host smart-d5cdf4c8-b704-4976-ae11-18fe447cd2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117686262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2117686262
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.1136764869
Short name T929
Test name
Test status
Simulation time 2398564658 ps
CPU time 30.27 seconds
Started Mar 28 03:27:30 PM PDT 24
Finished Mar 28 03:28:01 PM PDT 24
Peak memory 414960 kb
Host smart-941a01cb-4f2c-4aba-8ef2-39a54a1d0d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136764869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1136764869
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1506651777
Short name T1043
Test name
Test status
Simulation time 5144587905 ps
CPU time 56.48 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:28:29 PM PDT 24
Peak memory 203900 kb
Host smart-7884617a-a13b-4782-924e-d38020df7fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506651777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1506651777
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1528834880
Short name T994
Test name
Test status
Simulation time 10857657573 ps
CPU time 94.72 seconds
Started Mar 28 03:27:18 PM PDT 24
Finished Mar 28 03:28:53 PM PDT 24
Peak memory 455212 kb
Host smart-8b079bb4-3904-4630-afe3-46ff2bee24ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528834880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1528834880
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.2764232138
Short name T163
Test name
Test status
Simulation time 11149330334 ps
CPU time 279.15 seconds
Started Mar 28 03:27:24 PM PDT 24
Finished Mar 28 03:32:03 PM PDT 24
Peak memory 1080880 kb
Host smart-30b2c20e-aacd-4442-8d85-081730e804c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764232138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.2764232138
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.4165881685
Short name T661
Test name
Test status
Simulation time 2718831503 ps
CPU time 3.21 seconds
Started Mar 28 03:27:33 PM PDT 24
Finished Mar 28 03:27:36 PM PDT 24
Peak memory 203844 kb
Host smart-fecb8990-6eda-44e4-b944-c800441ca09b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165881685 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.4165881685
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2760758618
Short name T192
Test name
Test status
Simulation time 10113607157 ps
CPU time 14.44 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:27:46 PM PDT 24
Peak memory 307620 kb
Host smart-8ddeafbf-b140-46f1-a4ee-1cfdbd8282e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760758618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2760758618
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1536173685
Short name T1028
Test name
Test status
Simulation time 10158902779 ps
CPU time 39.12 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:28:10 PM PDT 24
Peak memory 474648 kb
Host smart-ec71dea8-5bfb-4eb0-aa08-443d3f6a6d0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536173685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1536173685
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.859416165
Short name T451
Test name
Test status
Simulation time 728343652 ps
CPU time 2.06 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:27:34 PM PDT 24
Peak memory 203800 kb
Host smart-bd625a7f-f8d4-4445-8ce4-2c9aa8d2ed4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859416165 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.859416165
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3681605077
Short name T242
Test name
Test status
Simulation time 2892278217 ps
CPU time 6.53 seconds
Started Mar 28 03:27:30 PM PDT 24
Finished Mar 28 03:27:37 PM PDT 24
Peak memory 212520 kb
Host smart-95893997-cbe4-4be0-9256-c96cd4a8e19a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681605077 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3681605077
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3272390401
Short name T899
Test name
Test status
Simulation time 3856477417 ps
CPU time 11.27 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:27:43 PM PDT 24
Peak memory 203900 kb
Host smart-a14aa8fd-859a-461d-95b1-2238ffd36566
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272390401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3272390401
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.793577076
Short name T1072
Test name
Test status
Simulation time 6488452159 ps
CPU time 25.44 seconds
Started Mar 28 03:27:30 PM PDT 24
Finished Mar 28 03:27:56 PM PDT 24
Peak memory 233780 kb
Host smart-bf49c86b-17f9-4396-b3cd-d2244d0cdbaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793577076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.793577076
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3198233508
Short name T1070
Test name
Test status
Simulation time 36213931594 ps
CPU time 75.15 seconds
Started Mar 28 03:27:30 PM PDT 24
Finished Mar 28 03:28:46 PM PDT 24
Peak memory 687096 kb
Host smart-99fc95b1-7e92-446c-8d67-184c7a7e05a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198233508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3198233508
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.747756179
Short name T993
Test name
Test status
Simulation time 2565340469 ps
CPU time 7.31 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:27:38 PM PDT 24
Peak memory 218944 kb
Host smart-213bc29e-c040-4c74-bb6b-0ac347997064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747756179 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.747756179
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1446207512
Short name T787
Test name
Test status
Simulation time 28794786 ps
CPU time 0.62 seconds
Started Mar 28 03:27:35 PM PDT 24
Finished Mar 28 03:27:36 PM PDT 24
Peak memory 203704 kb
Host smart-8947b2c7-31a5-4da5-8a6b-9c90270da7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446207512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1446207512
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.466165557
Short name T869
Test name
Test status
Simulation time 137153109 ps
CPU time 1.44 seconds
Started Mar 28 03:27:33 PM PDT 24
Finished Mar 28 03:27:35 PM PDT 24
Peak memory 211936 kb
Host smart-b50fcd8a-2229-4d26-b527-b657913a48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466165557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.466165557
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3284239238
Short name T653
Test name
Test status
Simulation time 363540504 ps
CPU time 7.39 seconds
Started Mar 28 03:27:35 PM PDT 24
Finished Mar 28 03:27:43 PM PDT 24
Peak memory 259056 kb
Host smart-a993816e-f187-416e-a29f-96fc7fbeb24b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284239238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3284239238
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1627701746
Short name T846
Test name
Test status
Simulation time 6271420315 ps
CPU time 99.73 seconds
Started Mar 28 03:27:35 PM PDT 24
Finished Mar 28 03:29:15 PM PDT 24
Peak memory 518944 kb
Host smart-df78924b-4ca2-4cd5-a722-e867942ad030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627701746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1627701746
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3383858544
Short name T537
Test name
Test status
Simulation time 1698624282 ps
CPU time 57.85 seconds
Started Mar 28 03:27:34 PM PDT 24
Finished Mar 28 03:28:32 PM PDT 24
Peak memory 595500 kb
Host smart-ea10e21b-84b0-457b-be63-354c4b9cc0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383858544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3383858544
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2284123298
Short name T530
Test name
Test status
Simulation time 345161836 ps
CPU time 0.96 seconds
Started Mar 28 03:27:34 PM PDT 24
Finished Mar 28 03:27:35 PM PDT 24
Peak memory 203628 kb
Host smart-ce651f6a-5f1b-43c7-a5d8-da48996eac6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284123298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2284123298
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3793498435
Short name T418
Test name
Test status
Simulation time 371227381 ps
CPU time 10.99 seconds
Started Mar 28 03:27:33 PM PDT 24
Finished Mar 28 03:27:44 PM PDT 24
Peak memory 238656 kb
Host smart-9bb16bc3-8635-4088-8703-b2bbd94e0943
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793498435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3793498435
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1677053576
Short name T421
Test name
Test status
Simulation time 5769435093 ps
CPU time 80.15 seconds
Started Mar 28 03:27:33 PM PDT 24
Finished Mar 28 03:28:53 PM PDT 24
Peak memory 908104 kb
Host smart-0dd2809e-a126-4077-ba70-ddd9f66ea510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677053576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1677053576
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.4175014895
Short name T1162
Test name
Test status
Simulation time 1141709703 ps
CPU time 12.21 seconds
Started Mar 28 03:27:43 PM PDT 24
Finished Mar 28 03:27:55 PM PDT 24
Peak memory 203764 kb
Host smart-1497925e-0508-4a12-ab85-6677068be171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175014895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.4175014895
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3967962687
Short name T479
Test name
Test status
Simulation time 1457732409 ps
CPU time 21.38 seconds
Started Mar 28 03:27:29 PM PDT 24
Finished Mar 28 03:27:50 PM PDT 24
Peak memory 325896 kb
Host smart-4b6a65cd-fd07-4e7a-8498-83fcedf28589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967962687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3967962687
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.836659415
Short name T176
Test name
Test status
Simulation time 39659112 ps
CPU time 0.68 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:27:33 PM PDT 24
Peak memory 203548 kb
Host smart-6c5f84d5-fae7-47a8-94ba-18c28d81fb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836659415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.836659415
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.213334733
Short name T1031
Test name
Test status
Simulation time 6937164790 ps
CPU time 100.58 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:29:12 PM PDT 24
Peak memory 991048 kb
Host smart-c42905db-3b7d-4f64-bc31-45a5d787d5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213334733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.213334733
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3493808035
Short name T356
Test name
Test status
Simulation time 2100237186 ps
CPU time 22.09 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:27:53 PM PDT 24
Peak memory 370580 kb
Host smart-25df1b1d-2116-4f4f-b430-7f532f6fe29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493808035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3493808035
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.122231158
Short name T973
Test name
Test status
Simulation time 1557838235 ps
CPU time 3.24 seconds
Started Mar 28 03:27:34 PM PDT 24
Finished Mar 28 03:27:37 PM PDT 24
Peak memory 203752 kb
Host smart-6584988c-365e-4b65-a70f-5207d8f4b3eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122231158 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.122231158
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1780828873
Short name T1192
Test name
Test status
Simulation time 10290165075 ps
CPU time 32.85 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:28:04 PM PDT 24
Peak memory 416100 kb
Host smart-d49d77db-ee7f-4c77-80c7-7ba66bd9821f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780828873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1780828873
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2706179113
Short name T68
Test name
Test status
Simulation time 10149060730 ps
CPU time 45.73 seconds
Started Mar 28 03:27:28 PM PDT 24
Finished Mar 28 03:28:13 PM PDT 24
Peak memory 522296 kb
Host smart-8619e557-93b5-4a4e-b134-7c6d6037c2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706179113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2706179113
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.3236489724
Short name T1101
Test name
Test status
Simulation time 1526273902 ps
CPU time 2.34 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:27:34 PM PDT 24
Peak memory 203836 kb
Host smart-fb7cf36f-1010-4b80-8dac-cdca6148bb45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236489724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.3236489724
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3603927266
Short name T532
Test name
Test status
Simulation time 1372523139 ps
CPU time 3.94 seconds
Started Mar 28 03:27:30 PM PDT 24
Finished Mar 28 03:27:34 PM PDT 24
Peak memory 203804 kb
Host smart-e287c316-5d0d-44ef-b12a-3ea954a1e195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603927266 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3603927266
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.464981148
Short name T878
Test name
Test status
Simulation time 897828205 ps
CPU time 33.55 seconds
Started Mar 28 03:27:33 PM PDT 24
Finished Mar 28 03:28:07 PM PDT 24
Peak memory 203784 kb
Host smart-45b7947c-4dbd-4dfa-bdf3-40f69983a6c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464981148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.464981148
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2311320192
Short name T859
Test name
Test status
Simulation time 944781906 ps
CPU time 6.89 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:27:39 PM PDT 24
Peak memory 204904 kb
Host smart-cacfdba6-a760-4aab-988d-fed570265b30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311320192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2311320192
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1353722446
Short name T810
Test name
Test status
Simulation time 22396378060 ps
CPU time 4.79 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:27:37 PM PDT 24
Peak memory 203880 kb
Host smart-a04de90d-8af2-4e4a-ab6a-1d8a57897895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353722446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1353722446
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1404224426
Short name T1061
Test name
Test status
Simulation time 13615725840 ps
CPU time 176.7 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:30:29 PM PDT 24
Peak memory 1861668 kb
Host smart-e3784f61-5512-4588-b094-2413a644dfa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404224426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1404224426
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1738352239
Short name T766
Test name
Test status
Simulation time 5604565646 ps
CPU time 7.38 seconds
Started Mar 28 03:27:33 PM PDT 24
Finished Mar 28 03:27:40 PM PDT 24
Peak memory 220120 kb
Host smart-1770102f-610d-4169-815c-3a71499f1fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738352239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1738352239
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1799353077
Short name T1050
Test name
Test status
Simulation time 37514149 ps
CPU time 0.66 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:27:56 PM PDT 24
Peak memory 203668 kb
Host smart-b2a6edee-9eb9-422c-88b0-19c4c3abb43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799353077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1799353077
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2821120205
Short name T367
Test name
Test status
Simulation time 68569687 ps
CPU time 1.23 seconds
Started Mar 28 03:27:51 PM PDT 24
Finished Mar 28 03:27:52 PM PDT 24
Peak memory 212028 kb
Host smart-21ce3600-2c57-4e85-95f1-fc89ac8bc57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821120205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2821120205
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.924016591
Short name T976
Test name
Test status
Simulation time 365447675 ps
CPU time 8.35 seconds
Started Mar 28 03:27:34 PM PDT 24
Finished Mar 28 03:27:43 PM PDT 24
Peak memory 279508 kb
Host smart-11bd9e6d-beac-43f0-931e-794a709c5800
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924016591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.924016591
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3119748762
Short name T228
Test name
Test status
Simulation time 2677711503 ps
CPU time 42.45 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:28:35 PM PDT 24
Peak memory 531196 kb
Host smart-6c82a724-95d0-4a2e-a72e-c0e1e2a98b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119748762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3119748762
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1856870972
Short name T820
Test name
Test status
Simulation time 5701054652 ps
CPU time 37.8 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:28:09 PM PDT 24
Peak memory 528604 kb
Host smart-437ebfec-b83a-4d75-8ee0-34f14013aa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856870972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1856870972
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3990472673
Short name T168
Test name
Test status
Simulation time 93406325 ps
CPU time 0.9 seconds
Started Mar 28 03:27:31 PM PDT 24
Finished Mar 28 03:27:32 PM PDT 24
Peak memory 203704 kb
Host smart-62ac4c9d-9a0a-46a3-9414-748bf3cdc0d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990472673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3990472673
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.990446482
Short name T893
Test name
Test status
Simulation time 384717193 ps
CPU time 8.21 seconds
Started Mar 28 03:27:29 PM PDT 24
Finished Mar 28 03:27:37 PM PDT 24
Peak memory 203852 kb
Host smart-465f739b-0aa0-4ef4-afc5-2a3207701fe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990446482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
990446482
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1099601136
Short name T149
Test name
Test status
Simulation time 31908266353 ps
CPU time 78.84 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:28:51 PM PDT 24
Peak memory 996772 kb
Host smart-43fd1d38-7a5e-4eff-b7da-495c9cde6b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099601136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1099601136
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.368531028
Short name T770
Test name
Test status
Simulation time 575425141 ps
CPU time 7.45 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:28:02 PM PDT 24
Peak memory 203836 kb
Host smart-b76181be-a8b1-4faf-bd90-f662a275f076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368531028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.368531028
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2581298858
Short name T31
Test name
Test status
Simulation time 5717385051 ps
CPU time 29.17 seconds
Started Mar 28 03:28:24 PM PDT 24
Finished Mar 28 03:28:54 PM PDT 24
Peak memory 422904 kb
Host smart-bbe09647-d770-45e6-b9e6-84f1ab13a657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581298858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2581298858
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.3256634117
Short name T655
Test name
Test status
Simulation time 19335472 ps
CPU time 0.64 seconds
Started Mar 28 03:27:32 PM PDT 24
Finished Mar 28 03:27:33 PM PDT 24
Peak memory 203540 kb
Host smart-62331071-933b-40d8-bed0-920351b29fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256634117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3256634117
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1589291937
Short name T991
Test name
Test status
Simulation time 7551268202 ps
CPU time 94.11 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:29:27 PM PDT 24
Peak memory 546976 kb
Host smart-0700f163-ebbe-4b74-ad08-9ef4eac41b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589291937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1589291937
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3920407995
Short name T263
Test name
Test status
Simulation time 4293462366 ps
CPU time 51.29 seconds
Started Mar 28 03:27:33 PM PDT 24
Finished Mar 28 03:28:24 PM PDT 24
Peak memory 316764 kb
Host smart-c3f39636-7f96-44f5-813b-9ed5b7534196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920407995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3920407995
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2262587339
Short name T464
Test name
Test status
Simulation time 10727260255 ps
CPU time 3.67 seconds
Started Mar 28 03:27:51 PM PDT 24
Finished Mar 28 03:27:55 PM PDT 24
Peak memory 203876 kb
Host smart-e09be160-5e25-4713-b352-161a2a611d01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262587339 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2262587339
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.1822586382
Short name T67
Test name
Test status
Simulation time 10049240588 ps
CPU time 65.29 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:29:00 PM PDT 24
Peak memory 493940 kb
Host smart-69c85485-fac9-4c7c-ad11-be50b96c4997
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822586382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.1822586382
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3885443658
Short name T569
Test name
Test status
Simulation time 10133847493 ps
CPU time 6.93 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 252572 kb
Host smart-55a4ed39-6223-412a-87b7-3abca51e4c66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885443658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3885443658
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2911844473
Short name T1149
Test name
Test status
Simulation time 1566072041 ps
CPU time 1.85 seconds
Started Mar 28 03:27:58 PM PDT 24
Finished Mar 28 03:28:00 PM PDT 24
Peak memory 203808 kb
Host smart-6fafc3a2-061f-4258-abbe-b33e964449b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911844473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2911844473
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2557363878
Short name T612
Test name
Test status
Simulation time 18142024054 ps
CPU time 6.33 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 214860 kb
Host smart-2e84c8b0-e6e7-4f92-8207-9b832bb6391f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557363878 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2557363878
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2500440587
Short name T378
Test name
Test status
Simulation time 4763550394 ps
CPU time 15.8 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:28:09 PM PDT 24
Peak memory 203872 kb
Host smart-0bb7d163-a90d-402b-b36d-99fc35f1db27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500440587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2500440587
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.1699593396
Short name T20
Test name
Test status
Simulation time 34673213204 ps
CPU time 37.12 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:28:29 PM PDT 24
Peak memory 249416 kb
Host smart-631d69a3-8285-4065-a7f9-eb0ae36ff22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699593396 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.1699593396
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3616535977
Short name T247
Test name
Test status
Simulation time 3492972124 ps
CPU time 16.51 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:28:10 PM PDT 24
Peak memory 213460 kb
Host smart-e845a10d-b230-4a08-a475-740dfc7e04ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616535977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3616535977
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1473514189
Short name T842
Test name
Test status
Simulation time 1441068242 ps
CPU time 7.05 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 212036 kb
Host smart-37fb4825-d768-440c-bcec-11a229be39fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473514189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1473514189
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.470092462
Short name T1013
Test name
Test status
Simulation time 27124759 ps
CPU time 0.62 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:27:54 PM PDT 24
Peak memory 203544 kb
Host smart-228345e0-7bb5-4318-b764-987632c5b1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470092462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.470092462
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.516432217
Short name T539
Test name
Test status
Simulation time 79880515 ps
CPU time 1.55 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:27:56 PM PDT 24
Peak memory 212016 kb
Host smart-d42473fd-eeda-45fb-a305-41b78a1da472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516432217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.516432217
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2488587017
Short name T677
Test name
Test status
Simulation time 1821717799 ps
CPU time 12.39 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:28:07 PM PDT 24
Peak memory 245360 kb
Host smart-676e69b7-1755-4bff-849a-c86ace25a118
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488587017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2488587017
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2346096886
Short name T1098
Test name
Test status
Simulation time 3574120941 ps
CPU time 110.28 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:29:42 PM PDT 24
Peak memory 536220 kb
Host smart-892b3cb5-bf9c-4b8e-9d99-ccc4a65439ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346096886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2346096886
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3652043847
Short name T1092
Test name
Test status
Simulation time 1308268918 ps
CPU time 36.86 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:28:29 PM PDT 24
Peak memory 522136 kb
Host smart-9ed15792-8798-43b3-a06d-d9f03e424cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652043847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3652043847
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1071634779
Short name T260
Test name
Test status
Simulation time 197240348 ps
CPU time 1.05 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:27:54 PM PDT 24
Peak memory 203824 kb
Host smart-210a638b-97de-4fff-bfdb-65a83d024ebd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071634779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1071634779
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.4260101765
Short name T700
Test name
Test status
Simulation time 135106397 ps
CPU time 6.52 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 203856 kb
Host smart-2af7e214-1316-4f6d-b8d9-8a52976498e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260101765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.4260101765
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.84094539
Short name T825
Test name
Test status
Simulation time 8487209947 ps
CPU time 138.93 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:30:13 PM PDT 24
Peak memory 1210840 kb
Host smart-b604df33-fd25-46df-b896-f5ec1b38258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84094539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.84094539
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1923220694
Short name T478
Test name
Test status
Simulation time 1087965819 ps
CPU time 3.98 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:27:57 PM PDT 24
Peak memory 203800 kb
Host smart-d97984b5-b064-4363-a23a-affb7757b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923220694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1923220694
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1377564824
Short name T788
Test name
Test status
Simulation time 1702621380 ps
CPU time 29.57 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:24 PM PDT 24
Peak memory 398628 kb
Host smart-85ddc8a3-f6b4-4786-beae-2b037a36ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377564824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1377564824
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2832115317
Short name T506
Test name
Test status
Simulation time 19416070 ps
CPU time 0.66 seconds
Started Mar 28 03:27:51 PM PDT 24
Finished Mar 28 03:27:52 PM PDT 24
Peak memory 203552 kb
Host smart-6efb10e6-3540-4f0c-a51b-2edd4e7caa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832115317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2832115317
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1089050892
Short name T529
Test name
Test status
Simulation time 28659767051 ps
CPU time 391.9 seconds
Started Mar 28 03:27:57 PM PDT 24
Finished Mar 28 03:34:30 PM PDT 24
Peak memory 203808 kb
Host smart-2945ca9e-7fa8-49c2-8dbf-b0b59c0e5b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089050892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1089050892
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1299621638
Short name T852
Test name
Test status
Simulation time 1353432469 ps
CPU time 74.38 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:29:08 PM PDT 24
Peak memory 402648 kb
Host smart-45ebfdcd-4cda-4a4e-b4f1-63ff99be40f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299621638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1299621638
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1551137971
Short name T34
Test name
Test status
Simulation time 2241947642 ps
CPU time 2.89 seconds
Started Mar 28 03:27:50 PM PDT 24
Finished Mar 28 03:27:53 PM PDT 24
Peak memory 203884 kb
Host smart-bb6a3f69-a62a-4878-b016-4fc80c7026f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551137971 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1551137971
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.2542153861
Short name T78
Test name
Test status
Simulation time 10041224273 ps
CPU time 66.32 seconds
Started Mar 28 03:27:51 PM PDT 24
Finished Mar 28 03:28:57 PM PDT 24
Peak memory 571008 kb
Host smart-8660e209-f88b-4370-adc1-c06e6d300e36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542153861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.2542153861
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3119597684
Short name T301
Test name
Test status
Simulation time 10107240159 ps
CPU time 41.47 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:36 PM PDT 24
Peak memory 515308 kb
Host smart-8858c040-7441-4396-a123-e1edcf6422fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119597684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3119597684
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.373404714
Short name T223
Test name
Test status
Simulation time 1780052156 ps
CPU time 2.57 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:27:54 PM PDT 24
Peak memory 203736 kb
Host smart-82c6ab22-f9c1-4fab-a866-01f67d2a3d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373404714 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.373404714
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1229548673
Short name T619
Test name
Test status
Simulation time 1874027563 ps
CPU time 5.13 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:27:57 PM PDT 24
Peak memory 203804 kb
Host smart-c84e5ae5-257d-4c9f-b91c-11633da63acf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229548673 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1229548673
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2818019566
Short name T525
Test name
Test status
Simulation time 678723368 ps
CPU time 25.19 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:19 PM PDT 24
Peak memory 203784 kb
Host smart-be27127a-2215-4209-8a1a-f145780c3be4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818019566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2818019566
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.169406174
Short name T691
Test name
Test status
Simulation time 2018242234 ps
CPU time 41.49 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:36 PM PDT 24
Peak memory 203772 kb
Host smart-0af4ed62-638b-4e0d-9bcd-855b7d42dcfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169406174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.169406174
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3684087504
Short name T745
Test name
Test status
Simulation time 38352217912 ps
CPU time 690.62 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:39:25 PM PDT 24
Peak memory 3966076 kb
Host smart-af71663a-efa3-47b5-bea7-8589f00d08a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684087504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3684087504
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.3451477219
Short name T1171
Test name
Test status
Simulation time 3951908830 ps
CPU time 8.11 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:02 PM PDT 24
Peak memory 211168 kb
Host smart-447f3fb5-9835-40ed-bfcd-c978e847cafe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451477219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.3451477219
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.545142310
Short name T275
Test name
Test status
Simulation time 51464980 ps
CPU time 0.63 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:27:55 PM PDT 24
Peak memory 203624 kb
Host smart-676512e2-a1f5-47d4-bbe6-b5d12737e82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545142310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.545142310
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3847921903
Short name T1021
Test name
Test status
Simulation time 111030862 ps
CPU time 1.22 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:27:55 PM PDT 24
Peak memory 203844 kb
Host smart-ec07b514-f843-43c4-a961-410a24563399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847921903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3847921903
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.1604995763
Short name T881
Test name
Test status
Simulation time 3429356844 ps
CPU time 17.37 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:28:11 PM PDT 24
Peak memory 242316 kb
Host smart-869a53c3-87b4-4ae2-8ea1-011a68db8186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604995763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.1604995763
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1692482666
Short name T76
Test name
Test status
Simulation time 2694270290 ps
CPU time 150.9 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:30:23 PM PDT 24
Peak memory 641904 kb
Host smart-49ac0441-9dd2-494e-afd3-637aff617040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692482666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1692482666
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.570728030
Short name T305
Test name
Test status
Simulation time 1956860761 ps
CPU time 138.9 seconds
Started Mar 28 03:27:51 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 620072 kb
Host smart-6fce93bd-bab8-4e03-9f80-bed39fd59153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570728030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.570728030
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3060314799
Short name T952
Test name
Test status
Simulation time 903566680 ps
CPU time 0.77 seconds
Started Mar 28 03:27:58 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 203656 kb
Host smart-2f0cc097-9883-46fa-9ee9-13dad7f348c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060314799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3060314799
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3970171529
Short name T946
Test name
Test status
Simulation time 125274301 ps
CPU time 3.86 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 223684 kb
Host smart-06d7c859-1666-40d2-87f1-b5ff72743391
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970171529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3970171529
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2993245756
Short name T236
Test name
Test status
Simulation time 4899811845 ps
CPU time 336.08 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 1235384 kb
Host smart-60c63b97-e2af-4dd5-b2ee-2bdb460174f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993245756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2993245756
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1246897423
Short name T1159
Test name
Test status
Simulation time 773055486 ps
CPU time 6.54 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:28:00 PM PDT 24
Peak memory 203768 kb
Host smart-2282c3ea-7443-400c-bdf5-8325cc00425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246897423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1246897423
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2682702833
Short name T629
Test name
Test status
Simulation time 3519948173 ps
CPU time 46.76 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:41 PM PDT 24
Peak memory 291512 kb
Host smart-b86a32bd-a49f-42d3-b4f2-8aa06def316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682702833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2682702833
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2016461566
Short name T1182
Test name
Test status
Simulation time 18003195 ps
CPU time 0.67 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:27:55 PM PDT 24
Peak memory 203588 kb
Host smart-aebbe786-55b8-4933-a1bc-d45a16eafb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016461566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2016461566
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2789557549
Short name T517
Test name
Test status
Simulation time 2528863837 ps
CPU time 86.48 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:29:21 PM PDT 24
Peak memory 787708 kb
Host smart-3e82b8bf-5005-434f-9acc-79ed9ff770e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789557549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2789557549
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.339707482
Short name T687
Test name
Test status
Simulation time 1009343631 ps
CPU time 17.66 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:28:09 PM PDT 24
Peak memory 342108 kb
Host smart-b7a5c94f-abac-4250-942c-984a791eeb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339707482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.339707482
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1048807071
Short name T660
Test name
Test status
Simulation time 874356000 ps
CPU time 4.54 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 203756 kb
Host smart-da664cdf-a9b0-4321-89cc-5f1810ad4e0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048807071 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1048807071
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.4000224419
Short name T962
Test name
Test status
Simulation time 10079614433 ps
CPU time 73.86 seconds
Started Mar 28 03:27:58 PM PDT 24
Finished Mar 28 03:29:12 PM PDT 24
Peak memory 577904 kb
Host smart-33033508-ad22-42d2-ad7b-44ea57d1d6ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000224419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.4000224419
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2937921441
Short name T77
Test name
Test status
Simulation time 10156038852 ps
CPU time 16.47 seconds
Started Mar 28 03:27:56 PM PDT 24
Finished Mar 28 03:28:12 PM PDT 24
Peak memory 334308 kb
Host smart-d7bda7c1-80ef-4f3e-b718-c00983948aaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937921441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2937921441
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.850550949
Short name T821
Test name
Test status
Simulation time 4023819482 ps
CPU time 2.38 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:27:55 PM PDT 24
Peak memory 203764 kb
Host smart-be593ef5-46b4-4030-b484-53bf8f3bef9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850550949 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.850550949
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.487190828
Short name T244
Test name
Test status
Simulation time 2739193104 ps
CPU time 3.87 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:27:59 PM PDT 24
Peak memory 203872 kb
Host smart-4586156f-2234-4315-b282-09ee947ccdf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487190828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.487190828
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2380965491
Short name T257
Test name
Test status
Simulation time 950114383 ps
CPU time 15.08 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:09 PM PDT 24
Peak memory 203708 kb
Host smart-5fac4461-9346-47ed-ba1f-5d6e52cad77c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380965491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2380965491
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2799298152
Short name T386
Test name
Test status
Simulation time 3071190975 ps
CPU time 5.45 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:28:00 PM PDT 24
Peak memory 204080 kb
Host smart-e4a71b7b-aa15-4d16-b092-1fba4fabac8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799298152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2799298152
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3523256323
Short name T340
Test name
Test status
Simulation time 7664187419 ps
CPU time 4.89 seconds
Started Mar 28 03:27:57 PM PDT 24
Finished Mar 28 03:28:03 PM PDT 24
Peak memory 203784 kb
Host smart-badf3dab-6847-48ab-9f84-99400f711a2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523256323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3523256323
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2996037177
Short name T570
Test name
Test status
Simulation time 7356072472 ps
CPU time 686 seconds
Started Mar 28 03:27:57 PM PDT 24
Finished Mar 28 03:39:24 PM PDT 24
Peak memory 1890060 kb
Host smart-c4802497-bc0c-4960-bb49-7263cd199b93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996037177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2996037177
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2990757490
Short name T598
Test name
Test status
Simulation time 1480671444 ps
CPU time 7.75 seconds
Started Mar 28 03:27:58 PM PDT 24
Finished Mar 28 03:28:06 PM PDT 24
Peak memory 216460 kb
Host smart-70a34c9c-4d58-468a-b9b8-b742ac128503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990757490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2990757490
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3074563304
Short name T642
Test name
Test status
Simulation time 40713719 ps
CPU time 0.64 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:28:09 PM PDT 24
Peak memory 203692 kb
Host smart-79da8fff-9100-440e-99ee-b0208e41545f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074563304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3074563304
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.4136573233
Short name T741
Test name
Test status
Simulation time 381316545 ps
CPU time 1.28 seconds
Started Mar 28 03:28:08 PM PDT 24
Finished Mar 28 03:28:09 PM PDT 24
Peak memory 212104 kb
Host smart-432750cc-5190-4f1a-8c78-f0a2db49f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136573233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4136573233
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.49884179
Short name T559
Test name
Test status
Simulation time 960387814 ps
CPU time 5.51 seconds
Started Mar 28 03:27:54 PM PDT 24
Finished Mar 28 03:28:00 PM PDT 24
Peak memory 251852 kb
Host smart-15f6aa76-e2e2-412e-b782-b2a508c47b4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49884179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty
.49884179
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2990693200
Short name T56
Test name
Test status
Simulation time 5273843439 ps
CPU time 83.59 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:29:19 PM PDT 24
Peak memory 517816 kb
Host smart-ffa93fd0-b1e9-4f9d-a8a9-b1ce5a4c64f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990693200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2990693200
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1660623461
Short name T1112
Test name
Test status
Simulation time 1515996162 ps
CPU time 47.94 seconds
Started Mar 28 03:27:56 PM PDT 24
Finished Mar 28 03:28:44 PM PDT 24
Peak memory 538420 kb
Host smart-ca02d836-c8b4-4f8f-91ef-cd2a5398fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660623461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1660623461
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1964075297
Short name T203
Test name
Test status
Simulation time 465070388 ps
CPU time 1.12 seconds
Started Mar 28 03:27:53 PM PDT 24
Finished Mar 28 03:27:54 PM PDT 24
Peak memory 203764 kb
Host smart-2b2ecdb5-158c-400f-a936-485cd5de5ead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964075297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1964075297
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.975705931
Short name T765
Test name
Test status
Simulation time 342675736 ps
CPU time 5.1 seconds
Started Mar 28 03:27:52 PM PDT 24
Finished Mar 28 03:27:57 PM PDT 24
Peak memory 235368 kb
Host smart-97a2accd-2cef-453c-80a6-c96cfb05c249
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975705931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
975705931
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.965627115
Short name T148
Test name
Test status
Simulation time 3648359863 ps
CPU time 46.27 seconds
Started Mar 28 03:27:56 PM PDT 24
Finished Mar 28 03:28:42 PM PDT 24
Peak memory 724392 kb
Host smart-bbf78f1c-eafe-4c76-8e34-fd08818a42c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965627115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.965627115
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3233889712
Short name T105
Test name
Test status
Simulation time 1758435023 ps
CPU time 5.77 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:28:15 PM PDT 24
Peak memory 203828 kb
Host smart-553d95bc-fe36-4982-baf1-2171c6a0e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233889712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3233889712
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.751816363
Short name T715
Test name
Test status
Simulation time 12105640989 ps
CPU time 27.64 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:38 PM PDT 24
Peak memory 380252 kb
Host smart-ec52e214-30aa-4678-9556-83b1ef2c7de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751816363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.751816363
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3118165727
Short name T179
Test name
Test status
Simulation time 64335502 ps
CPU time 0.7 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:27:56 PM PDT 24
Peak memory 203520 kb
Host smart-a094378d-d9e9-4cad-96c1-a417a3343e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118165727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3118165727
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.528274294
Short name T544
Test name
Test status
Simulation time 2095501218 ps
CPU time 46.71 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:28:42 PM PDT 24
Peak memory 292392 kb
Host smart-fc939e6a-fb9a-4239-870a-a7ab97c5153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528274294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.528274294
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3582930394
Short name T924
Test name
Test status
Simulation time 1060720912 ps
CPU time 46.2 seconds
Started Mar 28 03:27:55 PM PDT 24
Finished Mar 28 03:28:41 PM PDT 24
Peak memory 314968 kb
Host smart-0238b6ef-65c6-4f8e-a3e2-6d703a6831df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582930394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3582930394
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.1345447184
Short name T669
Test name
Test status
Simulation time 843342676 ps
CPU time 3.88 seconds
Started Mar 28 03:28:15 PM PDT 24
Finished Mar 28 03:28:20 PM PDT 24
Peak memory 203880 kb
Host smart-2c10b08c-d1ef-47f0-9725-8f2dfd1c9c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345447184 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.1345447184
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1736639040
Short name T911
Test name
Test status
Simulation time 10050690099 ps
CPU time 84.72 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:29:35 PM PDT 24
Peak memory 543724 kb
Host smart-2837d457-63df-46e4-bb21-c0f30a8452c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736639040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1736639040
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.1145854659
Short name T735
Test name
Test status
Simulation time 10032080724 ps
CPU time 113.83 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:30:06 PM PDT 24
Peak memory 756592 kb
Host smart-0c8444fc-e220-41c1-af0e-95f1be55641f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145854659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.1145854659
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.4172550545
Short name T371
Test name
Test status
Simulation time 1406429959 ps
CPU time 2.1 seconds
Started Mar 28 03:28:08 PM PDT 24
Finished Mar 28 03:28:11 PM PDT 24
Peak memory 203848 kb
Host smart-4a568cd3-3434-446d-b50f-371a88042cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172550545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.4172550545
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1706685282
Short name T572
Test name
Test status
Simulation time 4270445776 ps
CPU time 5.34 seconds
Started Mar 28 03:28:15 PM PDT 24
Finished Mar 28 03:28:21 PM PDT 24
Peak memory 209288 kb
Host smart-21a5eacb-ef1e-473d-8447-331ceb5151c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706685282 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1706685282
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2481513013
Short name T1
Test name
Test status
Simulation time 5412700728 ps
CPU time 3.34 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:14 PM PDT 24
Peak memory 203872 kb
Host smart-a2c83a2d-0612-4f0d-b93c-b6ae4a3455b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481513013 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2481513013
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.709682854
Short name T5
Test name
Test status
Simulation time 827687039 ps
CPU time 13.31 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:28:23 PM PDT 24
Peak memory 203788 kb
Host smart-1e104c87-98b1-4677-896f-6d0941689f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709682854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.709682854
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3297142761
Short name T1048
Test name
Test status
Simulation time 348773585 ps
CPU time 14.83 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:26 PM PDT 24
Peak memory 203768 kb
Host smart-a3b0f986-a2d3-480b-9ff4-ce324f4b2caa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297142761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3297142761
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3406335058
Short name T311
Test name
Test status
Simulation time 5369344580 ps
CPU time 7.59 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:18 PM PDT 24
Peak memory 220068 kb
Host smart-16aee1ab-1df9-4149-b173-ccdb3468bc1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406335058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3406335058
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.3713207083
Short name T37
Test name
Test status
Simulation time 853696095 ps
CPU time 5.79 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:28:15 PM PDT 24
Peak memory 203684 kb
Host smart-fdec45b0-1117-4b5e-9c84-30834f850c42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713207083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.3713207083
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3475993002
Short name T450
Test name
Test status
Simulation time 43600300 ps
CPU time 0.61 seconds
Started Mar 28 03:28:13 PM PDT 24
Finished Mar 28 03:28:14 PM PDT 24
Peak memory 203700 kb
Host smart-3819382a-ce0d-41e6-930c-e9d3ea3ec000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475993002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3475993002
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1684003602
Short name T493
Test name
Test status
Simulation time 785300156 ps
CPU time 1.59 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:28:13 PM PDT 24
Peak memory 212044 kb
Host smart-a7c342c8-5d98-46a3-85ee-502b73e99452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684003602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1684003602
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.189580215
Short name T500
Test name
Test status
Simulation time 319382481 ps
CPU time 6.62 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:28:16 PM PDT 24
Peak memory 268868 kb
Host smart-27f988e0-e920-4b53-a432-c093a85213e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189580215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empt
y.189580215
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3027222156
Short name T293
Test name
Test status
Simulation time 2349023298 ps
CPU time 57.24 seconds
Started Mar 28 03:28:13 PM PDT 24
Finished Mar 28 03:29:11 PM PDT 24
Peak memory 484504 kb
Host smart-b9e74b2c-5d9b-4f21-bd8c-4cbd6e81620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027222156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3027222156
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3500693071
Short name T527
Test name
Test status
Simulation time 1406276282 ps
CPU time 86.15 seconds
Started Mar 28 03:28:08 PM PDT 24
Finished Mar 28 03:29:35 PM PDT 24
Peak memory 497892 kb
Host smart-fafaea12-2aba-42a9-be67-e391921b8eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500693071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3500693071
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.467058364
Short name T1069
Test name
Test status
Simulation time 131609036 ps
CPU time 1.06 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:28:11 PM PDT 24
Peak memory 203736 kb
Host smart-b7d07ac3-3ab5-469a-b91f-80598632946c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467058364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.467058364
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2272269465
Short name T440
Test name
Test status
Simulation time 114328829 ps
CPU time 2.77 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:28:14 PM PDT 24
Peak memory 203788 kb
Host smart-e33d9e30-0152-4045-83a9-266f910aef02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272269465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2272269465
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2813884488
Short name T1065
Test name
Test status
Simulation time 3790862467 ps
CPU time 294.81 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:33:04 PM PDT 24
Peak memory 1144112 kb
Host smart-79d5b468-09e0-46a8-921c-e70ae5507066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813884488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2813884488
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2788975695
Short name T25
Test name
Test status
Simulation time 526555021 ps
CPU time 8.58 seconds
Started Mar 28 03:28:12 PM PDT 24
Finished Mar 28 03:28:21 PM PDT 24
Peak memory 203864 kb
Host smart-4a2fede2-296f-47bb-a1b8-095636947913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788975695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2788975695
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1493847273
Short name T463
Test name
Test status
Simulation time 3507544767 ps
CPU time 28.26 seconds
Started Mar 28 03:28:14 PM PDT 24
Finished Mar 28 03:28:43 PM PDT 24
Peak memory 327272 kb
Host smart-78e67683-fe10-497e-bae9-2cf64287c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493847273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1493847273
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.800470820
Short name T12
Test name
Test status
Simulation time 50342803 ps
CPU time 0.65 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:28:12 PM PDT 24
Peak memory 203552 kb
Host smart-0c899c6c-5ba3-4169-ae88-feed2ef8c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800470820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.800470820
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1043023967
Short name T1119
Test name
Test status
Simulation time 1262696072 ps
CPU time 20.92 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:31 PM PDT 24
Peak memory 306132 kb
Host smart-f0ba4346-8a0d-4a09-969d-a3e6f5ac4adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043023967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1043023967
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3919107371
Short name T165
Test name
Test status
Simulation time 43169589863 ps
CPU time 571.39 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:37:43 PM PDT 24
Peak memory 1912268 kb
Host smart-5657e761-6532-42fb-bb2c-d8e422792863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919107371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3919107371
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.4099852981
Short name T580
Test name
Test status
Simulation time 2534355081 ps
CPU time 3.06 seconds
Started Mar 28 03:28:14 PM PDT 24
Finished Mar 28 03:28:17 PM PDT 24
Peak memory 203888 kb
Host smart-db6b67a4-e61d-4646-8e77-51e8a610b685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099852981 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.4099852981
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.603293758
Short name T17
Test name
Test status
Simulation time 10349675012 ps
CPU time 12.18 seconds
Started Mar 28 03:28:12 PM PDT 24
Finished Mar 28 03:28:24 PM PDT 24
Peak memory 258148 kb
Host smart-7b2832cf-bf2d-436a-bcd9-22c96a2df14f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603293758 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.603293758
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.801631041
Short name T312
Test name
Test status
Simulation time 3764605672 ps
CPU time 2.17 seconds
Started Mar 28 03:28:12 PM PDT 24
Finished Mar 28 03:28:15 PM PDT 24
Peak memory 203896 kb
Host smart-e6c830be-9f64-41fb-bf00-55af6b4fe4c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801631041 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_hrst.801631041
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3871049820
Short name T8
Test name
Test status
Simulation time 1022954102 ps
CPU time 5.81 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:16 PM PDT 24
Peak memory 207256 kb
Host smart-ef823d3b-1e78-49b9-9060-7f657187fb76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871049820 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3871049820
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3702083459
Short name T1006
Test name
Test status
Simulation time 3818760254 ps
CPU time 11.21 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:21 PM PDT 24
Peak memory 203816 kb
Host smart-4ae30028-5081-43ed-acb7-8e1aaab12908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702083459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3702083459
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3560618923
Short name T501
Test name
Test status
Simulation time 1087662913 ps
CPU time 19.06 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:30 PM PDT 24
Peak memory 225856 kb
Host smart-096568d5-8be1-4592-889e-0a1eb2d91687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560618923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3560618923
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3550136964
Short name T258
Test name
Test status
Simulation time 17831817932 ps
CPU time 75.91 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:29:28 PM PDT 24
Peak memory 821804 kb
Host smart-d55fb519-40dd-415c-b8fc-bb18ba7ac0b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550136964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3550136964
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1698089475
Short name T833
Test name
Test status
Simulation time 2833931002 ps
CPU time 6.35 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:28:18 PM PDT 24
Peak memory 203872 kb
Host smart-fd8f3078-e1af-4de0-ae35-c5cf8aca49ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698089475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1698089475
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2719235342
Short name T518
Test name
Test status
Simulation time 55372922 ps
CPU time 0.63 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:28:37 PM PDT 24
Peak memory 203696 kb
Host smart-1fd7f005-8c2b-4f43-add4-6365649f2c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719235342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2719235342
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3363941362
Short name T828
Test name
Test status
Simulation time 46085476 ps
CPU time 1.18 seconds
Started Mar 28 03:28:13 PM PDT 24
Finished Mar 28 03:28:16 PM PDT 24
Peak memory 203824 kb
Host smart-849c0b07-2e53-4771-a108-bdf71027cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363941362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3363941362
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1877643664
Short name T336
Test name
Test status
Simulation time 6387648414 ps
CPU time 18.57 seconds
Started Mar 28 03:28:12 PM PDT 24
Finished Mar 28 03:28:32 PM PDT 24
Peak memory 276004 kb
Host smart-76bf2094-8e2c-47b6-9b42-e71ca402b443
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877643664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1877643664
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3907501315
Short name T733
Test name
Test status
Simulation time 20272041105 ps
CPU time 97.66 seconds
Started Mar 28 03:28:18 PM PDT 24
Finished Mar 28 03:29:55 PM PDT 24
Peak memory 559004 kb
Host smart-e79bb905-a4c0-4b36-a0ba-e15213012d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907501315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3907501315
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.649771163
Short name T902
Test name
Test status
Simulation time 1470418341 ps
CPU time 35.98 seconds
Started Mar 28 03:28:11 PM PDT 24
Finished Mar 28 03:28:47 PM PDT 24
Peak memory 513640 kb
Host smart-a3f25782-5c07-4b0b-8b48-52eabf96775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649771163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.649771163
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2067818433
Short name T1055
Test name
Test status
Simulation time 154500734 ps
CPU time 0.86 seconds
Started Mar 28 03:28:10 PM PDT 24
Finished Mar 28 03:28:12 PM PDT 24
Peak memory 203728 kb
Host smart-a3d119e3-17bf-43bb-9dbc-07a0c1d1332c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067818433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2067818433
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1807178593
Short name T596
Test name
Test status
Simulation time 790191246 ps
CPU time 12.01 seconds
Started Mar 28 03:28:13 PM PDT 24
Finished Mar 28 03:28:25 PM PDT 24
Peak memory 245012 kb
Host smart-243b67c0-5674-49d4-9ed4-fcd31e3e21f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807178593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1807178593
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3298642667
Short name T1104
Test name
Test status
Simulation time 13839788330 ps
CPU time 254.14 seconds
Started Mar 28 03:28:13 PM PDT 24
Finished Mar 28 03:32:28 PM PDT 24
Peak memory 1063524 kb
Host smart-3032e1f8-11ec-4577-8672-b7921aa51706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298642667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3298642667
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3589136912
Short name T289
Test name
Test status
Simulation time 650424993 ps
CPU time 13.15 seconds
Started Mar 28 03:28:35 PM PDT 24
Finished Mar 28 03:28:49 PM PDT 24
Peak memory 203880 kb
Host smart-48ca316a-9ff2-4bb4-a2ed-769a1b85e128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589136912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3589136912
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.480425028
Short name T341
Test name
Test status
Simulation time 1905819223 ps
CPU time 32.22 seconds
Started Mar 28 03:28:38 PM PDT 24
Finished Mar 28 03:29:11 PM PDT 24
Peak memory 435240 kb
Host smart-f7ba72ab-426c-44c6-9564-959f56c79d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480425028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.480425028
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.792872703
Short name T1117
Test name
Test status
Simulation time 30666079 ps
CPU time 0.67 seconds
Started Mar 28 03:28:14 PM PDT 24
Finished Mar 28 03:28:16 PM PDT 24
Peak memory 203576 kb
Host smart-e28b1690-8e88-488e-87fc-aed60fe47145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792872703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.792872703
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1521286534
Short name T536
Test name
Test status
Simulation time 6637343498 ps
CPU time 29.4 seconds
Started Mar 28 03:28:13 PM PDT 24
Finished Mar 28 03:28:44 PM PDT 24
Peak memory 232668 kb
Host smart-4fc89f52-5a68-4fd8-a494-3cd5318a097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521286534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1521286534
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.209081800
Short name T848
Test name
Test status
Simulation time 13943083115 ps
CPU time 27.28 seconds
Started Mar 28 03:28:09 PM PDT 24
Finished Mar 28 03:28:37 PM PDT 24
Peak memory 393632 kb
Host smart-cf720419-f367-466d-a27d-4095c5c02132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209081800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.209081800
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.52283683
Short name T595
Test name
Test status
Simulation time 1723463123 ps
CPU time 4.03 seconds
Started Mar 28 03:28:39 PM PDT 24
Finished Mar 28 03:28:43 PM PDT 24
Peak memory 203440 kb
Host smart-774689a8-aede-4608-88e0-64586b3db862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52283683 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_bad_addr.52283683
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2994598197
Short name T998
Test name
Test status
Simulation time 10067902259 ps
CPU time 81.17 seconds
Started Mar 28 03:28:37 PM PDT 24
Finished Mar 28 03:29:58 PM PDT 24
Peak memory 623256 kb
Host smart-f04568e0-11e7-4270-a98c-184f6762d724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994598197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2994598197
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3395664263
Short name T86
Test name
Test status
Simulation time 10049203740 ps
CPU time 86.83 seconds
Started Mar 28 03:28:35 PM PDT 24
Finished Mar 28 03:30:02 PM PDT 24
Peak memory 624948 kb
Host smart-7178f462-099c-4a01-9342-78a08ed37e57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395664263 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3395664263
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3296224836
Short name T698
Test name
Test status
Simulation time 5618979496 ps
CPU time 2.59 seconds
Started Mar 28 03:28:39 PM PDT 24
Finished Mar 28 03:28:41 PM PDT 24
Peak memory 203684 kb
Host smart-0ce4cbd7-2aeb-4e0e-986a-a66c4da99586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296224836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3296224836
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.960027506
Short name T495
Test name
Test status
Simulation time 761923547 ps
CPU time 4.27 seconds
Started Mar 28 03:28:16 PM PDT 24
Finished Mar 28 03:28:20 PM PDT 24
Peak memory 207844 kb
Host smart-9b499775-e8d7-420d-8304-bbc0f339cb5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960027506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.960027506
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2694043313
Short name T350
Test name
Test status
Simulation time 4237660191 ps
CPU time 10.07 seconds
Started Mar 28 03:28:16 PM PDT 24
Finished Mar 28 03:28:26 PM PDT 24
Peak memory 203912 kb
Host smart-b645a736-e3bb-4a2e-bf0b-a02d7d769da4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694043313 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2694043313
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.417240207
Short name T1134
Test name
Test status
Simulation time 4173051653 ps
CPU time 14.68 seconds
Started Mar 28 03:28:16 PM PDT 24
Finished Mar 28 03:28:31 PM PDT 24
Peak memory 203940 kb
Host smart-46933063-ae10-4231-941f-5ccb8b6145c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417240207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.417240207
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.750925275
Short name T591
Test name
Test status
Simulation time 1219294080 ps
CPU time 17.62 seconds
Started Mar 28 03:28:17 PM PDT 24
Finished Mar 28 03:28:35 PM PDT 24
Peak memory 218472 kb
Host smart-a7b9e08f-98fb-454f-8818-555c57ec3685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750925275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.750925275
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3677361917
Short name T1114
Test name
Test status
Simulation time 2302329608 ps
CPU time 6.76 seconds
Started Mar 28 03:28:14 PM PDT 24
Finished Mar 28 03:28:22 PM PDT 24
Peak memory 210068 kb
Host smart-0bfcb13b-5ab4-4f15-b50c-6a0ee1b67ace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677361917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3677361917
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1026625028
Short name T1116
Test name
Test status
Simulation time 59720016 ps
CPU time 0.59 seconds
Started Mar 28 03:28:32 PM PDT 24
Finished Mar 28 03:28:33 PM PDT 24
Peak memory 203552 kb
Host smart-59ebdd9c-523b-4828-a23e-34d49ebbff46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026625028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1026625028
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2352854680
Short name T38
Test name
Test status
Simulation time 301628790 ps
CPU time 1.42 seconds
Started Mar 28 03:28:43 PM PDT 24
Finished Mar 28 03:28:45 PM PDT 24
Peak memory 212040 kb
Host smart-4bc0c110-42fe-4dab-a506-5f8c1bd819a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352854680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2352854680
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2492463053
Short name T618
Test name
Test status
Simulation time 683692070 ps
CPU time 5.67 seconds
Started Mar 28 03:28:34 PM PDT 24
Finished Mar 28 03:28:40 PM PDT 24
Peak memory 267080 kb
Host smart-59f3afaa-c1f7-4d8f-8122-2cd37d2137bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492463053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2492463053
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.405382850
Short name T187
Test name
Test status
Simulation time 2410076473 ps
CPU time 33.26 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:29:10 PM PDT 24
Peak memory 332288 kb
Host smart-3099d2f1-8a12-4e83-8a5d-2bfe5349610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405382850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.405382850
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2970718022
Short name T460
Test name
Test status
Simulation time 2343200911 ps
CPU time 42.33 seconds
Started Mar 28 03:28:35 PM PDT 24
Finished Mar 28 03:29:18 PM PDT 24
Peak memory 512812 kb
Host smart-a5de6cde-2965-4a1b-aa99-bb17b4f7cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970718022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2970718022
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1980912757
Short name T1045
Test name
Test status
Simulation time 1269809086 ps
CPU time 1.02 seconds
Started Mar 28 03:28:40 PM PDT 24
Finished Mar 28 03:28:42 PM PDT 24
Peak memory 203772 kb
Host smart-e196792a-7ef1-4e29-8dc6-c059de8b2768
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980912757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1980912757
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.604912503
Short name T918
Test name
Test status
Simulation time 165168200 ps
CPU time 8.68 seconds
Started Mar 28 03:28:43 PM PDT 24
Finished Mar 28 03:28:52 PM PDT 24
Peak memory 203884 kb
Host smart-aab7d166-0ac2-4041-9821-51546d3046fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604912503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
604912503
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1958369975
Short name T155
Test name
Test status
Simulation time 16087092230 ps
CPU time 99.87 seconds
Started Mar 28 03:28:43 PM PDT 24
Finished Mar 28 03:30:23 PM PDT 24
Peak memory 1138716 kb
Host smart-01396078-68c2-4de0-a0aa-f53b2afe3b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958369975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1958369975
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.147136940
Short name T211
Test name
Test status
Simulation time 276642236 ps
CPU time 4.61 seconds
Started Mar 28 03:28:41 PM PDT 24
Finished Mar 28 03:28:46 PM PDT 24
Peak memory 203820 kb
Host smart-a375f45b-5d8b-4f14-8b00-532d96eb1591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147136940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.147136940
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1176591123
Short name T252
Test name
Test status
Simulation time 1441491289 ps
CPU time 26.69 seconds
Started Mar 28 03:28:39 PM PDT 24
Finished Mar 28 03:29:07 PM PDT 24
Peak memory 338044 kb
Host smart-e3c3ed11-a454-4d70-ae07-db00a366dbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176591123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1176591123
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.493722474
Short name T243
Test name
Test status
Simulation time 26202030 ps
CPU time 0.65 seconds
Started Mar 28 03:28:40 PM PDT 24
Finished Mar 28 03:28:42 PM PDT 24
Peak memory 203588 kb
Host smart-39f8d5f0-e94b-4927-a418-bd01512f2fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493722474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.493722474
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2544843830
Short name T824
Test name
Test status
Simulation time 5072092248 ps
CPU time 340.54 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:34:17 PM PDT 24
Peak memory 780052 kb
Host smart-59cff2e4-ec4d-4b96-9951-157ce3cc8ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544843830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2544843830
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3700187523
Short name T1184
Test name
Test status
Simulation time 5760892701 ps
CPU time 17.19 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:28:54 PM PDT 24
Peak memory 301368 kb
Host smart-cd7d5934-13ec-4b46-b586-165637acad42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700187523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3700187523
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3592892945
Short name T103
Test name
Test status
Simulation time 1962395440 ps
CPU time 2.91 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:28:39 PM PDT 24
Peak memory 211940 kb
Host smart-93bdf210-445c-4a33-8842-4060f98fa6ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592892945 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3592892945
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2079288642
Short name T871
Test name
Test status
Simulation time 10438926043 ps
CPU time 12.74 seconds
Started Mar 28 03:28:32 PM PDT 24
Finished Mar 28 03:28:45 PM PDT 24
Peak memory 280268 kb
Host smart-3e9afbde-61cc-4684-9c2f-4ef878da3486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079288642 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2079288642
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.2047818748
Short name T347
Test name
Test status
Simulation time 10048233968 ps
CPU time 126.31 seconds
Started Mar 28 03:28:40 PM PDT 24
Finished Mar 28 03:30:48 PM PDT 24
Peak memory 762188 kb
Host smart-be2c3382-d9f2-4a2e-a67f-6730a442c5c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047818748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.2047818748
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1285963233
Short name T528
Test name
Test status
Simulation time 978679019 ps
CPU time 2.64 seconds
Started Mar 28 03:28:33 PM PDT 24
Finished Mar 28 03:28:36 PM PDT 24
Peak memory 203784 kb
Host smart-ed695da1-4007-470b-9458-b8d4130a46b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285963233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1285963233
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1504927785
Short name T912
Test name
Test status
Simulation time 1241368567 ps
CPU time 5.63 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:51 PM PDT 24
Peak memory 202480 kb
Host smart-d7e5cfa6-4910-43fb-9be1-c5cdc9fc7784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504927785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1504927785
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2345372532
Short name T505
Test name
Test status
Simulation time 2614091840 ps
CPU time 23.16 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:29:00 PM PDT 24
Peak memory 203756 kb
Host smart-8a6a850a-e558-4153-a5b0-c0a4d62175d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345372532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2345372532
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.265789288
Short name T423
Test name
Test status
Simulation time 3315879206 ps
CPU time 13.09 seconds
Started Mar 28 03:28:42 PM PDT 24
Finished Mar 28 03:28:55 PM PDT 24
Peak memory 212704 kb
Host smart-fb9e3e40-feb4-475d-bba4-b51b92ea1ca1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265789288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.265789288
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.928527435
Short name T1089
Test name
Test status
Simulation time 1477123287 ps
CPU time 7.8 seconds
Started Mar 28 03:28:41 PM PDT 24
Finished Mar 28 03:28:49 PM PDT 24
Peak memory 220000 kb
Host smart-4f998997-ae59-4668-8f39-108dcfcf4157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928527435 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.928527435
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.3800321476
Short name T36
Test name
Test status
Simulation time 713929781 ps
CPU time 4.16 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:49 PM PDT 24
Peak memory 202440 kb
Host smart-946cd4df-3ea4-42a3-9edc-9c56e21d9956
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800321476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.i2c_target_unexp_stop.3800321476
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4059342542
Short name T547
Test name
Test status
Simulation time 31673355 ps
CPU time 0.59 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:25:05 PM PDT 24
Peak memory 203668 kb
Host smart-111be964-7f78-4a09-b23f-cefab7678b69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059342542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4059342542
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.205023984
Short name T936
Test name
Test status
Simulation time 400246441 ps
CPU time 1.86 seconds
Started Mar 28 03:25:07 PM PDT 24
Finished Mar 28 03:25:10 PM PDT 24
Peak memory 212012 kb
Host smart-5c5b9ab2-1556-4085-bdd0-7049f278ab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205023984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.205023984
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2940811453
Short name T1194
Test name
Test status
Simulation time 859558289 ps
CPU time 4.1 seconds
Started Mar 28 03:25:07 PM PDT 24
Finished Mar 28 03:25:11 PM PDT 24
Peak memory 244056 kb
Host smart-8a6f285c-f872-46d3-8d11-ff40df5ff052
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940811453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2940811453
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3313479788
Short name T58
Test name
Test status
Simulation time 2039421660 ps
CPU time 149.64 seconds
Started Mar 28 03:25:10 PM PDT 24
Finished Mar 28 03:27:41 PM PDT 24
Peak memory 666872 kb
Host smart-cb4bd919-7afd-4cd6-bd04-d45394b3fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313479788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3313479788
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.4059331330
Short name T379
Test name
Test status
Simulation time 2003663691 ps
CPU time 167.01 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:27:52 PM PDT 24
Peak memory 694904 kb
Host smart-5494c52a-a7ff-4973-a087-63809d5c34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059331330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.4059331330
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2818616172
Short name T686
Test name
Test status
Simulation time 180136283 ps
CPU time 0.84 seconds
Started Mar 28 03:25:06 PM PDT 24
Finished Mar 28 03:25:07 PM PDT 24
Peak memory 203692 kb
Host smart-67ad0f0c-137c-4f69-a539-c3862e1011bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818616172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2818616172
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1885094670
Short name T542
Test name
Test status
Simulation time 174927183 ps
CPU time 5.19 seconds
Started Mar 28 03:25:02 PM PDT 24
Finished Mar 28 03:25:07 PM PDT 24
Peak memory 235520 kb
Host smart-22e218fc-159e-464b-8dac-2b1f30f1a4df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885094670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1885094670
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2814175859
Short name T611
Test name
Test status
Simulation time 4006775101 ps
CPU time 127.28 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:27:13 PM PDT 24
Peak memory 1181024 kb
Host smart-608ae046-db42-48ec-89da-235302720f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814175859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2814175859
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.927666014
Short name T227
Test name
Test status
Simulation time 919912854 ps
CPU time 25.25 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:25:31 PM PDT 24
Peak memory 203772 kb
Host smart-d20d0d38-eccb-42fe-8183-b24402460b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927666014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.927666014
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.881069778
Short name T172
Test name
Test status
Simulation time 29725412280 ps
CPU time 36.41 seconds
Started Mar 28 03:25:09 PM PDT 24
Finished Mar 28 03:25:46 PM PDT 24
Peak memory 441288 kb
Host smart-9607279d-782e-4031-99c5-749c9ba7cd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881069778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.881069778
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2003676385
Short name T722
Test name
Test status
Simulation time 26349724 ps
CPU time 0.68 seconds
Started Mar 28 03:25:02 PM PDT 24
Finished Mar 28 03:25:03 PM PDT 24
Peak memory 203624 kb
Host smart-fc2c12ca-ae5e-4186-b59d-aee1fc366076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003676385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2003676385
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1618226763
Short name T940
Test name
Test status
Simulation time 31581307068 ps
CPU time 1228.8 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:45:35 PM PDT 24
Peak memory 2263972 kb
Host smart-c8b0315c-d4e5-4c34-b4a4-7d575a8aac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618226763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1618226763
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2156935085
Short name T956
Test name
Test status
Simulation time 3755850914 ps
CPU time 14.37 seconds
Started Mar 28 03:25:12 PM PDT 24
Finished Mar 28 03:25:27 PM PDT 24
Peak memory 285228 kb
Host smart-96e63b66-544e-4779-8f32-7cca27f3ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156935085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2156935085
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.188441813
Short name T100
Test name
Test status
Simulation time 131476541 ps
CPU time 0.82 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:25:06 PM PDT 24
Peak memory 221344 kb
Host smart-55c5a2f2-5436-4346-90e0-9c511a2e442d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188441813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.188441813
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1140895934
Short name T300
Test name
Test status
Simulation time 782790350 ps
CPU time 3.76 seconds
Started Mar 28 03:25:14 PM PDT 24
Finished Mar 28 03:25:18 PM PDT 24
Peak memory 211116 kb
Host smart-07d1f068-17b8-41ea-89d1-d327df3957cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140895934 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1140895934
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2853389951
Short name T583
Test name
Test status
Simulation time 10176024757 ps
CPU time 34.53 seconds
Started Mar 28 03:25:15 PM PDT 24
Finished Mar 28 03:25:50 PM PDT 24
Peak memory 408580 kb
Host smart-93698a2b-1959-4971-add8-64ceb66c53aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853389951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2853389951
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.4175514536
Short name T864
Test name
Test status
Simulation time 10196955199 ps
CPU time 34.18 seconds
Started Mar 28 03:25:14 PM PDT 24
Finished Mar 28 03:25:49 PM PDT 24
Peak memory 477612 kb
Host smart-293898dd-fc78-47ba-9712-75232fe60898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175514536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.4175514536
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3322394141
Short name T979
Test name
Test status
Simulation time 7931789643 ps
CPU time 2.82 seconds
Started Mar 28 03:25:15 PM PDT 24
Finished Mar 28 03:25:18 PM PDT 24
Peak memory 203920 kb
Host smart-9736d0f1-dfde-4ff8-91db-2bbf68414b6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322394141 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3322394141
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1629500361
Short name T326
Test name
Test status
Simulation time 17377296559 ps
CPU time 5.48 seconds
Started Mar 28 03:25:15 PM PDT 24
Finished Mar 28 03:25:21 PM PDT 24
Peak memory 220128 kb
Host smart-a5cd80c4-6f89-4d8f-8915-d76cf79e3ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629500361 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1629500361
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.399482241
Short name T330
Test name
Test status
Simulation time 3699226556 ps
CPU time 14.01 seconds
Started Mar 28 03:25:15 PM PDT 24
Finished Mar 28 03:25:29 PM PDT 24
Peak memory 203904 kb
Host smart-db254524-a2f8-4619-bb98-bef2a4933db1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399482241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.399482241
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1492874854
Short name T818
Test name
Test status
Simulation time 1737952534 ps
CPU time 15.5 seconds
Started Mar 28 03:25:03 PM PDT 24
Finished Mar 28 03:25:18 PM PDT 24
Peak memory 208988 kb
Host smart-29fb09eb-6861-4d36-8928-2a0e28799c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492874854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1492874854
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.609911109
Short name T364
Test name
Test status
Simulation time 38918721900 ps
CPU time 2987.03 seconds
Started Mar 28 03:25:08 PM PDT 24
Finished Mar 28 04:14:56 PM PDT 24
Peak memory 4330212 kb
Host smart-25d1b36e-34ac-4fc0-8ed7-c827c294ae0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609911109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.609911109
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2952573
Short name T22
Test name
Test status
Simulation time 2831633792 ps
CPU time 7.41 seconds
Started Mar 28 03:25:05 PM PDT 24
Finished Mar 28 03:25:13 PM PDT 24
Peak memory 220200 kb
Host smart-9d3b73f8-d36b-4b9c-9b0a-5495ce0ff26a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952573 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_timeout.2952573
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.837304382
Short name T411
Test name
Test status
Simulation time 25288647 ps
CPU time 0.62 seconds
Started Mar 28 03:28:38 PM PDT 24
Finished Mar 28 03:28:39 PM PDT 24
Peak memory 203608 kb
Host smart-9b751bbe-103b-46f2-b65a-b8d45cda6cb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837304382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.837304382
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1748706636
Short name T717
Test name
Test status
Simulation time 76466608 ps
CPU time 1.5 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:45 PM PDT 24
Peak memory 212028 kb
Host smart-58b06ffa-445d-440b-b132-fc4a0c8b065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748706636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1748706636
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3389404776
Short name T958
Test name
Test status
Simulation time 573010707 ps
CPU time 14.62 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:28:51 PM PDT 24
Peak memory 261844 kb
Host smart-3acbbeb9-bfc7-40ed-9cc8-9b9c3856de42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389404776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3389404776
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2036525712
Short name T428
Test name
Test status
Simulation time 9107162403 ps
CPU time 62.15 seconds
Started Mar 28 03:28:33 PM PDT 24
Finished Mar 28 03:29:36 PM PDT 24
Peak memory 615200 kb
Host smart-29a77407-5047-4e94-aec0-4a3899ac6de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036525712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2036525712
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2972778486
Short name T602
Test name
Test status
Simulation time 5549888665 ps
CPU time 87.22 seconds
Started Mar 28 03:28:43 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 506176 kb
Host smart-f6faceb7-b8f6-4d28-98c7-2800824f26cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972778486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2972778486
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.336921169
Short name T841
Test name
Test status
Simulation time 558504388 ps
CPU time 1.04 seconds
Started Mar 28 03:28:34 PM PDT 24
Finished Mar 28 03:28:35 PM PDT 24
Peak memory 203696 kb
Host smart-8c3b4bf1-231d-42f9-90a4-b183fec8567f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336921169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.336921169
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2340822299
Short name T9
Test name
Test status
Simulation time 366680274 ps
CPU time 6.25 seconds
Started Mar 28 03:28:43 PM PDT 24
Finished Mar 28 03:28:49 PM PDT 24
Peak memory 218876 kb
Host smart-6b97a0e1-5fd3-40fe-8c3e-6c8b23db451e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340822299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2340822299
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.730341439
Short name T154
Test name
Test status
Simulation time 18495908932 ps
CPU time 124.65 seconds
Started Mar 28 03:28:39 PM PDT 24
Finished Mar 28 03:30:44 PM PDT 24
Peak memory 1326924 kb
Host smart-3823d98c-a88d-4c09-9b09-172ca83f7c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730341439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.730341439
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1607191140
Short name T594
Test name
Test status
Simulation time 3785034345 ps
CPU time 4.74 seconds
Started Mar 28 03:28:42 PM PDT 24
Finished Mar 28 03:28:47 PM PDT 24
Peak memory 203928 kb
Host smart-f40b0227-4383-4328-a05f-1a6af78da82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607191140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1607191140
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.2115086369
Short name T360
Test name
Test status
Simulation time 5163347880 ps
CPU time 18.06 seconds
Started Mar 28 03:28:39 PM PDT 24
Finished Mar 28 03:28:59 PM PDT 24
Peak memory 317392 kb
Host smart-21d1f08b-86e1-46b8-8c54-0ddac008ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115086369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.2115086369
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.4246665879
Short name T651
Test name
Test status
Simulation time 45740425 ps
CPU time 0.68 seconds
Started Mar 28 03:28:35 PM PDT 24
Finished Mar 28 03:28:36 PM PDT 24
Peak memory 203576 kb
Host smart-8a2b257d-04c6-4623-a55b-fde212b0c784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246665879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.4246665879
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.770681310
Short name T433
Test name
Test status
Simulation time 29335711571 ps
CPU time 25.32 seconds
Started Mar 28 03:28:43 PM PDT 24
Finished Mar 28 03:29:09 PM PDT 24
Peak memory 263608 kb
Host smart-9c9a7adb-fbd0-419d-8c34-af8de5bcc5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770681310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.770681310
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1782902699
Short name T1095
Test name
Test status
Simulation time 1406962918 ps
CPU time 30.87 seconds
Started Mar 28 03:28:33 PM PDT 24
Finished Mar 28 03:29:04 PM PDT 24
Peak memory 382868 kb
Host smart-f765dd2c-1bcc-4c80-a295-05da1108926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782902699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1782902699
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1994671018
Short name T805
Test name
Test status
Simulation time 2605457358 ps
CPU time 5.1 seconds
Started Mar 28 03:28:40 PM PDT 24
Finished Mar 28 03:28:46 PM PDT 24
Peak memory 204380 kb
Host smart-9c8052ae-091f-4804-b4c9-c24eb492b48d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994671018 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1994671018
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.261929346
Short name T1076
Test name
Test status
Simulation time 10083543454 ps
CPU time 95.41 seconds
Started Mar 28 03:28:34 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 601180 kb
Host smart-0963b600-fd7d-447d-8c24-c759b0453642
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261929346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.261929346
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.624180417
Short name T891
Test name
Test status
Simulation time 10311787499 ps
CPU time 16.02 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:29:00 PM PDT 24
Peak memory 352152 kb
Host smart-df32d7fd-7a14-46de-bc79-89625a1bf43b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624180417 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.624180417
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2783583128
Short name T909
Test name
Test status
Simulation time 877508522 ps
CPU time 2.76 seconds
Started Mar 28 03:28:37 PM PDT 24
Finished Mar 28 03:28:40 PM PDT 24
Peak memory 203840 kb
Host smart-814ee5b3-72ee-491e-9a52-034cac7942a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783583128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2783583128
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.3043444495
Short name T798
Test name
Test status
Simulation time 1151129058 ps
CPU time 5.83 seconds
Started Mar 28 03:28:42 PM PDT 24
Finished Mar 28 03:28:49 PM PDT 24
Peak memory 209556 kb
Host smart-55d9745a-43f3-4d56-afaa-b6c936f95f6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043444495 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.3043444495
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2264375495
Short name T843
Test name
Test status
Simulation time 823295547 ps
CPU time 30.49 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:29:15 PM PDT 24
Peak memory 203780 kb
Host smart-dc1e3393-256e-4efd-bf57-e961827fcc1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264375495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2264375495
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.807393907
Short name T309
Test name
Test status
Simulation time 3070997122 ps
CPU time 32.49 seconds
Started Mar 28 03:28:36 PM PDT 24
Finished Mar 28 03:29:09 PM PDT 24
Peak memory 203576 kb
Host smart-ebb1b2c3-70c3-4aa0-9377-077756d3a63d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807393907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.807393907
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2398103953
Short name T1127
Test name
Test status
Simulation time 17393744236 ps
CPU time 94.13 seconds
Started Mar 28 03:28:39 PM PDT 24
Finished Mar 28 03:30:14 PM PDT 24
Peak memory 1040904 kb
Host smart-14552388-dc8f-49e1-91c9-182b7399035b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398103953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2398103953
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.28127403
Short name T315
Test name
Test status
Simulation time 2790918181 ps
CPU time 6.94 seconds
Started Mar 28 03:28:41 PM PDT 24
Finished Mar 28 03:28:48 PM PDT 24
Peak memory 212140 kb
Host smart-a265d9e8-931c-4c52-8978-d70c962f13d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28127403 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_timeout.28127403
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2641116661
Short name T808
Test name
Test status
Simulation time 18415867 ps
CPU time 0.62 seconds
Started Mar 28 03:28:55 PM PDT 24
Finished Mar 28 03:28:55 PM PDT 24
Peak memory 203732 kb
Host smart-65103dbe-be50-418f-a045-abadc2885314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641116661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2641116661
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.4281586298
Short name T387
Test name
Test status
Simulation time 153589030 ps
CPU time 1.52 seconds
Started Mar 28 03:28:41 PM PDT 24
Finished Mar 28 03:28:43 PM PDT 24
Peak memory 212012 kb
Host smart-2d42d4de-e72d-4dee-959b-7f3a5108a873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281586298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.4281586298
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1059752572
Short name T1030
Test name
Test status
Simulation time 119376290 ps
CPU time 2.67 seconds
Started Mar 28 03:28:40 PM PDT 24
Finished Mar 28 03:28:44 PM PDT 24
Peak memory 220508 kb
Host smart-935c6c51-d61b-41de-aea9-a41e9b3c2e23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059752572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1059752572
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2730845933
Short name T784
Test name
Test status
Simulation time 1761478408 ps
CPU time 43.96 seconds
Started Mar 28 03:28:45 PM PDT 24
Finished Mar 28 03:29:30 PM PDT 24
Peak memory 474640 kb
Host smart-6b58c51f-78c8-4a93-b063-fe7dd9950595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730845933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2730845933
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.4210083967
Short name T758
Test name
Test status
Simulation time 2278513036 ps
CPU time 67.51 seconds
Started Mar 28 03:28:41 PM PDT 24
Finished Mar 28 03:29:49 PM PDT 24
Peak memory 724784 kb
Host smart-3707eba5-6a1f-4af8-9304-3f290bd86907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210083967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.4210083967
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.81098141
Short name T1173
Test name
Test status
Simulation time 805865640 ps
CPU time 1.18 seconds
Started Mar 28 03:28:42 PM PDT 24
Finished Mar 28 03:28:44 PM PDT 24
Peak memory 203744 kb
Host smart-4547f67b-14f5-4302-9ca9-9cd33c5e05f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81098141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt
.81098141
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.4147660796
Short name T325
Test name
Test status
Simulation time 205716850 ps
CPU time 5.02 seconds
Started Mar 28 03:28:42 PM PDT 24
Finished Mar 28 03:28:48 PM PDT 24
Peak memory 239616 kb
Host smart-cc1aac1b-05b0-4b5a-99f5-dadb2a18c1b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147660796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.4147660796
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3955066500
Short name T73
Test name
Test status
Simulation time 2251736653 ps
CPU time 117.21 seconds
Started Mar 28 03:28:39 PM PDT 24
Finished Mar 28 03:30:38 PM PDT 24
Peak memory 479388 kb
Host smart-f87a9cb5-9ebb-4113-ad29-bac46ee7df14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955066500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3955066500
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.116510696
Short name T708
Test name
Test status
Simulation time 798799646 ps
CPU time 8.06 seconds
Started Mar 28 03:28:53 PM PDT 24
Finished Mar 28 03:29:01 PM PDT 24
Peak memory 203852 kb
Host smart-53895119-e9da-4a06-ae0f-dd803bb9ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116510696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.116510696
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.849119059
Short name T720
Test name
Test status
Simulation time 4483085637 ps
CPU time 22.63 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:29:16 PM PDT 24
Peak memory 384548 kb
Host smart-3204df62-fe58-4f16-be66-e7dd8b23730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849119059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.849119059
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.4131766109
Short name T1161
Test name
Test status
Simulation time 46870744 ps
CPU time 0.65 seconds
Started Mar 28 03:28:42 PM PDT 24
Finished Mar 28 03:28:43 PM PDT 24
Peak memory 203580 kb
Host smart-48dd8545-3a87-409d-adf1-fc0cede49804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131766109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.4131766109
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2549188670
Short name T551
Test name
Test status
Simulation time 172508556 ps
CPU time 7.86 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:52 PM PDT 24
Peak memory 228304 kb
Host smart-a576c452-4b94-4c87-8d08-9d988a8aa972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549188670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2549188670
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.131295206
Short name T1007
Test name
Test status
Simulation time 7318575969 ps
CPU time 36.74 seconds
Started Mar 28 03:28:37 PM PDT 24
Finished Mar 28 03:29:14 PM PDT 24
Peak memory 442880 kb
Host smart-cb0edfc8-771f-45dc-8f07-2e338a0cffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131295206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.131295206
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3848541421
Short name T730
Test name
Test status
Simulation time 1058645049 ps
CPU time 2.88 seconds
Started Mar 28 03:28:56 PM PDT 24
Finished Mar 28 03:28:59 PM PDT 24
Peak memory 203780 kb
Host smart-33cb734c-fb96-4385-bde3-a2e826e3c0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848541421 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3848541421
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2569566841
Short name T375
Test name
Test status
Simulation time 10054362650 ps
CPU time 74.26 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:29:58 PM PDT 24
Peak memory 587652 kb
Host smart-b5c869ae-c088-4f06-b198-192fa96aa4ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569566841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2569566841
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3980624262
Short name T419
Test name
Test status
Simulation time 10199102126 ps
CPU time 15.27 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:59 PM PDT 24
Peak memory 330056 kb
Host smart-939ba68e-6b67-473b-9ce9-be8b660abbc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980624262 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3980624262
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.269453278
Short name T779
Test name
Test status
Simulation time 5307189036 ps
CPU time 2.76 seconds
Started Mar 28 03:28:56 PM PDT 24
Finished Mar 28 03:28:59 PM PDT 24
Peak memory 203768 kb
Host smart-27d8a553-85d2-4697-97f1-2db2449a2f82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269453278 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.269453278
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1794508404
Short name T972
Test name
Test status
Simulation time 968371458 ps
CPU time 4.41 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:49 PM PDT 24
Peak memory 203544 kb
Host smart-9a5b8d69-bdd4-4521-85c5-43178106a189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794508404 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1794508404
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3444871461
Short name T459
Test name
Test status
Simulation time 1284859994 ps
CPU time 8.4 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:54 PM PDT 24
Peak memory 203796 kb
Host smart-21be0deb-afcd-46d8-a40e-a395386d8478
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444871461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3444871461
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1020860524
Short name T847
Test name
Test status
Simulation time 1951812813 ps
CPU time 14.35 seconds
Started Mar 28 03:28:44 PM PDT 24
Finished Mar 28 03:28:59 PM PDT 24
Peak memory 217404 kb
Host smart-41ecf734-2345-45d4-a6c5-4950921d48af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020860524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1020860524
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2320718621
Short name T754
Test name
Test status
Simulation time 11855331960 ps
CPU time 23.25 seconds
Started Mar 28 03:28:46 PM PDT 24
Finished Mar 28 03:29:10 PM PDT 24
Peak memory 203828 kb
Host smart-ecf3eeca-3cbb-44ef-a369-0f4f27205a16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320718621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2320718621
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1824367436
Short name T759
Test name
Test status
Simulation time 3060562369 ps
CPU time 7.5 seconds
Started Mar 28 03:28:43 PM PDT 24
Finished Mar 28 03:28:51 PM PDT 24
Peak memory 212132 kb
Host smart-ebbde993-6539-44b4-934b-b774281c3bc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824367436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1824367436
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1012832337
Short name T292
Test name
Test status
Simulation time 38044298 ps
CPU time 0.6 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:28:55 PM PDT 24
Peak memory 203656 kb
Host smart-42f6c9d4-e172-4187-8a34-6c6364339241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012832337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1012832337
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2868725354
Short name T728
Test name
Test status
Simulation time 48477013 ps
CPU time 1.25 seconds
Started Mar 28 03:28:59 PM PDT 24
Finished Mar 28 03:29:00 PM PDT 24
Peak memory 212088 kb
Host smart-af072861-172d-40d9-8445-1581722b7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868725354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2868725354
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3114176687
Short name T767
Test name
Test status
Simulation time 711141023 ps
CPU time 5.57 seconds
Started Mar 28 03:28:56 PM PDT 24
Finished Mar 28 03:29:02 PM PDT 24
Peak memory 254348 kb
Host smart-cc61d844-df4e-4472-b8ff-3a17b7376a3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114176687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3114176687
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.365113891
Short name T714
Test name
Test status
Simulation time 1526599305 ps
CPU time 46.9 seconds
Started Mar 28 03:28:55 PM PDT 24
Finished Mar 28 03:29:42 PM PDT 24
Peak memory 565896 kb
Host smart-ecfd3f51-c795-417c-be11-f1b9ebf85e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365113891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.365113891
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3030013520
Short name T574
Test name
Test status
Simulation time 4731986933 ps
CPU time 79.94 seconds
Started Mar 28 03:28:57 PM PDT 24
Finished Mar 28 03:30:17 PM PDT 24
Peak memory 736480 kb
Host smart-be57c5e9-8d79-443d-b851-f88d50d32b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030013520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3030013520
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3155510537
Short name T739
Test name
Test status
Simulation time 189762560 ps
CPU time 0.97 seconds
Started Mar 28 03:28:52 PM PDT 24
Finished Mar 28 03:28:54 PM PDT 24
Peak memory 203724 kb
Host smart-7bc4564b-b68a-4c34-bfa2-fe3c135b0831
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155510537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3155510537
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1155111529
Short name T420
Test name
Test status
Simulation time 953272754 ps
CPU time 4.3 seconds
Started Mar 28 03:28:57 PM PDT 24
Finished Mar 28 03:29:01 PM PDT 24
Peak memory 228596 kb
Host smart-d2297c61-1449-4455-90a1-397931e686c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155111529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1155111529
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2376665003
Short name T836
Test name
Test status
Simulation time 5628931046 ps
CPU time 189.25 seconds
Started Mar 28 03:28:53 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 874440 kb
Host smart-43485b70-eba6-451c-95de-d65ff2d227ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376665003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2376665003
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1823737482
Short name T917
Test name
Test status
Simulation time 380658499 ps
CPU time 5.87 seconds
Started Mar 28 03:28:58 PM PDT 24
Finished Mar 28 03:29:04 PM PDT 24
Peak memory 203720 kb
Host smart-ffb2f22d-e6c8-4617-9e89-b60e21d52548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823737482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1823737482
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.232214675
Short name T302
Test name
Test status
Simulation time 1143428645 ps
CPU time 16.26 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:29:10 PM PDT 24
Peak memory 278840 kb
Host smart-14eea9ec-b390-4074-91d5-8052df570669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232214675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.232214675
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.2718416765
Short name T636
Test name
Test status
Simulation time 14641100 ps
CPU time 0.65 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:28:55 PM PDT 24
Peak memory 203604 kb
Host smart-f7de9fd8-1961-4e29-9616-86aaa204edb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718416765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.2718416765
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1911035960
Short name T913
Test name
Test status
Simulation time 3159265040 ps
CPU time 15.55 seconds
Started Mar 28 03:28:56 PM PDT 24
Finished Mar 28 03:29:12 PM PDT 24
Peak memory 368764 kb
Host smart-0b2c1cb2-fce3-4d94-bdc8-67910851e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911035960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1911035960
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4016837697
Short name T807
Test name
Test status
Simulation time 5375955184 ps
CPU time 75.28 seconds
Started Mar 28 03:28:58 PM PDT 24
Finished Mar 28 03:30:13 PM PDT 24
Peak memory 439376 kb
Host smart-137822e5-94de-4264-bfa5-aa167222b24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016837697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4016837697
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1339762992
Short name T947
Test name
Test status
Simulation time 497196540 ps
CPU time 3.08 seconds
Started Mar 28 03:28:52 PM PDT 24
Finished Mar 28 03:28:56 PM PDT 24
Peak memory 203796 kb
Host smart-d864c35c-8472-4cc1-8b40-3bbbf969bf20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339762992 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1339762992
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.4089660577
Short name T64
Test name
Test status
Simulation time 10039052817 ps
CPU time 81.4 seconds
Started Mar 28 03:28:58 PM PDT 24
Finished Mar 28 03:30:20 PM PDT 24
Peak memory 582240 kb
Host smart-f37fedf4-237b-43f8-a900-32d70cb97ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089660577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.4089660577
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2986279070
Short name T1097
Test name
Test status
Simulation time 10132415980 ps
CPU time 34.27 seconds
Started Mar 28 03:28:53 PM PDT 24
Finished Mar 28 03:29:27 PM PDT 24
Peak memory 440888 kb
Host smart-67249d3b-ad13-45d2-869a-9eb5cdbb18e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986279070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2986279070
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3442589621
Short name T35
Test name
Test status
Simulation time 805192866 ps
CPU time 2.69 seconds
Started Mar 28 03:28:59 PM PDT 24
Finished Mar 28 03:29:02 PM PDT 24
Peak memory 203700 kb
Host smart-0d524a0f-bdf1-4ac4-8833-c286079c4d1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442589621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3442589621
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1261683819
Short name T261
Test name
Test status
Simulation time 533896308 ps
CPU time 3.42 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:28:58 PM PDT 24
Peak memory 203864 kb
Host smart-17801d1e-5f71-4e50-a055-383478733d28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261683819 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1261683819
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.4108919897
Short name T489
Test name
Test status
Simulation time 685532477 ps
CPU time 23.66 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:29:17 PM PDT 24
Peak memory 203784 kb
Host smart-337e1150-d847-4faa-a0f1-0848a9539312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108919897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.4108919897
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3711597683
Short name T984
Test name
Test status
Simulation time 2880212387 ps
CPU time 63.25 seconds
Started Mar 28 03:28:58 PM PDT 24
Finished Mar 28 03:30:01 PM PDT 24
Peak memory 206440 kb
Host smart-dd8eaa5b-d74d-4f95-a315-0a04a05933a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711597683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3711597683
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1318246159
Short name T851
Test name
Test status
Simulation time 9091037489 ps
CPU time 11.14 seconds
Started Mar 28 03:28:55 PM PDT 24
Finished Mar 28 03:29:06 PM PDT 24
Peak memory 203780 kb
Host smart-018b3a24-c574-4f6d-a9ce-c9d75ef51c00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318246159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1318246159
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.4013777486
Short name T277
Test name
Test status
Simulation time 4507809766 ps
CPU time 23.04 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:29:17 PM PDT 24
Peak memory 428652 kb
Host smart-0818a23b-3c87-4a05-adf6-c171231eabd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013777486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.4013777486
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3220063159
Short name T502
Test name
Test status
Simulation time 5172472406 ps
CPU time 6.76 seconds
Started Mar 28 03:28:57 PM PDT 24
Finished Mar 28 03:29:04 PM PDT 24
Peak memory 212124 kb
Host smart-cc25b39b-027e-489a-a909-75889fa32f93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220063159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3220063159
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.4268427342
Short name T567
Test name
Test status
Simulation time 326127357 ps
CPU time 1.73 seconds
Started Mar 28 03:28:58 PM PDT 24
Finished Mar 28 03:29:00 PM PDT 24
Peak memory 211996 kb
Host smart-54d25700-a8e9-4871-aea7-4201aecd4952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268427342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.4268427342
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3938088313
Short name T644
Test name
Test status
Simulation time 1725999941 ps
CPU time 8.83 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:29:03 PM PDT 24
Peak memory 285548 kb
Host smart-a1704879-8f7d-4cb0-88af-3028514c7229
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938088313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3938088313
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1675588890
Short name T1015
Test name
Test status
Simulation time 2757628665 ps
CPU time 85.98 seconds
Started Mar 28 03:28:54 PM PDT 24
Finished Mar 28 03:30:20 PM PDT 24
Peak memory 517012 kb
Host smart-e7891dce-d926-4585-9cde-9d1c3f53b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675588890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1675588890
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3629896787
Short name T14
Test name
Test status
Simulation time 2148920783 ps
CPU time 63.39 seconds
Started Mar 28 03:28:56 PM PDT 24
Finished Mar 28 03:30:00 PM PDT 24
Peak memory 714880 kb
Host smart-f85879e2-b0ed-45af-a37c-d25fa0800e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629896787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3629896787
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2101645777
Short name T1018
Test name
Test status
Simulation time 155559591 ps
CPU time 1.2 seconds
Started Mar 28 03:28:55 PM PDT 24
Finished Mar 28 03:28:56 PM PDT 24
Peak memory 203752 kb
Host smart-1eaebba6-c170-408c-9a26-3edf7f1653c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101645777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2101645777
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3294588388
Short name T1058
Test name
Test status
Simulation time 220376346 ps
CPU time 2.97 seconds
Started Mar 28 03:28:55 PM PDT 24
Finished Mar 28 03:28:58 PM PDT 24
Peak memory 220412 kb
Host smart-e258394b-4fb4-480d-a076-9b6f0af47aec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294588388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3294588388
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1546581239
Short name T313
Test name
Test status
Simulation time 3922965583 ps
CPU time 302.67 seconds
Started Mar 28 03:29:01 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 1160412 kb
Host smart-da9ce98f-44b8-45bc-9c08-2f9911860146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546581239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1546581239
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2141494565
Short name T776
Test name
Test status
Simulation time 1903632372 ps
CPU time 16.88 seconds
Started Mar 28 03:28:57 PM PDT 24
Finished Mar 28 03:29:14 PM PDT 24
Peak memory 203844 kb
Host smart-a111b5e2-1784-41ba-a4d1-d7d01d67fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141494565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2141494565
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.421270596
Short name T266
Test name
Test status
Simulation time 9086210580 ps
CPU time 24.5 seconds
Started Mar 28 03:29:02 PM PDT 24
Finished Mar 28 03:29:27 PM PDT 24
Peak memory 360960 kb
Host smart-215d5d1b-42ef-41a4-b059-8ef33bf8df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421270596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.421270596
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3133492111
Short name T181
Test name
Test status
Simulation time 19472350 ps
CPU time 0.66 seconds
Started Mar 28 03:28:59 PM PDT 24
Finished Mar 28 03:28:59 PM PDT 24
Peak memory 203600 kb
Host smart-c8104e8b-a7b1-4397-9e80-f6ceddcd968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133492111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3133492111
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.271854766
Short name T194
Test name
Test status
Simulation time 5440273617 ps
CPU time 27.66 seconds
Started Mar 28 03:28:59 PM PDT 24
Finished Mar 28 03:29:27 PM PDT 24
Peak memory 220632 kb
Host smart-d9680c2e-435f-4c60-aeee-bdc5a441b396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271854766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.271854766
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.387271480
Short name T267
Test name
Test status
Simulation time 6611780774 ps
CPU time 84.66 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:30:39 PM PDT 24
Peak memory 354704 kb
Host smart-ae796470-84fb-4140-9b97-1243c542a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387271480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.387271480
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2640815036
Short name T397
Test name
Test status
Simulation time 1148685184 ps
CPU time 3.06 seconds
Started Mar 28 03:29:00 PM PDT 24
Finished Mar 28 03:29:03 PM PDT 24
Peak memory 203804 kb
Host smart-8bd62da5-b77e-4d8b-b04e-382fafde3e35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640815036 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2640815036
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2820866406
Short name T978
Test name
Test status
Simulation time 10032219420 ps
CPU time 66.5 seconds
Started Mar 28 03:28:55 PM PDT 24
Finished Mar 28 03:30:02 PM PDT 24
Peak memory 590644 kb
Host smart-d25d5d3a-50c7-41e1-b976-80a6c53f723b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820866406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2820866406
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.57967601
Short name T1067
Test name
Test status
Simulation time 10074491739 ps
CPU time 102.1 seconds
Started Mar 28 03:28:56 PM PDT 24
Finished Mar 28 03:30:38 PM PDT 24
Peak memory 683760 kb
Host smart-3e371ca7-0d2a-433a-adce-734d8b40b76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57967601 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_fifo_reset_tx.57967601
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2202842153
Short name T628
Test name
Test status
Simulation time 313423525 ps
CPU time 2.32 seconds
Started Mar 28 03:29:04 PM PDT 24
Finished Mar 28 03:29:07 PM PDT 24
Peak memory 203796 kb
Host smart-4ac42401-3a18-4d51-b6fa-213de101d809
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202842153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2202842153
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2005307993
Short name T960
Test name
Test status
Simulation time 1968661448 ps
CPU time 5.19 seconds
Started Mar 28 03:28:56 PM PDT 24
Finished Mar 28 03:29:02 PM PDT 24
Peak memory 203844 kb
Host smart-0c1aa976-fa9c-498d-a069-e8394e62e864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005307993 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2005307993
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2205987013
Short name T346
Test name
Test status
Simulation time 1880813447 ps
CPU time 11.66 seconds
Started Mar 28 03:28:59 PM PDT 24
Finished Mar 28 03:29:10 PM PDT 24
Peak memory 203808 kb
Host smart-78fa183a-4e03-4510-b66d-2809f31009eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205987013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2205987013
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.323375846
Short name T678
Test name
Test status
Simulation time 2076060885 ps
CPU time 14.49 seconds
Started Mar 28 03:28:58 PM PDT 24
Finished Mar 28 03:29:12 PM PDT 24
Peak memory 203788 kb
Host smart-f24b10f6-a2b0-4da6-9a5f-2afe8ee6942c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323375846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.323375846
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2384037363
Short name T417
Test name
Test status
Simulation time 1130873786 ps
CPU time 6.86 seconds
Started Mar 28 03:28:57 PM PDT 24
Finished Mar 28 03:29:04 PM PDT 24
Peak memory 220012 kb
Host smart-e5e3703d-db07-45fd-9f2e-0f1a7713c1eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384037363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2384037363
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2348200116
Short name T175
Test name
Test status
Simulation time 17278696 ps
CPU time 0.64 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:18 PM PDT 24
Peak memory 203712 kb
Host smart-40a8c507-47d4-44a3-8e81-07c277753fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348200116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2348200116
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2344888278
Short name T443
Test name
Test status
Simulation time 219644382 ps
CPU time 1.47 seconds
Started Mar 28 03:29:04 PM PDT 24
Finished Mar 28 03:29:06 PM PDT 24
Peak memory 214892 kb
Host smart-3fea74ee-745e-4e77-9484-f3ccf9c905cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344888278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2344888278
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1067678463
Short name T957
Test name
Test status
Simulation time 1139752848 ps
CPU time 6.51 seconds
Started Mar 28 03:29:01 PM PDT 24
Finished Mar 28 03:29:08 PM PDT 24
Peak memory 263376 kb
Host smart-dcc36eff-22d1-4168-befb-086975e1011e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067678463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1067678463
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1089085885
Short name T409
Test name
Test status
Simulation time 19124066620 ps
CPU time 150.93 seconds
Started Mar 28 03:29:03 PM PDT 24
Finished Mar 28 03:31:34 PM PDT 24
Peak memory 697188 kb
Host smart-79242980-486a-4af9-938d-ce1761da259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089085885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1089085885
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.334897623
Short name T1077
Test name
Test status
Simulation time 2469361853 ps
CPU time 81.67 seconds
Started Mar 28 03:28:57 PM PDT 24
Finished Mar 28 03:30:19 PM PDT 24
Peak memory 486228 kb
Host smart-526997eb-903d-4637-b56a-0370e5cf4d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334897623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.334897623
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.4225937665
Short name T3
Test name
Test status
Simulation time 268976559 ps
CPU time 1.09 seconds
Started Mar 28 03:29:00 PM PDT 24
Finished Mar 28 03:29:01 PM PDT 24
Peak memory 203660 kb
Host smart-039fb4ca-0936-452c-9937-962fc3ce26c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225937665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.4225937665
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3278765020
Short name T1146
Test name
Test status
Simulation time 182512398 ps
CPU time 4.61 seconds
Started Mar 28 03:29:00 PM PDT 24
Finished Mar 28 03:29:05 PM PDT 24
Peak memory 236076 kb
Host smart-1bff1b9c-ca4d-4c9c-8d88-b35e3ea7582a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278765020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3278765020
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1091356515
Short name T923
Test name
Test status
Simulation time 343333872 ps
CPU time 2.67 seconds
Started Mar 28 03:29:13 PM PDT 24
Finished Mar 28 03:29:15 PM PDT 24
Peak memory 203808 kb
Host smart-eefffd1d-1aa8-4317-b033-9f8539b577dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091356515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1091356515
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3230355745
Short name T351
Test name
Test status
Simulation time 4067152115 ps
CPU time 103.57 seconds
Started Mar 28 03:29:14 PM PDT 24
Finished Mar 28 03:30:57 PM PDT 24
Peak memory 448940 kb
Host smart-c11b216f-9ef2-4b8f-8154-540c7793341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230355745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3230355745
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1426442865
Short name T180
Test name
Test status
Simulation time 46527536 ps
CPU time 0.66 seconds
Started Mar 28 03:29:02 PM PDT 24
Finished Mar 28 03:29:03 PM PDT 24
Peak memory 203604 kb
Host smart-4109268b-d80b-4128-bac9-70bdb34430a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426442865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1426442865
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1097552434
Short name T41
Test name
Test status
Simulation time 48569385650 ps
CPU time 324.6 seconds
Started Mar 28 03:29:01 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 203868 kb
Host smart-8b9ebf3f-bcc1-45e3-b784-e54a1bf03837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097552434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1097552434
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.439806824
Short name T271
Test name
Test status
Simulation time 2253096848 ps
CPU time 52.79 seconds
Started Mar 28 03:28:58 PM PDT 24
Finished Mar 28 03:29:51 PM PDT 24
Peak memory 302372 kb
Host smart-e396510c-77e1-4716-8a63-0f5652232047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439806824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.439806824
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2512702792
Short name T1136
Test name
Test status
Simulation time 535865331 ps
CPU time 2.82 seconds
Started Mar 28 03:29:18 PM PDT 24
Finished Mar 28 03:29:21 PM PDT 24
Peak memory 203844 kb
Host smart-f562a4ac-23e2-4290-826f-021901f0ecf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512702792 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2512702792
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1331682700
Short name T916
Test name
Test status
Simulation time 10069552652 ps
CPU time 33.01 seconds
Started Mar 28 03:29:03 PM PDT 24
Finished Mar 28 03:29:37 PM PDT 24
Peak memory 404912 kb
Host smart-cb9db63b-31f7-4b17-8a6b-ea8e80c5883b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331682700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1331682700
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3827998135
Short name T613
Test name
Test status
Simulation time 10126319154 ps
CPU time 30.75 seconds
Started Mar 28 03:29:03 PM PDT 24
Finished Mar 28 03:29:34 PM PDT 24
Peak memory 399716 kb
Host smart-90fb8326-140c-4b31-80ae-7dff2407bdd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827998135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3827998135
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3766627857
Short name T955
Test name
Test status
Simulation time 469107356 ps
CPU time 3.04 seconds
Started Mar 28 03:29:13 PM PDT 24
Finished Mar 28 03:29:16 PM PDT 24
Peak memory 203804 kb
Host smart-816119a3-4571-4ea1-8ceb-06e3f5f2e908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766627857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3766627857
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2159640235
Short name T1063
Test name
Test status
Simulation time 522033700 ps
CPU time 3.39 seconds
Started Mar 28 03:29:03 PM PDT 24
Finished Mar 28 03:29:07 PM PDT 24
Peak memory 203772 kb
Host smart-70a82850-c11e-4945-b52b-3835bd250471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159640235 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2159640235
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3146818225
Short name T606
Test name
Test status
Simulation time 8888758762 ps
CPU time 15.08 seconds
Started Mar 28 03:29:04 PM PDT 24
Finished Mar 28 03:29:20 PM PDT 24
Peak memory 203896 kb
Host smart-148fad6f-f993-4930-ab83-4b1b1f4fa790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146818225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3146818225
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3598238448
Short name T747
Test name
Test status
Simulation time 2362589629 ps
CPU time 22.77 seconds
Started Mar 28 03:29:02 PM PDT 24
Finished Mar 28 03:29:25 PM PDT 24
Peak memory 221896 kb
Host smart-9765b542-a766-4f86-8f5e-be6703ac264f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598238448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3598238448
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.698025502
Short name T437
Test name
Test status
Simulation time 13517005144 ps
CPU time 6.3 seconds
Started Mar 28 03:29:02 PM PDT 24
Finished Mar 28 03:29:08 PM PDT 24
Peak memory 203836 kb
Host smart-f3fe6b22-787f-4fc2-b6b3-7706658216b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698025502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.698025502
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.516968963
Short name T425
Test name
Test status
Simulation time 4684929061 ps
CPU time 142.01 seconds
Started Mar 28 03:29:03 PM PDT 24
Finished Mar 28 03:31:26 PM PDT 24
Peak memory 1195656 kb
Host smart-6f2802e7-d7bc-45a2-beb9-94dd809bfa58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516968963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.516968963
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2271903197
Short name T872
Test name
Test status
Simulation time 2132565727 ps
CPU time 6.07 seconds
Started Mar 28 03:29:04 PM PDT 24
Finished Mar 28 03:29:10 PM PDT 24
Peak memory 211980 kb
Host smart-196f03e4-1172-47e9-94d2-b300feac6230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271903197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2271903197
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2477193280
Short name T999
Test name
Test status
Simulation time 16344840 ps
CPU time 0.64 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:16 PM PDT 24
Peak memory 203624 kb
Host smart-63920ca1-7c03-4a94-978f-3d4ab3f7cff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477193280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2477193280
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2374707809
Short name T1124
Test name
Test status
Simulation time 237295671 ps
CPU time 1.39 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:29:17 PM PDT 24
Peak memory 220164 kb
Host smart-51c869e7-cc07-4960-8d33-a7f375d78741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374707809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2374707809
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3212897909
Short name T513
Test name
Test status
Simulation time 1104033601 ps
CPU time 6.62 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:24 PM PDT 24
Peak memory 249268 kb
Host smart-53784db4-263d-41f6-ad64-32d91f754e11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212897909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3212897909
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3951141653
Short name T762
Test name
Test status
Simulation time 4599197328 ps
CPU time 75.14 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:30:31 PM PDT 24
Peak memory 764356 kb
Host smart-ec07d6d3-8633-459f-b1c0-d0f3a3c04e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951141653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3951141653
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3035229209
Short name T1145
Test name
Test status
Simulation time 1309622001 ps
CPU time 85.44 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:30:42 PM PDT 24
Peak memory 481364 kb
Host smart-292d0f01-1ff1-4907-8da5-01114766c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035229209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3035229209
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2729179977
Short name T799
Test name
Test status
Simulation time 160960063 ps
CPU time 1.11 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:17 PM PDT 24
Peak memory 203704 kb
Host smart-d49ca431-8da3-4ae2-8ef5-209cd341d18a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729179977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2729179977
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2230037716
Short name T590
Test name
Test status
Simulation time 646687426 ps
CPU time 6.92 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 203828 kb
Host smart-4ad52a21-3fa4-4995-b745-fb9e663f4bdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230037716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2230037716
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.4253965765
Short name T904
Test name
Test status
Simulation time 18304685247 ps
CPU time 171.93 seconds
Started Mar 28 03:29:14 PM PDT 24
Finished Mar 28 03:32:06 PM PDT 24
Peak memory 842724 kb
Host smart-8a1ff293-15fe-45e2-9649-5f5a7823c4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253965765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.4253965765
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2948969275
Short name T631
Test name
Test status
Simulation time 2166475028 ps
CPU time 22.55 seconds
Started Mar 28 03:29:20 PM PDT 24
Finished Mar 28 03:29:43 PM PDT 24
Peak memory 203848 kb
Host smart-074f4824-3e0d-4ff1-afe5-f9fe08f9ac48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948969275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2948969275
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2725217826
Short name T535
Test name
Test status
Simulation time 908880395 ps
CPU time 15.6 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:32 PM PDT 24
Peak memory 303832 kb
Host smart-8944045d-a24f-47d5-ac61-b39dc0162cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725217826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2725217826
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2083387328
Short name T424
Test name
Test status
Simulation time 84924659 ps
CPU time 0.67 seconds
Started Mar 28 03:29:14 PM PDT 24
Finished Mar 28 03:29:15 PM PDT 24
Peak memory 203568 kb
Host smart-9384a168-fb79-4fc1-8df8-64f63760cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083387328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2083387328
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3942766219
Short name T781
Test name
Test status
Simulation time 7419839887 ps
CPU time 161.18 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:31:58 PM PDT 24
Peak memory 220288 kb
Host smart-3b90d72f-b9a0-4cb4-add8-4281c46d6d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942766219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3942766219
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1493805559
Short name T1004
Test name
Test status
Simulation time 1595975568 ps
CPU time 32.28 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:29:47 PM PDT 24
Peak memory 427120 kb
Host smart-b9378b34-1d8c-4812-b9b9-4c12e2253aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493805559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1493805559
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.696628486
Short name T964
Test name
Test status
Simulation time 2226238614 ps
CPU time 3.67 seconds
Started Mar 28 03:29:19 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 203876 kb
Host smart-a7079c36-ab33-40ac-8ffe-b848746c7d82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696628486 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.696628486
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.4277651077
Short name T1052
Test name
Test status
Simulation time 10430449698 ps
CPU time 16.31 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:33 PM PDT 24
Peak memory 295188 kb
Host smart-421afd29-b7c6-4d68-b0da-33f86e1dff7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277651077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.4277651077
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2526063385
Short name T1187
Test name
Test status
Simulation time 10055177209 ps
CPU time 98.16 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:30:55 PM PDT 24
Peak memory 707276 kb
Host smart-1cec06de-faea-4acf-a00b-bfce4472672f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526063385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2526063385
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.588040133
Short name T214
Test name
Test status
Simulation time 1267932646 ps
CPU time 2.85 seconds
Started Mar 28 03:29:20 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 203804 kb
Host smart-4ac9e80b-9f53-47de-b122-bf58d5f198d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588040133 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.588040133
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2953103785
Short name T627
Test name
Test status
Simulation time 2750140829 ps
CPU time 4.01 seconds
Started Mar 28 03:29:19 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 203916 kb
Host smart-0540f164-980d-4cd6-8f77-93f4e19002b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953103785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2953103785
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.318576493
Short name T1165
Test name
Test status
Simulation time 14351882224 ps
CPU time 15.5 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:31 PM PDT 24
Peak memory 203772 kb
Host smart-66f9322d-85b7-4a06-8024-864eace04056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318576493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.318576493
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1016983346
Short name T1047
Test name
Test status
Simulation time 1838960322 ps
CPU time 31.45 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:49 PM PDT 24
Peak memory 235196 kb
Host smart-1a721b46-6e25-4597-8240-ebe673b10057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016983346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1016983346
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2870311339
Short name T1064
Test name
Test status
Simulation time 17318178487 ps
CPU time 168.09 seconds
Started Mar 28 03:29:20 PM PDT 24
Finished Mar 28 03:32:08 PM PDT 24
Peak memory 1552180 kb
Host smart-4bbe1e33-d215-4081-a897-26d715960729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870311339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2870311339
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.83313457
Short name T1000
Test name
Test status
Simulation time 1277499970 ps
CPU time 6.77 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:24 PM PDT 24
Peak memory 203884 kb
Host smart-242a6252-c50f-487e-80e3-d5c2c00f4572
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83313457 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_timeout.83313457
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3879087195
Short name T272
Test name
Test status
Simulation time 25128027 ps
CPU time 0.64 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:18 PM PDT 24
Peak memory 203708 kb
Host smart-41e3c8da-4cec-48c2-b20a-c8cb34c36dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879087195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3879087195
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2492969323
Short name T566
Test name
Test status
Simulation time 82841880 ps
CPU time 1.31 seconds
Started Mar 28 03:29:18 PM PDT 24
Finished Mar 28 03:29:20 PM PDT 24
Peak memory 212060 kb
Host smart-cf3314e6-ef3f-4bc9-a78c-2fc8f2ca48af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492969323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2492969323
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2072537425
Short name T615
Test name
Test status
Simulation time 150533063 ps
CPU time 3.88 seconds
Started Mar 28 03:29:19 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 230624 kb
Host smart-cdb79ccb-fd1f-4dbc-b5f6-887870db30b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072537425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2072537425
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.616742022
Short name T465
Test name
Test status
Simulation time 2808934015 ps
CPU time 35.75 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:52 PM PDT 24
Peak memory 440300 kb
Host smart-c6166afe-c3c4-469b-a3ab-45d8110f9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616742022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.616742022
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1488927267
Short name T516
Test name
Test status
Simulation time 1167738596 ps
CPU time 75.23 seconds
Started Mar 28 03:29:18 PM PDT 24
Finished Mar 28 03:30:34 PM PDT 24
Peak memory 439632 kb
Host smart-039c1ee5-bd15-4c17-bb84-eb4c19840624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488927267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1488927267
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1241098459
Short name T605
Test name
Test status
Simulation time 356944822 ps
CPU time 1.34 seconds
Started Mar 28 03:29:18 PM PDT 24
Finished Mar 28 03:29:20 PM PDT 24
Peak memory 203848 kb
Host smart-54783eb8-58e3-4599-989f-eb0371b5e961
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241098459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1241098459
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.985874773
Short name T404
Test name
Test status
Simulation time 1770785141 ps
CPU time 5.47 seconds
Started Mar 28 03:29:20 PM PDT 24
Finished Mar 28 03:29:26 PM PDT 24
Peak memory 236796 kb
Host smart-3afff73a-622b-4195-a6c0-8e530cd03740
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985874773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
985874773
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2175641344
Short name T1086
Test name
Test status
Simulation time 6893800591 ps
CPU time 94.88 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:30:52 PM PDT 24
Peak memory 972552 kb
Host smart-427796df-5262-485e-89c1-2c678423c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175641344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2175641344
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1076551566
Short name T541
Test name
Test status
Simulation time 841681829 ps
CPU time 3.56 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:29:19 PM PDT 24
Peak memory 203780 kb
Host smart-0008c79b-1e31-45ea-9988-397afe8864f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076551566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1076551566
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.761639311
Short name T777
Test name
Test status
Simulation time 7347839855 ps
CPU time 20.18 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:29:35 PM PDT 24
Peak memory 357880 kb
Host smart-ded633de-f131-4ac6-a875-3a32bd00f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761639311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.761639311
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.235139023
Short name T183
Test name
Test status
Simulation time 47982545 ps
CPU time 0.65 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:18 PM PDT 24
Peak memory 203616 kb
Host smart-1437a2f4-8cd8-4e7c-86da-e8b988125ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235139023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.235139023
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1520252123
Short name T352
Test name
Test status
Simulation time 617905213 ps
CPU time 6.32 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 203748 kb
Host smart-ef8244a7-9184-4017-ac75-4e488a7ab46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520252123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1520252123
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.733148792
Short name T672
Test name
Test status
Simulation time 8810641190 ps
CPU time 85.18 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:30:42 PM PDT 24
Peak memory 411616 kb
Host smart-5c9ca05d-3014-498f-af48-187238ce5cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733148792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.733148792
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3645737536
Short name T402
Test name
Test status
Simulation time 10050124914 ps
CPU time 71.69 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:30:27 PM PDT 24
Peak memory 523320 kb
Host smart-31b9bd07-84a6-4028-a599-87c04e097a39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645737536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3645737536
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.3462674683
Short name T974
Test name
Test status
Simulation time 10068263450 ps
CPU time 95.81 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:30:53 PM PDT 24
Peak memory 756056 kb
Host smart-f2fec1b7-161b-4332-a26d-e777cd5f1513
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462674683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.3462674683
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2799589527
Short name T280
Test name
Test status
Simulation time 1277926828 ps
CPU time 2.26 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:19 PM PDT 24
Peak memory 203792 kb
Host smart-b4f0f02b-8279-4452-9134-c00793b48f63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799589527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2799589527
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3664123727
Short name T1131
Test name
Test status
Simulation time 873898303 ps
CPU time 4.75 seconds
Started Mar 28 03:29:18 PM PDT 24
Finished Mar 28 03:29:23 PM PDT 24
Peak memory 203748 kb
Host smart-c84b0f9d-5ffa-4219-a3fa-8b8755a15d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664123727 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3664123727
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.972845926
Short name T88
Test name
Test status
Simulation time 2731387558 ps
CPU time 20.2 seconds
Started Mar 28 03:29:16 PM PDT 24
Finished Mar 28 03:29:36 PM PDT 24
Peak memory 203892 kb
Host smart-673df4e8-8ac8-42d0-b584-34de8683dd02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972845926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.972845926
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3364661965
Short name T1130
Test name
Test status
Simulation time 9586395009 ps
CPU time 59.46 seconds
Started Mar 28 03:29:15 PM PDT 24
Finished Mar 28 03:30:14 PM PDT 24
Peak memory 209092 kb
Host smart-bf73dcef-89e5-45ce-9d28-8f2d7eb4423e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364661965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3364661965
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.77419672
Short name T637
Test name
Test status
Simulation time 19319589183 ps
CPU time 3.75 seconds
Started Mar 28 03:29:12 PM PDT 24
Finished Mar 28 03:29:16 PM PDT 24
Peak memory 203868 kb
Host smart-f7f10226-6529-4db9-8fef-03e57ffb861d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77419672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stress_wr.77419672
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1423963211
Short name T396
Test name
Test status
Simulation time 46667130569 ps
CPU time 609.3 seconds
Started Mar 28 03:29:19 PM PDT 24
Finished Mar 28 03:39:28 PM PDT 24
Peak memory 3129520 kb
Host smart-e6dfbdd0-5f7a-48b4-8aee-904f4349f56e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423963211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1423963211
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1770048739
Short name T21
Test name
Test status
Simulation time 2165217400 ps
CPU time 6.93 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:24 PM PDT 24
Peak memory 220016 kb
Host smart-d601679c-7014-4d15-809b-58fe7f58e270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770048739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1770048739
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2404440706
Short name T861
Test name
Test status
Simulation time 29731011 ps
CPU time 0.71 seconds
Started Mar 28 03:29:29 PM PDT 24
Finished Mar 28 03:29:30 PM PDT 24
Peak memory 203620 kb
Host smart-9877ed83-c524-4b5a-9650-507c133c602f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404440706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2404440706
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.570720258
Short name T753
Test name
Test status
Simulation time 207274971 ps
CPU time 1.59 seconds
Started Mar 28 03:29:29 PM PDT 24
Finished Mar 28 03:29:31 PM PDT 24
Peak memory 211980 kb
Host smart-da5f9c3d-6078-404e-b6fe-5d468815273e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570720258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.570720258
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1592166417
Short name T1107
Test name
Test status
Simulation time 235912526 ps
CPU time 4.55 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:21 PM PDT 24
Peak memory 252200 kb
Host smart-e7cfa264-72c6-4779-bd54-e2445f9b4f25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592166417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1592166417
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1851368150
Short name T82
Test name
Test status
Simulation time 2999435347 ps
CPU time 39.93 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:30:11 PM PDT 24
Peak memory 384504 kb
Host smart-86970b94-c7ad-4d10-b599-160784c6e56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851368150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1851368150
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1036854114
Short name T1106
Test name
Test status
Simulation time 5168376637 ps
CPU time 96.49 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:30:54 PM PDT 24
Peak memory 526168 kb
Host smart-d39b32e2-518d-4986-9351-45e0e600f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036854114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1036854114
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.466570047
Short name T383
Test name
Test status
Simulation time 160721166 ps
CPU time 1.32 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:19 PM PDT 24
Peak memory 203780 kb
Host smart-d8717ac4-c59c-401b-9af5-7c5f524da0e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466570047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.466570047
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1337462014
Short name T927
Test name
Test status
Simulation time 131065703 ps
CPU time 3.63 seconds
Started Mar 28 03:29:29 PM PDT 24
Finished Mar 28 03:29:33 PM PDT 24
Peak memory 221176 kb
Host smart-fe21c19a-509d-47d5-93da-caaee4fa0018
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337462014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1337462014
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1646602590
Short name T561
Test name
Test status
Simulation time 3832212854 ps
CPU time 246.53 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:33:24 PM PDT 24
Peak memory 992744 kb
Host smart-fa09d6a1-6e2a-4574-854f-50ff6a0d965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646602590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1646602590
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2457165163
Short name T939
Test name
Test status
Simulation time 862298202 ps
CPU time 3.82 seconds
Started Mar 28 03:29:28 PM PDT 24
Finished Mar 28 03:29:33 PM PDT 24
Peak memory 203760 kb
Host smart-d4bc0d5f-cb68-4bef-a642-710154bb5213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457165163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2457165163
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.3574120758
Short name T1008
Test name
Test status
Simulation time 4155969373 ps
CPU time 54.56 seconds
Started Mar 28 03:29:29 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 543200 kb
Host smart-a64947a0-269b-4436-9763-2d768538767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574120758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3574120758
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3879580217
Short name T488
Test name
Test status
Simulation time 17159873 ps
CPU time 0.66 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:29:18 PM PDT 24
Peak memory 203556 kb
Host smart-9376f65a-5529-42d9-9dcc-4cea15727842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879580217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3879580217
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1680108659
Short name T412
Test name
Test status
Simulation time 6155513602 ps
CPU time 60.6 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:30:31 PM PDT 24
Peak memory 203844 kb
Host smart-b7d4b609-8652-42bf-97a5-df49d7283b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680108659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1680108659
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1798641653
Short name T321
Test name
Test status
Simulation time 2292397564 ps
CPU time 54.84 seconds
Started Mar 28 03:29:17 PM PDT 24
Finished Mar 28 03:30:12 PM PDT 24
Peak memory 311848 kb
Host smart-80f593a6-96d9-4376-9275-0b9232d48ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798641653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1798641653
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1827343801
Short name T922
Test name
Test status
Simulation time 468864297 ps
CPU time 2.51 seconds
Started Mar 28 03:29:28 PM PDT 24
Finished Mar 28 03:29:30 PM PDT 24
Peak memory 203788 kb
Host smart-34a7d051-4e5b-42a9-9735-477d8a9be93a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827343801 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1827343801
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.542694229
Short name T328
Test name
Test status
Simulation time 10051958187 ps
CPU time 73.86 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:30:46 PM PDT 24
Peak memory 569208 kb
Host smart-b7874556-8909-4540-b3ec-567550c5bae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542694229 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.542694229
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3759263770
Short name T316
Test name
Test status
Simulation time 10055358459 ps
CPU time 98.39 seconds
Started Mar 28 03:29:29 PM PDT 24
Finished Mar 28 03:31:08 PM PDT 24
Peak memory 671448 kb
Host smart-229b417e-10d8-4848-816d-15357ad9f2a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759263770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3759263770
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.4004283612
Short name T816
Test name
Test status
Simulation time 754188535 ps
CPU time 1.7 seconds
Started Mar 28 03:29:28 PM PDT 24
Finished Mar 28 03:29:30 PM PDT 24
Peak memory 203740 kb
Host smart-47c5b92f-1c59-44d8-9cc2-ef31aed64cad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004283612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.4004283612
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.753206284
Short name T1020
Test name
Test status
Simulation time 1297720575 ps
CPU time 3.62 seconds
Started Mar 28 03:29:34 PM PDT 24
Finished Mar 28 03:29:37 PM PDT 24
Peak memory 203808 kb
Host smart-69993e56-87a1-4761-be85-9fa4203576e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753206284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_intr_smoke.753206284
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3898615686
Short name T1156
Test name
Test status
Simulation time 2486929677 ps
CPU time 17.68 seconds
Started Mar 28 03:29:30 PM PDT 24
Finished Mar 28 03:29:48 PM PDT 24
Peak memory 203820 kb
Host smart-358493fa-4e42-4233-8ef9-41801e69b92d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898615686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3898615686
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3928387641
Short name T854
Test name
Test status
Simulation time 803142694 ps
CPU time 4.16 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:29:35 PM PDT 24
Peak memory 203796 kb
Host smart-8ab1729e-09bb-46d8-986e-daf22db12191
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928387641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3928387641
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.240689807
Short name T457
Test name
Test status
Simulation time 27456712882 ps
CPU time 145.93 seconds
Started Mar 28 03:29:30 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 679572 kb
Host smart-38b6fc27-749d-4880-94e6-76de6454e9d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240689807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.240689807
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.503973462
Short name T648
Test name
Test status
Simulation time 13719063487 ps
CPU time 7.54 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:29:39 PM PDT 24
Peak memory 212096 kb
Host smart-bf71cb9d-3c89-4627-b2b8-e24f466fc3f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503973462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.503973462
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1247479501
Short name T681
Test name
Test status
Simulation time 16751907 ps
CPU time 0.63 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:29:32 PM PDT 24
Peak memory 203708 kb
Host smart-765a27a6-1f6e-46bf-a922-1de4a1975f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247479501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1247479501
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.578989545
Short name T1108
Test name
Test status
Simulation time 102489824 ps
CPU time 1.41 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:33 PM PDT 24
Peak memory 211916 kb
Host smart-dd9ceb71-4357-4454-85ac-2b2476545598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578989545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.578989545
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.872249773
Short name T875
Test name
Test status
Simulation time 458496928 ps
CPU time 3.57 seconds
Started Mar 28 03:29:30 PM PDT 24
Finished Mar 28 03:29:34 PM PDT 24
Peak memory 231940 kb
Host smart-e20d239d-08a9-44c0-948a-ec177b199508
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872249773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.872249773
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.4061593473
Short name T931
Test name
Test status
Simulation time 2466369815 ps
CPU time 55.64 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:30:28 PM PDT 24
Peak memory 613468 kb
Host smart-dc88f65d-21cd-4bea-b65a-ab76e45bbca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061593473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4061593473
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2474089417
Short name T276
Test name
Test status
Simulation time 1906445237 ps
CPU time 67.11 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:30:38 PM PDT 24
Peak memory 675092 kb
Host smart-b425a75f-f78a-4308-85bb-e875bc9a0102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474089417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2474089417
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3974500150
Short name T817
Test name
Test status
Simulation time 140111536 ps
CPU time 1.23 seconds
Started Mar 28 03:29:35 PM PDT 24
Finished Mar 28 03:29:36 PM PDT 24
Peak memory 203748 kb
Host smart-2cabe020-d746-4cfe-a5b4-06407859c0c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974500150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3974500150
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3812803552
Short name T388
Test name
Test status
Simulation time 538030940 ps
CPU time 3.18 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:36 PM PDT 24
Peak memory 223620 kb
Host smart-088d4a8e-d474-4496-ab7c-fdd9fc1662f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812803552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3812803552
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2213475376
Short name T1102
Test name
Test status
Simulation time 2880373902 ps
CPU time 87.92 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:31:00 PM PDT 24
Peak memory 919832 kb
Host smart-dcc6ff52-3b33-459e-b012-be1c66a3da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213475376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2213475376
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.1579252292
Short name T620
Test name
Test status
Simulation time 1026775630 ps
CPU time 12.18 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:44 PM PDT 24
Peak memory 203844 kb
Host smart-5773aefc-cf24-449a-a9a2-599934176ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579252292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1579252292
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1594152420
Short name T1060
Test name
Test status
Simulation time 1465049149 ps
CPU time 28.47 seconds
Started Mar 28 03:29:30 PM PDT 24
Finished Mar 28 03:29:59 PM PDT 24
Peak memory 399480 kb
Host smart-8e806073-98d3-49eb-b8e1-668f0998fa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594152420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1594152420
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.4208192638
Short name T13
Test name
Test status
Simulation time 42761067 ps
CPU time 0.63 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:33 PM PDT 24
Peak memory 203648 kb
Host smart-7ce07059-f94d-415b-a25e-e6befce12b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208192638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.4208192638
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1293924818
Short name T664
Test name
Test status
Simulation time 12800332937 ps
CPU time 15.78 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:29:47 PM PDT 24
Peak memory 252548 kb
Host smart-df62c485-4819-4617-af3f-754d6951214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293924818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1293924818
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1938876773
Short name T640
Test name
Test status
Simulation time 839884186 ps
CPU time 3.91 seconds
Started Mar 28 03:29:36 PM PDT 24
Finished Mar 28 03:29:40 PM PDT 24
Peak memory 212024 kb
Host smart-363f8514-1e82-461f-82c2-3e223eb5ce99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938876773 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1938876773
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.862228914
Short name T944
Test name
Test status
Simulation time 10488510608 ps
CPU time 13.5 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:46 PM PDT 24
Peak memory 285324 kb
Host smart-c6f836c5-9af3-4a26-a11f-8927df0ed383
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862228914 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.862228914
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.866289973
Short name T935
Test name
Test status
Simulation time 10097908744 ps
CPU time 108.42 seconds
Started Mar 28 03:29:36 PM PDT 24
Finished Mar 28 03:31:25 PM PDT 24
Peak memory 693892 kb
Host smart-eb4a17d0-d0ab-49f0-967d-c0083ae40afd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866289973 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.866289973
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.28384063
Short name T477
Test name
Test status
Simulation time 971157436 ps
CPU time 2.91 seconds
Started Mar 28 03:29:35 PM PDT 24
Finished Mar 28 03:29:38 PM PDT 24
Peak memory 204076 kb
Host smart-6f004778-5437-4014-8d50-8995e08da543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28384063 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.i2c_target_hrst.28384063
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3301164250
Short name T982
Test name
Test status
Simulation time 856531340 ps
CPU time 5.1 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:38 PM PDT 24
Peak memory 212000 kb
Host smart-bf391213-c7ee-4394-b735-5d1b081e6d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301164250 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3301164250
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3934933742
Short name T581
Test name
Test status
Simulation time 3601932098 ps
CPU time 8.15 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:40 PM PDT 24
Peak memory 203788 kb
Host smart-ebc4a2ac-4b4d-4268-8e5d-48d4a5e97903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934933742 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3934933742
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2315035028
Short name T492
Test name
Test status
Simulation time 3193543522 ps
CPU time 13.58 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:46 PM PDT 24
Peak memory 203660 kb
Host smart-1011cb9d-3ae4-4db9-aabe-70213f41e6ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315035028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2315035028
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1790846638
Short name T804
Test name
Test status
Simulation time 2462653005 ps
CPU time 76.65 seconds
Started Mar 28 03:29:30 PM PDT 24
Finished Mar 28 03:30:46 PM PDT 24
Peak memory 206784 kb
Host smart-ae41f420-c254-4cdb-82ea-c6d0abe95a8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790846638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1790846638
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3838185761
Short name T1035
Test name
Test status
Simulation time 57614229708 ps
CPU time 544.76 seconds
Started Mar 28 03:29:29 PM PDT 24
Finished Mar 28 03:38:34 PM PDT 24
Peak memory 3121536 kb
Host smart-270ca7cd-51f9-49b5-9620-4c5cc6b9b9e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838185761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3838185761
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2154846931
Short name T890
Test name
Test status
Simulation time 18966370351 ps
CPU time 7.24 seconds
Started Mar 28 03:29:33 PM PDT 24
Finished Mar 28 03:29:41 PM PDT 24
Peak memory 211272 kb
Host smart-5cf85cf5-5f71-4faf-a2f2-f2ee87d6ec25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154846931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2154846931
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1087809338
Short name T801
Test name
Test status
Simulation time 27730424 ps
CPU time 0.61 seconds
Started Mar 28 03:29:33 PM PDT 24
Finished Mar 28 03:29:34 PM PDT 24
Peak memory 203644 kb
Host smart-3365f514-6c30-458f-8df0-6a74898d45c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087809338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1087809338
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2745840303
Short name T608
Test name
Test status
Simulation time 252143067 ps
CPU time 1.51 seconds
Started Mar 28 03:29:33 PM PDT 24
Finished Mar 28 03:29:34 PM PDT 24
Peak memory 220192 kb
Host smart-b1b79faa-d07c-4f1a-90d0-a452c8c75ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745840303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2745840303
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.314329745
Short name T448
Test name
Test status
Simulation time 1338506586 ps
CPU time 17 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:29:48 PM PDT 24
Peak memory 273300 kb
Host smart-924628eb-34fe-4e86-a27d-b2517b19aee8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314329745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.314329745
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.447641220
Short name T75
Test name
Test status
Simulation time 2481728267 ps
CPU time 175.59 seconds
Started Mar 28 03:29:33 PM PDT 24
Finished Mar 28 03:32:29 PM PDT 24
Peak memory 714608 kb
Host smart-50abccc0-52a2-4c52-8552-d08d4d8417c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447641220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.447641220
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2453082671
Short name T552
Test name
Test status
Simulation time 5554132409 ps
CPU time 38.33 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 550712 kb
Host smart-0a7eaffb-641a-45f3-82f1-02198535c518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453082671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2453082671
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.416107700
Short name T202
Test name
Test status
Simulation time 1323648381 ps
CPU time 1.13 seconds
Started Mar 28 03:29:33 PM PDT 24
Finished Mar 28 03:29:34 PM PDT 24
Peak memory 203844 kb
Host smart-22d116e6-8dc1-4769-b9f2-ff6d36a5cc52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416107700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.416107700
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2747930544
Short name T883
Test name
Test status
Simulation time 816625159 ps
CPU time 11.21 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:44 PM PDT 24
Peak memory 241840 kb
Host smart-b0b92fe8-91cc-4967-8f15-e64f290d5199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747930544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2747930544
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3865199062
Short name T150
Test name
Test status
Simulation time 4918440400 ps
CPU time 107.29 seconds
Started Mar 28 03:29:36 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 1103844 kb
Host smart-cf099e40-f3b3-4a57-a66f-7aa288618b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865199062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3865199062
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3829069169
Short name T288
Test name
Test status
Simulation time 528095599 ps
CPU time 5.56 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:38 PM PDT 24
Peak memory 203800 kb
Host smart-9e2b46fe-1be8-4150-8883-ad0b72b82a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829069169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3829069169
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.938920384
Short name T903
Test name
Test status
Simulation time 978872370 ps
CPU time 41.93 seconds
Started Mar 28 03:29:34 PM PDT 24
Finished Mar 28 03:30:16 PM PDT 24
Peak memory 252704 kb
Host smart-f4caa7b5-a618-4ff3-b6db-198920597b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938920384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.938920384
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.3672543151
Short name T178
Test name
Test status
Simulation time 99308711 ps
CPU time 0.66 seconds
Started Mar 28 03:29:34 PM PDT 24
Finished Mar 28 03:29:35 PM PDT 24
Peak memory 203544 kb
Host smart-c3d61ff0-779c-4a35-9456-09f2f71e19c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672543151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3672543151
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3933871080
Short name T1079
Test name
Test status
Simulation time 12524673210 ps
CPU time 958.88 seconds
Started Mar 28 03:29:35 PM PDT 24
Finished Mar 28 03:45:34 PM PDT 24
Peak memory 3093268 kb
Host smart-d6d8e3d9-acc4-4ac4-a8cf-59863391ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933871080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3933871080
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.606477426
Short name T719
Test name
Test status
Simulation time 1341657024 ps
CPU time 29.88 seconds
Started Mar 28 03:29:34 PM PDT 24
Finished Mar 28 03:30:04 PM PDT 24
Peak memory 360024 kb
Host smart-5dfdef8c-2d29-4578-982f-aefbe5bec08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606477426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.606477426
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1278074842
Short name T445
Test name
Test status
Simulation time 5281680984 ps
CPU time 5.85 seconds
Started Mar 28 03:29:39 PM PDT 24
Finished Mar 28 03:29:46 PM PDT 24
Peak memory 206044 kb
Host smart-98a6b6c8-4a7f-40f2-8954-548dadfc4cfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278074842 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1278074842
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.789957216
Short name T354
Test name
Test status
Simulation time 10412446678 ps
CPU time 4.42 seconds
Started Mar 28 03:29:34 PM PDT 24
Finished Mar 28 03:29:38 PM PDT 24
Peak memory 231776 kb
Host smart-030c302a-ce8a-431d-ad78-9a3314c74181
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789957216 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.789957216
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.3821406589
Short name T949
Test name
Test status
Simulation time 298139929 ps
CPU time 2.32 seconds
Started Mar 28 03:29:34 PM PDT 24
Finished Mar 28 03:29:36 PM PDT 24
Peak memory 203796 kb
Host smart-61401a69-5b21-4754-af5e-95ddc6a893c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821406589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.3821406589
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2049194517
Short name T264
Test name
Test status
Simulation time 1079881563 ps
CPU time 5.59 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:38 PM PDT 24
Peak memory 214624 kb
Host smart-06110404-7117-4d16-9c8f-dee1a4caac77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049194517 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2049194517
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3358367875
Short name T401
Test name
Test status
Simulation time 5105174731 ps
CPU time 3.99 seconds
Started Mar 28 03:29:31 PM PDT 24
Finished Mar 28 03:29:35 PM PDT 24
Peak memory 203828 kb
Host smart-8db9fc1c-82c1-4cca-919f-e96a4cd70530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358367875 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3358367875
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1306062698
Short name T985
Test name
Test status
Simulation time 3063152006 ps
CPU time 11.73 seconds
Started Mar 28 03:29:36 PM PDT 24
Finished Mar 28 03:29:48 PM PDT 24
Peak memory 203812 kb
Host smart-45f7ab83-709c-4e40-b2b9-602acfdf0609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306062698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1306062698
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.705406729
Short name T108
Test name
Test status
Simulation time 646690764 ps
CPU time 5.99 seconds
Started Mar 28 03:29:33 PM PDT 24
Finished Mar 28 03:29:39 PM PDT 24
Peak memory 203724 kb
Host smart-e236e0a9-83ac-44fe-ad9a-0a1f603dd550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705406729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.705406729
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.278786290
Short name T248
Test name
Test status
Simulation time 7494657886 ps
CPU time 15.62 seconds
Started Mar 28 03:29:32 PM PDT 24
Finished Mar 28 03:29:48 PM PDT 24
Peak memory 203636 kb
Host smart-0cafe10d-e5c5-4369-b0f9-9b044db4fed9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278786290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.278786290
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3686878916
Short name T1148
Test name
Test status
Simulation time 7636799123 ps
CPU time 6.52 seconds
Started Mar 28 03:29:34 PM PDT 24
Finished Mar 28 03:29:40 PM PDT 24
Peak memory 212104 kb
Host smart-3374476b-f5b0-4abc-83ea-5468532a4c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686878916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3686878916
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.68418025
Short name T520
Test name
Test status
Simulation time 1728751619 ps
CPU time 4.69 seconds
Started Mar 28 03:29:35 PM PDT 24
Finished Mar 28 03:29:40 PM PDT 24
Peak memory 203812 kb
Host smart-6889c700-0c95-4c17-8fdc-973511255ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68418025 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_unexp_stop.68418025
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.1570678421
Short name T727
Test name
Test status
Simulation time 42068324 ps
CPU time 0.65 seconds
Started Mar 28 03:25:21 PM PDT 24
Finished Mar 28 03:25:23 PM PDT 24
Peak memory 203704 kb
Host smart-0bd621c3-0f52-495f-9ae8-0eb4a07383db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570678421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1570678421
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.476670117
Short name T894
Test name
Test status
Simulation time 172007834 ps
CPU time 1.07 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:25:19 PM PDT 24
Peak memory 212048 kb
Host smart-af040e6b-6aa8-4c90-86af-fd8647fb0350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476670117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.476670117
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2702453118
Short name T410
Test name
Test status
Simulation time 285283471 ps
CPU time 6.51 seconds
Started Mar 28 03:25:16 PM PDT 24
Finished Mar 28 03:25:23 PM PDT 24
Peak memory 249608 kb
Host smart-22edfe04-c8f6-4032-bf9a-953994da580b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702453118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2702453118
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1035172099
Short name T89
Test name
Test status
Simulation time 5399511750 ps
CPU time 48.77 seconds
Started Mar 28 03:25:16 PM PDT 24
Finished Mar 28 03:26:05 PM PDT 24
Peak memory 541232 kb
Host smart-890b3e84-b25a-419c-8e5d-086eb6dbcf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035172099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1035172099
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.560752638
Short name T599
Test name
Test status
Simulation time 1330248924 ps
CPU time 91.65 seconds
Started Mar 28 03:25:19 PM PDT 24
Finished Mar 28 03:26:51 PM PDT 24
Peak memory 524748 kb
Host smart-f0eac129-bbce-46d2-8bbf-1880eabf58cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560752638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.560752638
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2362382447
Short name T204
Test name
Test status
Simulation time 130661161 ps
CPU time 0.95 seconds
Started Mar 28 03:25:19 PM PDT 24
Finished Mar 28 03:25:20 PM PDT 24
Peak memory 203696 kb
Host smart-ef2bd44a-c4e9-43c3-857a-a8ce83d79abe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362382447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2362382447
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2439439718
Short name T395
Test name
Test status
Simulation time 1311092072 ps
CPU time 4.3 seconds
Started Mar 28 03:25:19 PM PDT 24
Finished Mar 28 03:25:24 PM PDT 24
Peak memory 228452 kb
Host smart-f271cc8c-1990-40a8-88ce-d0e1ab137c75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439439718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2439439718
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2043953491
Short name T695
Test name
Test status
Simulation time 18220405116 ps
CPU time 147.43 seconds
Started Mar 28 03:25:16 PM PDT 24
Finished Mar 28 03:27:43 PM PDT 24
Peak memory 1291460 kb
Host smart-77c6474d-ee9f-4a0a-95ef-1bf87c9a88d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043953491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2043953491
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1113447328
Short name T1023
Test name
Test status
Simulation time 9949258839 ps
CPU time 49.41 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:26:07 PM PDT 24
Peak memory 326960 kb
Host smart-4478b0b8-8923-434f-b325-04d25adf44da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113447328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1113447328
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3267523868
Short name T926
Test name
Test status
Simulation time 15074894 ps
CPU time 0.63 seconds
Started Mar 28 03:25:03 PM PDT 24
Finished Mar 28 03:25:04 PM PDT 24
Peak memory 203620 kb
Host smart-7e2d7f41-6d51-4a71-9f37-2d5027e6a0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267523868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3267523868
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3553506177
Short name T42
Test name
Test status
Simulation time 4035828727 ps
CPU time 30.37 seconds
Started Mar 28 03:25:19 PM PDT 24
Finished Mar 28 03:25:49 PM PDT 24
Peak memory 528744 kb
Host smart-677bdade-8506-454c-b532-7e77314a3634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553506177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3553506177
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1639292626
Short name T1170
Test name
Test status
Simulation time 14285272997 ps
CPU time 25.25 seconds
Started Mar 28 03:25:04 PM PDT 24
Finished Mar 28 03:25:30 PM PDT 24
Peak memory 343484 kb
Host smart-d974a9cc-524d-4eeb-933e-c92b2b21827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639292626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1639292626
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1589038418
Short name T99
Test name
Test status
Simulation time 43672677 ps
CPU time 0.85 seconds
Started Mar 28 03:25:20 PM PDT 24
Finished Mar 28 03:25:21 PM PDT 24
Peak memory 221380 kb
Host smart-b0d39b4d-8d90-47d1-8637-f2f37f800170
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589038418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1589038418
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.726282831
Short name T490
Test name
Test status
Simulation time 3979396507 ps
CPU time 4.44 seconds
Started Mar 28 03:25:19 PM PDT 24
Finished Mar 28 03:25:24 PM PDT 24
Peak memory 203920 kb
Host smart-52839703-ad3a-4341-a86f-4a77562682b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726282831 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.726282831
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.303670425
Short name T688
Test name
Test status
Simulation time 10272074197 ps
CPU time 30.37 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:25:47 PM PDT 24
Peak memory 406216 kb
Host smart-1dddf0e6-4d1f-4959-a64b-26176799b97f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303670425 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.303670425
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.589062431
Short name T110
Test name
Test status
Simulation time 10176571920 ps
CPU time 15.41 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:25:32 PM PDT 24
Peak memory 313648 kb
Host smart-396b5903-9237-4e72-bbd9-345fdd162de8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589062431 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.589062431
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2741483464
Short name T585
Test name
Test status
Simulation time 480383845 ps
CPU time 2.71 seconds
Started Mar 28 03:25:18 PM PDT 24
Finished Mar 28 03:25:21 PM PDT 24
Peak memory 203792 kb
Host smart-787e0e18-89aa-4c25-9e91-7e98c84d11a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741483464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2741483464
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.581822252
Short name T774
Test name
Test status
Simulation time 1068352862 ps
CPU time 5.65 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:25:22 PM PDT 24
Peak memory 217488 kb
Host smart-a816e05c-2c8e-4bb2-b727-5c4e48bb7ba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581822252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.581822252
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1495427065
Short name T646
Test name
Test status
Simulation time 4111016670 ps
CPU time 13.65 seconds
Started Mar 28 03:25:18 PM PDT 24
Finished Mar 28 03:25:32 PM PDT 24
Peak memory 203888 kb
Host smart-ecf4cd39-f585-4395-9074-e9998e2f708e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495427065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1495427065
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1286083070
Short name T217
Test name
Test status
Simulation time 1028221091 ps
CPU time 46.16 seconds
Started Mar 28 03:25:18 PM PDT 24
Finished Mar 28 03:26:04 PM PDT 24
Peak memory 203800 kb
Host smart-e39825b9-be1f-4509-85ae-0df9488031f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286083070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1286083070
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1469954937
Short name T384
Test name
Test status
Simulation time 5753812227 ps
CPU time 7.05 seconds
Started Mar 28 03:25:20 PM PDT 24
Finished Mar 28 03:25:27 PM PDT 24
Peak memory 203868 kb
Host smart-54fe4032-2313-4f54-a335-10a10dee8f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469954937 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1469954937
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1781908539
Short name T7
Test name
Test status
Simulation time 16691865 ps
CPU time 0.63 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:29:54 PM PDT 24
Peak memory 203656 kb
Host smart-2887bad2-22d6-4a06-a1d2-2c156839a363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781908539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1781908539
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3314736619
Short name T519
Test name
Test status
Simulation time 351418629 ps
CPU time 1.51 seconds
Started Mar 28 03:29:50 PM PDT 24
Finished Mar 28 03:29:52 PM PDT 24
Peak memory 212020 kb
Host smart-3ea1129b-8222-4f13-8564-642c172a03b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314736619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3314736619
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.4159096086
Short name T72
Test name
Test status
Simulation time 252382673 ps
CPU time 4.68 seconds
Started Mar 28 03:29:56 PM PDT 24
Finished Mar 28 03:30:00 PM PDT 24
Peak memory 251544 kb
Host smart-1cf786c9-44b0-4a0c-9f00-be99313487cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159096086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.4159096086
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1613789703
Short name T469
Test name
Test status
Simulation time 5760849350 ps
CPU time 75.52 seconds
Started Mar 28 03:29:55 PM PDT 24
Finished Mar 28 03:31:11 PM PDT 24
Peak memory 477664 kb
Host smart-340a59b9-62f2-4a95-86e6-f213182b91f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613789703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1613789703
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1458812810
Short name T323
Test name
Test status
Simulation time 3108518299 ps
CPU time 44.71 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:30:36 PM PDT 24
Peak memory 591436 kb
Host smart-f928ea49-a1d6-4ad1-8dfa-1ecbeffe0c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458812810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1458812810
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3099905752
Short name T914
Test name
Test status
Simulation time 354467346 ps
CPU time 1 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:29:52 PM PDT 24
Peak memory 203752 kb
Host smart-433809ac-9b74-4cc6-ba07-b0761950084a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099905752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3099905752
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1395848939
Short name T889
Test name
Test status
Simulation time 181325769 ps
CPU time 10.95 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:30:04 PM PDT 24
Peak memory 238920 kb
Host smart-268507ba-6bc0-48f6-8117-46dc5fa746fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395848939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1395848939
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3965698833
Short name T582
Test name
Test status
Simulation time 21846714359 ps
CPU time 325.61 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:35:19 PM PDT 24
Peak memory 1238488 kb
Host smart-17c681b1-79b3-4b83-8051-b3f86d20ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965698833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3965698833
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.422261777
Short name T439
Test name
Test status
Simulation time 2228247104 ps
CPU time 13.92 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:30:05 PM PDT 24
Peak memory 203968 kb
Host smart-d002fdc7-1e6d-44aa-b541-e6dd0a28cd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422261777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.422261777
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.882220225
Short name T614
Test name
Test status
Simulation time 5161295338 ps
CPU time 19.35 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:30:14 PM PDT 24
Peak memory 315384 kb
Host smart-d263831e-14e9-4c5a-b1e9-f816e8a5ea53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882220225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.882220225
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3677149588
Short name T188
Test name
Test status
Simulation time 47179080 ps
CPU time 0.65 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:29:55 PM PDT 24
Peak memory 203544 kb
Host smart-dfc58dbb-c593-4f6f-9267-6848c23147ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677149588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3677149588
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.482106544
Short name T867
Test name
Test status
Simulation time 5230649909 ps
CPU time 77.38 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:31:11 PM PDT 24
Peak memory 509860 kb
Host smart-b7335adb-000c-4ea1-8008-1d1f5fa67246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482106544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.482106544
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.3565396328
Short name T262
Test name
Test status
Simulation time 2017371151 ps
CPU time 22.85 seconds
Started Mar 28 03:29:39 PM PDT 24
Finished Mar 28 03:30:03 PM PDT 24
Peak memory 341860 kb
Host smart-4aea6a1a-47a2-45c3-9662-9717d04a0bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565396328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3565396328
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1409979769
Short name T162
Test name
Test status
Simulation time 28186285074 ps
CPU time 314.11 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:35:05 PM PDT 24
Peak memory 1451596 kb
Host smart-00d4cff1-7750-4e9c-8376-c289434e1af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409979769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1409979769
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3645031225
Short name T546
Test name
Test status
Simulation time 1961080044 ps
CPU time 3.12 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:29:56 PM PDT 24
Peak memory 203728 kb
Host smart-e8b63fd4-63d0-457d-a95c-7f2a5056f684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645031225 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3645031225
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2892123434
Short name T63
Test name
Test status
Simulation time 10052094754 ps
CPU time 87.12 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:31:20 PM PDT 24
Peak memory 655560 kb
Host smart-c8ace1fe-7f5e-4a49-8c0d-aea91cceead0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892123434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2892123434
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1663913658
Short name T992
Test name
Test status
Simulation time 10282779121 ps
CPU time 17.03 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 324756 kb
Host smart-418f5d26-fae6-4add-801e-fe696d0b40b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663913658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1663913658
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3926923247
Short name T995
Test name
Test status
Simulation time 327055893 ps
CPU time 2.16 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:29:54 PM PDT 24
Peak memory 203704 kb
Host smart-b43dca09-3f97-42e8-90c5-6c117d7c1b3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926923247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3926923247
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2402526817
Short name T268
Test name
Test status
Simulation time 5473815970 ps
CPU time 4.75 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:29:58 PM PDT 24
Peak memory 203848 kb
Host smart-3b42b574-2f72-4332-888f-d08b43f80b95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402526817 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2402526817
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2909710698
Short name T394
Test name
Test status
Simulation time 4448726313 ps
CPU time 30.32 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 203824 kb
Host smart-61f7fd13-2ed0-442a-a7c1-bc74f3b2e5c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909710698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2909710698
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2022848353
Short name T430
Test name
Test status
Simulation time 10698657131 ps
CPU time 13.71 seconds
Started Mar 28 03:29:57 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 218996 kb
Host smart-80dfc311-36a1-4448-b0e8-593b6d79ae74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022848353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2022848353
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.4158134490
Short name T740
Test name
Test status
Simulation time 14160674676 ps
CPU time 14.88 seconds
Started Mar 28 03:29:56 PM PDT 24
Finished Mar 28 03:30:11 PM PDT 24
Peak memory 203872 kb
Host smart-0d2feea8-d284-4802-a396-f5426eefe0ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158134490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.4158134490
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1438250215
Short name T1056
Test name
Test status
Simulation time 19704150131 ps
CPU time 445.93 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:37:18 PM PDT 24
Peak memory 2481304 kb
Host smart-469be488-1b65-4fcf-8218-7930499b94ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438250215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1438250215
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3224018941
Short name T1096
Test name
Test status
Simulation time 2075374144 ps
CPU time 6.48 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:30:00 PM PDT 24
Peak memory 216492 kb
Host smart-191b574d-c3e9-421e-bc04-20001a5684d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224018941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3224018941
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.922565720
Short name T663
Test name
Test status
Simulation time 42956999 ps
CPU time 0.61 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:29:59 PM PDT 24
Peak memory 203676 kb
Host smart-0c745ab9-42bc-4351-a49d-2071c730a68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922565720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.922565720
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1944475954
Short name T1073
Test name
Test status
Simulation time 298821573 ps
CPU time 2.06 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:29:55 PM PDT 24
Peak memory 212056 kb
Host smart-a1b4b7fc-d998-43fb-a4e1-b7bc82257c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944475954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1944475954
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3000000000
Short name T624
Test name
Test status
Simulation time 298160180 ps
CPU time 3.59 seconds
Started Mar 28 03:29:56 PM PDT 24
Finished Mar 28 03:29:59 PM PDT 24
Peak memory 235832 kb
Host smart-b00dbb3f-49e2-4093-a3e7-12c49eafe2d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000000000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3000000000
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2409294279
Short name T514
Test name
Test status
Simulation time 9637757053 ps
CPU time 171.8 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:32:44 PM PDT 24
Peak memory 757672 kb
Host smart-b8b2bd6e-5ef5-4777-867d-3bdbfaee9605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409294279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2409294279
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2799975217
Short name T685
Test name
Test status
Simulation time 7096323266 ps
CPU time 61.07 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:30:53 PM PDT 24
Peak memory 617788 kb
Host smart-eafd80f3-7acb-4ea7-b174-2724813b76ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799975217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2799975217
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2270260137
Short name T1046
Test name
Test status
Simulation time 106117425 ps
CPU time 0.87 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 03:29:54 PM PDT 24
Peak memory 203692 kb
Host smart-195309ea-a1e6-4a9e-852d-5bdd0c4726d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270260137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2270260137
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2890744886
Short name T855
Test name
Test status
Simulation time 480134579 ps
CPU time 3.78 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:29:55 PM PDT 24
Peak memory 223376 kb
Host smart-eadabec4-936d-4861-886f-a77dd3a37d3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890744886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2890744886
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3518879181
Short name T981
Test name
Test status
Simulation time 378387563 ps
CPU time 14.79 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:30:13 PM PDT 24
Peak memory 203872 kb
Host smart-02bc1447-8bc4-46cf-9ff2-000bb8662e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518879181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3518879181
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.51861991
Short name T577
Test name
Test status
Simulation time 1055748949 ps
CPU time 53.72 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:30:52 PM PDT 24
Peak memory 336068 kb
Host smart-773e1d1e-384e-4339-8110-b10e7704b81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51861991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.51861991
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2561980476
Short name T171
Test name
Test status
Simulation time 58253449 ps
CPU time 0.7 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:29:52 PM PDT 24
Peak memory 203496 kb
Host smart-4556ac13-4f75-419d-a56e-9c983672e331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561980476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2561980476
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.1653071776
Short name T1088
Test name
Test status
Simulation time 23250082327 ps
CPU time 2715.28 seconds
Started Mar 28 03:29:53 PM PDT 24
Finished Mar 28 04:15:09 PM PDT 24
Peak memory 5499064 kb
Host smart-423ad138-76dd-45c5-b7d1-f24d0b9d54e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653071776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.1653071776
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2329868613
Short name T887
Test name
Test status
Simulation time 5529328242 ps
CPU time 76.88 seconds
Started Mar 28 03:29:50 PM PDT 24
Finished Mar 28 03:31:07 PM PDT 24
Peak memory 309404 kb
Host smart-4c21f28a-fb4a-4f4f-a07b-d8e75028cf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329868613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2329868613
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.407953198
Short name T906
Test name
Test status
Simulation time 727857830 ps
CPU time 3.32 seconds
Started Mar 28 03:29:57 PM PDT 24
Finished Mar 28 03:30:00 PM PDT 24
Peak memory 203820 kb
Host smart-72d2294e-29e4-42fd-b7ec-2d41a81f54ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407953198 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.407953198
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.307989421
Short name T983
Test name
Test status
Simulation time 10040725804 ps
CPU time 111.75 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:31:50 PM PDT 24
Peak memory 593588 kb
Host smart-9491358e-7db5-48db-8081-a6793ed7f7ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307989421 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.307989421
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1621005459
Short name T563
Test name
Test status
Simulation time 10070339289 ps
CPU time 98.2 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:31:32 PM PDT 24
Peak memory 695408 kb
Host smart-ce387964-179a-42f1-9d97-b791fdf1552e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621005459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1621005459
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2422195451
Short name T793
Test name
Test status
Simulation time 1284001652 ps
CPU time 2.03 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:29:56 PM PDT 24
Peak memory 203768 kb
Host smart-48e6b48c-7abc-45e8-bee0-35f4a039322c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422195451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2422195451
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1787028759
Short name T679
Test name
Test status
Simulation time 7678898341 ps
CPU time 7 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:29:59 PM PDT 24
Peak memory 203920 kb
Host smart-3452b745-5342-4b16-932b-62698ca5941f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787028759 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1787028759
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.112197372
Short name T373
Test name
Test status
Simulation time 6037300712 ps
CPU time 2.8 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:29:55 PM PDT 24
Peak memory 203936 kb
Host smart-4f31c655-6cab-4772-99f4-7a150a2bd976
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112197372 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.112197372
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3118819316
Short name T710
Test name
Test status
Simulation time 9371620893 ps
CPU time 12.99 seconds
Started Mar 28 03:29:57 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 203848 kb
Host smart-a68d3eac-d34a-4091-a022-4115fd304c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118819316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3118819316
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2185385955
Short name T339
Test name
Test status
Simulation time 393161232 ps
CPU time 16.19 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 03:30:08 PM PDT 24
Peak memory 203800 kb
Host smart-3a19c19f-acec-42f8-ae87-57d82b7015ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185385955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2185385955
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2650842137
Short name T377
Test name
Test status
Simulation time 50980391251 ps
CPU time 392.07 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:36:26 PM PDT 24
Peak memory 2749608 kb
Host smart-d85d87ce-07da-42ec-b2b6-7453e47a9bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650842137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2650842137
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.335531506
Short name T540
Test name
Test status
Simulation time 3165198600 ps
CPU time 8.79 seconds
Started Mar 28 03:33:06 PM PDT 24
Finished Mar 28 03:33:15 PM PDT 24
Peak memory 213688 kb
Host smart-2feebd45-25ac-422b-8092-83cf000fdfbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335531506 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_timeout.335531506
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3935919509
Short name T382
Test name
Test status
Simulation time 37533854 ps
CPU time 0.6 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:30:18 PM PDT 24
Peak memory 203676 kb
Host smart-8fd023f6-ae1c-417b-81d5-73fde67e5b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935919509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3935919509
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.4201645202
Short name T389
Test name
Test status
Simulation time 367386441 ps
CPU time 1.41 seconds
Started Mar 28 03:30:00 PM PDT 24
Finished Mar 28 03:30:02 PM PDT 24
Peak memory 212032 kb
Host smart-d7282ddb-79ab-4ee6-b4e0-ca2ec73a2071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201645202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.4201645202
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1813877508
Short name T697
Test name
Test status
Simulation time 1006316886 ps
CPU time 5.21 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:30:03 PM PDT 24
Peak memory 255456 kb
Host smart-27443b5d-3f90-42aa-bc7b-0be1e4b1a0d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813877508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1813877508
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2584488947
Short name T59
Test name
Test status
Simulation time 1852043711 ps
CPU time 135.24 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:32:09 PM PDT 24
Peak memory 627832 kb
Host smart-5b060861-3e3f-450b-a7e7-07b54b083ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584488947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2584488947
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.44526677
Short name T1121
Test name
Test status
Simulation time 2570596551 ps
CPU time 37.93 seconds
Started Mar 28 03:29:52 PM PDT 24
Finished Mar 28 03:30:30 PM PDT 24
Peak memory 511056 kb
Host smart-906ccdbe-2d38-4d35-94cb-9669ed254d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44526677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.44526677
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.4132853081
Short name T941
Test name
Test status
Simulation time 868627093 ps
CPU time 1.09 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:29:59 PM PDT 24
Peak memory 203828 kb
Host smart-2d682bed-6bb6-4bb5-be24-f7ff78e51f4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132853081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.4132853081
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1525575
Short name T83
Test name
Test status
Simulation time 183205867 ps
CPU time 9.1 seconds
Started Mar 28 03:30:00 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 203852 kb
Host smart-2cab10d1-04f4-4734-a7d3-ebcac7e560db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.1525575
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1270224305
Short name T742
Test name
Test status
Simulation time 25410572104 ps
CPU time 153.84 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 1341444 kb
Host smart-c5260832-deab-4d5b-82b9-119571e16eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270224305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1270224305
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2699738631
Short name T343
Test name
Test status
Simulation time 4870865778 ps
CPU time 11.61 seconds
Started Mar 28 03:30:14 PM PDT 24
Finished Mar 28 03:30:26 PM PDT 24
Peak memory 203916 kb
Host smart-32a63199-2f71-4b7c-b00c-cfd58abf1142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699738631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2699738631
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2992802245
Short name T555
Test name
Test status
Simulation time 5560363713 ps
CPU time 32.49 seconds
Started Mar 28 03:30:16 PM PDT 24
Finished Mar 28 03:30:49 PM PDT 24
Peak memory 376528 kb
Host smart-e2d1596a-8330-45a4-8d82-32c6b6e0dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992802245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2992802245
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.3552066719
Short name T853
Test name
Test status
Simulation time 27913568 ps
CPU time 0.67 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:29:59 PM PDT 24
Peak memory 203600 kb
Host smart-ce0623ae-4c09-4711-8296-ce9b7986bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552066719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.3552066719
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2482312924
Short name T324
Test name
Test status
Simulation time 7455447950 ps
CPU time 427.88 seconds
Started Mar 28 03:30:00 PM PDT 24
Finished Mar 28 03:37:09 PM PDT 24
Peak memory 594936 kb
Host smart-0a192feb-c758-4b71-8ce9-679b62582ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482312924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2482312924
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1237047459
Short name T317
Test name
Test status
Simulation time 3119795150 ps
CPU time 38.32 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:59 PM PDT 24
Peak memory 280980 kb
Host smart-852e5b9c-5631-4315-988e-68d209bb2e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237047459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1237047459
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.4028074734
Short name T662
Test name
Test status
Simulation time 27751361328 ps
CPU time 2400.06 seconds
Started Mar 28 03:29:51 PM PDT 24
Finished Mar 28 04:09:52 PM PDT 24
Peak memory 2735200 kb
Host smart-4568c770-6233-4d52-b8a0-3b08fa8a77ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028074734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.4028074734
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2374514097
Short name T357
Test name
Test status
Simulation time 886415201 ps
CPU time 3.88 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:25 PM PDT 24
Peak memory 203740 kb
Host smart-a884be0e-a660-4763-828e-4cf5a21a527d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374514097 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2374514097
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3955525520
Short name T768
Test name
Test status
Simulation time 10231324907 ps
CPU time 20.12 seconds
Started Mar 28 03:30:14 PM PDT 24
Finished Mar 28 03:30:34 PM PDT 24
Peak memory 313100 kb
Host smart-2af1b416-ff30-4b2b-890d-00ad92b5ca60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955525520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3955525520
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.283580514
Short name T60
Test name
Test status
Simulation time 10062464346 ps
CPU time 41.14 seconds
Started Mar 28 03:30:16 PM PDT 24
Finished Mar 28 03:30:58 PM PDT 24
Peak memory 458376 kb
Host smart-fe3bbd76-5964-4395-8759-bd975355d05e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283580514 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.283580514
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1897286291
Short name T522
Test name
Test status
Simulation time 728939047 ps
CPU time 2.44 seconds
Started Mar 28 03:30:16 PM PDT 24
Finished Mar 28 03:30:19 PM PDT 24
Peak memory 203848 kb
Host smart-6fcb0634-c681-444d-8d68-3bbb19012ebd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897286291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1897286291
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2535953848
Short name T474
Test name
Test status
Simulation time 1232047606 ps
CPU time 5.34 seconds
Started Mar 28 03:29:59 PM PDT 24
Finished Mar 28 03:30:05 PM PDT 24
Peak memory 212020 kb
Host smart-7e44bdee-1b82-4537-ad9e-b5a5a3c9991f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535953848 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2535953848
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3085808934
Short name T1057
Test name
Test status
Simulation time 9591103473 ps
CPU time 5.33 seconds
Started Mar 28 03:30:00 PM PDT 24
Finished Mar 28 03:30:05 PM PDT 24
Peak memory 203836 kb
Host smart-c68d9884-5527-48e6-a76d-23c529450ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085808934 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3085808934
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2281419405
Short name T938
Test name
Test status
Simulation time 3462365823 ps
CPU time 10.05 seconds
Started Mar 28 03:30:00 PM PDT 24
Finished Mar 28 03:30:10 PM PDT 24
Peak memory 203868 kb
Host smart-39bed079-c55e-472f-997d-d35cb14b2303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281419405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2281419405
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2542205268
Short name T1068
Test name
Test status
Simulation time 370107221 ps
CPU time 6.29 seconds
Started Mar 28 03:29:58 PM PDT 24
Finished Mar 28 03:30:04 PM PDT 24
Peak memory 203876 kb
Host smart-c031b6d8-26d9-4f47-af4f-dee071901473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542205268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2542205268
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2944914062
Short name T1090
Test name
Test status
Simulation time 33268550417 ps
CPU time 1020.39 seconds
Started Mar 28 03:29:54 PM PDT 24
Finished Mar 28 03:46:55 PM PDT 24
Peak memory 3942380 kb
Host smart-3f2b506e-26f7-419b-97c0-7773640d18ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944914062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2944914062
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2506449125
Short name T109
Test name
Test status
Simulation time 1242744918 ps
CPU time 6.72 seconds
Started Mar 28 03:29:59 PM PDT 24
Finished Mar 28 03:30:06 PM PDT 24
Peak memory 212040 kb
Host smart-482412a1-3e16-42c7-95d6-7aa87208ede8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506449125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2506449125
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1279552840
Short name T245
Test name
Test status
Simulation time 17007903 ps
CPU time 0.65 seconds
Started Mar 28 03:30:15 PM PDT 24
Finished Mar 28 03:30:17 PM PDT 24
Peak memory 203408 kb
Host smart-8647a677-4543-4558-a6b6-4ef7b2d08899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279552840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1279552840
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2911793578
Short name T456
Test name
Test status
Simulation time 64559894 ps
CPU time 1.26 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:21 PM PDT 24
Peak memory 212056 kb
Host smart-8a7dd847-35e8-4543-bcc2-deb629bbd2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911793578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2911793578
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3515583945
Short name T638
Test name
Test status
Simulation time 1286168044 ps
CPU time 6.7 seconds
Started Mar 28 03:30:15 PM PDT 24
Finished Mar 28 03:30:22 PM PDT 24
Peak memory 263280 kb
Host smart-10fdf92e-f272-46fd-b000-3780feff8573
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515583945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3515583945
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2754392857
Short name T1128
Test name
Test status
Simulation time 6327129889 ps
CPU time 59.12 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:31:18 PM PDT 24
Peak memory 599324 kb
Host smart-a6aa8eca-db89-49f0-a84d-acbfd3f119f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754392857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2754392857
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.812642318
Short name T1181
Test name
Test status
Simulation time 3224976952 ps
CPU time 58.68 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:31:19 PM PDT 24
Peak memory 629968 kb
Host smart-b87024ac-3e2c-450f-8688-3351d3a07b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812642318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.812642318
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.195165136
Short name T427
Test name
Test status
Simulation time 552473722 ps
CPU time 1.11 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:30:19 PM PDT 24
Peak memory 203644 kb
Host smart-7d1ff33e-f8bf-426b-84e7-cb9ea4118093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195165136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.195165136
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3648571054
Short name T813
Test name
Test status
Simulation time 120947372 ps
CPU time 3.12 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:30:21 PM PDT 24
Peak memory 203812 kb
Host smart-716b4877-7b71-4c23-8c3c-ff89cde677ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648571054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3648571054
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.373466128
Short name T659
Test name
Test status
Simulation time 3099044910 ps
CPU time 138.46 seconds
Started Mar 28 03:30:13 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 698164 kb
Host smart-ecee0226-4075-4ec7-9f94-7647603b4bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373466128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.373466128
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1398352621
Short name T431
Test name
Test status
Simulation time 336134104 ps
CPU time 4.49 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:30:22 PM PDT 24
Peak memory 203748 kb
Host smart-eb4e11c5-f7bf-4c5c-80c3-89961fe7132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398352621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1398352621
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2849839664
Short name T173
Test name
Test status
Simulation time 915035302 ps
CPU time 38.95 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:59 PM PDT 24
Peak memory 298296 kb
Host smart-c8aa48ee-c2d6-441f-a398-27cb9af3d1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849839664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2849839664
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1140083820
Short name T390
Test name
Test status
Simulation time 94143340 ps
CPU time 0.65 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:21 PM PDT 24
Peak memory 203608 kb
Host smart-391f814f-e647-450d-9945-3e623e9e5259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140083820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1140083820
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.33028095
Short name T476
Test name
Test status
Simulation time 7604338965 ps
CPU time 139.33 seconds
Started Mar 28 03:30:15 PM PDT 24
Finished Mar 28 03:32:35 PM PDT 24
Peak memory 1002956 kb
Host smart-88a76b6b-96fb-4607-93d3-7857785cb4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33028095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.33028095
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3738768771
Short name T705
Test name
Test status
Simulation time 15760802081 ps
CPU time 47.9 seconds
Started Mar 28 03:30:13 PM PDT 24
Finished Mar 28 03:31:01 PM PDT 24
Peak memory 332592 kb
Host smart-70f98511-fd75-4970-a84b-0c2b258c4963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738768771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3738768771
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.289313155
Short name T658
Test name
Test status
Simulation time 4039742633 ps
CPU time 4.44 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 204140 kb
Host smart-b633f41f-df3f-4353-b125-768d4dce84cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289313155 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.289313155
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3799838975
Short name T429
Test name
Test status
Simulation time 10146573785 ps
CPU time 73.69 seconds
Started Mar 28 03:30:15 PM PDT 24
Finished Mar 28 03:31:29 PM PDT 24
Peak memory 550496 kb
Host smart-7339ecad-74f9-42e0-b001-f28967428bd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799838975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3799838975
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.851508097
Short name T441
Test name
Test status
Simulation time 10247769793 ps
CPU time 19.79 seconds
Started Mar 28 03:30:16 PM PDT 24
Finished Mar 28 03:30:36 PM PDT 24
Peak memory 349292 kb
Host smart-96034424-23d3-4572-b2d9-9ae20057e488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851508097 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.851508097
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2252439242
Short name T50
Test name
Test status
Simulation time 982811133 ps
CPU time 2.88 seconds
Started Mar 28 03:30:15 PM PDT 24
Finished Mar 28 03:30:18 PM PDT 24
Peak memory 203792 kb
Host smart-7a2eb441-1b9b-4014-8052-8c5f789add4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252439242 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2252439242
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1296883350
Short name T578
Test name
Test status
Simulation time 4806916482 ps
CPU time 5.65 seconds
Started Mar 28 03:30:15 PM PDT 24
Finished Mar 28 03:30:21 PM PDT 24
Peak memory 220048 kb
Host smart-ffbb80d6-84d6-4ffd-8309-55825abddec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296883350 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1296883350
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3463478702
Short name T374
Test name
Test status
Simulation time 484537368 ps
CPU time 7.54 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:30:25 PM PDT 24
Peak memory 203760 kb
Host smart-62b8fb9c-cb15-4cbb-b35c-1f95982d299c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463478702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3463478702
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.194604964
Short name T874
Test name
Test status
Simulation time 1559973989 ps
CPU time 33.21 seconds
Started Mar 28 03:30:16 PM PDT 24
Finished Mar 28 03:30:50 PM PDT 24
Peak memory 203852 kb
Host smart-34e7c170-c175-493a-8721-26531da67709
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194604964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.194604964
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2393991019
Short name T969
Test name
Test status
Simulation time 26772707768 ps
CPU time 1334.72 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:52:34 PM PDT 24
Peak memory 4435676 kb
Host smart-7293ff5e-ee43-4cd4-8f8d-b13eb0c554da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393991019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2393991019
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.351705350
Short name T1186
Test name
Test status
Simulation time 1622476949 ps
CPU time 8.55 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:30:26 PM PDT 24
Peak memory 219120 kb
Host smart-a592145a-8569-4df0-ba81-8892d0ea7cef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351705350 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.351705350
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.99449921
Short name T863
Test name
Test status
Simulation time 19029070 ps
CPU time 0.65 seconds
Started Mar 28 03:30:23 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 203712 kb
Host smart-9ab50ea2-cbbf-454e-b731-7a9bd5a61315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99449921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.99449921
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3548463588
Short name T732
Test name
Test status
Simulation time 260704784 ps
CPU time 1.86 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:23 PM PDT 24
Peak memory 212004 kb
Host smart-5caf5a59-7abb-4438-bebd-37b77cf848e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548463588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3548463588
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2829910043
Short name T533
Test name
Test status
Simulation time 167885703 ps
CPU time 3.33 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:23 PM PDT 24
Peak memory 235108 kb
Host smart-b307ec45-4d5a-43b6-b6a5-34b8ccd28bca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829910043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2829910043
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.451023356
Short name T1113
Test name
Test status
Simulation time 10770689180 ps
CPU time 32.14 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:50 PM PDT 24
Peak memory 371064 kb
Host smart-dbc253e0-e8f3-4c42-ae5f-03aa88345475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451023356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.451023356
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3537724963
Short name T617
Test name
Test status
Simulation time 6878005764 ps
CPU time 60.2 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:31:18 PM PDT 24
Peak memory 631212 kb
Host smart-7e5ecb1a-d71e-4e8c-b9f3-99c37f53c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537724963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3537724963
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1995330985
Short name T1041
Test name
Test status
Simulation time 1131121086 ps
CPU time 1.16 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:21 PM PDT 24
Peak memory 203848 kb
Host smart-fa8425ac-c736-430b-80b9-ed31351f1ec0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995330985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1995330985
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.4104745853
Short name T886
Test name
Test status
Simulation time 223190312 ps
CPU time 3.16 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 219756 kb
Host smart-000b9552-aa4e-45ae-a274-57c2de9fa430
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104745853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.4104745853
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.881648349
Short name T868
Test name
Test status
Simulation time 3266005808 ps
CPU time 238.54 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:34:20 PM PDT 24
Peak memory 1015896 kb
Host smart-488b41eb-d273-421a-a0ff-3df67d326601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881648349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.881648349
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2168773414
Short name T333
Test name
Test status
Simulation time 4244444536 ps
CPU time 17.18 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:37 PM PDT 24
Peak memory 203884 kb
Host smart-94df5eee-6535-493b-8387-774d65e7b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168773414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2168773414
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.946479775
Short name T616
Test name
Test status
Simulation time 7890277483 ps
CPU time 33.62 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:52 PM PDT 24
Peak memory 366228 kb
Host smart-9fd0da4b-6647-4b15-8bdb-15e1caaf196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946479775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.946479775
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2279512148
Short name T1017
Test name
Test status
Simulation time 76450113 ps
CPU time 0.67 seconds
Started Mar 28 03:30:14 PM PDT 24
Finished Mar 28 03:30:15 PM PDT 24
Peak memory 203552 kb
Host smart-0bce7760-270a-404e-b57c-1074b06f2161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279512148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2279512148
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.471461557
Short name T310
Test name
Test status
Simulation time 49985275683 ps
CPU time 492.63 seconds
Started Mar 28 03:30:15 PM PDT 24
Finished Mar 28 03:38:28 PM PDT 24
Peak memory 1546844 kb
Host smart-6f72ce71-1de5-4e93-90f2-30eda8d050cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471461557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.471461557
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.964000020
Short name T703
Test name
Test status
Simulation time 1096605191 ps
CPU time 56.92 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:31:15 PM PDT 24
Peak memory 365128 kb
Host smart-8dfd7722-4dcf-465d-95e4-18f730a5dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964000020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.964000020
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3690854917
Short name T621
Test name
Test status
Simulation time 826997664 ps
CPU time 2.89 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 203892 kb
Host smart-41f05200-0402-4728-bf73-fdf57ee4de8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690854917 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3690854917
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2690315233
Short name T332
Test name
Test status
Simulation time 10043223228 ps
CPU time 75.72 seconds
Started Mar 28 03:30:22 PM PDT 24
Finished Mar 28 03:31:38 PM PDT 24
Peak memory 569980 kb
Host smart-f014dc46-6664-4036-a26e-1841073a725f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690315233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2690315233
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2767705946
Short name T335
Test name
Test status
Simulation time 10067374148 ps
CPU time 92.95 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:31:55 PM PDT 24
Peak memory 668924 kb
Host smart-db1e5fa1-bc53-49f6-8772-0a418e5cc35b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767705946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2767705946
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2254908542
Short name T1084
Test name
Test status
Simulation time 473632598 ps
CPU time 2.16 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:30:23 PM PDT 24
Peak memory 203820 kb
Host smart-3c93d3a1-9ae1-4f45-87f6-07dfd4bce52b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254908542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2254908542
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3107635184
Short name T928
Test name
Test status
Simulation time 1665850394 ps
CPU time 4.74 seconds
Started Mar 28 03:30:16 PM PDT 24
Finished Mar 28 03:30:21 PM PDT 24
Peak memory 205688 kb
Host smart-ad804a00-9ef6-4ecf-8b28-de2c52183450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107635184 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3107635184
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.2422191474
Short name T666
Test name
Test status
Simulation time 6639744846 ps
CPU time 3.15 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 203888 kb
Host smart-4e78b1b5-1e70-42a9-b513-95e83258a019
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422191474 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.2422191474
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2735833102
Short name T87
Test name
Test status
Simulation time 995024469 ps
CPU time 16.29 seconds
Started Mar 28 03:30:16 PM PDT 24
Finished Mar 28 03:30:33 PM PDT 24
Peak memory 203784 kb
Host smart-8935b256-7090-4701-92f9-aa36c2a5e3c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735833102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2735833102
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2218241711
Short name T369
Test name
Test status
Simulation time 5760920942 ps
CPU time 13.73 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:32 PM PDT 24
Peak memory 214428 kb
Host smart-7050670f-b926-4f27-ba82-5122d85cd157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218241711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2218241711
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3434264350
Short name T1153
Test name
Test status
Simulation time 8352345358 ps
CPU time 5.21 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:25 PM PDT 24
Peak memory 203936 kb
Host smart-87a3930f-f8d6-4fcb-bc52-d6f15e56cda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434264350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3434264350
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3120747375
Short name T967
Test name
Test status
Simulation time 44015394355 ps
CPU time 315.42 seconds
Started Mar 28 03:30:20 PM PDT 24
Finished Mar 28 03:35:36 PM PDT 24
Peak memory 2350312 kb
Host smart-d8d15f6d-1c7e-4cfe-93ab-cd1ee1d48df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120747375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3120747375
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.63338907
Short name T704
Test name
Test status
Simulation time 10185026396 ps
CPU time 7.21 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:27 PM PDT 24
Peak memory 218976 kb
Host smart-d7633bb8-6d85-45f6-ae55-af8038fde5d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63338907 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_timeout.63338907
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3826223618
Short name T398
Test name
Test status
Simulation time 21940867 ps
CPU time 0.65 seconds
Started Mar 28 03:30:14 PM PDT 24
Finished Mar 28 03:30:15 PM PDT 24
Peak memory 203648 kb
Host smart-6b95a064-5b81-42c9-aa92-4b83e8abd13b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826223618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3826223618
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.552886230
Short name T391
Test name
Test status
Simulation time 382951116 ps
CPU time 1.77 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:30:23 PM PDT 24
Peak memory 203808 kb
Host smart-d9d41aec-69bd-4926-ba19-68a9a63b7432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552886230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.552886230
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2229613020
Short name T690
Test name
Test status
Simulation time 331208365 ps
CPU time 8.59 seconds
Started Mar 28 03:30:23 PM PDT 24
Finished Mar 28 03:30:31 PM PDT 24
Peak memory 233884 kb
Host smart-17b3d070-25a9-44fc-b922-2d192bbbb062
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229613020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2229613020
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3701536736
Short name T229
Test name
Test status
Simulation time 2576596889 ps
CPU time 81.2 seconds
Started Mar 28 03:30:20 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 792832 kb
Host smart-60509bd7-8b70-446b-9c0d-1ca3a5be7fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701536736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3701536736
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1486788978
Short name T92
Test name
Test status
Simulation time 3638698022 ps
CPU time 55.68 seconds
Started Mar 28 03:30:23 PM PDT 24
Finished Mar 28 03:31:19 PM PDT 24
Peak memory 578620 kb
Host smart-b324dd40-839e-40fb-bc4e-84044da5d9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486788978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1486788978
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.972195257
Short name T359
Test name
Test status
Simulation time 754891805 ps
CPU time 0.94 seconds
Started Mar 28 03:30:23 PM PDT 24
Finished Mar 28 03:30:25 PM PDT 24
Peak memory 203244 kb
Host smart-3e91048c-8465-4a22-adbf-1b804be7bb42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972195257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.972195257
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.4228214449
Short name T796
Test name
Test status
Simulation time 144126851 ps
CPU time 4.11 seconds
Started Mar 28 03:30:19 PM PDT 24
Finished Mar 28 03:30:25 PM PDT 24
Peak memory 203852 kb
Host smart-895ad14c-32df-440b-bb47-cd7410ecfb64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228214449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.4228214449
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.4121332664
Short name T592
Test name
Test status
Simulation time 17191899323 ps
CPU time 138.74 seconds
Started Mar 28 03:30:23 PM PDT 24
Finished Mar 28 03:32:42 PM PDT 24
Peak memory 1275220 kb
Host smart-271cabac-ca53-4eb0-945a-ff056ce432d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121332664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.4121332664
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.189021906
Short name T558
Test name
Test status
Simulation time 1754328198 ps
CPU time 16.28 seconds
Started Mar 28 03:30:17 PM PDT 24
Finished Mar 28 03:30:34 PM PDT 24
Peak memory 203792 kb
Host smart-36e442c2-9f44-4312-93a7-e9595d02b1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189021906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.189021906
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.929563434
Short name T726
Test name
Test status
Simulation time 3670768617 ps
CPU time 13.97 seconds
Started Mar 28 03:30:20 PM PDT 24
Finished Mar 28 03:30:35 PM PDT 24
Peak memory 290840 kb
Host smart-e3da9b07-ddea-4342-8442-bbf9ce7c14ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929563434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.929563434
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1191009826
Short name T752
Test name
Test status
Simulation time 28978568693 ps
CPU time 72.15 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:31:34 PM PDT 24
Peak memory 370292 kb
Host smart-f95de4f0-5843-4219-9b9b-c92f06ca1bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191009826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1191009826
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2494620716
Short name T711
Test name
Test status
Simulation time 2289493017 ps
CPU time 22.88 seconds
Started Mar 28 03:30:18 PM PDT 24
Finished Mar 28 03:30:43 PM PDT 24
Peak memory 353692 kb
Host smart-d4477292-5259-4852-b2a6-3cfd8847d52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494620716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2494620716
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.796567579
Short name T1099
Test name
Test status
Simulation time 535089759 ps
CPU time 2.98 seconds
Started Mar 28 03:30:20 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 203848 kb
Host smart-805965c3-d6f2-4fa7-9a5b-8d080c945c37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796567579 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.796567579
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3745039716
Short name T191
Test name
Test status
Simulation time 10341135576 ps
CPU time 15.6 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:30:38 PM PDT 24
Peak memory 322284 kb
Host smart-0c464fd8-ce9c-43c6-a49d-9775a78368dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745039716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3745039716
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.719494991
Short name T48
Test name
Test status
Simulation time 726198722 ps
CPU time 1.64 seconds
Started Mar 28 03:30:22 PM PDT 24
Finished Mar 28 03:30:24 PM PDT 24
Peak memory 203772 kb
Host smart-a15f6e09-2e61-4a4c-be1b-46c5d00a8542
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719494991 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.719494991
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3265941022
Short name T670
Test name
Test status
Simulation time 880869662 ps
CPU time 5.13 seconds
Started Mar 28 03:30:20 PM PDT 24
Finished Mar 28 03:30:26 PM PDT 24
Peak memory 218056 kb
Host smart-3b3aee0d-7c11-437e-8951-55305a3f134b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265941022 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3265941022
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.397598648
Short name T444
Test name
Test status
Simulation time 678374640 ps
CPU time 11.05 seconds
Started Mar 28 03:30:20 PM PDT 24
Finished Mar 28 03:30:32 PM PDT 24
Peak memory 203492 kb
Host smart-be11a1ef-c38c-45c7-ac06-63c3e3827729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397598648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.397598648
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.302957851
Short name T286
Test name
Test status
Simulation time 3572586773 ps
CPU time 35.5 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:30:56 PM PDT 24
Peak memory 231080 kb
Host smart-a70976b3-bf2e-4187-9b77-f7b165b4275a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302957851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.302957851
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3786499072
Short name T945
Test name
Test status
Simulation time 11397129592 ps
CPU time 139.34 seconds
Started Mar 28 03:30:20 PM PDT 24
Finished Mar 28 03:32:40 PM PDT 24
Peak memory 1337824 kb
Host smart-2f0676e9-9e47-47d7-9a8a-71480b4636ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786499072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3786499072
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1511338275
Short name T348
Test name
Test status
Simulation time 1485241862 ps
CPU time 7.23 seconds
Started Mar 28 03:30:21 PM PDT 24
Finished Mar 28 03:30:28 PM PDT 24
Peak memory 203864 kb
Host smart-29b84fb8-a5fa-4526-964e-e1efd4dcdeef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511338275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1511338275
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2636399860
Short name T482
Test name
Test status
Simulation time 16298122 ps
CPU time 0.65 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:30:37 PM PDT 24
Peak memory 203704 kb
Host smart-24e37285-ac96-43f7-8553-04fe564fe8cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636399860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2636399860
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2911157936
Short name T850
Test name
Test status
Simulation time 164586741 ps
CPU time 1.29 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:30:36 PM PDT 24
Peak memory 211980 kb
Host smart-b8df422b-b1a0-48b7-8beb-e1e5ada17e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911157936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2911157936
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.385584173
Short name T835
Test name
Test status
Simulation time 509684181 ps
CPU time 13.43 seconds
Started Mar 28 03:30:38 PM PDT 24
Finished Mar 28 03:30:52 PM PDT 24
Peak memory 254344 kb
Host smart-347ad95b-1cbc-47be-8bc4-a468e8fb0d35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385584173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.385584173
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3368687184
Short name T988
Test name
Test status
Simulation time 8886180812 ps
CPU time 67.75 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 734536 kb
Host smart-5ac03381-7e9b-4f92-8562-60d536f47dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368687184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3368687184
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1965221981
Short name T797
Test name
Test status
Simulation time 1730330131 ps
CPU time 52.64 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:31:34 PM PDT 24
Peak memory 631444 kb
Host smart-6105e0d7-cbea-4a4f-bed9-faf0bae4acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965221981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1965221981
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.836293188
Short name T832
Test name
Test status
Simulation time 114515546 ps
CPU time 0.96 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:30:37 PM PDT 24
Peak memory 203680 kb
Host smart-74ae7389-2939-4d3f-89fa-a93bf28a73ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836293188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.836293188
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1312424716
Short name T406
Test name
Test status
Simulation time 140746532 ps
CPU time 3.38 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:30:38 PM PDT 24
Peak memory 224792 kb
Host smart-f301058c-5737-4acb-967f-4ea3185ac410
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312424716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1312424716
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1844674595
Short name T2
Test name
Test status
Simulation time 2369541540 ps
CPU time 154.54 seconds
Started Mar 28 03:30:39 PM PDT 24
Finished Mar 28 03:33:14 PM PDT 24
Peak memory 715408 kb
Host smart-7ee738d6-4378-4344-97dc-0c811476e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844674595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1844674595
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.830704053
Short name T512
Test name
Test status
Simulation time 311040498 ps
CPU time 12.09 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:30:54 PM PDT 24
Peak memory 203756 kb
Host smart-1b5cdebb-7163-4513-b1f8-38268a47f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830704053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.830704053
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.1279931593
Short name T1103
Test name
Test status
Simulation time 24005501852 ps
CPU time 47.03 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 448592 kb
Host smart-166d6195-121a-4222-9009-f31e2b0a1da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279931593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.1279931593
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.907955305
Short name T831
Test name
Test status
Simulation time 48746867 ps
CPU time 0.66 seconds
Started Mar 28 03:30:38 PM PDT 24
Finished Mar 28 03:30:38 PM PDT 24
Peak memory 203588 kb
Host smart-fda0def3-9c7e-4010-90cc-ac94f7748f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907955305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.907955305
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2415025172
Short name T531
Test name
Test status
Simulation time 6823016987 ps
CPU time 319.19 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:36:01 PM PDT 24
Peak memory 1637836 kb
Host smart-f1354eb2-b800-4627-8aca-137779f7f525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415025172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2415025172
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2821937131
Short name T221
Test name
Test status
Simulation time 4096455235 ps
CPU time 15.88 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:30:57 PM PDT 24
Peak memory 280788 kb
Host smart-80886e2f-c169-410b-80c2-3f6ac94947fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821937131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2821937131
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3765232024
Short name T772
Test name
Test status
Simulation time 2781951076 ps
CPU time 4.09 seconds
Started Mar 28 03:30:32 PM PDT 24
Finished Mar 28 03:30:36 PM PDT 24
Peak memory 203892 kb
Host smart-f3797c3f-feff-40b4-ac5a-5e44e7f4cb9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765232024 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3765232024
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3785818110
Short name T66
Test name
Test status
Simulation time 10077817740 ps
CPU time 81.75 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 605852 kb
Host smart-d1a8c08b-588c-4f35-8c13-bea032046248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785818110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3785818110
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3694470207
Short name T1011
Test name
Test status
Simulation time 10094412124 ps
CPU time 74.55 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 622984 kb
Host smart-35f22b2a-845c-4504-b0b4-5e6cf9fc4ff6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694470207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3694470207
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.540165271
Short name T822
Test name
Test status
Simulation time 943882024 ps
CPU time 2.92 seconds
Started Mar 28 03:30:33 PM PDT 24
Finished Mar 28 03:30:37 PM PDT 24
Peak memory 203716 kb
Host smart-80fe5bb8-dfc8-407b-bd7a-af894a39e2d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540165271 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.540165271
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2334356630
Short name T1189
Test name
Test status
Simulation time 6348224247 ps
CPU time 7.76 seconds
Started Mar 28 03:30:35 PM PDT 24
Finished Mar 28 03:30:43 PM PDT 24
Peak memory 210892 kb
Host smart-34820ce8-50d5-44c2-b79e-3b01fb6749ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334356630 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2334356630
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.3471592323
Short name T565
Test name
Test status
Simulation time 2688592004 ps
CPU time 5.37 seconds
Started Mar 28 03:30:38 PM PDT 24
Finished Mar 28 03:30:44 PM PDT 24
Peak memory 203832 kb
Host smart-d199dd03-be60-4f85-b77d-705fe63f1f75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471592323 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.3471592323
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.373926660
Short name T322
Test name
Test status
Simulation time 1274571790 ps
CPU time 8.08 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:30:42 PM PDT 24
Peak memory 203804 kb
Host smart-30b63c3a-2ba8-4a74-b63e-1aeb66d6584c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373926660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.373926660
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.291585581
Short name T948
Test name
Test status
Simulation time 1080844555 ps
CPU time 16.49 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:30:58 PM PDT 24
Peak memory 218428 kb
Host smart-4bc77fbc-ed9d-42ac-86fa-50b00bc36630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291585581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.291585581
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1124723855
Short name T919
Test name
Test status
Simulation time 11572703201 ps
CPU time 13.35 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:30:48 PM PDT 24
Peak memory 203860 kb
Host smart-58af2259-5146-435c-9b9a-b36ee53843f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124723855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1124723855
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3988572198
Short name T53
Test name
Test status
Simulation time 34079519163 ps
CPU time 283.55 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:35:20 PM PDT 24
Peak memory 1917648 kb
Host smart-be612295-11c7-434b-86a7-aeb3653a7c25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988572198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3988572198
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2205050685
Short name T557
Test name
Test status
Simulation time 4215998021 ps
CPU time 6.27 seconds
Started Mar 28 03:30:35 PM PDT 24
Finished Mar 28 03:30:42 PM PDT 24
Peak memory 203860 kb
Host smart-11cbfaef-ed5a-45f3-ad34-3978d3b9165f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205050685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2205050685
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3601832751
Short name T158
Test name
Test status
Simulation time 27892196 ps
CPU time 0.62 seconds
Started Mar 28 03:30:38 PM PDT 24
Finished Mar 28 03:30:39 PM PDT 24
Peak memory 203640 kb
Host smart-da276741-81ce-4e47-97cf-917ec202a531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601832751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3601832751
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1482744233
Short name T830
Test name
Test status
Simulation time 92571505 ps
CPU time 1.54 seconds
Started Mar 28 03:30:38 PM PDT 24
Finished Mar 28 03:30:39 PM PDT 24
Peak memory 212076 kb
Host smart-9a94b698-3dd1-4e40-bb86-3a7fe6de6fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482744233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1482744233
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.182831811
Short name T604
Test name
Test status
Simulation time 1378534357 ps
CPU time 5.16 seconds
Started Mar 28 03:30:33 PM PDT 24
Finished Mar 28 03:30:39 PM PDT 24
Peak memory 255272 kb
Host smart-28204181-611e-42c3-9fb8-8b21ddab3ab9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182831811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.182831811
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3523479031
Short name T403
Test name
Test status
Simulation time 4507880643 ps
CPU time 49.79 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:31:26 PM PDT 24
Peak memory 556460 kb
Host smart-e65aed48-31bc-4561-9d8f-35befc9f6525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523479031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3523479031
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3484233106
Short name T1123
Test name
Test status
Simulation time 1501685819 ps
CPU time 40 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:31:14 PM PDT 24
Peak memory 558812 kb
Host smart-6ca16efd-5225-4b58-84b5-c5c01ac2d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484233106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3484233106
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2518495531
Short name T600
Test name
Test status
Simulation time 765793454 ps
CPU time 0.96 seconds
Started Mar 28 03:30:39 PM PDT 24
Finished Mar 28 03:30:40 PM PDT 24
Peak memory 203740 kb
Host smart-e7b33005-cda0-4f69-ad67-e20ec3918426
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518495531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2518495531
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.2188064037
Short name T380
Test name
Test status
Simulation time 1333632812 ps
CPU time 3.62 seconds
Started Mar 28 03:30:37 PM PDT 24
Finished Mar 28 03:30:41 PM PDT 24
Peak memory 203788 kb
Host smart-ea5574e4-1d26-431b-a1b2-5165562bbe19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188064037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.2188064037
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.291554081
Short name T147
Test name
Test status
Simulation time 4328204147 ps
CPU time 112.11 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:32:34 PM PDT 24
Peak memory 1246056 kb
Host smart-2e677897-592f-4d78-adc5-2df0598257ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291554081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.291554081
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2036654936
Short name T743
Test name
Test status
Simulation time 936200609 ps
CPU time 18.05 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:31:00 PM PDT 24
Peak memory 203828 kb
Host smart-dd0e544a-d3b0-46f5-8deb-65386a3a3f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036654936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2036654936
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.574979871
Short name T486
Test name
Test status
Simulation time 1789189880 ps
CPU time 95.53 seconds
Started Mar 28 03:30:37 PM PDT 24
Finished Mar 28 03:32:13 PM PDT 24
Peak memory 398720 kb
Host smart-4edf630e-db7e-4da8-9314-093a80910361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574979871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.574979871
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.3868240069
Short name T1062
Test name
Test status
Simulation time 18063574 ps
CPU time 0.67 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:30:37 PM PDT 24
Peak memory 203580 kb
Host smart-1eb473f7-df62-45a3-9f77-13aa3f4b108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868240069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3868240069
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3858266489
Short name T327
Test name
Test status
Simulation time 5932566527 ps
CPU time 26.8 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:31:03 PM PDT 24
Peak memory 373992 kb
Host smart-4a67f517-6405-4009-b000-599a35dff290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858266489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3858266489
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1014495513
Short name T1120
Test name
Test status
Simulation time 9485180486 ps
CPU time 3.09 seconds
Started Mar 28 03:30:43 PM PDT 24
Finished Mar 28 03:30:46 PM PDT 24
Peak memory 203920 kb
Host smart-761f7070-40a0-4dd8-972d-85bd641bf6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014495513 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1014495513
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3547269899
Short name T1074
Test name
Test status
Simulation time 10120971877 ps
CPU time 86.15 seconds
Started Mar 28 03:30:35 PM PDT 24
Finished Mar 28 03:32:01 PM PDT 24
Peak memory 589208 kb
Host smart-c925d440-5463-425d-8d20-e66a39b45235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547269899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3547269899
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1588208412
Short name T1154
Test name
Test status
Simulation time 10129038398 ps
CPU time 88.36 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:32:11 PM PDT 24
Peak memory 709120 kb
Host smart-25f43133-0f48-4bc3-a13c-d0a0e9d44971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588208412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1588208412
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1338160642
Short name T213
Test name
Test status
Simulation time 1599414269 ps
CPU time 2.7 seconds
Started Mar 28 03:30:35 PM PDT 24
Finished Mar 28 03:30:38 PM PDT 24
Peak memory 203764 kb
Host smart-ce83d23a-e69d-4284-85e9-3b68b033a604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338160642 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1338160642
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3591855942
Short name T1172
Test name
Test status
Simulation time 1817052371 ps
CPU time 5.29 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:04 PM PDT 24
Peak memory 205504 kb
Host smart-1d6a0e30-7481-48b8-b880-2307f202e3fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591855942 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3591855942
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1736452598
Short name T746
Test name
Test status
Simulation time 4319304973 ps
CPU time 40.65 seconds
Started Mar 28 03:30:32 PM PDT 24
Finished Mar 28 03:31:13 PM PDT 24
Peak memory 203796 kb
Host smart-1aac57a7-a9b7-49a4-bb61-94513af3f713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736452598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1736452598
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1672318601
Short name T635
Test name
Test status
Simulation time 235962001 ps
CPU time 8.9 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 03:30:43 PM PDT 24
Peak memory 203848 kb
Host smart-4573ee78-804f-4689-aced-03b6f3b5b1e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672318601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1672318601
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.4133647434
Short name T1152
Test name
Test status
Simulation time 6178544384 ps
CPU time 8.2 seconds
Started Mar 28 03:30:33 PM PDT 24
Finished Mar 28 03:30:41 PM PDT 24
Peak memory 220132 kb
Host smart-768fbe7c-f9ae-42f7-82bb-c3661e832c93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133647434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.4133647434
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.287381640
Short name T795
Test name
Test status
Simulation time 28052217 ps
CPU time 0.59 seconds
Started Mar 28 03:30:35 PM PDT 24
Finished Mar 28 03:30:35 PM PDT 24
Peak memory 203692 kb
Host smart-c0ef6db5-11e8-43a6-afda-d7c5619aaa4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287381640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.287381640
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.487377629
Short name T480
Test name
Test status
Simulation time 243613424 ps
CPU time 1.33 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:30:43 PM PDT 24
Peak memory 211904 kb
Host smart-f06cd9a9-4125-4643-9902-f34b1f3e7cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487377629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.487377629
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2522013250
Short name T249
Test name
Test status
Simulation time 1533568164 ps
CPU time 19.28 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:31:01 PM PDT 24
Peak memory 283396 kb
Host smart-da075636-67a4-48cc-8e3b-4d580e0dda8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522013250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2522013250
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3892692917
Short name T304
Test name
Test status
Simulation time 1987476704 ps
CPU time 68.79 seconds
Started Mar 28 03:30:39 PM PDT 24
Finished Mar 28 03:31:47 PM PDT 24
Peak memory 665780 kb
Host smart-e6d8ae81-9f1f-473b-8a13-04e891cc2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892692917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3892692917
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1488559263
Short name T579
Test name
Test status
Simulation time 3714155166 ps
CPU time 126.48 seconds
Started Mar 28 03:30:39 PM PDT 24
Finished Mar 28 03:32:45 PM PDT 24
Peak memory 611872 kb
Host smart-11d6d758-9bc7-445c-bd39-ac460b4cb2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488559263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1488559263
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3640849385
Short name T284
Test name
Test status
Simulation time 371284956 ps
CPU time 0.92 seconds
Started Mar 28 03:30:39 PM PDT 24
Finished Mar 28 03:30:40 PM PDT 24
Peak memory 203696 kb
Host smart-c07db7c7-cea3-4746-bba6-1f8677939375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640849385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3640849385
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3979509689
Short name T511
Test name
Test status
Simulation time 172833827 ps
CPU time 5.19 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:30:46 PM PDT 24
Peak memory 216444 kb
Host smart-591c00a2-87aa-47b3-b045-68772d3a7082
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979509689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3979509689
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.227770424
Short name T734
Test name
Test status
Simulation time 14097654897 ps
CPU time 74.1 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 836288 kb
Host smart-3f4a8ea0-618d-4b3a-a79d-8742ed2ae33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227770424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.227770424
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3232159270
Short name T399
Test name
Test status
Simulation time 320929008 ps
CPU time 5.11 seconds
Started Mar 28 03:30:45 PM PDT 24
Finished Mar 28 03:30:50 PM PDT 24
Peak memory 203788 kb
Host smart-553688f8-426b-4de5-be82-adcd1a6fa7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232159270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3232159270
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1254007285
Short name T337
Test name
Test status
Simulation time 8857021392 ps
CPU time 60.92 seconds
Started Mar 28 03:30:47 PM PDT 24
Finished Mar 28 03:31:48 PM PDT 24
Peak memory 403320 kb
Host smart-92ee9a40-866c-4a00-969c-a08221ab5037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254007285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1254007285
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.291696153
Short name T937
Test name
Test status
Simulation time 98796337 ps
CPU time 0.66 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:00 PM PDT 24
Peak memory 203548 kb
Host smart-dc06f837-4252-4200-955c-fd694240a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291696153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.291696153
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1305512854
Short name T933
Test name
Test status
Simulation time 71328754643 ps
CPU time 2946.61 seconds
Started Mar 28 03:30:34 PM PDT 24
Finished Mar 28 04:19:41 PM PDT 24
Peak memory 2926012 kb
Host smart-c68a51b2-ba94-4c44-9a33-798fbcf399a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305512854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1305512854
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3562389456
Short name T785
Test name
Test status
Simulation time 3111770601 ps
CPU time 78.39 seconds
Started Mar 28 03:30:36 PM PDT 24
Finished Mar 28 03:31:55 PM PDT 24
Peak memory 355196 kb
Host smart-e16f2268-8d34-41b2-a005-aa04bacdbe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562389456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3562389456
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.4066522357
Short name T643
Test name
Test status
Simulation time 1533622081 ps
CPU time 2.52 seconds
Started Mar 28 03:30:39 PM PDT 24
Finished Mar 28 03:30:42 PM PDT 24
Peak memory 203852 kb
Host smart-36eeefe4-6a5f-4b4f-9690-b5e0fa11372f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066522357 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.4066522357
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1826590163
Short name T809
Test name
Test status
Simulation time 10042110458 ps
CPU time 73.4 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:31:54 PM PDT 24
Peak memory 584484 kb
Host smart-e9118f3e-0103-428c-b6d8-18b1d527e03a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826590163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1826590163
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3511297773
Short name T1138
Test name
Test status
Simulation time 11071719402 ps
CPU time 6.17 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:30:48 PM PDT 24
Peak memory 260868 kb
Host smart-c7c1f9d2-8c4a-4dac-9462-824761693951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511297773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3511297773
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1486130459
Short name T372
Test name
Test status
Simulation time 7050618038 ps
CPU time 2.82 seconds
Started Mar 28 03:30:47 PM PDT 24
Finished Mar 28 03:30:50 PM PDT 24
Peak memory 203860 kb
Host smart-ed814f93-ec44-4cbc-8c87-cfa79f938abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486130459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1486130459
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2924680512
Short name T218
Test name
Test status
Simulation time 1436990159 ps
CPU time 6.78 seconds
Started Mar 28 03:30:45 PM PDT 24
Finished Mar 28 03:30:52 PM PDT 24
Peak memory 211964 kb
Host smart-f01fd3d8-9892-4e65-b8e6-edc1bf7fd59f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924680512 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2924680512
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1088343781
Short name T461
Test name
Test status
Simulation time 2716893546 ps
CPU time 6.54 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:30:48 PM PDT 24
Peak memory 203740 kb
Host smart-576ffcf7-c4ae-4eec-8f49-e997c4d4108a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088343781 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1088343781
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1200111174
Short name T446
Test name
Test status
Simulation time 8792698619 ps
CPU time 17.23 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:30:59 PM PDT 24
Peak memory 203804 kb
Host smart-5534117e-d37b-4c02-9726-f5bd8ad17336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200111174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1200111174
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2024172294
Short name T1019
Test name
Test status
Simulation time 1660546533 ps
CPU time 31.23 seconds
Started Mar 28 03:30:42 PM PDT 24
Finished Mar 28 03:31:14 PM PDT 24
Peak memory 227448 kb
Host smart-5513c84b-38a8-4a3c-98a5-86ae756135b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024172294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2024172294
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2310044520
Short name T220
Test name
Test status
Simulation time 39677782540 ps
CPU time 830.95 seconds
Started Mar 28 03:30:38 PM PDT 24
Finished Mar 28 03:44:30 PM PDT 24
Peak memory 2106460 kb
Host smart-5fedcf2c-8a35-469c-9158-c687788ed013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310044520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2310044520
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1028171502
Short name T1115
Test name
Test status
Simulation time 1416000257 ps
CPU time 6.58 seconds
Started Mar 28 03:30:41 PM PDT 24
Finished Mar 28 03:30:47 PM PDT 24
Peak memory 211984 kb
Host smart-8f8945fa-90b7-409e-b4b9-51c9109f26bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028171502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1028171502
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.2308605460
Short name T780
Test name
Test status
Simulation time 35977931 ps
CPU time 0.62 seconds
Started Mar 28 03:30:56 PM PDT 24
Finished Mar 28 03:30:57 PM PDT 24
Peak memory 203700 kb
Host smart-8fcdf1e9-5c7c-46a8-a262-c14d6bb60057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308605460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2308605460
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1486956997
Short name T673
Test name
Test status
Simulation time 336544323 ps
CPU time 1.5 seconds
Started Mar 28 03:30:56 PM PDT 24
Finished Mar 28 03:30:58 PM PDT 24
Peak memory 211912 kb
Host smart-f13d6161-38fb-43b9-ae10-b4f5fb3e0795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486956997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1486956997
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2640834707
Short name T1003
Test name
Test status
Simulation time 319841815 ps
CPU time 17.07 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:17 PM PDT 24
Peak memory 270824 kb
Host smart-e0dbdfe0-75d8-4a77-94bb-854029bc8a68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640834707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2640834707
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1244628507
Short name T702
Test name
Test status
Simulation time 2611396998 ps
CPU time 87.93 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:32:26 PM PDT 24
Peak memory 754504 kb
Host smart-a7a62af1-8684-4a47-a715-78cef5710d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244628507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1244628507
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1553422204
Short name T416
Test name
Test status
Simulation time 6220488063 ps
CPU time 36.79 seconds
Started Mar 28 03:31:00 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 468420 kb
Host smart-a66c05b8-4212-4f4e-87fc-0496d4953c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553422204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1553422204
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3276085842
Short name T775
Test name
Test status
Simulation time 105426246 ps
CPU time 1.04 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:00 PM PDT 24
Peak memory 203764 kb
Host smart-2b514935-67da-4301-b4c5-0e0441c343c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276085842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3276085842
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2100336994
Short name T81
Test name
Test status
Simulation time 176618362 ps
CPU time 4 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:31:01 PM PDT 24
Peak memory 203768 kb
Host smart-a6559a3f-0a5f-4a74-91c8-65b01bacac33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100336994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2100336994
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.563863885
Short name T723
Test name
Test status
Simulation time 517901962 ps
CPU time 21.99 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:21 PM PDT 24
Peak memory 203880 kb
Host smart-c94cc787-076d-4b2e-8e05-27d24ec3292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563863885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.563863885
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.812597740
Short name T1143
Test name
Test status
Simulation time 1581916578 ps
CPU time 71.35 seconds
Started Mar 28 03:30:56 PM PDT 24
Finished Mar 28 03:32:08 PM PDT 24
Peak memory 312228 kb
Host smart-7d343af4-5e2c-49e5-929d-7f688fb92780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812597740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.812597740
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1403236759
Short name T1118
Test name
Test status
Simulation time 401185185 ps
CPU time 0.68 seconds
Started Mar 28 03:30:45 PM PDT 24
Finished Mar 28 03:30:46 PM PDT 24
Peak memory 203568 kb
Host smart-7cdf8d6c-5c1e-421e-b4eb-d9860cd7ab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403236759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1403236759
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.152732439
Short name T1178
Test name
Test status
Simulation time 5153823953 ps
CPU time 504.55 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:39:21 PM PDT 24
Peak memory 1451640 kb
Host smart-937df0e1-dc24-479c-9ed9-fa388d3f8278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152732439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.152732439
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3644534155
Short name T1150
Test name
Test status
Simulation time 4801732351 ps
CPU time 64.16 seconds
Started Mar 28 03:30:47 PM PDT 24
Finished Mar 28 03:31:51 PM PDT 24
Peak memory 362764 kb
Host smart-86e99244-383f-4a91-a857-d2ca0838d3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644534155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3644534155
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2615024948
Short name T294
Test name
Test status
Simulation time 3188070681 ps
CPU time 4.11 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:07 PM PDT 24
Peak memory 212092 kb
Host smart-c785c28c-1d1b-48e9-8513-65b98607bf4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615024948 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2615024948
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1346140295
Short name T338
Test name
Test status
Simulation time 10076161378 ps
CPU time 69.59 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:32:07 PM PDT 24
Peak memory 595308 kb
Host smart-24e601d7-9d79-410c-9f94-f605b164a3a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346140295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1346140295
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2325322532
Short name T625
Test name
Test status
Simulation time 10155932403 ps
CPU time 57.37 seconds
Started Mar 28 03:30:55 PM PDT 24
Finished Mar 28 03:31:52 PM PDT 24
Peak memory 573732 kb
Host smart-a45795c7-1b97-4ff4-99bd-b8ef2d53c3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325322532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2325322532
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.907849258
Short name T811
Test name
Test status
Simulation time 5192930361 ps
CPU time 2.45 seconds
Started Mar 28 03:31:00 PM PDT 24
Finished Mar 28 03:31:03 PM PDT 24
Peak memory 203836 kb
Host smart-125bc84d-2d19-4246-a453-9ffb7a47e828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907849258 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.907849258
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.93501167
Short name T170
Test name
Test status
Simulation time 1910559211 ps
CPU time 3.41 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:31:01 PM PDT 24
Peak memory 203892 kb
Host smart-1cfddc59-ce65-43d9-8fc5-edec7b72e6ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93501167 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.93501167
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1879566400
Short name T1033
Test name
Test status
Simulation time 21800112793 ps
CPU time 5.7 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:04 PM PDT 24
Peak memory 203840 kb
Host smart-a87927e7-d1b6-4b32-b118-b411337b34e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879566400 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1879566400
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.138265629
Short name T738
Test name
Test status
Simulation time 1437794714 ps
CPU time 48.83 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:48 PM PDT 24
Peak memory 203824 kb
Host smart-6099a477-10df-4911-94d4-f709c6f3e876
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138265629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.138265629
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.387957739
Short name T844
Test name
Test status
Simulation time 3436313533 ps
CPU time 29.41 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:28 PM PDT 24
Peak memory 234200 kb
Host smart-a8e88ae0-696f-4da7-88dd-c8dc8ed55237
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387957739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.387957739
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1088565567
Short name T725
Test name
Test status
Simulation time 11848701790 ps
CPU time 606.3 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:41:05 PM PDT 24
Peak memory 1806836 kb
Host smart-e9810ff6-654f-49a5-9204-54bd2acb6306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088565567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1088565567
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1468859238
Short name T190
Test name
Test status
Simulation time 5752716176 ps
CPU time 6.65 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:06 PM PDT 24
Peak memory 203932 kb
Host smart-f92a4f37-12e0-4c11-8780-4172deae9d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468859238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1468859238
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.4237482632
Short name T93
Test name
Test status
Simulation time 54231520 ps
CPU time 0.6 seconds
Started Mar 28 03:25:34 PM PDT 24
Finished Mar 28 03:25:35 PM PDT 24
Peak memory 203644 kb
Host smart-fdf5c634-6bbe-4d6f-b661-1f504346f69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237482632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.4237482632
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3500380043
Short name T694
Test name
Test status
Simulation time 71624582 ps
CPU time 1.33 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:25:19 PM PDT 24
Peak memory 212016 kb
Host smart-84be630a-5260-4794-b15d-2be51190b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500380043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3500380043
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1942358663
Short name T1105
Test name
Test status
Simulation time 247482424 ps
CPU time 5.37 seconds
Started Mar 28 03:25:18 PM PDT 24
Finished Mar 28 03:25:24 PM PDT 24
Peak memory 248732 kb
Host smart-1ed32583-e623-4ef6-aafd-6610389eb145
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942358663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1942358663
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1807612689
Short name T496
Test name
Test status
Simulation time 5680859347 ps
CPU time 41.03 seconds
Started Mar 28 03:25:18 PM PDT 24
Finished Mar 28 03:25:59 PM PDT 24
Peak memory 544996 kb
Host smart-6cfab011-a85f-48d5-8abe-ab088d573b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807612689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1807612689
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.787058244
Short name T898
Test name
Test status
Simulation time 8103267437 ps
CPU time 101.9 seconds
Started Mar 28 03:25:20 PM PDT 24
Finished Mar 28 03:27:02 PM PDT 24
Peak memory 546936 kb
Host smart-94dfc0dc-c1c9-40ce-9e18-ee89c00d75f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787058244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.787058244
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3571666114
Short name T279
Test name
Test status
Simulation time 268735803 ps
CPU time 0.81 seconds
Started Mar 28 03:25:18 PM PDT 24
Finished Mar 28 03:25:19 PM PDT 24
Peak memory 203692 kb
Host smart-148e6645-9b49-4e26-9f1a-b1c58afc2d50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571666114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3571666114
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3751812150
Short name T573
Test name
Test status
Simulation time 191524585 ps
CPU time 9.87 seconds
Started Mar 28 03:25:19 PM PDT 24
Finished Mar 28 03:25:29 PM PDT 24
Peak memory 203796 kb
Host smart-e76b8237-dc20-4557-a5a6-c16c7ce1e359
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751812150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3751812150
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1676201789
Short name T966
Test name
Test status
Simulation time 12391214893 ps
CPU time 226.87 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:29:04 PM PDT 24
Peak memory 975740 kb
Host smart-4bd141fd-9ad2-4a31-a149-43cbeaed0e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676201789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1676201789
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2039534183
Short name T1051
Test name
Test status
Simulation time 259711877 ps
CPU time 10.32 seconds
Started Mar 28 03:25:32 PM PDT 24
Finished Mar 28 03:25:43 PM PDT 24
Peak memory 203824 kb
Host smart-ba1b7b03-1a46-4954-b182-54c0ce4039cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039534183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2039534183
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.3502413738
Short name T1059
Test name
Test status
Simulation time 5135356190 ps
CPU time 30.58 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:26:07 PM PDT 24
Peak memory 427284 kb
Host smart-06b36979-8ee2-4f47-9b09-146051feb5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502413738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3502413738
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3012537029
Short name T837
Test name
Test status
Simulation time 141844477 ps
CPU time 0.67 seconds
Started Mar 28 03:25:18 PM PDT 24
Finished Mar 28 03:25:19 PM PDT 24
Peak memory 203584 kb
Host smart-edb7e7b8-5a5a-4b7b-90f7-844cd07ea0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012537029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3012537029
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1253458266
Short name T1191
Test name
Test status
Simulation time 12088542622 ps
CPU time 479.37 seconds
Started Mar 28 03:25:21 PM PDT 24
Finished Mar 28 03:33:20 PM PDT 24
Peak memory 203904 kb
Host smart-c8c693fc-f86c-47f7-a765-afe2450776cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253458266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1253458266
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.491503671
Short name T792
Test name
Test status
Simulation time 3308930125 ps
CPU time 27.4 seconds
Started Mar 28 03:25:17 PM PDT 24
Finished Mar 28 03:25:45 PM PDT 24
Peak memory 344104 kb
Host smart-5360912f-9ac4-4ac8-9969-202688a688dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491503671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.491503671
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.237194667
Short name T701
Test name
Test status
Simulation time 1608807404 ps
CPU time 4.31 seconds
Started Mar 28 03:25:33 PM PDT 24
Finished Mar 28 03:25:37 PM PDT 24
Peak memory 203848 kb
Host smart-a507b2f1-0c61-4999-aa8a-15aa78b967c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237194667 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.237194667
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2783936003
Short name T504
Test name
Test status
Simulation time 10059154641 ps
CPU time 93.86 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:27:10 PM PDT 24
Peak memory 680128 kb
Host smart-bc97bf18-1395-466e-a91a-b5f77e651883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783936003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2783936003
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.687885330
Short name T1166
Test name
Test status
Simulation time 1071272599 ps
CPU time 3.1 seconds
Started Mar 28 03:25:34 PM PDT 24
Finished Mar 28 03:25:38 PM PDT 24
Peak memory 203772 kb
Host smart-068df484-2441-4c27-b283-5465357635ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687885330 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.687885330
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3867243522
Short name T641
Test name
Test status
Simulation time 611302636 ps
CPU time 3.56 seconds
Started Mar 28 03:25:32 PM PDT 24
Finished Mar 28 03:25:36 PM PDT 24
Peak memory 203844 kb
Host smart-374d780b-5082-4e7a-b15f-e170be95b14d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867243522 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3867243522
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.871537766
Short name T721
Test name
Test status
Simulation time 824374991 ps
CPU time 10.34 seconds
Started Mar 28 03:25:34 PM PDT 24
Finished Mar 28 03:25:45 PM PDT 24
Peak memory 203788 kb
Host smart-2298311b-6e6a-487e-9725-230b20e17811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871537766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.871537766
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.65386792
Short name T934
Test name
Test status
Simulation time 8765980144 ps
CPU time 62.09 seconds
Started Mar 28 03:25:34 PM PDT 24
Finished Mar 28 03:26:37 PM PDT 24
Peak memory 206792 kb
Host smart-8307ed6c-dc2c-4107-b587-c0d091244ce3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65386792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stress_rd.65386792
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3103439099
Short name T1133
Test name
Test status
Simulation time 20051754056 ps
CPU time 7.07 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:25:44 PM PDT 24
Peak memory 212364 kb
Host smart-c2d124d7-93fd-4ebf-a6c5-d98fca2c0844
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103439099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3103439099
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.119945602
Short name T1075
Test name
Test status
Simulation time 14418264 ps
CPU time 0.62 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:25:36 PM PDT 24
Peak memory 203488 kb
Host smart-1cf80385-d761-47bb-a289-aa02b3857b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119945602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.119945602
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3738768461
Short name T189
Test name
Test status
Simulation time 99998503 ps
CPU time 1.48 seconds
Started Mar 28 03:25:34 PM PDT 24
Finished Mar 28 03:25:36 PM PDT 24
Peak memory 212060 kb
Host smart-cd0a5e2d-ab4b-45a4-80ee-e799c8870730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738768461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3738768461
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.4220741095
Short name T85
Test name
Test status
Simulation time 3063457680 ps
CPU time 4.87 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:43 PM PDT 24
Peak memory 238424 kb
Host smart-ddb8d0bd-f71a-40b9-9cc7-a1a7ead971c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220741095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.4220741095
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.34023640
Short name T74
Test name
Test status
Simulation time 6738752551 ps
CPU time 104.43 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:27:22 PM PDT 24
Peak memory 440392 kb
Host smart-296adef8-2f57-4002-ad75-76282ba35263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34023640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.34023640
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3684922461
Short name T1026
Test name
Test status
Simulation time 10608946927 ps
CPU time 34.5 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:26:14 PM PDT 24
Peak memory 489072 kb
Host smart-f0418436-8ac1-4046-b64b-496662678256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684922461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3684922461
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3141611109
Short name T206
Test name
Test status
Simulation time 167787613 ps
CPU time 1.02 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:38 PM PDT 24
Peak memory 203796 kb
Host smart-62d8a7d2-ad31-4a24-8b20-77b404795188
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141611109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3141611109
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3592075023
Short name T786
Test name
Test status
Simulation time 535326886 ps
CPU time 3.75 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:40 PM PDT 24
Peak memory 203808 kb
Host smart-9223b096-3b61-4f49-a671-5923f62acb9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592075023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3592075023
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3127668439
Short name T823
Test name
Test status
Simulation time 4565052691 ps
CPU time 345.42 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:31:24 PM PDT 24
Peak memory 1251112 kb
Host smart-4ab91c9c-47da-40d3-81d6-b2b7bc86b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127668439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3127668439
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2590296945
Short name T756
Test name
Test status
Simulation time 227787491 ps
CPU time 9.1 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:46 PM PDT 24
Peak memory 203792 kb
Host smart-af49741c-38b8-487f-b74a-2556caff31a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590296945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2590296945
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2646066293
Short name T385
Test name
Test status
Simulation time 15853675239 ps
CPU time 28.08 seconds
Started Mar 28 03:25:34 PM PDT 24
Finished Mar 28 03:26:02 PM PDT 24
Peak memory 350808 kb
Host smart-705349ea-1f45-4ff7-b756-d975de1d0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646066293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2646066293
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3351855704
Short name T665
Test name
Test status
Simulation time 17000703 ps
CPU time 0.68 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:38 PM PDT 24
Peak memory 203620 kb
Host smart-ee085bc7-ffaf-4dc2-a7d1-8f49bb193499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351855704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3351855704
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1909936623
Short name T610
Test name
Test status
Simulation time 1052468476 ps
CPU time 3.93 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:25:43 PM PDT 24
Peak memory 212020 kb
Host smart-3e6e4898-af56-4e70-99d5-d95bfa34fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909936623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1909936623
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1434490679
Short name T51
Test name
Test status
Simulation time 4095520640 ps
CPU time 19.79 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:57 PM PDT 24
Peak memory 309688 kb
Host smart-f0056ccd-4622-4c0e-8186-aca772121f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434490679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1434490679
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2413146631
Short name T97
Test name
Test status
Simulation time 23623418437 ps
CPU time 483.72 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:33:39 PM PDT 24
Peak memory 1107092 kb
Host smart-14c8893a-bb67-4c45-8f7b-ba3922f55a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413146631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2413146631
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1453428280
Short name T905
Test name
Test status
Simulation time 1091433758 ps
CPU time 3.08 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:25:38 PM PDT 24
Peak memory 203752 kb
Host smart-e9de17c2-8afa-4706-a828-d262ce215312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453428280 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1453428280
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.4017911923
Short name T879
Test name
Test status
Simulation time 10071352361 ps
CPU time 93.92 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:27:09 PM PDT 24
Peak memory 690848 kb
Host smart-abaddd8c-0155-4691-b296-85a4e179c039
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017911923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.4017911923
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.4102707120
Short name T1129
Test name
Test status
Simulation time 1072156585 ps
CPU time 2.42 seconds
Started Mar 28 03:25:33 PM PDT 24
Finished Mar 28 03:25:36 PM PDT 24
Peak memory 203812 kb
Host smart-6af8c4c0-771f-420c-8448-6610b5eafd83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102707120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.4102707120
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3292792068
Short name T253
Test name
Test status
Simulation time 2803724831 ps
CPU time 5.29 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:42 PM PDT 24
Peak memory 210108 kb
Host smart-db2c8ca0-69bc-4c88-83f8-a9d7d70db547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292792068 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3292792068
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.815121270
Short name T907
Test name
Test status
Simulation time 12120672427 ps
CPU time 5.22 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:25:44 PM PDT 24
Peak memory 203836 kb
Host smart-fac5ac36-62cd-43fc-9c67-824e6a3e3b16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815121270 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.815121270
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.911313334
Short name T453
Test name
Test status
Simulation time 1310219436 ps
CPU time 11.31 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:25:49 PM PDT 24
Peak memory 203784 kb
Host smart-60055c43-4fae-4a10-8370-8776055b87dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911313334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.911313334
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1013662477
Short name T1009
Test name
Test status
Simulation time 1096890158 ps
CPU time 4.44 seconds
Started Mar 28 03:25:40 PM PDT 24
Finished Mar 28 03:25:46 PM PDT 24
Peak memory 203864 kb
Host smart-3d6411f4-583b-4fd2-af1a-54f9c0a68c59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013662477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1013662477
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.3449251077
Short name T269
Test name
Test status
Simulation time 17440710549 ps
CPU time 250.1 seconds
Started Mar 28 03:25:39 PM PDT 24
Finished Mar 28 03:29:51 PM PDT 24
Peak memory 1752820 kb
Host smart-72c2417c-4b42-4569-9522-871429da3e2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449251077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.3449251077
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2332319034
Short name T845
Test name
Test status
Simulation time 4489261284 ps
CPU time 6.68 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:25:46 PM PDT 24
Peak memory 203868 kb
Host smart-81ccf055-0d05-4903-9895-3ac2b777b7f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332319034 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2332319034
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2343086099
Short name T415
Test name
Test status
Simulation time 18597137 ps
CPU time 0.64 seconds
Started Mar 28 03:25:56 PM PDT 24
Finished Mar 28 03:25:57 PM PDT 24
Peak memory 203712 kb
Host smart-62def83a-a380-42e2-b8fb-55f6edf21e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343086099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2343086099
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.102046296
Short name T647
Test name
Test status
Simulation time 354856050 ps
CPU time 1.29 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:25:41 PM PDT 24
Peak memory 211992 kb
Host smart-cc9e32f3-9fe8-48f0-84f7-1c0c0298a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102046296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.102046296
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.138424333
Short name T270
Test name
Test status
Simulation time 1180881118 ps
CPU time 5.88 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:25:46 PM PDT 24
Peak memory 258048 kb
Host smart-f7608ce7-9386-49b2-a653-385a3748b97c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138424333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.138424333
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.341505575
Short name T308
Test name
Test status
Simulation time 1810345540 ps
CPU time 49.47 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:26:29 PM PDT 24
Peak memory 561348 kb
Host smart-c006b2d0-4f12-41d7-b68a-b6e9c4b9af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341505575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.341505575
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.445347574
Short name T1029
Test name
Test status
Simulation time 5418257150 ps
CPU time 69.37 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:26:48 PM PDT 24
Peak memory 745508 kb
Host smart-f7114673-5085-4a42-9c74-914bbe2f0ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445347574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.445347574
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1742636858
Short name T951
Test name
Test status
Simulation time 658996145 ps
CPU time 1.17 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:25:39 PM PDT 24
Peak memory 203592 kb
Host smart-7d72dec6-948a-44c1-9214-50bc73489da6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742636858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1742636858
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1900947199
Short name T4
Test name
Test status
Simulation time 119855659 ps
CPU time 6.19 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:44 PM PDT 24
Peak memory 203324 kb
Host smart-2be0b0bf-e9d2-444b-9405-90a93f80fe05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900947199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1900947199
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.4211530233
Short name T91
Test name
Test status
Simulation time 12654908560 ps
CPU time 55.67 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:26:31 PM PDT 24
Peak memory 776636 kb
Host smart-6d77943f-4550-4af7-834a-8b26c3343a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211530233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.4211530233
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1924801539
Short name T748
Test name
Test status
Simulation time 1670995374 ps
CPU time 5.37 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:25:59 PM PDT 24
Peak memory 203860 kb
Host smart-9aebe843-2574-492f-9b11-cad6ccccafb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924801539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1924801539
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.113468619
Short name T630
Test name
Test status
Simulation time 3838633111 ps
CPU time 42.33 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:26:36 PM PDT 24
Peak memory 454692 kb
Host smart-cbf3ec31-30d5-4f4b-ba22-bf83f3785244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113468619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.113468619
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1492489477
Short name T1122
Test name
Test status
Simulation time 28857421 ps
CPU time 0.68 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:25:39 PM PDT 24
Peak memory 203600 kb
Host smart-100fcd4a-d261-490a-96da-3afe0cbc2fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492489477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1492489477
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1895780836
Short name T281
Test name
Test status
Simulation time 419151109 ps
CPU time 8.74 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:47 PM PDT 24
Peak memory 298284 kb
Host smart-2a26a53a-21f0-4445-897b-09eab88f0c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895780836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1895780836
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.311217545
Short name T692
Test name
Test status
Simulation time 1515133419 ps
CPU time 37.59 seconds
Started Mar 28 03:25:35 PM PDT 24
Finished Mar 28 03:26:13 PM PDT 24
Peak memory 436788 kb
Host smart-57ff0c6d-fae9-4fc6-995d-0ced5163a8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311217545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.311217545
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2144340637
Short name T870
Test name
Test status
Simulation time 1088068416 ps
CPU time 2.82 seconds
Started Mar 28 03:26:00 PM PDT 24
Finished Mar 28 03:26:03 PM PDT 24
Peak memory 203792 kb
Host smart-5544a24b-7adb-432f-b285-a66e49cad68b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144340637 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2144340637
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2982242908
Short name T497
Test name
Test status
Simulation time 10080038554 ps
CPU time 88.9 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:27:09 PM PDT 24
Peak memory 595360 kb
Host smart-29b84065-e477-4438-ab91-08445aaeb9c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982242908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2982242908
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.401343487
Short name T1168
Test name
Test status
Simulation time 10060284380 ps
CPU time 76.96 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:26:55 PM PDT 24
Peak memory 670784 kb
Host smart-ba93fdba-dcd7-4161-bcfc-b624719dbaea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401343487 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_tx.401343487
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2222437123
Short name T1093
Test name
Test status
Simulation time 3796794396 ps
CPU time 2.94 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:25:55 PM PDT 24
Peak memory 203908 kb
Host smart-e6520142-3c8f-477a-8197-10319f48970d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222437123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2222437123
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1406057623
Short name T749
Test name
Test status
Simulation time 761975979 ps
CPU time 4.06 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:25:41 PM PDT 24
Peak memory 203856 kb
Host smart-6493f90f-d804-4cc6-9842-5552f7be5f06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406057623 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1406057623
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1739930809
Short name T790
Test name
Test status
Simulation time 4459250392 ps
CPU time 3.71 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:25:42 PM PDT 24
Peak memory 203916 kb
Host smart-ab1ed6b8-657b-451a-b16f-34f279d6d0c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739930809 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1739930809
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.966280193
Short name T1188
Test name
Test status
Simulation time 1252932075 ps
CPU time 10.07 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:25:50 PM PDT 24
Peak memory 203500 kb
Host smart-7f5d47af-06f6-4f44-b3e9-cf5e6804aa61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966280193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.966280193
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.1869763364
Short name T990
Test name
Test status
Simulation time 1433558083 ps
CPU time 22.6 seconds
Started Mar 28 03:25:37 PM PDT 24
Finished Mar 28 03:26:01 PM PDT 24
Peak memory 217012 kb
Host smart-357d100b-0a14-4ab3-9f5e-b0a2b9f139bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869763364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.1869763364
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3602739194
Short name T910
Test name
Test status
Simulation time 10836445193 ps
CPU time 23.31 seconds
Started Mar 28 03:25:36 PM PDT 24
Finished Mar 28 03:26:01 PM PDT 24
Peak memory 203388 kb
Host smart-3ce3519b-bdbf-409e-84c2-5c05cbb64cf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602739194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3602739194
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.1075039624
Short name T438
Test name
Test status
Simulation time 26778700134 ps
CPU time 2139.41 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 04:01:20 PM PDT 24
Peak memory 6533776 kb
Host smart-a97fb37c-4049-410b-b418-95e6b12ae8e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075039624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.1075039624
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2220464668
Short name T812
Test name
Test status
Simulation time 1095421363 ps
CPU time 6.56 seconds
Started Mar 28 03:25:38 PM PDT 24
Finished Mar 28 03:25:46 PM PDT 24
Peak memory 220028 kb
Host smart-f07e34ce-11cd-43ad-93d0-849c08f8c25b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220464668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2220464668
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.786253879
Short name T970
Test name
Test status
Simulation time 29092018 ps
CPU time 0.61 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:25:54 PM PDT 24
Peak memory 203696 kb
Host smart-483e050a-263d-435a-8927-d63f6387c90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786253879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.786253879
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3236561003
Short name T209
Test name
Test status
Simulation time 107908211 ps
CPU time 2.07 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:25:55 PM PDT 24
Peak memory 211960 kb
Host smart-f1630449-dfaf-40d4-81a2-f37eb704d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236561003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3236561003
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.28262885
Short name T921
Test name
Test status
Simulation time 357068993 ps
CPU time 7.27 seconds
Started Mar 28 03:25:58 PM PDT 24
Finished Mar 28 03:26:05 PM PDT 24
Peak memory 280208 kb
Host smart-87750f7f-8097-4f2d-88b7-a5c14ada7d3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28262885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.28262885
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.4004090863
Short name T113
Test name
Test status
Simulation time 7182557361 ps
CPU time 53.14 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:26:46 PM PDT 24
Peak memory 634788 kb
Host smart-0bb0c716-034d-4d30-ba07-bf77d2cb859e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004090863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.4004090863
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3920754886
Short name T299
Test name
Test status
Simulation time 3695612326 ps
CPU time 148.05 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:28:22 PM PDT 24
Peak memory 673936 kb
Host smart-6ec059aa-cabb-4f29-9280-41491590721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920754886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3920754886
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3372696213
Short name T632
Test name
Test status
Simulation time 892015938 ps
CPU time 0.9 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:25:54 PM PDT 24
Peak memory 203668 kb
Host smart-aab3d415-4664-4969-a190-e71fab6e8a78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372696213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3372696213
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1009690185
Short name T556
Test name
Test status
Simulation time 135413578 ps
CPU time 3.12 seconds
Started Mar 28 03:25:50 PM PDT 24
Finished Mar 28 03:25:53 PM PDT 24
Peak memory 220448 kb
Host smart-3ad5d1e6-fa2c-449a-9a49-e000a15cab8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009690185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1009690185
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3452527954
Short name T884
Test name
Test status
Simulation time 3022469333 ps
CPU time 93.16 seconds
Started Mar 28 03:25:50 PM PDT 24
Finished Mar 28 03:27:24 PM PDT 24
Peak memory 940488 kb
Host smart-f6058bc3-05ee-477c-bf44-09d23a321cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452527954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3452527954
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.22681011
Short name T1053
Test name
Test status
Simulation time 428246988 ps
CPU time 8.74 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:26:03 PM PDT 24
Peak memory 203372 kb
Host smart-18d390ee-defc-4369-bd24-53f4e6a11066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22681011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.22681011
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.2899847549
Short name T19
Test name
Test status
Simulation time 1153026327 ps
CPU time 55.76 seconds
Started Mar 28 03:25:51 PM PDT 24
Finished Mar 28 03:26:47 PM PDT 24
Peak memory 317284 kb
Host smart-d4022d70-aee1-46c9-b8f3-d5c5fcb9372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899847549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.2899847549
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2635231724
Short name T888
Test name
Test status
Simulation time 22818126 ps
CPU time 0.66 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:25:53 PM PDT 24
Peak memory 203576 kb
Host smart-e29c8629-321a-4e4f-a0d6-689d42c52663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635231724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2635231724
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1594632991
Short name T197
Test name
Test status
Simulation time 2906331921 ps
CPU time 38.62 seconds
Started Mar 28 03:25:50 PM PDT 24
Finished Mar 28 03:26:28 PM PDT 24
Peak memory 538052 kb
Host smart-dae3f104-3165-4cfe-b49a-5d56c954fcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594632991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1594632991
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.85568432
Short name T1100
Test name
Test status
Simulation time 35920819009 ps
CPU time 32.66 seconds
Started Mar 28 03:25:51 PM PDT 24
Finished Mar 28 03:26:24 PM PDT 24
Peak memory 383428 kb
Host smart-b44cc892-95fa-4668-a07a-770d89d744ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85568432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.85568432
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1752929467
Short name T1147
Test name
Test status
Simulation time 4128533321 ps
CPU time 3.54 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:25:57 PM PDT 24
Peak memory 212040 kb
Host smart-d4e498df-afd3-4dcf-b14e-d2641624d13b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752929467 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1752929467
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3516458284
Short name T61
Test name
Test status
Simulation time 10052030403 ps
CPU time 96.73 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:27:31 PM PDT 24
Peak memory 625280 kb
Host smart-fe05131d-d819-463d-a458-bb6174f22651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516458284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3516458284
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3572243081
Short name T771
Test name
Test status
Simulation time 10143732718 ps
CPU time 36.53 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:26:29 PM PDT 24
Peak memory 434100 kb
Host smart-87094013-f86e-4a17-b74b-5f27b44ad860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572243081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3572243081
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3789916246
Short name T683
Test name
Test status
Simulation time 4653992484 ps
CPU time 2.94 seconds
Started Mar 28 03:25:51 PM PDT 24
Finished Mar 28 03:25:54 PM PDT 24
Peak memory 203872 kb
Host smart-c8f457c1-3fcb-4c14-98ea-a15d1ee809c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789916246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3789916246
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3267084216
Short name T862
Test name
Test status
Simulation time 916468788 ps
CPU time 4.85 seconds
Started Mar 28 03:25:57 PM PDT 24
Finished Mar 28 03:26:01 PM PDT 24
Peak memory 203812 kb
Host smart-b159ebbe-ab5f-49b9-837a-030350361d9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267084216 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3267084216
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.819169955
Short name T344
Test name
Test status
Simulation time 5700775441 ps
CPU time 7.31 seconds
Started Mar 28 03:25:50 PM PDT 24
Finished Mar 28 03:25:58 PM PDT 24
Peak memory 203852 kb
Host smart-df5e145a-c7e2-45a3-a835-bd969d2715a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819169955 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.819169955
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1741245686
Short name T1040
Test name
Test status
Simulation time 3982192158 ps
CPU time 38.17 seconds
Started Mar 28 03:25:57 PM PDT 24
Finished Mar 28 03:26:35 PM PDT 24
Peak memory 203836 kb
Host smart-7b092610-7bc3-4375-a4c2-6c92ae2d40e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741245686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1741245686
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.373896160
Short name T873
Test name
Test status
Simulation time 2406588892 ps
CPU time 12.38 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:26:06 PM PDT 24
Peak memory 203808 kb
Host smart-a0c41d10-acf8-4ab8-8ea1-116348c13cf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373896160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.373896160
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1887083009
Short name T712
Test name
Test status
Simulation time 1386347283 ps
CPU time 6.88 seconds
Started Mar 28 03:25:58 PM PDT 24
Finished Mar 28 03:26:05 PM PDT 24
Peak memory 203860 kb
Host smart-390acc3d-0f58-4c3d-824c-ca7dae45ea51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887083009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1887083009
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2966806602
Short name T656
Test name
Test status
Simulation time 53598161 ps
CPU time 0.61 seconds
Started Mar 28 03:26:02 PM PDT 24
Finished Mar 28 03:26:02 PM PDT 24
Peak memory 203700 kb
Host smart-b1ab663c-d8f6-4ed8-a2f1-b789bdc3cac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966806602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2966806602
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2136311412
Short name T996
Test name
Test status
Simulation time 126063115 ps
CPU time 1.23 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:25:55 PM PDT 24
Peak memory 215024 kb
Host smart-e863750e-79b1-465d-8e90-e43abc09ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136311412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2136311412
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.946814546
Short name T287
Test name
Test status
Simulation time 1695723943 ps
CPU time 17.27 seconds
Started Mar 28 03:25:56 PM PDT 24
Finished Mar 28 03:26:13 PM PDT 24
Peak memory 270904 kb
Host smart-2f36c557-cc4a-4c9b-83e6-0a5d09c4a3b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946814546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.946814546
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2507244599
Short name T989
Test name
Test status
Simulation time 35397126595 ps
CPU time 163.91 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:28:36 PM PDT 24
Peak memory 732356 kb
Host smart-b9f8198e-4e7d-41d9-927f-add3692009d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507244599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2507244599
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3563515173
Short name T1111
Test name
Test status
Simulation time 2148975270 ps
CPU time 69.81 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:27:03 PM PDT 24
Peak memory 705812 kb
Host smart-5ec120ff-1780-4a3f-b00f-3df89bdfe641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563515173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3563515173
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.997503554
Short name T314
Test name
Test status
Simulation time 137591597 ps
CPU time 1.14 seconds
Started Mar 28 03:25:50 PM PDT 24
Finished Mar 28 03:25:51 PM PDT 24
Peak memory 203828 kb
Host smart-5ee7d39b-1eeb-4d3e-8322-a1c7c0045472
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997503554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.997503554
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2986725051
Short name T200
Test name
Test status
Simulation time 137126597 ps
CPU time 6.99 seconds
Started Mar 28 03:25:53 PM PDT 24
Finished Mar 28 03:26:00 PM PDT 24
Peak memory 203848 kb
Host smart-fe684901-0dca-4649-8222-e36f8a1d9bf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986725051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2986725051
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3831462044
Short name T814
Test name
Test status
Simulation time 6755661443 ps
CPU time 232.43 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:29:47 PM PDT 24
Peak memory 997452 kb
Host smart-a0c5f021-387e-4988-bc07-966dd3c0f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831462044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3831462044
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3066175432
Short name T534
Test name
Test status
Simulation time 490038225 ps
CPU time 7.78 seconds
Started Mar 28 03:25:56 PM PDT 24
Finished Mar 28 03:26:04 PM PDT 24
Peak memory 203816 kb
Host smart-dc3c0734-7296-427c-8495-4fac0766ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066175432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3066175432
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.64901250
Short name T104
Test name
Test status
Simulation time 5164542948 ps
CPU time 17.16 seconds
Started Mar 28 03:25:58 PM PDT 24
Finished Mar 28 03:26:15 PM PDT 24
Peak memory 284040 kb
Host smart-80a7005b-7a3c-4f6c-9437-7ae4970efd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64901250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.64901250
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.634847351
Short name T426
Test name
Test status
Simulation time 68876930 ps
CPU time 0.66 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:25:55 PM PDT 24
Peak memory 203592 kb
Host smart-81ee0e43-ed1f-4cb7-b637-5c2261b2e4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634847351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.634847351
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.42743350
Short name T603
Test name
Test status
Simulation time 1020371612 ps
CPU time 21.29 seconds
Started Mar 28 03:25:56 PM PDT 24
Finished Mar 28 03:26:17 PM PDT 24
Peak memory 324328 kb
Host smart-0d3e9caa-3fe4-44f4-9738-e080d5d41be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42743350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.42743350
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.744238489
Short name T207
Test name
Test status
Simulation time 16564716909 ps
CPU time 1966.41 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:58:41 PM PDT 24
Peak memory 2247944 kb
Host smart-7ede72a0-274e-461b-b09c-e18e0791d50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744238489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.744238489
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.392085133
Short name T866
Test name
Test status
Simulation time 931994511 ps
CPU time 4.64 seconds
Started Mar 28 03:25:56 PM PDT 24
Finished Mar 28 03:26:01 PM PDT 24
Peak memory 203812 kb
Host smart-e6807adb-2b3e-4efc-bfb7-9bf373f4bfe5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392085133 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.392085133
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3340629523
Short name T238
Test name
Test status
Simulation time 10105985242 ps
CPU time 14.01 seconds
Started Mar 28 03:25:56 PM PDT 24
Finished Mar 28 03:26:10 PM PDT 24
Peak memory 296384 kb
Host smart-6c028998-82ab-4f25-bdc2-d381629258eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340629523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3340629523
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.3090890809
Short name T668
Test name
Test status
Simulation time 10616763287 ps
CPU time 16.96 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:26:12 PM PDT 24
Peak memory 328584 kb
Host smart-9c78149e-1644-4b24-84a1-2a3459b99335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090890809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.3090890809
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3828280821
Short name T953
Test name
Test status
Simulation time 590081626 ps
CPU time 3.34 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:25:57 PM PDT 24
Peak memory 203724 kb
Host smart-db62fb74-dac3-4b30-b5d1-6ab0e7a156e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828280821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3828280821
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2931703028
Short name T434
Test name
Test status
Simulation time 943986792 ps
CPU time 4.29 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:25:57 PM PDT 24
Peak memory 203824 kb
Host smart-d9eb3225-2236-493e-8423-045a60b91b01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931703028 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2931703028
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.241522733
Short name T543
Test name
Test status
Simulation time 4408864270 ps
CPU time 8.51 seconds
Started Mar 28 03:25:57 PM PDT 24
Finished Mar 28 03:26:05 PM PDT 24
Peak memory 203888 kb
Host smart-f73317d2-4fcb-446a-b741-bf8eb28d77b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241522733 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.241522733
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3988634259
Short name T783
Test name
Test status
Simulation time 2673938486 ps
CPU time 46.79 seconds
Started Mar 28 03:25:54 PM PDT 24
Finished Mar 28 03:26:41 PM PDT 24
Peak memory 203864 kb
Host smart-9a7efc2c-6f11-4985-a7df-959ee9b1c1d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988634259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3988634259
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2196651899
Short name T802
Test name
Test status
Simulation time 675690116 ps
CPU time 6.81 seconds
Started Mar 28 03:25:52 PM PDT 24
Finished Mar 28 03:25:58 PM PDT 24
Peak memory 203804 kb
Host smart-082caa8e-7070-4370-908f-a03f0fab2988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196651899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2196651899
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.3024019218
Short name T800
Test name
Test status
Simulation time 10794702336 ps
CPU time 21.54 seconds
Started Mar 28 03:25:55 PM PDT 24
Finished Mar 28 03:26:17 PM PDT 24
Peak memory 203876 kb
Host smart-7186d58c-6bdb-4f27-a0e2-91b726b099ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024019218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.3024019218
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.316524756
Short name T216
Test name
Test status
Simulation time 41149256288 ps
CPU time 949.23 seconds
Started Mar 28 03:25:50 PM PDT 24
Finished Mar 28 03:41:40 PM PDT 24
Peak memory 4393828 kb
Host smart-8ef6cb0e-20be-4e73-9121-4f78f93210b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316524756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.316524756
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2929080778
Short name T435
Test name
Test status
Simulation time 2342710007 ps
CPU time 6.55 seconds
Started Mar 28 03:25:55 PM PDT 24
Finished Mar 28 03:26:01 PM PDT 24
Peak memory 220060 kb
Host smart-de698414-c03d-4f47-928f-f3e01b02a517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929080778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2929080778
Directory /workspace/9.i2c_target_timeout/latest
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