Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	92948	1			T1	1		T2	2		T3	3
all_values[1]	92948	1			T1	1		T2	2		T3	3
all_values[2]	92948	1			T1	1		T2	2		T3	3
all_values[3]	92948	1			T1	1		T2	2		T3	3
all_values[4]	92948	1			T1	1		T2	2		T3	3
all_values[5]	92948	1			T1	1		T2	2		T3	3
all_values[6]	92948	1			T1	1		T2	2		T3	3
all_values[7]	92948	1			T1	1		T2	2		T3	3
all_values[8]	92948	1			T1	1		T2	2		T3	3
all_values[9]	92948	1			T1	1		T2	2		T3	3
all_values[10]	92948	1			T1	1		T2	2		T3	3
all_values[11]	92948	1			T1	1		T2	2		T3	3
all_values[12]	92948	1			T1	1		T2	2		T3	3
all_values[13]	92948	1			T1	1		T2	2		T3	3
all_values[14]	92948	1			T1	1		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1194477

1

T1

15

T2

26

T3

40

auto[1]

199743

1

T2

4

T3

5

T4

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1314290

1

T1

15

T2

30

T3

45

auto[1]

79930

1

T20

4173

T99

9566

T100

199

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	20357	1			T1	1		T4	1		T6	3
all_values[0]	auto[0]	auto[1]	1589	1			T20	12		T99	37		T100	9
all_values[0]	auto[1]	auto[0]	66690	1			T2	2		T3	3		T4	2
all_values[0]	auto[1]	auto[1]	4312	1			T20	267		T99	601		T100	4
all_values[1]	auto[0]	auto[0]	87372	1			T1	1		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	5412	1			T20	275		T99	632		T100	7
all_values[1]	auto[1]	auto[0]	39	1			T213	1		T214	3		T215	6
all_values[1]	auto[1]	auto[1]	125	1			T20	3		T99	5		T100	2
all_values[2]	auto[0]	auto[0]	87396	1			T1	1		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	5421	1			T20	274		T99	636		T100	10
all_values[2]	auto[1]	auto[1]	131	1			T20	5		T99	2		T100	3
all_values[3]	auto[0]	auto[0]	87400	1			T1	1		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	5404	1			T20	278		T99	629		T100	4
all_values[3]	auto[1]	auto[1]	144	1			T20	1		T99	9		T100	10
all_values[4]	auto[0]	auto[0]	87736	1			T1	1		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	5047	1			T20	276		T99	634		T100	13
all_values[4]	auto[1]	auto[0]	12	1			T216	1		T217	1		T218	1
all_values[4]	auto[1]	auto[1]	153	1			T20	3		T99	4		T100	1
all_values[5]	auto[0]	auto[0]	89989	1			T1	1		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	2803	1			T20	275		T99	629		T100	6
all_values[5]	auto[1]	auto[1]	156	1			T20	4		T99	9		T100	7
all_values[6]	auto[0]	auto[0]	84568	1			T1	1		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	5213	1			T20	268		T99	605		T100	5
all_values[6]	auto[1]	auto[0]	2946	1			T4	1		T6	1		T8	1
all_values[6]	auto[1]	auto[1]	221	1			T20	10		T99	33		T100	9
all_values[7]	auto[0]	auto[0]	66355	1			T1	1		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	3912	1			T20	202		T99	454		T100	6
all_values[7]	auto[1]	auto[0]	21147	1			T4	1		T7	1		T8	1
all_values[7]	auto[1]	auto[1]	1534	1			T20	76		T99	184		T100	7
all_values[8]	auto[0]	auto[0]	79945	1			T1	1		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	5195	1			T20	233		T99	543		T100	9
all_values[8]	auto[1]	auto[0]	7074	1			T4	1		T7	1		T8	1
all_values[8]	auto[1]	auto[1]	734	1			T20	46		T99	95		T100	5
all_values[9]	auto[0]	auto[0]	87311	1			T1	1		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	2668	1			T20	260		T99	593		T100	7
all_values[9]	auto[1]	auto[0]	2678	1			T3	1		T4	1		T7	1
all_values[9]	auto[1]	auto[1]	291	1			T20	19		T99	45		T100	6
all_values[10]	auto[0]	auto[0]	87010	1			T1	1		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	5793	1			T20	274		T99	635		T100	9
all_values[10]	auto[1]	auto[1]	145	1			T20	5		T99	3		T100	4
all_values[11]	auto[0]	auto[0]	1956	1			T1	1		T3	2		T4	1
all_values[11]	auto[0]	auto[1]	259	1			T20	12		T99	20		T100	8
all_values[11]	auto[1]	auto[0]	85248	1			T2	2		T3	1		T4	2
all_values[11]	auto[1]	auto[1]	5485	1			T20	261		T99	618		T100	6
all_values[12]	auto[0]	auto[0]	87021	1			T1	1		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	5786	1			T20	272		T99	633		T100	10
all_values[12]	auto[1]	auto[1]	141	1			T20	6		T99	3		T100	4
all_values[13]	auto[0]	auto[0]	87016	1			T1	1		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	5752	1			T20	274		T99	629		T100	5
all_values[13]	auto[1]	auto[0]	8	1			T34	1		T219	1		T220	1
all_values[13]	auto[1]	auto[1]	172	1			T20	5		T99	9		T100	9
all_values[14]	auto[0]	auto[0]	87016	1			T1	1		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	5775	1			T20	271		T99	630		T100	9
all_values[14]	auto[1]	auto[1]	157	1			T20	6		T99	7		T100	5