ASSERT | PROPERTIES | SEQUENCES | |
Total | 441 | 0 | 10 |
Category 0 | 441 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 441 | 0 | 10 |
Severity 0 | 441 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 441 | 100.00 |
Uncovered | 8 | 1.81 |
Success | 433 | 98.19 |
Failure | 0 | 0.00 |
Incomplete | 1 | 0.23 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.i2c_core.HostDisablePulse_A | 0 | 0 | 231277358 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.AcqWriteStableBeforeHandshake_A | 0 | 0 | 231277358 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.FmtWriteStableBeforeHandshake_A | 0 | 0 | 231277358 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.TxWriteStableBeforeHandshake_A | 0 | 0 | 231277358 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.NoSramWriteWhenFull_A | 0 | 0 | 231277358 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.LockArbDecision_A | 0 | 0 | 231277358 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.NoReadyValidNoGrant_A | 0 | 0 | 231277358 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqStaysHighUntilGranted0_M | 0 | 0 | 231277358 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.RoundRobin_A | 0 | 0 | 231277358 | 442 | 0 | 1150 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 231961733 | 137371 | 137371 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 231961733 | 148 | 148 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 231961733 | 157 | 157 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 231961733 | 105 | 105 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 231961733 | 20 | 20 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 231961733 | 84 | 84 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 231961733 | 69 | 69 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 231961733 | 2552 | 2552 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 231961733 | 1959667 | 1959667 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 231961733 | 17350402 | 17350402 | 1293 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 231961733 | 137371 | 137371 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 231961733 | 148 | 148 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 231961733 | 157 | 157 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 231961733 | 105 | 105 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 231961733 | 20 | 20 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 231961733 | 84 | 84 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 231961733 | 69 | 69 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 231961733 | 2552 | 2552 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 231961733 | 1959667 | 1959667 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 231961733 | 17350402 | 17350402 | 1293 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |