Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	92948	1			T1	1		T2	2		T3	3
all_pins[1]	92948	1			T1	1		T2	2		T3	3
all_pins[2]	92948	1			T1	1		T2	2		T3	3
all_pins[3]	92948	1			T1	1		T2	2		T3	3
all_pins[4]	92948	1			T1	1		T2	2		T3	3
all_pins[5]	92948	1			T1	1		T2	2		T3	3
all_pins[6]	92948	1			T1	1		T2	2		T3	3
all_pins[7]	92948	1			T1	1		T2	2		T3	3
all_pins[8]	92948	1			T1	1		T2	2		T3	3
all_pins[9]	92948	1			T1	1		T2	2		T3	3
all_pins[10]	92948	1			T1	1		T2	2		T3	3
all_pins[11]	92948	1			T1	1		T2	2		T3	3
all_pins[12]	92948	1			T1	1		T2	2		T3	3
all_pins[13]	92948	1			T1	1		T2	2		T3	3
all_pins[14]	92948	1			T1	1		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1202316	1			T1	15		T2	26		T3	40
values[0x1]	191904	1			T2	4		T3	5		T4	8
transitions[0x0=>0x1]	186269	1			T2	4		T3	5		T4	5
transitions[0x1=>0x0]	185385	1			T2	3		T3	4		T4	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	24922	1			T1	1		T4	1		T6	3
all_pins[0]	values[0x1]	68026	1			T2	2		T3	3		T4	2
all_pins[0]	transitions[0x0=>0x1]	67964	1			T2	2		T3	3		T4	2
all_pins[0]	transitions[0x1=>0x0]	49	1			T231	1		T160	1		T165	1
all_pins[1]	values[0x0]	92837	1			T1	1		T2	2		T3	3
all_pins[1]	values[0x1]	111	1			T20	2		T213	1		T25	1
all_pins[1]	transitions[0x0=>0x1]	90	1			T20	1		T213	1		T25	1
all_pins[1]	transitions[0x1=>0x0]	51	1			T20	4		T99	1		T100	1
all_pins[2]	values[0x0]	92876	1			T1	1		T2	2		T3	3
all_pins[2]	values[0x1]	72	1			T20	5		T99	2		T100	1
all_pins[2]	transitions[0x0=>0x1]	57	1			T20	4		T99	2		T160	1
all_pins[2]	transitions[0x1=>0x0]	66	1			T99	4		T100	6		T160	4
all_pins[3]	values[0x0]	92867	1			T1	1		T2	2		T3	3
all_pins[3]	values[0x1]	81	1			T20	1		T99	4		T100	7
all_pins[3]	transitions[0x0=>0x1]	61	1			T20	1		T99	4		T100	7
all_pins[3]	transitions[0x1=>0x0]	68	1			T20	2		T216	1		T217	1
all_pins[4]	values[0x0]	92860	1			T1	1		T2	2		T3	3
all_pins[4]	values[0x1]	88	1			T20	2		T216	1		T217	1
all_pins[4]	transitions[0x0=>0x1]	73	1			T216	1		T217	1		T218	1
all_pins[4]	transitions[0x1=>0x0]	57	1			T99	7		T100	5		T160	2
all_pins[5]	values[0x0]	92876	1			T1	1		T2	2		T3	3
all_pins[5]	values[0x1]	72	1			T20	2		T99	7		T100	5
all_pins[5]	transitions[0x0=>0x1]	62	1			T20	2		T99	7		T100	5
all_pins[5]	transitions[0x1=>0x0]	2868	1			T4	1		T6	1		T8	1
all_pins[6]	values[0x0]	90070	1			T1	1		T2	2		T3	3
all_pins[6]	values[0x1]	2878	1			T4	1		T6	1		T8	1
all_pins[6]	transitions[0x0=>0x1]	1569	1			T6	1		T9	1		T36	1
all_pins[6]	transitions[0x1=>0x0]	21135	1			T7	1		T9	16		T46	61
all_pins[7]	values[0x0]	70504	1			T1	1		T2	2		T3	3
all_pins[7]	values[0x1]	22444	1			T4	1		T7	1		T8	1
all_pins[7]	transitions[0x0=>0x1]	19408	1			T9	15		T46	54		T11	37
all_pins[7]	transitions[0x1=>0x0]	4507	1			T46	12		T11	17		T12	28
all_pins[8]	values[0x0]	85405	1			T1	1		T2	2		T3	3
all_pins[8]	values[0x1]	7543	1			T4	1		T7	1		T8	1
all_pins[8]	transitions[0x0=>0x1]	6515	1			T9	1		T46	16		T11	21
all_pins[8]	transitions[0x1=>0x0]	1896	1			T3	1		T9	1		T10	1
all_pins[9]	values[0x0]	90024	1			T1	1		T2	2		T3	2
all_pins[9]	values[0x1]	2924	1			T3	1		T4	1		T7	1
all_pins[9]	transitions[0x0=>0x1]	2903	1			T3	1		T4	1		T7	1
all_pins[9]	transitions[0x1=>0x0]	59	1			T20	2		T99	3		T100	1
all_pins[10]	values[0x0]	92868	1			T1	1		T2	2		T3	3
all_pins[10]	values[0x1]	80	1			T20	2		T99	3		T100	2
all_pins[10]	transitions[0x0=>0x1]	60	1			T99	3		T100	2		T21	1
all_pins[10]	transitions[0x1=>0x0]	87343	1			T2	2		T3	1		T4	2
all_pins[11]	values[0x0]	5585	1			T1	1		T3	2		T4	1
all_pins[11]	values[0x1]	87363	1			T2	2		T3	1		T4	2
all_pins[11]	transitions[0x0=>0x1]	87351	1			T2	2		T3	1		T4	2
all_pins[11]	transitions[0x1=>0x0]	50	1			T20	1		T99	1		T100	1
all_pins[12]	values[0x0]	92886	1			T1	1		T2	2		T3	3
all_pins[12]	values[0x1]	62	1			T20	1		T99	2		T100	1
all_pins[12]	transitions[0x0=>0x1]	46	1			T20	1		T99	2		T100	1
all_pins[12]	transitions[0x1=>0x0]	80	1			T20	2		T34	1		T99	6
all_pins[13]	values[0x0]	92852	1			T1	1		T2	2		T3	3
all_pins[13]	values[0x1]	96	1			T20	2		T34	1		T99	6
all_pins[13]	transitions[0x0=>0x1]	74	1			T20	2		T34	1		T99	5
all_pins[13]	transitions[0x1=>0x0]	42	1			T20	3		T22	1		T171	1
all_pins[14]	values[0x0]	92884	1			T1	1		T2	2		T3	3
all_pins[14]	values[0x1]	64	1			T20	3		T99	1		T100	2
all_pins[14]	transitions[0x0=>0x1]	36	1			T20	2		T100	1		T171	1
all_pins[14]	transitions[0x1=>0x0]	67114	1			T2	1		T3	2		T4	1