Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	342	1			T20	11		T99	11		T100	11
all_values[1]	342	1			T20	11		T99	11		T100	11
all_values[2]	342	1			T20	11		T99	11		T100	11
all_values[3]	342	1			T20	11		T99	11		T100	11
all_values[4]	342	1			T20	11		T99	11		T100	11
all_values[5]	342	1			T20	11		T99	11		T100	11
all_values[6]	342	1			T20	11		T99	11		T100	11
all_values[7]	342	1			T20	11		T99	11		T100	11
all_values[8]	342	1			T20	11		T99	11		T100	11
all_values[9]	342	1			T20	11		T99	11		T100	11
all_values[10]	342	1			T20	11		T99	11		T100	11
all_values[11]	342	1			T20	11		T99	11		T100	11
all_values[12]	342	1			T20	11		T99	11		T100	11
all_values[13]	342	1			T20	11		T99	11		T100	11
all_values[14]	342	1			T20	11		T99	11		T100	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2708

1

T20

94

T99

81

T100

80

auto[1]

2422

1

T20

71

T99

84

T100

85

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

915

1

T20

11

T99

4

T100

10

auto[1]

4215

1

T20

154

T99

161

T100

155

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3084

1

T20

97

T99

98

T100

96

auto[1]

2046

1

T20

68

T99

67

T100

69

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	47	1			T160	1		T230	1		T232	2
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T20	4		T99	3		T100	2
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T100	1		T165	2		T172	1
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T20	3		T99	3		T100	4
all_values[0]	auto[1]	auto[0]	auto[1]	76	1			T20	2		T99	1		T100	3
all_values[0]	auto[1]	auto[1]	auto[1]	54	1			T20	2		T99	4		T100	1
all_values[1]	auto[0]	auto[0]	auto[0]	45	1			T20	1		T100	3		T160	1
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T20	3		T99	3		T100	4
all_values[1]	auto[0]	auto[1]	auto[0]	33	1			T99	1		T100	1		T160	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T20	4		T99	2		T100	1
all_values[1]	auto[1]	auto[0]	auto[1]	68	1			T20	3		T99	2		T100	2
all_values[1]	auto[1]	auto[1]	auto[1]	56	1			T99	3		T160	1		T165	1
all_values[2]	auto[0]	auto[0]	auto[0]	38	1			T100	1		T160	1		T233	1
all_values[2]	auto[0]	auto[0]	auto[1]	66	1			T20	3		T99	3		T100	3
all_values[2]	auto[0]	auto[1]	auto[0]	29	1			T230	4		T232	2		T234	3
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T20	3		T99	6		T100	4
all_values[2]	auto[1]	auto[0]	auto[1]	61	1			T20	1		T100	2		T22	3
all_values[2]	auto[1]	auto[1]	auto[1]	70	1			T20	4		T99	2		T100	1
all_values[3]	auto[0]	auto[0]	auto[0]	39	1			T22	4		T230	3		T232	1
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T20	3		T99	1		T100	1
all_values[3]	auto[0]	auto[1]	auto[0]	30	1			T230	1		T234	1		T235	4
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T20	5		T99	4		T100	4
all_values[3]	auto[1]	auto[0]	auto[1]	73	1			T99	3		T100	3		T160	1
all_values[3]	auto[1]	auto[1]	auto[1]	63	1			T20	3		T99	3		T100	3
all_values[4]	auto[0]	auto[0]	auto[0]	45	1			T160	3		T230	2		T232	1
all_values[4]	auto[0]	auto[0]	auto[1]	67	1			T20	2		T99	5		T100	1
all_values[4]	auto[0]	auto[1]	auto[0]	23	1			T160	4		T172	1		T233	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T20	4		T99	4		T100	8
all_values[4]	auto[1]	auto[0]	auto[1]	70	1			T20	4		T99	1		T230	1
all_values[4]	auto[1]	auto[1]	auto[1]	64	1			T20	1		T99	1		T100	2
all_values[5]	auto[0]	auto[0]	auto[0]	40	1			T100	1		T160	1		T21	2
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T20	5		T99	2		T100	2
all_values[5]	auto[0]	auto[1]	auto[0]	22	1			T165	1		T21	2		T230	1
all_values[5]	auto[0]	auto[1]	auto[1]	73	1			T20	2		T99	4		T100	4
all_values[5]	auto[1]	auto[0]	auto[1]	72	1			T20	2		T99	3		T100	2
all_values[5]	auto[1]	auto[1]	auto[1]	59	1			T20	2		T99	2		T100	2
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T20	1		T160	1		T165	2
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T20	3		T99	3		T100	3
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T165	2		T230	1		T171	1
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T20	4		T99	2		T100	1
all_values[6]	auto[1]	auto[0]	auto[1]	72	1			T20	2		T99	4		T100	1
all_values[6]	auto[1]	auto[1]	auto[1]	69	1			T20	1		T99	2		T100	6
all_values[7]	auto[0]	auto[0]	auto[0]	30	1			T20	1		T165	2		T22	1
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T20	4		T99	3		T100	3
all_values[7]	auto[0]	auto[1]	auto[0]	25	1			T100	1		T165	2		T22	2
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T20	1		T99	2		T100	1
all_values[7]	auto[1]	auto[0]	auto[1]	72	1			T20	4		T99	2		T100	4
all_values[7]	auto[1]	auto[1]	auto[1]	72	1			T20	1		T99	4		T100	2
all_values[8]	auto[0]	auto[0]	auto[0]	26	1			T160	1		T172	1		T233	1
all_values[8]	auto[0]	auto[0]	auto[1]	76	1			T20	5		T99	5		T100	2
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T160	2		T230	1		T172	1
all_values[8]	auto[0]	auto[1]	auto[1]	65	1			T20	1		T99	3		T100	5
all_values[8]	auto[1]	auto[0]	auto[1]	86	1			T20	2		T99	1		T100	2
all_values[8]	auto[1]	auto[1]	auto[1]	64	1			T20	3		T99	2		T100	2
all_values[9]	auto[0]	auto[0]	auto[0]	45	1			T100	1		T160	1		T21	2
all_values[9]	auto[0]	auto[0]	auto[1]	58	1			T20	3		T99	6		T100	2
all_values[9]	auto[0]	auto[1]	auto[0]	21	1			T21	2		T230	1		T172	1
all_values[9]	auto[0]	auto[1]	auto[1]	82	1			T20	2		T100	2		T160	4
all_values[9]	auto[1]	auto[0]	auto[1]	71	1			T20	4		T99	3		T100	4
all_values[9]	auto[1]	auto[1]	auto[1]	65	1			T20	2		T99	2		T100	2
all_values[10]	auto[0]	auto[0]	auto[0]	23	1			T165	2		T232	1		T236	1
all_values[10]	auto[0]	auto[0]	auto[1]	65	1			T20	4		T99	5		T100	2
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T100	1		T21	1		T172	1
all_values[10]	auto[0]	auto[1]	auto[1]	89	1			T20	2		T99	3		T100	4
all_values[10]	auto[1]	auto[0]	auto[1]	67	1			T20	2		T99	1		T100	1
all_values[10]	auto[1]	auto[1]	auto[1]	78	1			T20	3		T99	2		T100	3
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T20	2		T22	2		T172	1
all_values[11]	auto[0]	auto[0]	auto[1]	75	1			T20	1		T99	2		T100	4
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T20	3		T230	1		T172	3
all_values[11]	auto[0]	auto[1]	auto[1]	76	1			T20	1		T99	4		T100	1
all_values[11]	auto[1]	auto[0]	auto[1]	70	1			T20	4		T99	5		T100	5
all_values[11]	auto[1]	auto[1]	auto[1]	59	1			T100	1		T165	3		T21	1
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T20	1		T99	2		T160	2
all_values[12]	auto[0]	auto[0]	auto[1]	67	1			T20	3		T99	1		T100	2
all_values[12]	auto[0]	auto[1]	auto[0]	16	1			T171	1		T172	2		T237	2
all_values[12]	auto[0]	auto[1]	auto[1]	82	1			T20	1		T99	5		T100	5
all_values[12]	auto[1]	auto[0]	auto[1]	86	1			T20	5		T99	1		T100	4
all_values[12]	auto[1]	auto[1]	auto[1]	55	1			T20	1		T99	2		T22	1
all_values[13]	auto[0]	auto[0]	auto[0]	45	1			T160	4		T171	1		T233	5
all_values[13]	auto[0]	auto[0]	auto[1]	74	1			T20	3		T99	1		T100	1
all_values[13]	auto[0]	auto[1]	auto[0]	10	1			T171	1		T233	2		T238	1
all_values[13]	auto[0]	auto[1]	auto[1]	72	1			T20	3		T99	4		T100	4
all_values[13]	auto[1]	auto[0]	auto[1]	77	1			T20	4		T99	2		T100	1
all_values[13]	auto[1]	auto[1]	auto[1]	64	1			T20	1		T99	4		T100	5
all_values[14]	auto[0]	auto[0]	auto[0]	28	1			T236	1		T239	2		T240	1
all_values[14]	auto[0]	auto[0]	auto[1]	90	1			T20	1		T99	4		T100	3
all_values[14]	auto[0]	auto[1]	auto[0]	22	1			T20	2		T99	1		T165	1
all_values[14]	auto[0]	auto[1]	auto[1]	69	1			T20	3		T99	1		T100	3
all_values[14]	auto[1]	auto[0]	auto[1]	76	1			T20	2		T99	3		T100	5
all_values[14]	auto[1]	auto[1]	auto[1]	57	1			T20	3		T99	2		T165	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal