Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	93823	1			T1	2		T2	2		T3	2
all_values[1]	93823	1			T1	2		T2	2		T3	2
all_values[2]	93823	1			T1	2		T2	2		T3	2
all_values[3]	93823	1			T1	2		T2	2		T3	2
all_values[4]	93823	1			T1	2		T2	2		T3	2
all_values[5]	93823	1			T1	2		T2	2		T3	2
all_values[6]	93823	1			T1	2		T2	2		T3	2
all_values[7]	93823	1			T1	2		T2	2		T3	2
all_values[8]	93823	1			T1	2		T2	2		T3	2
all_values[9]	93823	1			T1	2		T2	2		T3	2
all_values[10]	93823	1			T1	2		T2	2		T3	2
all_values[11]	93823	1			T1	2		T2	2		T3	2
all_values[12]	93823	1			T1	2		T2	2		T3	2
all_values[13]	93823	1			T1	2		T2	2		T3	2
all_values[14]	93823	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1211302

1

T1

26

T2

26

T3

26

auto[1]

196043

1

T1

4

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1363873

1

T1

30

T2

30

T3

30

auto[1]

43472

1

T98

109

T30

118

T112

149

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	23759	1			T4	3		T7	1		T17	3
all_values[0]	auto[0]	auto[1]	1430	1			T98	3		T112	3		T95	1241
all_values[0]	auto[1]	auto[0]	67169	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	1465	1			T98	4		T30	6		T112	7
all_values[1]	auto[0]	auto[0]	90878	1			T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	2762	1			T98	7		T30	5		T112	11
all_values[1]	auto[1]	auto[0]	37	1			T17	1		T16	1		T162	1
all_values[1]	auto[1]	auto[1]	146	1			T98	1		T30	4		T112	1
all_values[2]	auto[0]	auto[0]	90941	1			T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	2739	1			T30	6		T112	9		T95	2536
all_values[2]	auto[1]	auto[1]	143	1			T30	2		T112	3		T95	5
all_values[3]	auto[0]	auto[0]	90923	1			T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	2744	1			T98	7		T30	4		T112	11
all_values[3]	auto[1]	auto[1]	156	1			T98	2		T30	1		T95	8
all_values[4]	auto[0]	auto[0]	90914	1			T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	2747	1			T98	5		T30	4		T112	10
all_values[4]	auto[1]	auto[0]	9	1			T213	1		T214	1		T215	1
all_values[4]	auto[1]	auto[1]	153	1			T98	2		T30	3		T112	2
all_values[5]	auto[0]	auto[0]	90945	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	2711	1			T30	2		T95	2535		T31	19
all_values[5]	auto[1]	auto[1]	167	1			T30	7		T95	6		T31	2
all_values[6]	auto[0]	auto[0]	88456	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	2750	1			T98	6		T30	2		T112	7
all_values[6]	auto[1]	auto[0]	2450	1			T4	1		T7	1		T17	8
all_values[6]	auto[1]	auto[1]	167	1			T98	3		T30	6		T112	5
all_values[7]	auto[0]	auto[0]	69115	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	2635	1			T98	5		T30	5		T112	9
all_values[7]	auto[1]	auto[0]	21804	1			T17	70		T18	4		T49	1
all_values[7]	auto[1]	auto[1]	269	1			T98	4		T30	4		T112	3
all_values[8]	auto[0]	auto[0]	84146	1			T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	2588	1			T98	7		T30	4		T112	6
all_values[8]	auto[1]	auto[0]	6772	1			T7	1		T17	14		T18	32
all_values[8]	auto[1]	auto[1]	317	1			T98	2		T30	5		T112	4
all_values[9]	auto[0]	auto[0]	88519	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	2740	1			T98	5		T30	6		T112	9
all_values[9]	auto[1]	auto[0]	2402	1			T6	1		T7	1		T17	12
all_values[9]	auto[1]	auto[1]	162	1			T98	4		T30	3		T112	3
all_values[10]	auto[0]	auto[0]	90930	1			T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	2762	1			T98	7		T30	4		T112	9
all_values[10]	auto[1]	auto[1]	131	1			T98	2		T30	2		T112	2
all_values[11]	auto[0]	auto[0]	1949	1			T4	3		T7	1		T17	3
all_values[11]	auto[0]	auto[1]	214	1			T98	5		T95	25		T31	6
all_values[11]	auto[1]	auto[0]	88995	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	2665	1			T98	4		T30	9		T95	2516
all_values[12]	auto[0]	auto[0]	90922	1			T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	2760	1			T98	7		T30	5		T112	9
all_values[12]	auto[1]	auto[1]	141	1			T98	2		T30	4		T112	3
all_values[13]	auto[0]	auto[0]	90903	1			T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	2749	1			T98	6		T30	2		T112	9
all_values[13]	auto[1]	auto[0]	5	1			T205	1		T206	1		T216	1
all_values[13]	auto[1]	auto[1]	166	1			T98	2		T30	5		T112	2
all_values[14]	auto[0]	auto[0]	90930	1			T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	2741	1			T98	5		T30	5		T112	11
all_values[14]	auto[1]	auto[1]	152	1			T98	2		T30	3		T112	1