Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	93823	1			T1	2		T2	2		T3	2
all_pins[1]	93823	1			T1	2		T2	2		T3	2
all_pins[2]	93823	1			T1	2		T2	2		T3	2
all_pins[3]	93823	1			T1	2		T2	2		T3	2
all_pins[4]	93823	1			T1	2		T2	2		T3	2
all_pins[5]	93823	1			T1	2		T2	2		T3	2
all_pins[6]	93823	1			T1	2		T2	2		T3	2
all_pins[7]	93823	1			T1	2		T2	2		T3	2
all_pins[8]	93823	1			T1	2		T2	2		T3	2
all_pins[9]	93823	1			T1	2		T2	2		T3	2
all_pins[10]	93823	1			T1	2		T2	2		T3	2
all_pins[11]	93823	1			T1	2		T2	2		T3	2
all_pins[12]	93823	1			T1	2		T2	2		T3	2
all_pins[13]	93823	1			T1	2		T2	2		T3	2
all_pins[14]	93823	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1219030	1			T1	26		T2	26		T3	26
values[0x1]	188315	1			T1	4		T2	4		T3	4
transitions[0x0=>0x1]	183545	1			T1	4		T2	4		T3	4
transitions[0x1=>0x0]	182673	1			T1	3		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	28102	1			T4	3		T7	1		T17	3
all_pins[0]	values[0x1]	65721	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	65655	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	60	1			T98	1		T112	1		T95	3
all_pins[1]	values[0x0]	93697	1			T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	126	1			T17	1		T16	1		T162	1
all_pins[1]	transitions[0x0=>0x1]	102	1			T17	1		T16	1		T162	1
all_pins[1]	transitions[0x1=>0x0]	45	1			T30	1		T95	2		T32	2
all_pins[2]	values[0x0]	93754	1			T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	69	1			T30	2		T95	4		T31	1
all_pins[2]	transitions[0x0=>0x1]	55	1			T30	2		T31	1		T32	3
all_pins[2]	transitions[0x1=>0x0]	62	1			T95	4		T31	2		T168	1
all_pins[3]	values[0x0]	93747	1			T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	76	1			T95	8		T31	2		T168	1
all_pins[3]	transitions[0x0=>0x1]	54	1			T95	6		T31	1		T168	1
all_pins[3]	transitions[0x1=>0x0]	58	1			T213	1		T214	1		T215	1
all_pins[4]	values[0x0]	93743	1			T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	80	1			T213	1		T214	1		T215	1
all_pins[4]	transitions[0x0=>0x1]	63	1			T213	1		T214	1		T215	1
all_pins[4]	transitions[0x1=>0x0]	75	1			T30	5		T95	3		T32	3
all_pins[5]	values[0x0]	93731	1			T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	92	1			T30	5		T95	3		T31	2
all_pins[5]	transitions[0x0=>0x1]	69	1			T30	3		T95	2		T31	2
all_pins[5]	transitions[0x1=>0x0]	2306	1			T4	1		T7	1		T17	8
all_pins[6]	values[0x0]	91494	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	2329	1			T4	1		T7	1		T17	8
all_pins[6]	transitions[0x0=>0x1]	1311	1			T4	1		T7	1		T17	5
all_pins[6]	transitions[0x1=>0x0]	20881	1			T17	71		T18	3		T16	86
all_pins[7]	values[0x0]	71924	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	21899	1			T17	74		T18	4		T49	1
all_pins[7]	transitions[0x0=>0x1]	19333	1			T17	70		T18	2		T16	83
all_pins[7]	transitions[0x1=>0x0]	4221	1			T7	1		T17	10		T18	31
all_pins[8]	values[0x0]	87036	1			T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	6787	1			T7	1		T17	14		T18	33
all_pins[8]	transitions[0x0=>0x1]	5870	1			T17	9		T18	33		T16	41
all_pins[8]	transitions[0x1=>0x0]	1597	1			T6	1		T17	7		T18	2
all_pins[9]	values[0x0]	91309	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	2514	1			T6	1		T7	1		T17	12
all_pins[9]	transitions[0x0=>0x1]	2498	1			T6	1		T7	1		T17	12
all_pins[9]	transitions[0x1=>0x0]	44	1			T30	1		T112	1		T95	1
all_pins[10]	values[0x0]	93763	1			T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	60	1			T30	1		T112	2		T95	1
all_pins[10]	transitions[0x0=>0x1]	46	1			T30	1		T112	2		T31	1
all_pins[10]	transitions[0x1=>0x0]	88320	1			T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	5489	1			T4	3		T7	1		T17	3
all_pins[11]	values[0x1]	88334	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	88325	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	53	1			T30	2		T112	2		T95	1
all_pins[12]	values[0x0]	93761	1			T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	62	1			T30	2		T112	2		T95	1
all_pins[12]	transitions[0x0=>0x1]	44	1			T30	2		T112	1		T168	2
all_pins[12]	transitions[0x1=>0x0]	69	1			T205	1		T98	2		T206	1
all_pins[13]	values[0x0]	93736	1			T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	87	1			T205	1		T98	2		T206	1
all_pins[13]	transitions[0x0=>0x1]	63	1			T205	1		T206	1		T30	2
all_pins[13]	transitions[0x1=>0x0]	55	1			T30	1		T112	1		T95	1
all_pins[14]	values[0x0]	93744	1			T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	79	1			T98	2		T30	1		T112	1
all_pins[14]	transitions[0x0=>0x1]	57	1			T98	1		T112	1		T95	3
all_pins[14]	transitions[0x1=>0x0]	64827	1			T1	1		T2	1		T3	1