Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	340	1			T98	4		T30	7		T112	4
all_values[1]	340	1			T98	4		T30	7		T112	4
all_values[2]	340	1			T98	4		T30	7		T112	4
all_values[3]	340	1			T98	4		T30	7		T112	4
all_values[4]	340	1			T98	4		T30	7		T112	4
all_values[5]	340	1			T98	4		T30	7		T112	4
all_values[6]	340	1			T98	4		T30	7		T112	4
all_values[7]	340	1			T98	4		T30	7		T112	4
all_values[8]	340	1			T98	4		T30	7		T112	4
all_values[9]	340	1			T98	4		T30	7		T112	4
all_values[10]	340	1			T98	4		T30	7		T112	4
all_values[11]	340	1			T98	4		T30	7		T112	4
all_values[12]	340	1			T98	4		T30	7		T112	4
all_values[13]	340	1			T98	4		T30	7		T112	4
all_values[14]	340	1			T98	4		T30	7		T112	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2711

1

T98

41

T30

55

T112

34

auto[1]

2389

1

T98

19

T30

50

T112

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

825

1

T98

16

T30

17

T112

15

auto[1]

4275

1

T98

44

T30

88

T112

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2999

1

T98

37

T30

62

T112

35

auto[1]

2101

1

T98

23

T30

43

T112

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	44	1			T98	1		T112	2		T32	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T112	1		T95	1		T31	4
all_values[0]	auto[0]	auto[1]	auto[0]	17	1			T98	1		T30	3		T95	2
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T98	1		T30	1		T95	4
all_values[0]	auto[1]	auto[0]	auto[1]	74	1			T95	2		T31	2		T32	3
all_values[0]	auto[1]	auto[1]	auto[1]	62	1			T98	1		T30	3		T112	1
all_values[1]	auto[0]	auto[0]	auto[0]	33	1			T98	1		T168	3		T223	1
all_values[1]	auto[0]	auto[0]	auto[1]	68	1			T30	1		T112	1		T95	3
all_values[1]	auto[0]	auto[1]	auto[0]	14	1			T168	1		T223	1		T224	1
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T98	2		T30	2		T112	2
all_values[1]	auto[1]	auto[0]	auto[1]	72	1			T98	1		T30	2		T112	1
all_values[1]	auto[1]	auto[1]	auto[1]	74	1			T30	2		T95	2		T31	3
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T98	3		T168	1		T223	2
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T30	2		T112	1		T95	2
all_values[2]	auto[0]	auto[1]	auto[0]	22	1			T98	1		T30	1		T31	1
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T30	2		T95	4		T31	3
all_values[2]	auto[1]	auto[0]	auto[1]	79	1			T30	1		T112	3		T31	1
all_values[2]	auto[1]	auto[1]	auto[1]	64	1			T30	1		T95	5		T31	2
all_values[3]	auto[0]	auto[0]	auto[0]	33	1			T30	1		T112	1		T32	2
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T98	1		T30	1		T112	1
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T30	3		T32	3		T225	3
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T95	6		T31	2		T32	1
all_values[3]	auto[1]	auto[0]	auto[1]	78	1			T98	2		T30	2		T112	2
all_values[3]	auto[1]	auto[1]	auto[1]	72	1			T98	1		T95	5		T31	2
all_values[4]	auto[0]	auto[0]	auto[0]	25	1			T98	1		T95	1		T226	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T98	1		T112	2		T95	1
all_values[4]	auto[0]	auto[1]	auto[0]	26	1			T98	1		T30	2		T95	4
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T30	3		T112	1		T95	3
all_values[4]	auto[1]	auto[0]	auto[1]	80	1			T98	1		T30	2		T112	1
all_values[4]	auto[1]	auto[1]	auto[1]	60	1			T95	1		T31	1		T32	3
all_values[5]	auto[0]	auto[0]	auto[0]	35	1			T98	4		T112	1		T227	1
all_values[5]	auto[0]	auto[0]	auto[1]	55	1			T30	2		T168	3		T223	2
all_values[5]	auto[0]	auto[1]	auto[0]	29	1			T112	3		T32	2		T228	1
all_values[5]	auto[0]	auto[1]	auto[1]	65	1			T30	1		T95	5		T31	4
all_values[5]	auto[1]	auto[0]	auto[1]	75	1			T30	1		T95	2		T32	2
all_values[5]	auto[1]	auto[1]	auto[1]	81	1			T30	3		T95	4		T31	3
all_values[6]	auto[0]	auto[0]	auto[0]	25	1			T30	1		T226	1		T229	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T98	3		T95	6		T31	2
all_values[6]	auto[0]	auto[1]	auto[0]	14	1			T230	1		T231	1		T232	2
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T30	2		T112	1		T95	1
all_values[6]	auto[1]	auto[0]	auto[1]	81	1			T98	1		T30	3		T112	1
all_values[6]	auto[1]	auto[1]	auto[1]	60	1			T30	1		T112	2		T95	3
all_values[7]	auto[0]	auto[0]	auto[0]	25	1			T227	2		T233	2		T226	1
all_values[7]	auto[0]	auto[0]	auto[1]	67	1			T30	4		T95	4		T31	4
all_values[7]	auto[0]	auto[1]	auto[0]	26	1			T226	1		T231	1		T234	3
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T98	1		T112	3		T95	3
all_values[7]	auto[1]	auto[0]	auto[1]	74	1			T98	3		T30	3		T112	1
all_values[7]	auto[1]	auto[1]	auto[1]	75	1			T95	2		T31	1		T32	3
all_values[8]	auto[0]	auto[0]	auto[0]	32	1			T112	1		T31	1		T168	1
all_values[8]	auto[0]	auto[0]	auto[1]	88	1			T98	1		T30	1		T32	1
all_values[8]	auto[0]	auto[1]	auto[0]	20	1			T112	1		T95	2		T31	1
all_values[8]	auto[0]	auto[1]	auto[1]	67	1			T98	1		T30	4		T112	1
all_values[8]	auto[1]	auto[0]	auto[1]	67	1			T98	1		T30	1		T112	1
all_values[8]	auto[1]	auto[1]	auto[1]	66	1			T98	1		T30	1		T95	5
all_values[9]	auto[0]	auto[0]	auto[0]	27	1			T223	1		T228	1		T225	1
all_values[9]	auto[0]	auto[0]	auto[1]	73	1			T30	4		T112	1		T95	2
all_values[9]	auto[0]	auto[1]	auto[0]	27	1			T235	1		T169	6		T230	1
all_values[9]	auto[0]	auto[1]	auto[1]	73	1			T98	1		T30	1		T95	4
all_values[9]	auto[1]	auto[0]	auto[1]	72	1			T98	1		T30	1		T112	2
all_values[9]	auto[1]	auto[1]	auto[1]	68	1			T98	2		T30	1		T112	1
all_values[10]	auto[0]	auto[0]	auto[0]	36	1			T30	2		T112	1		T95	6
all_values[10]	auto[0]	auto[0]	auto[1]	78	1			T98	2		T30	1		T95	1
all_values[10]	auto[0]	auto[1]	auto[0]	22	1			T30	1		T95	2		T228	1
all_values[10]	auto[0]	auto[1]	auto[1]	73	1			T30	1		T112	1		T32	1
all_values[10]	auto[1]	auto[0]	auto[1]	70	1			T98	2		T30	1		T112	1
all_values[10]	auto[1]	auto[1]	auto[1]	61	1			T30	1		T112	1		T95	1
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T112	2		T223	4		T235	1
all_values[11]	auto[0]	auto[0]	auto[1]	75	1			T98	2		T30	3		T95	2
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T112	2		T32	1		T223	1
all_values[11]	auto[0]	auto[1]	auto[1]	76	1			T98	1		T95	4		T32	2
all_values[11]	auto[1]	auto[0]	auto[1]	71	1			T98	1		T30	4		T95	2
all_values[11]	auto[1]	auto[1]	auto[1]	51	1			T95	3		T31	2		T32	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T32	2		T223	1		T225	1
all_values[12]	auto[0]	auto[0]	auto[1]	79	1			T98	2		T30	2		T95	2
all_values[12]	auto[0]	auto[1]	auto[0]	23	1			T31	1		T228	2		T225	3
all_values[12]	auto[0]	auto[1]	auto[1]	66	1			T30	1		T112	1		T95	5
all_values[12]	auto[1]	auto[0]	auto[1]	87	1			T98	1		T30	2		T112	2
all_values[12]	auto[1]	auto[1]	auto[1]	54	1			T98	1		T30	2		T112	1
all_values[13]	auto[0]	auto[0]	auto[0]	23	1			T98	1		T112	1		T32	1
all_values[13]	auto[0]	auto[0]	auto[1]	85	1			T30	1		T95	6		T31	1
all_values[13]	auto[0]	auto[1]	auto[0]	20	1			T30	2		T31	1		T228	1
all_values[13]	auto[0]	auto[1]	auto[1]	74	1			T98	1		T30	1		T112	1
all_values[13]	auto[1]	auto[0]	auto[1]	79	1			T98	2		T30	1		T112	2
all_values[13]	auto[1]	auto[1]	auto[1]	59	1			T30	2		T95	4		T31	1
all_values[14]	auto[0]	auto[0]	auto[0]	34	1			T98	1		T30	1		T168	1
all_values[14]	auto[0]	auto[0]	auto[1]	69	1			T30	2		T95	5		T32	1
all_values[14]	auto[0]	auto[1]	auto[0]	29	1			T98	1		T31	3		T32	1
all_values[14]	auto[0]	auto[1]	auto[1]	73	1			T98	1		T30	2		T112	2
all_values[14]	auto[1]	auto[0]	auto[1]	69	1			T98	1		T30	2		T112	1
all_values[14]	auto[1]	auto[1]	auto[1]	66	1			T112	1		T95	3		T31	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal