Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.01 97.51 91.32 97.65 45.51 94.97 98.23 90.86


Total test records in report: 1299
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
T1259 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1581607825 Apr 02 12:40:34 PM PDT 24 Apr 02 12:40:35 PM PDT 24 81785139 ps
T1260 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2511758043 Apr 02 12:40:29 PM PDT 24 Apr 02 12:40:31 PM PDT 24 148993911 ps
T1261 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2836014879 Apr 02 12:40:53 PM PDT 24 Apr 02 12:40:56 PM PDT 24 182949627 ps
T138 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1267900911 Apr 02 12:40:31 PM PDT 24 Apr 02 12:40:32 PM PDT 24 16920617 ps
T1262 /workspace/coverage/cover_reg_top/47.i2c_intr_test.864889378 Apr 02 12:40:47 PM PDT 24 Apr 02 12:40:47 PM PDT 24 35419857 ps
T1263 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.39740537 Apr 02 12:40:46 PM PDT 24 Apr 02 12:40:49 PM PDT 24 289671582 ps
T1264 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2028821921 Apr 02 12:40:29 PM PDT 24 Apr 02 12:40:32 PM PDT 24 80482339 ps
T1265 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2815631594 Apr 02 12:40:54 PM PDT 24 Apr 02 12:40:57 PM PDT 24 451567552 ps
T1266 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2523720924 Apr 02 12:40:49 PM PDT 24 Apr 02 12:40:50 PM PDT 24 23857658 ps
T1267 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.380271587 Apr 02 12:40:47 PM PDT 24 Apr 02 12:40:49 PM PDT 24 181065119 ps
T1268 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2930511179 Apr 02 12:40:26 PM PDT 24 Apr 02 12:40:28 PM PDT 24 608289183 ps
T128 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1315881529 Apr 02 12:40:27 PM PDT 24 Apr 02 12:40:29 PM PDT 24 125045022 ps
T1269 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2477984921 Apr 02 12:40:41 PM PDT 24 Apr 02 12:40:43 PM PDT 24 32499755 ps
T1270 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2249801553 Apr 02 12:40:29 PM PDT 24 Apr 02 12:40:32 PM PDT 24 1027128963 ps
T139 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3863555011 Apr 02 12:40:42 PM PDT 24 Apr 02 12:40:43 PM PDT 24 22495790 ps
T1271 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2077020267 Apr 02 12:40:55 PM PDT 24 Apr 02 12:40:58 PM PDT 24 127732444 ps
T1272 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4081514336 Apr 02 12:40:31 PM PDT 24 Apr 02 12:40:32 PM PDT 24 29934092 ps
T1273 /workspace/coverage/cover_reg_top/0.i2c_intr_test.609365673 Apr 02 12:40:24 PM PDT 24 Apr 02 12:40:26 PM PDT 24 23670902 ps
T1274 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.365506459 Apr 02 12:40:41 PM PDT 24 Apr 02 12:40:42 PM PDT 24 67766771 ps
T1275 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2881511730 Apr 02 12:40:33 PM PDT 24 Apr 02 12:40:34 PM PDT 24 21483470 ps
T1276 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.615987518 Apr 02 12:40:53 PM PDT 24 Apr 02 12:40:54 PM PDT 24 36169584 ps
T1277 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2101357280 Apr 02 12:40:38 PM PDT 24 Apr 02 12:40:41 PM PDT 24 96608048 ps
T1278 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1234134696 Apr 02 12:40:28 PM PDT 24 Apr 02 12:40:29 PM PDT 24 65965785 ps
T1279 /workspace/coverage/cover_reg_top/33.i2c_intr_test.794453077 Apr 02 12:40:51 PM PDT 24 Apr 02 12:40:52 PM PDT 24 41396098 ps
T1280 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3071848483 Apr 02 12:40:34 PM PDT 24 Apr 02 12:40:35 PM PDT 24 37155494 ps
T1281 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1442318710 Apr 02 12:40:46 PM PDT 24 Apr 02 12:40:48 PM PDT 24 26130484 ps
T1282 /workspace/coverage/cover_reg_top/11.i2c_intr_test.937758792 Apr 02 12:40:38 PM PDT 24 Apr 02 12:40:39 PM PDT 24 58780948 ps
T140 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.735011419 Apr 02 12:40:28 PM PDT 24 Apr 02 12:40:29 PM PDT 24 36756964 ps
T1283 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4199573533 Apr 02 12:40:52 PM PDT 24 Apr 02 12:40:54 PM PDT 24 388922096 ps
T126 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2107484012 Apr 02 12:40:48 PM PDT 24 Apr 02 12:40:51 PM PDT 24 227243413 ps
T1284 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3919747130 Apr 02 12:40:26 PM PDT 24 Apr 02 12:40:28 PM PDT 24 116962911 ps
T1285 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1966822367 Apr 02 12:40:53 PM PDT 24 Apr 02 12:40:54 PM PDT 24 150074764 ps
T1286 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1185785898 Apr 02 12:40:46 PM PDT 24 Apr 02 12:40:47 PM PDT 24 16088469 ps
T127 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.251387802 Apr 02 12:40:53 PM PDT 24 Apr 02 12:40:54 PM PDT 24 66027451 ps
T1287 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4203676491 Apr 02 12:40:27 PM PDT 24 Apr 02 12:40:28 PM PDT 24 19361344 ps
T1288 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.246085526 Apr 02 12:40:35 PM PDT 24 Apr 02 12:40:39 PM PDT 24 52443364 ps
T1289 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.365301003 Apr 02 12:40:27 PM PDT 24 Apr 02 12:40:30 PM PDT 24 425824309 ps
T1290 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1338332667 Apr 02 12:40:52 PM PDT 24 Apr 02 12:40:52 PM PDT 24 248363173 ps
T1291 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1653063230 Apr 02 12:40:27 PM PDT 24 Apr 02 12:40:28 PM PDT 24 45607401 ps
T1292 /workspace/coverage/cover_reg_top/41.i2c_intr_test.104373777 Apr 02 12:40:51 PM PDT 24 Apr 02 12:40:51 PM PDT 24 26182657 ps
T1293 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2957856940 Apr 02 12:40:44 PM PDT 24 Apr 02 12:40:45 PM PDT 24 27686084 ps
T1294 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2697875514 Apr 02 12:40:35 PM PDT 24 Apr 02 12:40:36 PM PDT 24 49591069 ps
T1295 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.814494913 Apr 02 12:40:24 PM PDT 24 Apr 02 12:40:28 PM PDT 24 131531091 ps
T1296 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3176244226 Apr 02 12:40:43 PM PDT 24 Apr 02 12:40:45 PM PDT 24 27573661 ps
T141 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2904293829 Apr 02 12:40:27 PM PDT 24 Apr 02 12:40:29 PM PDT 24 45549869 ps
T1297 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3288673454 Apr 02 12:40:29 PM PDT 24 Apr 02 12:40:32 PM PDT 24 116398922 ps
T1298 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2801317071 Apr 02 12:40:39 PM PDT 24 Apr 02 12:40:40 PM PDT 24 17395592 ps
T129 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1825976025 Apr 02 12:40:30 PM PDT 24 Apr 02 12:40:33 PM PDT 24 146969511 ps
T1299 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4277928622 Apr 02 12:40:43 PM PDT 24 Apr 02 12:40:44 PM PDT 24 150796582 ps

Test location /workspace/coverage/default/10.i2c_target_timeout.3883253178
Short name T1
Test name
Test status
Simulation time 1313328069 ps
CPU time 6.63 seconds
Started Apr 02 03:37:11 PM PDT 24
Finished Apr 02 03:37:18 PM PDT 24
Peak memory 210616 kb
Host smart-a5d1edd0-fbcd-4738-89a5-608b7bc32405
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883253178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3883253178
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1980932944
Short name T44
Test name
Test status
Simulation time 11438918610 ps
CPU time 25.25 seconds
Started Apr 02 03:38:40 PM PDT 24
Finished Apr 02 03:39:05 PM PDT 24
Peak memory 262004 kb
Host smart-a701e2d9-cf9a-4ea4-bc28-aa10f55df07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980932944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1980932944
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3200258915
Short name T30
Test name
Test status
Simulation time 46177434055 ps
CPU time 691.16 seconds
Started Apr 02 03:37:45 PM PDT 24
Finished Apr 02 03:49:16 PM PDT 24
Peak memory 1831856 kb
Host smart-a23bdaad-a9bf-416a-9de4-20497c85f31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200258915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3200258915
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4208540788
Short name T77
Test name
Test status
Simulation time 34277507 ps
CPU time 0.78 seconds
Started Apr 02 12:40:24 PM PDT 24
Finished Apr 02 12:40:26 PM PDT 24
Peak memory 203504 kb
Host smart-442d555f-050d-4053-96d9-3845b141036f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208540788 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.4208540788
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.3211338036
Short name T21
Test name
Test status
Simulation time 161015783309 ps
CPU time 1342.85 seconds
Started Apr 02 03:36:45 PM PDT 24
Finished Apr 02 03:59:08 PM PDT 24
Peak memory 3923476 kb
Host smart-f25fb06b-0099-47f3-a3ab-a04331a4e4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211338036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.3211338036
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.1513254394
Short name T41
Test name
Test status
Simulation time 17863153549 ps
CPU time 63.51 seconds
Started Apr 02 03:39:36 PM PDT 24
Finished Apr 02 03:40:41 PM PDT 24
Peak memory 284460 kb
Host smart-15997081-fcc7-42fb-be0d-9f8b0f5dfa29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513254394 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.1513254394
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_override.650293913
Short name T11
Test name
Test status
Simulation time 18478124 ps
CPU time 0.65 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:26 PM PDT 24
Peak memory 203540 kb
Host smart-d4206b1d-21c8-45e1-94d3-6c2cde483f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650293913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.650293913
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.878547554
Short name T213
Test name
Test status
Simulation time 380656794 ps
CPU time 15.71 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:37:40 PM PDT 24
Peak memory 203816 kb
Host smart-390f6dc3-6936-4749-a41a-f0a7a299e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878547554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.878547554
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3457586883
Short name T99
Test name
Test status
Simulation time 286358357 ps
CPU time 0.91 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:36:45 PM PDT 24
Peak memory 221312 kb
Host smart-be11d14f-3483-43c2-b1bc-b9b672ca752b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457586883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3457586883
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3002302053
Short name T16
Test name
Test status
Simulation time 3520559963 ps
CPU time 41.32 seconds
Started Apr 02 03:39:37 PM PDT 24
Finished Apr 02 03:40:19 PM PDT 24
Peak memory 424664 kb
Host smart-3ed27ab9-161d-453a-ad58-5901b8176021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002302053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3002302053
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2647090085
Short name T61
Test name
Test status
Simulation time 10071322603 ps
CPU time 108.58 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:40:38 PM PDT 24
Peak memory 783356 kb
Host smart-7ee89c1d-0129-4acd-bd3f-5799c755ae3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647090085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2647090085
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.4242796045
Short name T235
Test name
Test status
Simulation time 53649639 ps
CPU time 0.67 seconds
Started Apr 02 12:40:49 PM PDT 24
Finished Apr 02 12:40:50 PM PDT 24
Peak memory 203368 kb
Host smart-ff157685-7868-42ea-ac8a-d05ae13834f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242796045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4242796045
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.962960807
Short name T76
Test name
Test status
Simulation time 78834683 ps
CPU time 2.07 seconds
Started Apr 02 12:40:33 PM PDT 24
Finished Apr 02 12:40:36 PM PDT 24
Peak memory 203612 kb
Host smart-a9c974db-af8a-4336-afc1-7964945c7b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962960807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.962960807
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3863555011
Short name T139
Test name
Test status
Simulation time 22495790 ps
CPU time 0.73 seconds
Started Apr 02 12:40:42 PM PDT 24
Finished Apr 02 12:40:43 PM PDT 24
Peak memory 203332 kb
Host smart-5d7c3a8a-9bf1-423e-a9a7-9f3e5d6ebc6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863555011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3863555011
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3044744122
Short name T3
Test name
Test status
Simulation time 851333826 ps
CPU time 2.4 seconds
Started Apr 02 03:39:35 PM PDT 24
Finished Apr 02 03:39:38 PM PDT 24
Peak memory 203788 kb
Host smart-f9284860-4cda-4e8a-a3bb-3993e703603f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044744122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3044744122
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_host_perf.416304187
Short name T964
Test name
Test status
Simulation time 28129612627 ps
CPU time 1903.76 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 04:11:57 PM PDT 24
Peak memory 3085760 kb
Host smart-98c96640-08f5-4bbe-8529-d875e81e1536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416304187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.416304187
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.802727006
Short name T118
Test name
Test status
Simulation time 97003464 ps
CPU time 2.11 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 203564 kb
Host smart-f066bf81-9cef-4590-b865-e87856751c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802727006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.802727006
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2872260080
Short name T60
Test name
Test status
Simulation time 14335721865 ps
CPU time 972.06 seconds
Started Apr 02 03:40:33 PM PDT 24
Finished Apr 02 03:56:45 PM PDT 24
Peak memory 3389788 kb
Host smart-81724eb1-4e66-43d9-9807-54b9a03d27cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872260080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2872260080
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.778869633
Short name T4
Test name
Test status
Simulation time 116835879 ps
CPU time 1.01 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:38:50 PM PDT 24
Peak memory 203708 kb
Host smart-44a0afcc-d43b-4ebc-94f5-7774a9ed1b55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778869633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.778869633
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2775340948
Short name T394
Test name
Test status
Simulation time 509889727 ps
CPU time 3.03 seconds
Started Apr 02 03:37:32 PM PDT 24
Finished Apr 02 03:37:35 PM PDT 24
Peak memory 203792 kb
Host smart-3c2a82e1-1065-4dcf-8598-b6a714ac40bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775340948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2775340948
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.2058158917
Short name T40
Test name
Test status
Simulation time 1132486918 ps
CPU time 6.13 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:36:48 PM PDT 24
Peak memory 203876 kb
Host smart-765e0df0-9815-49c3-9ffd-a34609169f14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058158917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.2058158917
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1054708184
Short name T223
Test name
Test status
Simulation time 60403589 ps
CPU time 0.66 seconds
Started Apr 02 12:40:48 PM PDT 24
Finished Apr 02 12:40:49 PM PDT 24
Peak memory 203352 kb
Host smart-c3357f6c-3157-4c18-8165-0a856543eb6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054708184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1054708184
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.452745795
Short name T226
Test name
Test status
Simulation time 134294470 ps
CPU time 0.69 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:31 PM PDT 24
Peak memory 203280 kb
Host smart-c8296ff8-8c63-46c7-9951-9f839d7ed442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452745795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.452745795
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1903008936
Short name T274
Test name
Test status
Simulation time 22548554 ps
CPU time 0.62 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:37:29 PM PDT 24
Peak memory 203720 kb
Host smart-adeb14f1-aa53-4000-8f9d-51ee698abe66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903008936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1903008936
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1284346586
Short name T145
Test name
Test status
Simulation time 122546287 ps
CPU time 0.85 seconds
Started Apr 02 12:40:36 PM PDT 24
Finished Apr 02 12:40:38 PM PDT 24
Peak memory 203452 kb
Host smart-af900786-ab8d-4e9e-9d72-d3341151d3a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284346586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1284346586
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.4093350702
Short name T196
Test name
Test status
Simulation time 113522953 ps
CPU time 3.02 seconds
Started Apr 02 03:37:20 PM PDT 24
Finished Apr 02 03:37:23 PM PDT 24
Peak memory 220824 kb
Host smart-a377220c-ba4c-4bce-b2cd-2e56a63b4bbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093350702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.4093350702
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.1286852511
Short name T194
Test name
Test status
Simulation time 10093524206 ps
CPU time 91.47 seconds
Started Apr 02 03:39:15 PM PDT 24
Finished Apr 02 03:40:48 PM PDT 24
Peak memory 630880 kb
Host smart-c514acaa-d2b0-4ca2-990e-484426361130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286852511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.1286852511
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.7119026
Short name T6
Test name
Test status
Simulation time 2611492548 ps
CPU time 49.12 seconds
Started Apr 02 03:40:19 PM PDT 24
Finished Apr 02 03:41:09 PM PDT 24
Peak memory 203896 kb
Host smart-a8a97b19-ad09-4416-a928-5270e4831a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7119026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_targe
t_smoke.7119026
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1495295346
Short name T211
Test name
Test status
Simulation time 1468838049 ps
CPU time 2.2 seconds
Started Apr 02 03:37:06 PM PDT 24
Finished Apr 02 03:37:09 PM PDT 24
Peak memory 203772 kb
Host smart-3b3245a2-0941-46e5-9977-20da9663716a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495295346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1495295346
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2850102041
Short name T18
Test name
Test status
Simulation time 2915210788 ps
CPU time 32.78 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:40:35 PM PDT 24
Peak memory 218144 kb
Host smart-d47ccbc7-39eb-4d67-9cc8-040356a801a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850102041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2850102041
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.183060707
Short name T95
Test name
Test status
Simulation time 16923851435 ps
CPU time 304.15 seconds
Started Apr 02 03:37:36 PM PDT 24
Finished Apr 02 03:42:41 PM PDT 24
Peak memory 682732 kb
Host smart-8fdd216d-25e5-4ca8-a01a-aeb0d721eeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183060707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.183060707
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1740428801
Short name T46
Test name
Test status
Simulation time 48326204564 ps
CPU time 1832.65 seconds
Started Apr 02 03:40:27 PM PDT 24
Finished Apr 02 04:11:00 PM PDT 24
Peak memory 3120152 kb
Host smart-f22a1b36-25a9-4da0-896f-220925978ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740428801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1740428801
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2425600461
Short name T149
Test name
Test status
Simulation time 63955109 ps
CPU time 1.04 seconds
Started Apr 02 12:40:34 PM PDT 24
Finished Apr 02 12:40:35 PM PDT 24
Peak memory 203640 kb
Host smart-4ffd56d8-bc90-424e-a645-464672c5dddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425600461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2425600461
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.976941410
Short name T199
Test name
Test status
Simulation time 144885588 ps
CPU time 1.1 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:40:03 PM PDT 24
Peak memory 203760 kb
Host smart-8d8de0a0-8cfc-4030-9652-a78da9fb247a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976941410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.976941410
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3548089659
Short name T80
Test name
Test status
Simulation time 10065102802 ps
CPU time 29.43 seconds
Started Apr 02 03:37:42 PM PDT 24
Finished Apr 02 03:38:13 PM PDT 24
Peak memory 376100 kb
Host smart-51987020-f1ff-4f50-957c-fbcb41e90073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548089659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3548089659
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.121198925
Short name T305
Test name
Test status
Simulation time 3035746369 ps
CPU time 4 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 203852 kb
Host smart-16d26263-f1b0-42af-ae59-5698fd5df0b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121198925 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.121198925
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2443272122
Short name T59
Test name
Test status
Simulation time 4638597545 ps
CPU time 90.14 seconds
Started Apr 02 03:37:54 PM PDT 24
Finished Apr 02 03:39:26 PM PDT 24
Peak memory 780312 kb
Host smart-6e261299-ad6b-45a5-9977-2ca4a5851e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443272122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2443272122
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1581607825
Short name T1259
Test name
Test status
Simulation time 81785139 ps
CPU time 0.68 seconds
Started Apr 02 12:40:34 PM PDT 24
Finished Apr 02 12:40:35 PM PDT 24
Peak memory 203276 kb
Host smart-7c46f5da-5719-42f1-99eb-aad30e65dce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581607825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1581607825
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2909628083
Short name T242
Test name
Test status
Simulation time 59047695 ps
CPU time 0.74 seconds
Started Apr 02 12:40:28 PM PDT 24
Finished Apr 02 12:40:30 PM PDT 24
Peak memory 203284 kb
Host smart-68175890-a72e-47ad-8a03-a1f2de8d783c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909628083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2909628083
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3538813538
Short name T936
Test name
Test status
Simulation time 5892966060 ps
CPU time 40.3 seconds
Started Apr 02 03:37:16 PM PDT 24
Finished Apr 02 03:37:58 PM PDT 24
Peak memory 519336 kb
Host smart-1e3c0c06-aa98-4652-abf7-e9429e53eace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538813538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3538813538
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.607882867
Short name T220
Test name
Test status
Simulation time 10274132597 ps
CPU time 370.51 seconds
Started Apr 02 03:37:12 PM PDT 24
Finished Apr 02 03:43:23 PM PDT 24
Peak memory 1278620 kb
Host smart-89e15b3e-06d5-42de-ba9d-f7e27a3e31ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607882867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.607882867
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3586690723
Short name T221
Test name
Test status
Simulation time 3619362092 ps
CPU time 260.02 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:41:47 PM PDT 24
Peak memory 1057340 kb
Host smart-f82d149b-4927-4fc1-a49a-fbf5a1d5ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586690723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3586690723
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3204537903
Short name T1102
Test name
Test status
Simulation time 3748686759 ps
CPU time 16.55 seconds
Started Apr 02 03:37:41 PM PDT 24
Finished Apr 02 03:37:58 PM PDT 24
Peak memory 213708 kb
Host smart-4f1af213-975d-4889-9367-dc89e6a7541c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204537903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3204537903
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3871434966
Short name T218
Test name
Test status
Simulation time 12632207331 ps
CPU time 86.57 seconds
Started Apr 02 03:37:49 PM PDT 24
Finished Apr 02 03:39:16 PM PDT 24
Peak memory 933720 kb
Host smart-2dd77996-937e-48fa-9b2d-85d5f77f374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871434966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3871434966
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1024796029
Short name T66
Test name
Test status
Simulation time 10085804183 ps
CPU time 48.58 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:38:16 PM PDT 24
Peak memory 481324 kb
Host smart-297e1a71-a642-4876-af42-e25bec3e4e3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024796029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1024796029
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2667201267
Short name T1218
Test name
Test status
Simulation time 274389803 ps
CPU time 1.37 seconds
Started Apr 02 12:40:21 PM PDT 24
Finished Apr 02 12:40:23 PM PDT 24
Peak memory 203660 kb
Host smart-deb18cdd-5214-40b3-94d3-1d4e427efe6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667201267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2667201267
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2325214436
Short name T124
Test name
Test status
Simulation time 197428957 ps
CPU time 1.26 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203680 kb
Host smart-f9f97749-af23-4423-81a7-c06dbcafe8b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325214436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2325214436
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1825976025
Short name T129
Test name
Test status
Simulation time 146969511 ps
CPU time 2.33 seconds
Started Apr 02 12:40:30 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 203704 kb
Host smart-9269c948-afef-489f-93ab-60343f5f6eba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825976025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1825976025
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4055133425
Short name T125
Test name
Test status
Simulation time 277093101 ps
CPU time 2.09 seconds
Started Apr 02 12:40:40 PM PDT 24
Finished Apr 02 12:40:42 PM PDT 24
Peak memory 203720 kb
Host smart-006cfc1a-ba6c-41b8-9311-4318cb4f779b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055133425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4055133425
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1267458805
Short name T1241
Test name
Test status
Simulation time 66853979 ps
CPU time 1.63 seconds
Started Apr 02 12:40:22 PM PDT 24
Finished Apr 02 12:40:24 PM PDT 24
Peak memory 203576 kb
Host smart-88230e6c-5081-4839-ad3f-94dc37c6678f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267458805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1267458805
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2235766740
Short name T1227
Test name
Test status
Simulation time 48068975 ps
CPU time 0.75 seconds
Started Apr 02 12:40:21 PM PDT 24
Finished Apr 02 12:40:23 PM PDT 24
Peak memory 203380 kb
Host smart-14ff040c-68af-4d8a-aaa8-40529765b02c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235766740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2235766740
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2984754619
Short name T148
Test name
Test status
Simulation time 69520242 ps
CPU time 0.74 seconds
Started Apr 02 12:40:23 PM PDT 24
Finished Apr 02 12:40:25 PM PDT 24
Peak memory 203352 kb
Host smart-c750aacb-e32c-450e-a349-5a1bd11aa101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984754619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2984754619
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.609365673
Short name T1273
Test name
Test status
Simulation time 23670902 ps
CPU time 0.65 seconds
Started Apr 02 12:40:24 PM PDT 24
Finished Apr 02 12:40:26 PM PDT 24
Peak memory 203340 kb
Host smart-f72bda42-a1b5-4d0f-975b-4f99d2a15eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609365673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.609365673
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2942103966
Short name T142
Test name
Test status
Simulation time 28658536 ps
CPU time 1.17 seconds
Started Apr 02 12:40:25 PM PDT 24
Finished Apr 02 12:40:27 PM PDT 24
Peak memory 203604 kb
Host smart-b482b973-2ddf-47d2-b128-d358e04d02a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942103966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2942103966
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4057192561
Short name T116
Test name
Test status
Simulation time 148243807 ps
CPU time 2.22 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203528 kb
Host smart-34b6fb6a-30c7-4f72-890b-a32ecc9f6db2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057192561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.4057192561
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2075764199
Short name T166
Test name
Test status
Simulation time 112592205 ps
CPU time 1.18 seconds
Started Apr 02 12:40:24 PM PDT 24
Finished Apr 02 12:40:27 PM PDT 24
Peak memory 203584 kb
Host smart-57aeed40-04b1-4ce1-8f66-6f9cfc5b285a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075764199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2075764199
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.814494913
Short name T1295
Test name
Test status
Simulation time 131531091 ps
CPU time 2.59 seconds
Started Apr 02 12:40:24 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203536 kb
Host smart-0bd77441-626b-4822-8eed-f0979018e426
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814494913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.814494913
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3767585974
Short name T1248
Test name
Test status
Simulation time 33707895 ps
CPU time 0.67 seconds
Started Apr 02 12:40:23 PM PDT 24
Finished Apr 02 12:40:25 PM PDT 24
Peak memory 203288 kb
Host smart-4ad7608f-5d01-4487-b121-16fc4bead372
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767585974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3767585974
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.615987518
Short name T1276
Test name
Test status
Simulation time 36169584 ps
CPU time 0.94 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203272 kb
Host smart-0a0154f0-2ec3-4d13-8fad-547f4eecd0a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615987518 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.615987518
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2580867961
Short name T1254
Test name
Test status
Simulation time 17213220 ps
CPU time 0.67 seconds
Started Apr 02 12:40:24 PM PDT 24
Finished Apr 02 12:40:26 PM PDT 24
Peak memory 203332 kb
Host smart-8afb950b-9968-41cf-9a6a-386a9e70a487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580867961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2580867961
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1653063230
Short name T1291
Test name
Test status
Simulation time 45607401 ps
CPU time 0.67 seconds
Started Apr 02 12:40:27 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203352 kb
Host smart-e6835f1a-7511-449c-a2f2-2e6e96c85c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653063230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1653063230
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2930511179
Short name T1268
Test name
Test status
Simulation time 608289183 ps
CPU time 1.09 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203684 kb
Host smart-4d87b9e0-68f8-4229-b59b-21c4b771046b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930511179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2930511179
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.19195894
Short name T119
Test name
Test status
Simulation time 84643004 ps
CPU time 1.84 seconds
Started Apr 02 12:40:23 PM PDT 24
Finished Apr 02 12:40:25 PM PDT 24
Peak memory 203580 kb
Host smart-6ab5f416-72d9-4c5c-bfe6-134971a34fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19195894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.19195894
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3106525934
Short name T1251
Test name
Test status
Simulation time 73889111 ps
CPU time 1.09 seconds
Started Apr 02 12:40:37 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203508 kb
Host smart-d6dd155a-6d52-46a2-9299-2c7c1a87d75b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106525934 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3106525934
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3386071923
Short name T136
Test name
Test status
Simulation time 54996363 ps
CPU time 0.75 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:30 PM PDT 24
Peak memory 203316 kb
Host smart-bfba37fb-6b74-41b6-b2a9-a5c507efae9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386071923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3386071923
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3127141749
Short name T1215
Test name
Test status
Simulation time 16244009 ps
CPU time 0.66 seconds
Started Apr 02 12:40:30 PM PDT 24
Finished Apr 02 12:40:31 PM PDT 24
Peak memory 203340 kb
Host smart-888e8f03-e8bd-4aae-a107-dae4cdc45157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127141749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3127141749
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1442318710
Short name T1281
Test name
Test status
Simulation time 26130484 ps
CPU time 1.08 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:48 PM PDT 24
Peak memory 203604 kb
Host smart-8afb4467-6cf6-48e0-a766-4c71251b8626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442318710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1442318710
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1508044060
Short name T117
Test name
Test status
Simulation time 144608751 ps
CPU time 1.64 seconds
Started Apr 02 12:40:32 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 203624 kb
Host smart-e5171c01-e3b3-4892-865b-cd21e914bcc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508044060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1508044060
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3660884562
Short name T1238
Test name
Test status
Simulation time 98936042 ps
CPU time 0.93 seconds
Started Apr 02 12:40:45 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 203464 kb
Host smart-f4fea576-cef6-4b18-b244-3d428c0c02fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660884562 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3660884562
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3058305335
Short name T1225
Test name
Test status
Simulation time 51067099 ps
CPU time 0.68 seconds
Started Apr 02 12:40:44 PM PDT 24
Finished Apr 02 12:40:45 PM PDT 24
Peak memory 203328 kb
Host smart-e45b749c-ac67-47b8-b429-790197c9f88f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058305335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3058305335
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.937758792
Short name T1282
Test name
Test status
Simulation time 58780948 ps
CPU time 0.66 seconds
Started Apr 02 12:40:38 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203276 kb
Host smart-19e067ad-9a79-4cb2-b767-199444708dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937758792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.937758792
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.380271587
Short name T1267
Test name
Test status
Simulation time 181065119 ps
CPU time 1.23 seconds
Started Apr 02 12:40:47 PM PDT 24
Finished Apr 02 12:40:49 PM PDT 24
Peak memory 203616 kb
Host smart-e1d8ebac-355b-4774-af33-833104cbcfdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380271587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.380271587
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.275924230
Short name T1205
Test name
Test status
Simulation time 151017468 ps
CPU time 1.39 seconds
Started Apr 02 12:40:35 PM PDT 24
Finished Apr 02 12:40:38 PM PDT 24
Peak memory 203480 kb
Host smart-200db77d-aa51-4553-862a-252032ae2750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275924230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.275924230
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1917623953
Short name T130
Test name
Test status
Simulation time 32861645 ps
CPU time 0.85 seconds
Started Apr 02 12:40:32 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 203472 kb
Host smart-44620d94-c603-4405-afe3-38298332ca83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917623953 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1917623953
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.365506459
Short name T1274
Test name
Test status
Simulation time 67766771 ps
CPU time 0.75 seconds
Started Apr 02 12:40:41 PM PDT 24
Finished Apr 02 12:40:42 PM PDT 24
Peak memory 203348 kb
Host smart-db1af7de-2600-41e3-9fce-a5563843cdaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365506459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.365506459
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2801317071
Short name T1298
Test name
Test status
Simulation time 17395592 ps
CPU time 0.69 seconds
Started Apr 02 12:40:39 PM PDT 24
Finished Apr 02 12:40:40 PM PDT 24
Peak memory 203352 kb
Host smart-9195c766-b524-4190-8ad2-a0c2f996c8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801317071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2801317071
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.966409611
Short name T1253
Test name
Test status
Simulation time 100756803 ps
CPU time 1.04 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203624 kb
Host smart-40948e16-468d-47a8-bdab-47de12994308
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966409611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.966409611
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1921672986
Short name T1256
Test name
Test status
Simulation time 67385696 ps
CPU time 1.67 seconds
Started Apr 02 12:40:34 PM PDT 24
Finished Apr 02 12:40:36 PM PDT 24
Peak memory 203616 kb
Host smart-8ad2a03e-5165-403f-a5cc-44ca9d9ba069
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921672986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1921672986
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3184477607
Short name T1233
Test name
Test status
Simulation time 155022621 ps
CPU time 1.37 seconds
Started Apr 02 12:40:44 PM PDT 24
Finished Apr 02 12:40:45 PM PDT 24
Peak memory 203652 kb
Host smart-7add551b-4f67-48fb-a980-289497eb425f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184477607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3184477607
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2697875514
Short name T1294
Test name
Test status
Simulation time 49591069 ps
CPU time 1.27 seconds
Started Apr 02 12:40:35 PM PDT 24
Finished Apr 02 12:40:36 PM PDT 24
Peak memory 203760 kb
Host smart-5c45ca58-d181-4b05-95d0-96feb4f7db28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697875514 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2697875514
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1338332667
Short name T1290
Test name
Test status
Simulation time 248363173 ps
CPU time 0.73 seconds
Started Apr 02 12:40:52 PM PDT 24
Finished Apr 02 12:40:52 PM PDT 24
Peak memory 203352 kb
Host smart-c914fdbf-1e96-4f7d-bc5e-c96862cd73bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338332667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1338332667
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3969308804
Short name T1200
Test name
Test status
Simulation time 27169844 ps
CPU time 0.7 seconds
Started Apr 02 12:40:54 PM PDT 24
Finished Apr 02 12:40:55 PM PDT 24
Peak memory 203284 kb
Host smart-56077da3-b9e7-425e-86c3-f9574a6d01aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969308804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3969308804
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2304726893
Short name T147
Test name
Test status
Simulation time 27729790 ps
CPU time 1.05 seconds
Started Apr 02 12:40:36 PM PDT 24
Finished Apr 02 12:40:38 PM PDT 24
Peak memory 203648 kb
Host smart-10a7a474-8dec-45db-985a-a4aabf9eebb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304726893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2304726893
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2397289398
Short name T120
Test name
Test status
Simulation time 43936632 ps
CPU time 2.03 seconds
Started Apr 02 12:40:34 PM PDT 24
Finished Apr 02 12:40:37 PM PDT 24
Peak memory 203664 kb
Host smart-096e34ff-9c16-484c-a307-441860133326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397289398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2397289398
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1881674034
Short name T1213
Test name
Test status
Simulation time 20473990 ps
CPU time 0.88 seconds
Started Apr 02 12:40:40 PM PDT 24
Finished Apr 02 12:40:41 PM PDT 24
Peak memory 203512 kb
Host smart-61d73363-6763-4230-91e3-5f354bb914ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881674034 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1881674034
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3071848483
Short name T1280
Test name
Test status
Simulation time 37155494 ps
CPU time 0.96 seconds
Started Apr 02 12:40:34 PM PDT 24
Finished Apr 02 12:40:35 PM PDT 24
Peak memory 203492 kb
Host smart-3cbe8a54-7ad9-4b4e-925a-7cea25fb7f33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071848483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.3071848483
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.39740537
Short name T1263
Test name
Test status
Simulation time 289671582 ps
CPU time 2.11 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:49 PM PDT 24
Peak memory 203652 kb
Host smart-bd3812e0-91ce-4af8-a289-80dbdc4e6355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.39740537
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4199573533
Short name T1283
Test name
Test status
Simulation time 388922096 ps
CPU time 1.38 seconds
Started Apr 02 12:40:52 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203584 kb
Host smart-444a7328-9f97-4277-9d05-0da2077af009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199573533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.4199573533
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3176244226
Short name T1296
Test name
Test status
Simulation time 27573661 ps
CPU time 0.87 seconds
Started Apr 02 12:40:43 PM PDT 24
Finished Apr 02 12:40:45 PM PDT 24
Peak memory 203380 kb
Host smart-cf6d8334-9378-4825-a81b-1f5281e12e41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176244226 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3176244226
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3468167903
Short name T134
Test name
Test status
Simulation time 55639674 ps
CPU time 0.67 seconds
Started Apr 02 12:40:35 PM PDT 24
Finished Apr 02 12:40:36 PM PDT 24
Peak memory 203192 kb
Host smart-0602fd0f-d0fc-4922-a431-2ec197e9d793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468167903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3468167903
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2101357280
Short name T1277
Test name
Test status
Simulation time 96608048 ps
CPU time 2.07 seconds
Started Apr 02 12:40:38 PM PDT 24
Finished Apr 02 12:40:41 PM PDT 24
Peak memory 203580 kb
Host smart-44e8938c-6a98-42d6-bf77-662647dab9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101357280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2101357280
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.246085526
Short name T1288
Test name
Test status
Simulation time 52443364 ps
CPU time 1.41 seconds
Started Apr 02 12:40:35 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203640 kb
Host smart-0b230cdc-9c21-44ef-b1b4-2a19dd9890fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246085526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.246085526
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2430570443
Short name T131
Test name
Test status
Simulation time 49894075 ps
CPU time 0.89 seconds
Started Apr 02 12:40:48 PM PDT 24
Finished Apr 02 12:40:49 PM PDT 24
Peak memory 203456 kb
Host smart-2c1144f5-4bae-4094-84e3-353fa5b9538d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430570443 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2430570443
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.84984531
Short name T1207
Test name
Test status
Simulation time 39711292 ps
CPU time 0.69 seconds
Started Apr 02 12:40:49 PM PDT 24
Finished Apr 02 12:40:50 PM PDT 24
Peak memory 203348 kb
Host smart-c5b405c5-ac02-4ee7-82ac-26cf3d1232d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84984531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.84984531
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1548777790
Short name T1221
Test name
Test status
Simulation time 27856400 ps
CPU time 0.68 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:48 PM PDT 24
Peak memory 203252 kb
Host smart-3249f95e-fc68-4fe5-a0dd-dcdbcfad78c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548777790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1548777790
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.875365538
Short name T1208
Test name
Test status
Simulation time 235566042 ps
CPU time 1.2 seconds
Started Apr 02 12:40:38 PM PDT 24
Finished Apr 02 12:40:40 PM PDT 24
Peak memory 203568 kb
Host smart-0de5fa64-5681-4732-bd1b-65ca700a656c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875365538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.875365538
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2815631594
Short name T1265
Test name
Test status
Simulation time 451567552 ps
CPU time 2.22 seconds
Started Apr 02 12:40:54 PM PDT 24
Finished Apr 02 12:40:57 PM PDT 24
Peak memory 203592 kb
Host smart-8cd9d3aa-9fde-442a-8274-92c548bd67e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815631594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2815631594
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2716236049
Short name T122
Test name
Test status
Simulation time 130411531 ps
CPU time 2.07 seconds
Started Apr 02 12:40:40 PM PDT 24
Finished Apr 02 12:40:42 PM PDT 24
Peak memory 203604 kb
Host smart-6f2e4180-8914-4182-8756-e67722f81242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716236049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2716236049
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3464469697
Short name T165
Test name
Test status
Simulation time 73427410 ps
CPU time 0.96 seconds
Started Apr 02 12:40:38 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203500 kb
Host smart-faa04d28-7aff-4947-8dae-3d15382d0ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464469697 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3464469697
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1280594058
Short name T1198
Test name
Test status
Simulation time 183988121 ps
CPU time 0.75 seconds
Started Apr 02 12:40:38 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203240 kb
Host smart-24338613-14c3-4b78-aa92-3390d7624d4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280594058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1280594058
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2910069908
Short name T1214
Test name
Test status
Simulation time 23218070 ps
CPU time 0.67 seconds
Started Apr 02 12:40:39 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203560 kb
Host smart-741f8a11-c514-4ad0-8c70-fbdce2a4b6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910069908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2910069908
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1777250034
Short name T144
Test name
Test status
Simulation time 55597683 ps
CPU time 1.05 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203656 kb
Host smart-b0df69f1-b476-4b74-b587-0089d4cd83a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777250034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1777250034
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3916910946
Short name T1236
Test name
Test status
Simulation time 162881711 ps
CPU time 2.36 seconds
Started Apr 02 12:40:41 PM PDT 24
Finished Apr 02 12:40:44 PM PDT 24
Peak memory 203696 kb
Host smart-574b7f5d-fbee-4c95-9613-055be3080d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916910946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3916910946
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.251387802
Short name T127
Test name
Test status
Simulation time 66027451 ps
CPU time 1.44 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203624 kb
Host smart-a0026f1e-e84d-47da-9a7e-a6dcf7fd3a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251387802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.251387802
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3751310147
Short name T121
Test name
Test status
Simulation time 101021051 ps
CPU time 1.28 seconds
Started Apr 02 12:40:39 PM PDT 24
Finished Apr 02 12:40:41 PM PDT 24
Peak memory 203928 kb
Host smart-9f4100ac-d070-4969-bc6c-9b39b2c8f73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751310147 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3751310147
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1313966783
Short name T137
Test name
Test status
Simulation time 50278604 ps
CPU time 0.81 seconds
Started Apr 02 12:40:38 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203332 kb
Host smart-d27c16eb-378b-41aa-ab49-b7ba9f3fe224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313966783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1313966783
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1257551997
Short name T1252
Test name
Test status
Simulation time 16187130 ps
CPU time 0.65 seconds
Started Apr 02 12:40:51 PM PDT 24
Finished Apr 02 12:40:52 PM PDT 24
Peak memory 203220 kb
Host smart-5a34a633-a3ba-4e18-ad1a-ddc044a6d093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257551997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1257551997
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2441046612
Short name T146
Test name
Test status
Simulation time 85840976 ps
CPU time 0.87 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:48 PM PDT 24
Peak memory 203344 kb
Host smart-be0dbd23-dc59-4986-91ca-a1d77ca201a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441046612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2441046612
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.645552296
Short name T167
Test name
Test status
Simulation time 133008357 ps
CPU time 2.37 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:49 PM PDT 24
Peak memory 203548 kb
Host smart-4c3d04c0-bc4f-429f-896a-efb1910676b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645552296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.645552296
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3298239495
Short name T114
Test name
Test status
Simulation time 75618588 ps
CPU time 1.37 seconds
Started Apr 02 12:40:39 PM PDT 24
Finished Apr 02 12:40:41 PM PDT 24
Peak memory 203688 kb
Host smart-8fc4153b-cac8-4c8b-bb48-e468311d7724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298239495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3298239495
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.302985810
Short name T1250
Test name
Test status
Simulation time 76358560 ps
CPU time 0.81 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 203472 kb
Host smart-6ee6db7d-9284-4063-ba40-028f27238ff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302985810 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.302985810
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3959671733
Short name T1228
Test name
Test status
Simulation time 131623012 ps
CPU time 0.66 seconds
Started Apr 02 12:40:44 PM PDT 24
Finished Apr 02 12:40:45 PM PDT 24
Peak memory 203308 kb
Host smart-2489b9b4-b7c6-4303-a827-55ebf941a273
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959671733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3959671733
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2477984921
Short name T1269
Test name
Test status
Simulation time 32499755 ps
CPU time 0.71 seconds
Started Apr 02 12:40:41 PM PDT 24
Finished Apr 02 12:40:43 PM PDT 24
Peak memory 203328 kb
Host smart-0fc7e621-1e9c-452c-9a83-fc96bb4351f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477984921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2477984921
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.388524102
Short name T1243
Test name
Test status
Simulation time 118768941 ps
CPU time 0.82 seconds
Started Apr 02 12:40:50 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 203376 kb
Host smart-e3bf1aa8-2d6a-41d1-84be-2ee39077c9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388524102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.388524102
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3365012524
Short name T1226
Test name
Test status
Simulation time 44967405 ps
CPU time 1.36 seconds
Started Apr 02 12:40:51 PM PDT 24
Finished Apr 02 12:40:52 PM PDT 24
Peak memory 203528 kb
Host smart-00e5a6e9-26ed-438f-8c8a-fb3fd2779c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365012524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3365012524
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2107484012
Short name T126
Test name
Test status
Simulation time 227243413 ps
CPU time 2.26 seconds
Started Apr 02 12:40:48 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 203688 kb
Host smart-37f0382b-6d5b-47dc-acba-5fd1d7c205e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107484012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2107484012
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4202686495
Short name T1201
Test name
Test status
Simulation time 437810698 ps
CPU time 1.84 seconds
Started Apr 02 12:40:35 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203516 kb
Host smart-f7958b25-6c40-4838-a981-eae7ab1a24a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202686495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.4202686495
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.4265233626
Short name T1197
Test name
Test status
Simulation time 504522849 ps
CPU time 4.67 seconds
Started Apr 02 12:40:28 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 203620 kb
Host smart-e8c14a3e-c4dd-405d-9f0f-f4ab227e01c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265233626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.4265233626
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3261865711
Short name T135
Test name
Test status
Simulation time 19116853 ps
CPU time 0.74 seconds
Started Apr 02 12:40:25 PM PDT 24
Finished Apr 02 12:40:27 PM PDT 24
Peak memory 203276 kb
Host smart-2e53b0d2-a392-4542-ad55-46cb0aa97333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261865711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3261865711
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3683029225
Short name T97
Test name
Test status
Simulation time 62144316 ps
CPU time 1.49 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203692 kb
Host smart-e38fcd89-aaa6-4209-b762-c25f2098526b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683029225 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3683029225
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1234134696
Short name T1278
Test name
Test status
Simulation time 65965785 ps
CPU time 0.77 seconds
Started Apr 02 12:40:28 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 203256 kb
Host smart-91418fb4-ef91-4da3-adfd-a25b1f0c1c3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234134696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1234134696
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2151229952
Short name T225
Test name
Test status
Simulation time 37270519 ps
CPU time 0.67 seconds
Started Apr 02 12:40:24 PM PDT 24
Finished Apr 02 12:40:26 PM PDT 24
Peak memory 203272 kb
Host smart-48c7b5b9-7e1b-4f9d-89a3-877fd09f8841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151229952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2151229952
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1312467493
Short name T1239
Test name
Test status
Simulation time 93958946 ps
CPU time 1.12 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:31 PM PDT 24
Peak memory 203576 kb
Host smart-6bd9ccd9-b2fa-46d2-a0d7-2339a37e1574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312467493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1312467493
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3338446161
Short name T1258
Test name
Test status
Simulation time 64658165 ps
CPU time 1.81 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203656 kb
Host smart-6cc3cb88-3835-4840-bf73-b132027839d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338446161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3338446161
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1315881529
Short name T128
Test name
Test status
Simulation time 125045022 ps
CPU time 1.4 seconds
Started Apr 02 12:40:27 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 203556 kb
Host smart-dfdaf8e5-b042-4926-bb3d-267137b8917f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315881529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1315881529
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1185785898
Short name T1286
Test name
Test status
Simulation time 16088469 ps
CPU time 0.66 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 203320 kb
Host smart-4983d652-82bb-4b75-b3e7-9840c16fe770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185785898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1185785898
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2745509088
Short name T169
Test name
Test status
Simulation time 55109949 ps
CPU time 0.65 seconds
Started Apr 02 12:40:45 PM PDT 24
Finished Apr 02 12:40:46 PM PDT 24
Peak memory 203308 kb
Host smart-e54d1b78-1e56-44eb-afa7-4f30eab66584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745509088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2745509088
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3447622307
Short name T1219
Test name
Test status
Simulation time 35319363 ps
CPU time 0.63 seconds
Started Apr 02 12:40:40 PM PDT 24
Finished Apr 02 12:40:41 PM PDT 24
Peak memory 203276 kb
Host smart-31e1cfaa-86b2-4874-96ed-318ee983ba7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447622307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3447622307
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1131299457
Short name T1220
Test name
Test status
Simulation time 18628913 ps
CPU time 0.69 seconds
Started Apr 02 12:40:50 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 203348 kb
Host smart-b24549fa-5bce-4416-b413-ee7639fad3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131299457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1131299457
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.3052590131
Short name T1204
Test name
Test status
Simulation time 50609848 ps
CPU time 0.7 seconds
Started Apr 02 12:40:39 PM PDT 24
Finished Apr 02 12:40:40 PM PDT 24
Peak memory 203344 kb
Host smart-3f62dceb-006a-4319-892c-5509ffe8b70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052590131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3052590131
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.515604729
Short name T234
Test name
Test status
Simulation time 44697394 ps
CPU time 0.78 seconds
Started Apr 02 12:40:52 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203276 kb
Host smart-dbe688e0-fa40-4c02-8049-c2982f3dbd34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515604729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.515604729
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3232616926
Short name T1232
Test name
Test status
Simulation time 26217624 ps
CPU time 0.65 seconds
Started Apr 02 12:40:50 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 203364 kb
Host smart-385ccff2-736d-4107-80c9-5e14dda238bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232616926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3232616926
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1951073954
Short name T231
Test name
Test status
Simulation time 17773366 ps
CPU time 0.68 seconds
Started Apr 02 12:40:51 PM PDT 24
Finished Apr 02 12:40:52 PM PDT 24
Peak memory 203348 kb
Host smart-af9cd5f8-65c7-471b-b0ba-27ebf9662132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951073954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1951073954
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.182450340
Short name T1249
Test name
Test status
Simulation time 44631583 ps
CPU time 0.67 seconds
Started Apr 02 12:40:50 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 203360 kb
Host smart-7e9028af-f110-4b9a-abeb-19b19e20e439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182450340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.182450340
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3060476766
Short name T1199
Test name
Test status
Simulation time 89045078 ps
CPU time 1.81 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 203584 kb
Host smart-ba9046b1-7f14-4e38-8c0b-264e03c989f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060476766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3060476766
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4203676491
Short name T1287
Test name
Test status
Simulation time 19361344 ps
CPU time 0.7 seconds
Started Apr 02 12:40:27 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203108 kb
Host smart-6ea80752-2f2b-44c9-b096-32b87c2bb3c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203676491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.4203676491
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.229424449
Short name T1231
Test name
Test status
Simulation time 45666135 ps
CPU time 0.94 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203348 kb
Host smart-67d7487d-9e99-4e25-9495-a76986bf3d44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229424449 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.229424449
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.912211750
Short name T133
Test name
Test status
Simulation time 17398612 ps
CPU time 0.72 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203240 kb
Host smart-5f2e19a6-18cf-4305-bd8b-d96884ffb920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912211750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.912211750
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2250944848
Short name T232
Test name
Test status
Simulation time 46222089 ps
CPU time 0.68 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:30 PM PDT 24
Peak memory 203348 kb
Host smart-193155ca-205e-4035-927c-53c4e758fca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250944848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2250944848
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.720674928
Short name T1230
Test name
Test status
Simulation time 104861042 ps
CPU time 0.87 seconds
Started Apr 02 12:40:27 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203336 kb
Host smart-1fc785ac-b2a5-4ea0-bfab-de884dd20e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720674928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.720674928
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.834985512
Short name T1224
Test name
Test status
Simulation time 55635774 ps
CPU time 2.04 seconds
Started Apr 02 12:40:25 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203656 kb
Host smart-e3c683c8-877d-40eb-b528-952796a72a12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834985512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.834985512
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.699133221
Short name T1212
Test name
Test status
Simulation time 225292945 ps
CPU time 2.23 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 203712 kb
Host smart-b21729d9-5472-4a20-b2fb-48e152467af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699133221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.699133221
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1771265818
Short name T1210
Test name
Test status
Simulation time 52279933 ps
CPU time 0.65 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 203352 kb
Host smart-02c67bc1-abfc-422c-9959-d1daa22b1b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771265818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1771265818
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.59489129
Short name T1234
Test name
Test status
Simulation time 58675126 ps
CPU time 0.72 seconds
Started Apr 02 12:40:52 PM PDT 24
Finished Apr 02 12:40:53 PM PDT 24
Peak memory 203284 kb
Host smart-cd59eb74-2cc9-402b-a799-1dc9697d0fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59489129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.59489129
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2957856940
Short name T1293
Test name
Test status
Simulation time 27686084 ps
CPU time 0.7 seconds
Started Apr 02 12:40:44 PM PDT 24
Finished Apr 02 12:40:45 PM PDT 24
Peak memory 203340 kb
Host smart-928a867c-1897-4c0e-8710-50bede91946b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957856940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2957856940
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.794453077
Short name T1279
Test name
Test status
Simulation time 41396098 ps
CPU time 0.71 seconds
Started Apr 02 12:40:51 PM PDT 24
Finished Apr 02 12:40:52 PM PDT 24
Peak memory 203216 kb
Host smart-ac3aee66-dcf9-48ef-b88e-ff86a56b3e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794453077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.794453077
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.670528287
Short name T224
Test name
Test status
Simulation time 81507541 ps
CPU time 0.68 seconds
Started Apr 02 12:40:47 PM PDT 24
Finished Apr 02 12:40:48 PM PDT 24
Peak memory 203372 kb
Host smart-020f1ed7-0b08-44eb-9037-4d241a43e4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670528287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.670528287
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.4291958336
Short name T1255
Test name
Test status
Simulation time 15943560 ps
CPU time 0.64 seconds
Started Apr 02 12:40:42 PM PDT 24
Finished Apr 02 12:40:44 PM PDT 24
Peak memory 203356 kb
Host smart-21a992da-cd89-44b8-a5f9-df0904e483f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291958336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.4291958336
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.4148673904
Short name T1247
Test name
Test status
Simulation time 22260019 ps
CPU time 0.66 seconds
Started Apr 02 12:40:49 PM PDT 24
Finished Apr 02 12:40:50 PM PDT 24
Peak memory 203356 kb
Host smart-bcb7e5ad-6f78-48ea-82db-7899cb2b1b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148673904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.4148673904
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.126247886
Short name T227
Test name
Test status
Simulation time 26127370 ps
CPU time 0.67 seconds
Started Apr 02 12:40:51 PM PDT 24
Finished Apr 02 12:40:52 PM PDT 24
Peak memory 203276 kb
Host smart-74fe34bc-bf95-4357-b3dc-06eb91a211e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126247886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.126247886
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1645476202
Short name T1206
Test name
Test status
Simulation time 17651633 ps
CPU time 0.69 seconds
Started Apr 02 12:40:40 PM PDT 24
Finished Apr 02 12:40:41 PM PDT 24
Peak memory 203344 kb
Host smart-484e5e66-05bc-4523-8fc8-ae7505538068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645476202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1645476202
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.4284951749
Short name T168
Test name
Test status
Simulation time 111119916 ps
CPU time 0.67 seconds
Started Apr 02 12:40:44 PM PDT 24
Finished Apr 02 12:40:45 PM PDT 24
Peak memory 203276 kb
Host smart-b4018873-62ba-4221-ad9b-b2364e6f0040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284951749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.4284951749
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3393401903
Short name T1203
Test name
Test status
Simulation time 55031072 ps
CPU time 1.23 seconds
Started Apr 02 12:40:42 PM PDT 24
Finished Apr 02 12:40:43 PM PDT 24
Peak memory 203516 kb
Host smart-1c62316c-dcc4-4efe-8fe8-75a9d767d148
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393401903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3393401903
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2249801553
Short name T1270
Test name
Test status
Simulation time 1027128963 ps
CPU time 2.99 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203604 kb
Host smart-0c8569eb-b71e-4cb6-a889-05c8058c8850
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249801553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2249801553
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3919747130
Short name T1284
Test name
Test status
Simulation time 116962911 ps
CPU time 0.98 seconds
Started Apr 02 12:40:26 PM PDT 24
Finished Apr 02 12:40:28 PM PDT 24
Peak memory 203468 kb
Host smart-0bef78fa-4fba-4a25-bd0e-d4fe8b1511f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919747130 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3919747130
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2904293829
Short name T141
Test name
Test status
Simulation time 45549869 ps
CPU time 0.72 seconds
Started Apr 02 12:40:27 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 203336 kb
Host smart-ecf84b27-4797-4fb8-b8a0-2ccbd5fcf706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904293829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2904293829
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1968684930
Short name T233
Test name
Test status
Simulation time 24330099 ps
CPU time 0.64 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203192 kb
Host smart-729e2d0b-154e-4c04-9378-e3149792e71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968684930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1968684930
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1380983994
Short name T1209
Test name
Test status
Simulation time 68846451 ps
CPU time 1.09 seconds
Started Apr 02 12:40:52 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203424 kb
Host smart-cd2ee0e9-89de-43db-863d-15eb786c59df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380983994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1380983994
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.365301003
Short name T1289
Test name
Test status
Simulation time 425824309 ps
CPU time 2.49 seconds
Started Apr 02 12:40:27 PM PDT 24
Finished Apr 02 12:40:30 PM PDT 24
Peak memory 203564 kb
Host smart-bfe79a1f-dd0d-4107-b1cc-fdca8621220d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365301003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.365301003
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2074219286
Short name T123
Test name
Test status
Simulation time 162693376 ps
CPU time 1.41 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:55 PM PDT 24
Peak memory 203540 kb
Host smart-bad80626-263c-42a9-bfd3-f20677694204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074219286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2074219286
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3637260650
Short name T1229
Test name
Test status
Simulation time 16981216 ps
CPU time 0.67 seconds
Started Apr 02 12:40:44 PM PDT 24
Finished Apr 02 12:40:46 PM PDT 24
Peak memory 203352 kb
Host smart-34e02da5-9e72-4699-a5ca-dc9770b5126a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637260650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3637260650
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.104373777
Short name T1292
Test name
Test status
Simulation time 26182657 ps
CPU time 0.69 seconds
Started Apr 02 12:40:51 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 203368 kb
Host smart-1123f65c-c741-493a-b716-8011b1efc14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104373777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.104373777
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2523720924
Short name T1266
Test name
Test status
Simulation time 23857658 ps
CPU time 0.7 seconds
Started Apr 02 12:40:49 PM PDT 24
Finished Apr 02 12:40:50 PM PDT 24
Peak memory 203352 kb
Host smart-d1435664-0d40-4460-b71a-ffd7d193f64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523720924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2523720924
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.505838217
Short name T1242
Test name
Test status
Simulation time 16726622 ps
CPU time 0.69 seconds
Started Apr 02 12:40:42 PM PDT 24
Finished Apr 02 12:40:44 PM PDT 24
Peak memory 203324 kb
Host smart-b9387e1c-4f00-4060-afcd-3d49fd270b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505838217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.505838217
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3968197991
Short name T1202
Test name
Test status
Simulation time 40624197 ps
CPU time 0.66 seconds
Started Apr 02 12:40:43 PM PDT 24
Finished Apr 02 12:40:45 PM PDT 24
Peak memory 203352 kb
Host smart-62468686-da4b-4eca-b449-8cf29d67a15d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968197991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3968197991
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2967350533
Short name T1245
Test name
Test status
Simulation time 18418079 ps
CPU time 0.69 seconds
Started Apr 02 12:40:46 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 203356 kb
Host smart-e5edf063-5ccb-467a-9ca1-b8e8ce1d32f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967350533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2967350533
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.99103817
Short name T1222
Test name
Test status
Simulation time 67984602 ps
CPU time 0.69 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203360 kb
Host smart-1c8c4ff7-1e28-4978-92e2-34ae92b0c818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99103817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.99103817
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.864889378
Short name T1262
Test name
Test status
Simulation time 35419857 ps
CPU time 0.6 seconds
Started Apr 02 12:40:47 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 203356 kb
Host smart-e6d6e04b-db89-4507-9630-bf94185ef523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864889378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.864889378
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3428704482
Short name T230
Test name
Test status
Simulation time 27516283 ps
CPU time 0.68 seconds
Started Apr 02 12:40:50 PM PDT 24
Finished Apr 02 12:40:51 PM PDT 24
Peak memory 203368 kb
Host smart-ad506f11-4b78-4a36-8c96-ac32a0942677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428704482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3428704482
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.193090014
Short name T1217
Test name
Test status
Simulation time 25447939 ps
CPU time 0.65 seconds
Started Apr 02 12:40:49 PM PDT 24
Finished Apr 02 12:40:50 PM PDT 24
Peak memory 203284 kb
Host smart-4754044d-2aef-4e35-9438-fd66e25d846f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193090014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.193090014
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3209995682
Short name T132
Test name
Test status
Simulation time 22489297 ps
CPU time 0.98 seconds
Started Apr 02 12:40:45 PM PDT 24
Finished Apr 02 12:40:47 PM PDT 24
Peak memory 203432 kb
Host smart-dc264526-0dd0-4ae7-94b7-51db45fd2994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209995682 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3209995682
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4076706359
Short name T1223
Test name
Test status
Simulation time 32794240 ps
CPU time 0.68 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203184 kb
Host smart-ff405bcb-9439-4358-ae61-6cef1ab58d34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076706359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.4076706359
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2757568913
Short name T228
Test name
Test status
Simulation time 45483856 ps
CPU time 0.68 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:30 PM PDT 24
Peak memory 203356 kb
Host smart-ff53901f-b351-4ac1-905a-4227e3d7b96f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757568913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2757568913
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2081680686
Short name T143
Test name
Test status
Simulation time 181015770 ps
CPU time 1.16 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:31 PM PDT 24
Peak memory 203588 kb
Host smart-31ac4066-bdeb-4fd4-885f-03d48599c21e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081680686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2081680686
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2836014879
Short name T1261
Test name
Test status
Simulation time 182949627 ps
CPU time 2.42 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:56 PM PDT 24
Peak memory 203492 kb
Host smart-e3d8c725-a5a4-4af7-841a-574166c1b2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836014879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2836014879
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4234287587
Short name T1240
Test name
Test status
Simulation time 31761169 ps
CPU time 1.34 seconds
Started Apr 02 12:40:28 PM PDT 24
Finished Apr 02 12:40:30 PM PDT 24
Peak memory 203692 kb
Host smart-2e64a59d-d2a3-4544-9031-350c396a33ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234287587 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.4234287587
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.735011419
Short name T140
Test name
Test status
Simulation time 36756964 ps
CPU time 0.67 seconds
Started Apr 02 12:40:28 PM PDT 24
Finished Apr 02 12:40:29 PM PDT 24
Peak memory 203364 kb
Host smart-fb05a926-3136-4ba8-bd3e-828b69301bb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735011419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.735011419
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1966822367
Short name T1285
Test name
Test status
Simulation time 150074764 ps
CPU time 1.06 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:54 PM PDT 24
Peak memory 203400 kb
Host smart-0a3456d9-d928-4172-9630-3eda44aa09d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966822367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1966822367
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2077020267
Short name T1271
Test name
Test status
Simulation time 127732444 ps
CPU time 2.15 seconds
Started Apr 02 12:40:55 PM PDT 24
Finished Apr 02 12:40:58 PM PDT 24
Peak memory 203492 kb
Host smart-1fc55506-d3d2-461e-acf5-f8095f97e565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077020267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2077020267
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2881511730
Short name T1275
Test name
Test status
Simulation time 21483470 ps
CPU time 0.95 seconds
Started Apr 02 12:40:33 PM PDT 24
Finished Apr 02 12:40:34 PM PDT 24
Peak memory 203528 kb
Host smart-888931eb-e2c3-4795-ae36-e09347968a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881511730 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2881511730
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1766526434
Short name T1244
Test name
Test status
Simulation time 67232650 ps
CPU time 0.73 seconds
Started Apr 02 12:40:31 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203344 kb
Host smart-3f97a29c-526f-4a0a-b432-cc6114b0db87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766526434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1766526434
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.4250051320
Short name T1211
Test name
Test status
Simulation time 22844847 ps
CPU time 0.71 seconds
Started Apr 02 12:40:31 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203356 kb
Host smart-92d62150-90f7-4878-838c-654ac27cbf76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250051320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.4250051320
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4081514336
Short name T1272
Test name
Test status
Simulation time 29934092 ps
CPU time 0.84 seconds
Started Apr 02 12:40:31 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203320 kb
Host smart-ed786343-2776-41f3-9119-e9ab46a0c943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081514336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.4081514336
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3484806391
Short name T113
Test name
Test status
Simulation time 447966640 ps
CPU time 2.96 seconds
Started Apr 02 12:40:28 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203684 kb
Host smart-c4142b5c-08cf-4e22-95a8-88f7483c4b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484806391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3484806391
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2511758043
Short name T1260
Test name
Test status
Simulation time 148993911 ps
CPU time 1.48 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:31 PM PDT 24
Peak memory 203700 kb
Host smart-d4101d6c-fd57-46fa-9758-c5fdb3ce758c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511758043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2511758043
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1768835533
Short name T115
Test name
Test status
Simulation time 60960611 ps
CPU time 1.58 seconds
Started Apr 02 12:40:53 PM PDT 24
Finished Apr 02 12:40:55 PM PDT 24
Peak memory 203544 kb
Host smart-002758e1-c544-4ef0-97b5-9cd1413bb00e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768835533 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1768835533
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1267900911
Short name T138
Test name
Test status
Simulation time 16920617 ps
CPU time 0.77 seconds
Started Apr 02 12:40:31 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203288 kb
Host smart-66facd1c-75bc-4251-9264-59984d378c5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267900911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1267900911
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.296999157
Short name T229
Test name
Test status
Simulation time 150684609 ps
CPU time 0.69 seconds
Started Apr 02 12:40:30 PM PDT 24
Finished Apr 02 12:40:31 PM PDT 24
Peak memory 203352 kb
Host smart-a15703db-6654-40f9-85ed-b31289ecff5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296999157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.296999157
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3571954186
Short name T75
Test name
Test status
Simulation time 166578821 ps
CPU time 0.81 seconds
Started Apr 02 12:40:32 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 203404 kb
Host smart-6ad20be5-ec33-442b-aae8-e906747f2c82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571954186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3571954186
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.4008609586
Short name T1216
Test name
Test status
Simulation time 144901971 ps
CPU time 2.12 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203628 kb
Host smart-1cd6fe7a-a07d-417f-89ab-eb306d751c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008609586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.4008609586
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2028821921
Short name T1264
Test name
Test status
Simulation time 80482339 ps
CPU time 1.37 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203700 kb
Host smart-bb726b1c-6fce-46ea-bd64-b1007ebb7009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028821921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2028821921
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3248146611
Short name T1257
Test name
Test status
Simulation time 36748682 ps
CPU time 0.96 seconds
Started Apr 02 12:40:41 PM PDT 24
Finished Apr 02 12:40:43 PM PDT 24
Peak memory 203488 kb
Host smart-b68ceabb-e31a-4de5-afe1-aadf183630cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248146611 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3248146611
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4277928622
Short name T1299
Test name
Test status
Simulation time 150796582 ps
CPU time 0.74 seconds
Started Apr 02 12:40:43 PM PDT 24
Finished Apr 02 12:40:44 PM PDT 24
Peak memory 203344 kb
Host smart-a1490f2c-02f4-4c85-a4b8-2dc74e816ff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277928622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4277928622
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2190497985
Short name T1237
Test name
Test status
Simulation time 15539340 ps
CPU time 0.74 seconds
Started Apr 02 12:40:39 PM PDT 24
Finished Apr 02 12:40:39 PM PDT 24
Peak memory 203304 kb
Host smart-cb9a8e6a-e802-4be7-a22d-fa3463b58670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190497985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2190497985
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3537754977
Short name T1246
Test name
Test status
Simulation time 46425141 ps
CPU time 0.95 seconds
Started Apr 02 12:40:31 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 203428 kb
Host smart-dee54cd4-9219-44c3-a7c6-d80cd2a593bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537754977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3537754977
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3288673454
Short name T1297
Test name
Test status
Simulation time 116398922 ps
CPU time 2.6 seconds
Started Apr 02 12:40:29 PM PDT 24
Finished Apr 02 12:40:32 PM PDT 24
Peak memory 203644 kb
Host smart-14462d40-578a-48b8-b563-0f59cca5eda0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288673454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3288673454
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3783557320
Short name T1235
Test name
Test status
Simulation time 158525039 ps
CPU time 2.01 seconds
Started Apr 02 12:40:31 PM PDT 24
Finished Apr 02 12:40:33 PM PDT 24
Peak memory 203628 kb
Host smart-bb549c69-6106-4db1-aa8a-d2ba9053b919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783557320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3783557320
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3184730064
Short name T450
Test name
Test status
Simulation time 16535078 ps
CPU time 0.66 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:36:38 PM PDT 24
Peak memory 203628 kb
Host smart-5dd908ff-5e21-470e-87e4-e1ebbf0a2a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184730064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3184730064
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2544793909
Short name T897
Test name
Test status
Simulation time 183273541 ps
CPU time 1.57 seconds
Started Apr 02 03:36:29 PM PDT 24
Finished Apr 02 03:36:31 PM PDT 24
Peak memory 212096 kb
Host smart-63967c7e-8cf7-461b-a72e-2d24872947af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544793909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2544793909
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2483039289
Short name T604
Test name
Test status
Simulation time 371851996 ps
CPU time 7.63 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:36:38 PM PDT 24
Peak memory 267180 kb
Host smart-37e415ec-59ba-418e-9e9a-4b5e139c503e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483039289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2483039289
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2507138707
Short name T445
Test name
Test status
Simulation time 2236489091 ps
CPU time 131.06 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:38:46 PM PDT 24
Peak memory 501648 kb
Host smart-84272d1f-6acf-41ec-bc8c-ca13631a8185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507138707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2507138707
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1851745087
Short name T534
Test name
Test status
Simulation time 7425714068 ps
CPU time 63.69 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:37:39 PM PDT 24
Peak memory 636580 kb
Host smart-1f4ed01b-216e-422b-9205-9129ae274087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851745087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1851745087
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.1400937233
Short name T622
Test name
Test status
Simulation time 122118793 ps
CPU time 0.98 seconds
Started Apr 02 03:36:28 PM PDT 24
Finished Apr 02 03:36:30 PM PDT 24
Peak memory 203624 kb
Host smart-2150e8da-3c7e-4d78-baca-8d70e44df4dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400937233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.1400937233
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1931533761
Short name T568
Test name
Test status
Simulation time 659488798 ps
CPU time 8.91 seconds
Started Apr 02 03:36:29 PM PDT 24
Finished Apr 02 03:36:38 PM PDT 24
Peak memory 203896 kb
Host smart-6838012c-4614-4edd-ad34-a27e0e93a3e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931533761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1931533761
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1408535343
Short name T944
Test name
Test status
Simulation time 4888212696 ps
CPU time 327.1 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:41:58 PM PDT 24
Peak memory 1194896 kb
Host smart-b0bff7db-a1ec-4059-ad09-e174eb90333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408535343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1408535343
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.809109407
Short name T1060
Test name
Test status
Simulation time 2975629711 ps
CPU time 3.97 seconds
Started Apr 02 03:36:39 PM PDT 24
Finished Apr 02 03:36:43 PM PDT 24
Peak memory 203824 kb
Host smart-0f92b1be-67f5-4a87-a20e-ea1dca9b27a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809109407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.809109407
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3292456962
Short name T789
Test name
Test status
Simulation time 1636791653 ps
CPU time 34.81 seconds
Started Apr 02 03:36:28 PM PDT 24
Finished Apr 02 03:37:03 PM PDT 24
Peak memory 353676 kb
Host smart-fed703a9-e1e6-4898-bc87-5841781cfe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292456962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3292456962
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.1404407936
Short name T181
Test name
Test status
Simulation time 30208487 ps
CPU time 0.68 seconds
Started Apr 02 03:36:39 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 203640 kb
Host smart-95403a41-1bcb-4db4-b199-03ffd46e646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404407936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1404407936
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2311349184
Short name T189
Test name
Test status
Simulation time 13713950392 ps
CPU time 86.37 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:38:02 PM PDT 24
Peak memory 664060 kb
Host smart-fba7f2e5-a324-438e-9fd0-ffebb82442b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311349184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2311349184
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1691500465
Short name T371
Test name
Test status
Simulation time 14452391818 ps
CPU time 73.03 seconds
Started Apr 02 03:36:32 PM PDT 24
Finished Apr 02 03:37:45 PM PDT 24
Peak memory 394988 kb
Host smart-3733fa02-dcb1-4812-834d-3e58e8a77a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691500465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1691500465
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.4066630667
Short name T102
Test name
Test status
Simulation time 84328327 ps
CPU time 0.87 seconds
Started Apr 02 03:36:40 PM PDT 24
Finished Apr 02 03:36:42 PM PDT 24
Peak memory 221372 kb
Host smart-28e8b34b-8a56-4e33-bb4e-75307086027f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066630667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.4066630667
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.7020818
Short name T786
Test name
Test status
Simulation time 2760705730 ps
CPU time 3.47 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 212068 kb
Host smart-76b42f32-d018-4798-92d6-dd14ae5e8aa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7020818 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_bad_addr.7020818
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3252065171
Short name T489
Test name
Test status
Simulation time 10601100043 ps
CPU time 10.52 seconds
Started Apr 02 03:36:33 PM PDT 24
Finished Apr 02 03:36:44 PM PDT 24
Peak memory 262668 kb
Host smart-5479be98-0d74-49a3-8014-c5ac1d483642
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252065171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3252065171
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3893888889
Short name T71
Test name
Test status
Simulation time 10302717943 ps
CPU time 15.87 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:36:53 PM PDT 24
Peak memory 321040 kb
Host smart-011652e2-3cd7-4a6d-ac6e-a4f673f159cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893888889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3893888889
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.133608873
Short name T917
Test name
Test status
Simulation time 1252141820 ps
CPU time 2.05 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:36:39 PM PDT 24
Peak memory 203796 kb
Host smart-b95d6b16-a196-471f-a75a-8ed7c2b22b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133608873 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.133608873
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1468691779
Short name T943
Test name
Test status
Simulation time 973244071 ps
CPU time 4.59 seconds
Started Apr 02 03:36:21 PM PDT 24
Finished Apr 02 03:36:26 PM PDT 24
Peak memory 203772 kb
Host smart-1186dc63-a8e7-4e1d-9df0-35831e4f5069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468691779 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1468691779
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.797129096
Short name T717
Test name
Test status
Simulation time 3827496564 ps
CPU time 15.81 seconds
Started Apr 02 03:36:21 PM PDT 24
Finished Apr 02 03:36:37 PM PDT 24
Peak memory 203840 kb
Host smart-9ef5e32e-26f0-4dd7-8565-0fd98a861320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797129096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.797129096
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1472776279
Short name T566
Test name
Test status
Simulation time 376058145 ps
CPU time 14.83 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 203732 kb
Host smart-551b9835-ad89-40b1-aa23-fe3618015b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472776279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1472776279
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1258018238
Short name T650
Test name
Test status
Simulation time 24727734620 ps
CPU time 1877.3 seconds
Started Apr 02 03:36:29 PM PDT 24
Finished Apr 02 04:07:47 PM PDT 24
Peak memory 5971708 kb
Host smart-cce4998f-1eaf-4655-9007-52d65f1b0cfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258018238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1258018238
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3987675484
Short name T811
Test name
Test status
Simulation time 1169476975 ps
CPU time 6.54 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:50 PM PDT 24
Peak memory 220044 kb
Host smart-82dc8246-e08c-4efe-a1e9-c43df267a72e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987675484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3987675484
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.430156330
Short name T826
Test name
Test status
Simulation time 1055937603 ps
CPU time 5.68 seconds
Started Apr 02 03:36:32 PM PDT 24
Finished Apr 02 03:36:37 PM PDT 24
Peak memory 209060 kb
Host smart-1c7358b0-787d-4176-ada2-21be4f13dbba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430156330 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_unexp_stop.430156330
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3274248180
Short name T282
Test name
Test status
Simulation time 15473719 ps
CPU time 0.59 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:36 PM PDT 24
Peak memory 203716 kb
Host smart-bb47da43-fa87-4685-8228-46037c6c9a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274248180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3274248180
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2096052304
Short name T1145
Test name
Test status
Simulation time 470159570 ps
CPU time 1.96 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:36:37 PM PDT 24
Peak memory 211992 kb
Host smart-b675700d-af3a-4bc2-8c15-1442c1d3f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096052304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2096052304
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.844895877
Short name T794
Test name
Test status
Simulation time 174183843 ps
CPU time 3.06 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 229040 kb
Host smart-78e03547-31e0-49a3-8613-f24af9e9cef3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844895877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.844895877
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1275963930
Short name T821
Test name
Test status
Simulation time 5250031482 ps
CPU time 82.02 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 518756 kb
Host smart-294d9a60-70e4-49ce-85b5-54096c02c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275963930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1275963930
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.406897351
Short name T1026
Test name
Test status
Simulation time 2374936259 ps
CPU time 86.55 seconds
Started Apr 02 03:36:27 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 768900 kb
Host smart-63729c36-358b-4a23-ae0f-0286f8fd95b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406897351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.406897351
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1469064936
Short name T968
Test name
Test status
Simulation time 136581273 ps
CPU time 1.09 seconds
Started Apr 02 03:36:30 PM PDT 24
Finished Apr 02 03:36:32 PM PDT 24
Peak memory 203820 kb
Host smart-82da9bec-6bba-4386-9259-0c333b46ff81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469064936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1469064936
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.93872787
Short name T632
Test name
Test status
Simulation time 129282950 ps
CPU time 2.86 seconds
Started Apr 02 03:36:47 PM PDT 24
Finished Apr 02 03:36:50 PM PDT 24
Peak memory 203816 kb
Host smart-0ad4b3a6-a3ab-40c8-b6e7-2c3ab6e04daa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93872787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.93872787
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1266938432
Short name T152
Test name
Test status
Simulation time 3742082738 ps
CPU time 56.19 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:37:28 PM PDT 24
Peak memory 825260 kb
Host smart-5f8f6862-961c-46f1-8a90-0fd9a6d2f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266938432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1266938432
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.76555327
Short name T1186
Test name
Test status
Simulation time 665298122 ps
CPU time 9.82 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:36:45 PM PDT 24
Peak memory 203720 kb
Host smart-0f34cd90-19ed-4dc5-86ab-9c2b4bd5f5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76555327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.76555327
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2130740678
Short name T762
Test name
Test status
Simulation time 7775096283 ps
CPU time 40.53 seconds
Started Apr 02 03:36:30 PM PDT 24
Finished Apr 02 03:37:11 PM PDT 24
Peak memory 410772 kb
Host smart-66ecb675-cf65-43b0-9362-2595920a1048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130740678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2130740678
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.1741671300
Short name T183
Test name
Test status
Simulation time 54166910 ps
CPU time 0.67 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:36 PM PDT 24
Peak memory 203592 kb
Host smart-9e24c861-f767-4acd-b19a-01113ea9e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741671300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1741671300
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3011081413
Short name T596
Test name
Test status
Simulation time 27552392114 ps
CPU time 168.59 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:39:30 PM PDT 24
Peak memory 215196 kb
Host smart-25fb940f-7ec2-4f82-a4f3-19549aadfb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011081413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3011081413
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.992756494
Short name T395
Test name
Test status
Simulation time 1118309841 ps
CPU time 52.96 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:37:24 PM PDT 24
Peak memory 309228 kb
Host smart-d9d7256c-42ed-4873-aaa2-d6d9e1ca2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992756494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.992756494
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.3223137335
Short name T103
Test name
Test status
Simulation time 131832959 ps
CPU time 0.93 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:36:39 PM PDT 24
Peak memory 222396 kb
Host smart-b02ebb90-f597-4f33-9af7-d62ad6f567f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223137335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3223137335
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3488712698
Short name T1133
Test name
Test status
Simulation time 851567807 ps
CPU time 3.91 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 203824 kb
Host smart-a4f9758e-0046-41d6-8654-6edd2da54136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488712698 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3488712698
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2603575215
Short name T798
Test name
Test status
Simulation time 10046568151 ps
CPU time 80.1 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:37:57 PM PDT 24
Peak memory 618740 kb
Host smart-31da7832-2058-4a7a-b6f3-888942924da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603575215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2603575215
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1353137852
Short name T767
Test name
Test status
Simulation time 10055635332 ps
CPU time 92.19 seconds
Started Apr 02 03:36:34 PM PDT 24
Finished Apr 02 03:38:07 PM PDT 24
Peak memory 744280 kb
Host smart-bd2e6750-43e6-4576-88b5-9ce60e3bb65a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353137852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1353137852
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.588587668
Short name T1107
Test name
Test status
Simulation time 1547140501 ps
CPU time 2.43 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 203876 kb
Host smart-a7d713e0-6d34-46dd-acdf-3dc7e5ec375a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588587668 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.588587668
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.636020981
Short name T443
Test name
Test status
Simulation time 1210782967 ps
CPU time 6.31 seconds
Started Apr 02 03:36:27 PM PDT 24
Finished Apr 02 03:36:35 PM PDT 24
Peak memory 206996 kb
Host smart-5453a6c2-cfbd-4794-8d82-cd28c2e02c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636020981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.636020981
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3389427352
Short name T572
Test name
Test status
Simulation time 5809154425 ps
CPU time 12.38 seconds
Started Apr 02 03:36:32 PM PDT 24
Finished Apr 02 03:36:44 PM PDT 24
Peak memory 203856 kb
Host smart-459d2a8b-b7b3-488e-80f1-f1d9f527dc1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389427352 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3389427352
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1667764664
Short name T466
Test name
Test status
Simulation time 743313466 ps
CPU time 11.2 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:36:42 PM PDT 24
Peak memory 203836 kb
Host smart-b867800f-da46-4b0a-bc4e-cc0de01a2563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667764664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1667764664
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2515091510
Short name T562
Test name
Test status
Simulation time 6292131322 ps
CPU time 27.43 seconds
Started Apr 02 03:36:34 PM PDT 24
Finished Apr 02 03:37:01 PM PDT 24
Peak memory 222924 kb
Host smart-896ff3fa-e2a6-45ba-9943-06eb0917e792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515091510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2515091510
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.166250705
Short name T515
Test name
Test status
Simulation time 37107770742 ps
CPU time 128.06 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:38:39 PM PDT 24
Peak memory 1043712 kb
Host smart-977956ec-e468-4aa0-817a-23723faeca1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166250705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.166250705
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3406075653
Short name T809
Test name
Test status
Simulation time 5745354787 ps
CPU time 7.37 seconds
Started Apr 02 03:36:32 PM PDT 24
Finished Apr 02 03:36:39 PM PDT 24
Peak memory 203892 kb
Host smart-6de7f59d-33ef-4f1e-b99b-b3566d9b839a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406075653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3406075653
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.2324287578
Short name T694
Test name
Test status
Simulation time 986333416 ps
CPU time 5.61 seconds
Started Apr 02 03:36:40 PM PDT 24
Finished Apr 02 03:36:46 PM PDT 24
Peak memory 210120 kb
Host smart-087e20de-9573-4a12-94b1-6ec96c25d62e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324287578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.2324287578
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2099293468
Short name T331
Test name
Test status
Simulation time 94010337 ps
CPU time 1.21 seconds
Started Apr 02 03:37:04 PM PDT 24
Finished Apr 02 03:37:06 PM PDT 24
Peak memory 212060 kb
Host smart-04a9c954-8e98-4285-8cc2-f26243526246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099293468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2099293468
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3047922130
Short name T1103
Test name
Test status
Simulation time 323807556 ps
CPU time 5.88 seconds
Started Apr 02 03:37:16 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 270936 kb
Host smart-011ab444-ee8d-43f3-a547-205b3fd9bd15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047922130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3047922130
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2559421789
Short name T714
Test name
Test status
Simulation time 4232273677 ps
CPU time 178.98 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:40:27 PM PDT 24
Peak memory 792392 kb
Host smart-f91c9d14-0bcb-443a-b8ce-97f9878b7f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559421789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2559421789
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3165433943
Short name T642
Test name
Test status
Simulation time 33402049995 ps
CPU time 60.68 seconds
Started Apr 02 03:37:05 PM PDT 24
Finished Apr 02 03:38:06 PM PDT 24
Peak memory 618924 kb
Host smart-1d60b7ee-55e7-4d6f-8a03-eaa8e44a93c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165433943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3165433943
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.945734129
Short name T1171
Test name
Test status
Simulation time 84216031 ps
CPU time 0.82 seconds
Started Apr 02 03:37:06 PM PDT 24
Finished Apr 02 03:37:07 PM PDT 24
Peak memory 203660 kb
Host smart-f95047df-9eb0-4114-85b6-8935abb062a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945734129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.945734129
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3576916581
Short name T753
Test name
Test status
Simulation time 936708218 ps
CPU time 7.14 seconds
Started Apr 02 03:37:23 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 223660 kb
Host smart-fd7f07f1-e14b-4dae-ac34-34742e0dc63f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576916581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3576916581
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2377869473
Short name T542
Test name
Test status
Simulation time 13009565916 ps
CPU time 72.81 seconds
Started Apr 02 03:37:12 PM PDT 24
Finished Apr 02 03:38:25 PM PDT 24
Peak memory 979588 kb
Host smart-f0ef423a-487a-421f-b484-b0d319083eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377869473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2377869473
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1093822555
Short name T1082
Test name
Test status
Simulation time 345971314 ps
CPU time 14.27 seconds
Started Apr 02 03:37:08 PM PDT 24
Finished Apr 02 03:37:23 PM PDT 24
Peak memory 203836 kb
Host smart-5c425c04-8073-421f-b74a-41e58173edd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093822555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1093822555
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1447715929
Short name T354
Test name
Test status
Simulation time 3473336535 ps
CPU time 53.48 seconds
Started Apr 02 03:37:16 PM PDT 24
Finished Apr 02 03:38:11 PM PDT 24
Peak memory 558320 kb
Host smart-eca085e0-64c6-4908-a3fa-5140586b74fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447715929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1447715929
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1204687819
Short name T723
Test name
Test status
Simulation time 58620724 ps
CPU time 0.65 seconds
Started Apr 02 03:37:23 PM PDT 24
Finished Apr 02 03:37:24 PM PDT 24
Peak memory 203604 kb
Host smart-4bef6d27-faa8-4a3b-abc9-bff4a5ced5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204687819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1204687819
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.2166078853
Short name T192
Test name
Test status
Simulation time 27461382176 ps
CPU time 327.07 seconds
Started Apr 02 03:37:07 PM PDT 24
Finished Apr 02 03:42:35 PM PDT 24
Peak memory 1684072 kb
Host smart-a060e95e-61c9-401f-9a9d-d67ee4b69ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166078853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2166078853
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3032119066
Short name T813
Test name
Test status
Simulation time 1645714102 ps
CPU time 41.18 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:38:09 PM PDT 24
Peak memory 297240 kb
Host smart-f145ccc1-ee0a-4a87-9a3e-7c89c7c6ca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032119066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3032119066
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.4104519209
Short name T98
Test name
Test status
Simulation time 12036645101 ps
CPU time 464.94 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:45:12 PM PDT 24
Peak memory 1048576 kb
Host smart-154707c7-5d59-49d3-a3bf-c82f6b0bf667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104519209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.4104519209
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2686716832
Short name T687
Test name
Test status
Simulation time 4057367579 ps
CPU time 4.46 seconds
Started Apr 02 03:37:18 PM PDT 24
Finished Apr 02 03:37:23 PM PDT 24
Peak memory 204564 kb
Host smart-26b4c420-85ee-40b3-aa28-8cc20ed53a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686716832 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2686716832
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2742935316
Short name T528
Test name
Test status
Simulation time 10090403744 ps
CPU time 21.49 seconds
Started Apr 02 03:37:17 PM PDT 24
Finished Apr 02 03:37:40 PM PDT 24
Peak memory 359128 kb
Host smart-88e69084-61b7-46aa-a9ac-3706f3c87027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742935316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2742935316
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.182041936
Short name T623
Test name
Test status
Simulation time 10037307385 ps
CPU time 57.36 seconds
Started Apr 02 03:37:10 PM PDT 24
Finished Apr 02 03:38:09 PM PDT 24
Peak memory 586000 kb
Host smart-d959b756-d4d5-4b50-9fc8-ce50e825a834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182041936 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.182041936
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3293932252
Short name T861
Test name
Test status
Simulation time 375394594 ps
CPU time 2.49 seconds
Started Apr 02 03:37:22 PM PDT 24
Finished Apr 02 03:37:25 PM PDT 24
Peak memory 203832 kb
Host smart-ecad294a-8c87-470d-a4a4-bac11872c270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293932252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3293932252
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2733940645
Short name T323
Test name
Test status
Simulation time 3420716874 ps
CPU time 4.71 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 205340 kb
Host smart-74d2b6d5-ac59-4fee-b08c-d1d68db085d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733940645 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2733940645
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2452312248
Short name T493
Test name
Test status
Simulation time 5172286030 ps
CPU time 46.67 seconds
Started Apr 02 03:37:12 PM PDT 24
Finished Apr 02 03:37:59 PM PDT 24
Peak memory 203728 kb
Host smart-b738f42c-584e-4636-9689-bedda576c415
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452312248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2452312248
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3103857414
Short name T836
Test name
Test status
Simulation time 15916019978 ps
CPU time 14.14 seconds
Started Apr 02 03:37:14 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 221416 kb
Host smart-b99418cf-a32f-4db6-805b-1a858bc25fa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103857414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3103857414
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1148515268
Short name T497
Test name
Test status
Simulation time 29044034288 ps
CPU time 437.84 seconds
Started Apr 02 03:37:18 PM PDT 24
Finished Apr 02 03:44:37 PM PDT 24
Peak memory 3337576 kb
Host smart-18328914-5539-475f-8f2a-51bb8022c178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148515268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1148515268
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2203145975
Short name T334
Test name
Test status
Simulation time 51939279 ps
CPU time 0.59 seconds
Started Apr 02 03:37:22 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 203648 kb
Host smart-8a0d5938-abb8-48d2-80aa-e4603717f6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203145975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2203145975
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2303410901
Short name T617
Test name
Test status
Simulation time 94791702 ps
CPU time 1.46 seconds
Started Apr 02 03:37:21 PM PDT 24
Finished Apr 02 03:37:23 PM PDT 24
Peak memory 212112 kb
Host smart-8698651c-4e79-4a73-8036-eefdd7aa7855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303410901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2303410901
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3732820096
Short name T399
Test name
Test status
Simulation time 1166827103 ps
CPU time 14 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:37:41 PM PDT 24
Peak memory 256216 kb
Host smart-a56336b7-10ee-493a-b719-1c079029b1b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732820096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3732820096
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1670477904
Short name T93
Test name
Test status
Simulation time 2410640515 ps
CPU time 28.91 seconds
Started Apr 02 03:37:11 PM PDT 24
Finished Apr 02 03:37:40 PM PDT 24
Peak memory 375272 kb
Host smart-307dc7de-3275-43f0-848d-c632a6f7dccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670477904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1670477904
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1903312191
Short name T930
Test name
Test status
Simulation time 384984977 ps
CPU time 0.89 seconds
Started Apr 02 03:37:21 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 203692 kb
Host smart-c5c6128f-e36a-44cd-bc83-bdcc09251c8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903312191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1903312191
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.845181621
Short name T795
Test name
Test status
Simulation time 381423754 ps
CPU time 15.96 seconds
Started Apr 02 03:37:30 PM PDT 24
Finished Apr 02 03:37:47 PM PDT 24
Peak memory 203836 kb
Host smart-d6c2fb66-870b-4b79-b893-e02462ceda43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845181621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.845181621
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.4068371363
Short name T891
Test name
Test status
Simulation time 3176930953 ps
CPU time 83.16 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:38:51 PM PDT 24
Peak memory 492036 kb
Host smart-2c1b3fad-c280-49be-b939-56a443fa76ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068371363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4068371363
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2840931001
Short name T287
Test name
Test status
Simulation time 94261044 ps
CPU time 0.62 seconds
Started Apr 02 03:37:10 PM PDT 24
Finished Apr 02 03:37:11 PM PDT 24
Peak memory 203544 kb
Host smart-1feb46bb-907e-49ae-aa8e-1b08bea973e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840931001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2840931001
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1649569692
Short name T188
Test name
Test status
Simulation time 505931015 ps
CPU time 12.22 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:38 PM PDT 24
Peak memory 260300 kb
Host smart-b4100fd3-46d2-483b-99d0-7b37314d4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649569692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1649569692
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1399499820
Short name T639
Test name
Test status
Simulation time 1326878722 ps
CPU time 29.27 seconds
Started Apr 02 03:37:09 PM PDT 24
Finished Apr 02 03:37:39 PM PDT 24
Peak memory 376156 kb
Host smart-c38298be-8bdc-4ff5-9331-d9353dd681c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399499820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1399499820
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.2259738042
Short name T342
Test name
Test status
Simulation time 646610723 ps
CPU time 3.7 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:37:28 PM PDT 24
Peak memory 212020 kb
Host smart-33c18b48-a087-466d-8baf-7245e89416c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259738042 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.2259738042
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1323879983
Short name T984
Test name
Test status
Simulation time 10069779518 ps
CPU time 13.56 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:37:42 PM PDT 24
Peak memory 311488 kb
Host smart-b52dad3a-8a6e-4b81-b623-ff0450ba9cbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323879983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1323879983
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1424674897
Short name T206
Test name
Test status
Simulation time 515973291 ps
CPU time 2.01 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:37:27 PM PDT 24
Peak memory 203824 kb
Host smart-620baff6-7d81-4833-a620-c8acc681b986
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424674897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1424674897
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2252020337
Short name T673
Test name
Test status
Simulation time 1083499621 ps
CPU time 4.98 seconds
Started Apr 02 03:37:11 PM PDT 24
Finished Apr 02 03:37:16 PM PDT 24
Peak memory 203772 kb
Host smart-cefc1a22-e4af-471f-a8de-4bcd773d711e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252020337 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2252020337
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1568165804
Short name T715
Test name
Test status
Simulation time 4901244571 ps
CPU time 11.86 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:37:39 PM PDT 24
Peak memory 203844 kb
Host smart-55218f97-2abd-415f-b7af-5eecbd1edb23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568165804 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1568165804
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.818035255
Short name T999
Test name
Test status
Simulation time 959896198 ps
CPU time 13.15 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:37:41 PM PDT 24
Peak memory 203788 kb
Host smart-e5cb3c88-5990-45f7-9cfd-b2c1e8d1064b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818035255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.818035255
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.4207632206
Short name T840
Test name
Test status
Simulation time 1089781323 ps
CPU time 18.43 seconds
Started Apr 02 03:37:17 PM PDT 24
Finished Apr 02 03:37:37 PM PDT 24
Peak memory 221092 kb
Host smart-d600dec0-f07c-41fc-ad45-af0a935ce2b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207632206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.4207632206
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3738427389
Short name T1153
Test name
Test status
Simulation time 8629926240 ps
CPU time 72.63 seconds
Started Apr 02 03:37:11 PM PDT 24
Finished Apr 02 03:38:24 PM PDT 24
Peak memory 1065088 kb
Host smart-d840b8cb-5d31-4035-8667-3126d7faca5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738427389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3738427389
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2855538561
Short name T427
Test name
Test status
Simulation time 2146959070 ps
CPU time 6.18 seconds
Started Apr 02 03:37:11 PM PDT 24
Finished Apr 02 03:37:17 PM PDT 24
Peak memory 219972 kb
Host smart-56bdabab-0a4d-4ceb-8cf8-87ef01a28ffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855538561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2855538561
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.703565088
Short name T1033
Test name
Test status
Simulation time 15136603 ps
CPU time 0.59 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:26 PM PDT 24
Peak memory 203660 kb
Host smart-55dcd021-2321-4e8e-a03e-2df78d31edf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703565088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.703565088
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.1902922862
Short name T43
Test name
Test status
Simulation time 227731681 ps
CPU time 1.3 seconds
Started Apr 02 03:37:19 PM PDT 24
Finished Apr 02 03:37:20 PM PDT 24
Peak memory 211936 kb
Host smart-4dd3e273-cc79-4009-bb25-58a6fa4efd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902922862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1902922862
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3890700821
Short name T1184
Test name
Test status
Simulation time 658157266 ps
CPU time 6.7 seconds
Started Apr 02 03:37:29 PM PDT 24
Finished Apr 02 03:37:35 PM PDT 24
Peak memory 275132 kb
Host smart-1d89e4af-04c3-4567-a0df-393a82ecf115
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890700821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3890700821
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3638886043
Short name T490
Test name
Test status
Simulation time 6023016908 ps
CPU time 44.09 seconds
Started Apr 02 03:37:29 PM PDT 24
Finished Apr 02 03:38:13 PM PDT 24
Peak memory 562292 kb
Host smart-5f7828a4-821d-478d-9197-d77a91602402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638886043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3638886043
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.536510463
Short name T1053
Test name
Test status
Simulation time 4829096374 ps
CPU time 37.27 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:38:01 PM PDT 24
Peak memory 490388 kb
Host smart-872b7444-f0f3-43f8-9b55-63bf3e42eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536510463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.536510463
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2676405504
Short name T198
Test name
Test status
Simulation time 225212219 ps
CPU time 0.83 seconds
Started Apr 02 03:37:18 PM PDT 24
Finished Apr 02 03:37:20 PM PDT 24
Peak memory 203668 kb
Host smart-64e9cf3d-5d21-49ec-866d-bd400d984d43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676405504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2676405504
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2239046156
Short name T86
Test name
Test status
Simulation time 135011037 ps
CPU time 6.89 seconds
Started Apr 02 03:37:17 PM PDT 24
Finished Apr 02 03:37:26 PM PDT 24
Peak memory 203804 kb
Host smart-9d43215d-4b7b-4eb0-96a6-8bb4409a9953
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239046156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2239046156
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1458142602
Short name T741
Test name
Test status
Simulation time 33479380115 ps
CPU time 72.96 seconds
Started Apr 02 03:37:20 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 952548 kb
Host smart-87cae78a-4154-45c3-9553-22cb1596bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458142602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1458142602
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.707904934
Short name T174
Test name
Test status
Simulation time 357267841 ps
CPU time 14.62 seconds
Started Apr 02 03:37:23 PM PDT 24
Finished Apr 02 03:37:38 PM PDT 24
Peak memory 203908 kb
Host smart-3d2d63bd-b2d3-4a49-8db7-cf67cdb495f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707904934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.707904934
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2579124915
Short name T370
Test name
Test status
Simulation time 5442218395 ps
CPU time 64.87 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 365848 kb
Host smart-3f3dcec7-0bca-455c-8132-8639b7cae279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579124915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2579124915
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.4168529590
Short name T620
Test name
Test status
Simulation time 29209433 ps
CPU time 0.64 seconds
Started Apr 02 03:37:17 PM PDT 24
Finished Apr 02 03:37:19 PM PDT 24
Peak memory 203620 kb
Host smart-b881e5f5-a728-4cf4-a717-4d68b031514d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168529590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4168529590
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1578583247
Short name T833
Test name
Test status
Simulation time 4168564827 ps
CPU time 48.73 seconds
Started Apr 02 03:37:10 PM PDT 24
Finished Apr 02 03:38:00 PM PDT 24
Peak memory 330264 kb
Host smart-ac323596-431e-4083-8a39-f65c3303b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578583247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1578583247
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.3472780875
Short name T827
Test name
Test status
Simulation time 24677477880 ps
CPU time 1104.29 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:55:52 PM PDT 24
Peak memory 2142740 kb
Host smart-c4393024-4eb6-4aeb-8cea-ec424ba3cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472780875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.3472780875
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.353541581
Short name T996
Test name
Test status
Simulation time 2617411465 ps
CPU time 3.33 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:37:28 PM PDT 24
Peak memory 203832 kb
Host smart-5d4b64cf-25b2-44cd-8416-3b5cf6c9c4f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353541581 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.353541581
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2226247091
Short name T690
Test name
Test status
Simulation time 10054222755 ps
CPU time 96.56 seconds
Started Apr 02 03:37:23 PM PDT 24
Finished Apr 02 03:39:00 PM PDT 24
Peak memory 631596 kb
Host smart-a8c93d17-2d99-40ad-937d-3a25fb9a3f08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226247091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2226247091
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.365438645
Short name T1136
Test name
Test status
Simulation time 10039471164 ps
CPU time 93.36 seconds
Started Apr 02 03:37:15 PM PDT 24
Finished Apr 02 03:38:49 PM PDT 24
Peak memory 703760 kb
Host smart-1e1eb23a-e78a-40fd-a6c9-2999699e29c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365438645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.365438645
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.4038154791
Short name T730
Test name
Test status
Simulation time 6944890052 ps
CPU time 2.88 seconds
Started Apr 02 03:37:31 PM PDT 24
Finished Apr 02 03:37:34 PM PDT 24
Peak memory 203920 kb
Host smart-f22f54b6-1c15-4169-941b-79cb905addbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038154791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.4038154791
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.2790670686
Short name T552
Test name
Test status
Simulation time 1233152141 ps
CPU time 6.7 seconds
Started Apr 02 03:37:22 PM PDT 24
Finished Apr 02 03:37:29 PM PDT 24
Peak memory 210004 kb
Host smart-e5195411-1c3d-4a37-a09e-5e14c28fc3ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790670686 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.2790670686
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.883430029
Short name T1006
Test name
Test status
Simulation time 3823173265 ps
CPU time 17.08 seconds
Started Apr 02 03:37:18 PM PDT 24
Finished Apr 02 03:37:36 PM PDT 24
Peak memory 203864 kb
Host smart-b81c07b3-f7aa-4952-b0f6-114299c16cbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883430029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.883430029
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3537875148
Short name T363
Test name
Test status
Simulation time 1219652293 ps
CPU time 51.43 seconds
Started Apr 02 03:37:23 PM PDT 24
Finished Apr 02 03:38:14 PM PDT 24
Peak memory 205800 kb
Host smart-65e7190d-43f2-4879-b071-a46db7138796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537875148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3537875148
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3121173876
Short name T548
Test name
Test status
Simulation time 27174818437 ps
CPU time 2025.29 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 04:11:14 PM PDT 24
Peak memory 6311048 kb
Host smart-d2b39c1a-66a8-471a-9134-38e6f74fb5c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121173876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3121173876
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1368390011
Short name T881
Test name
Test status
Simulation time 1603994230 ps
CPU time 7.62 seconds
Started Apr 02 03:37:15 PM PDT 24
Finished Apr 02 03:37:24 PM PDT 24
Peak memory 220028 kb
Host smart-c52134c2-72a7-4bc8-8cd0-d96077c202a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368390011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1368390011
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3853292409
Short name T1127
Test name
Test status
Simulation time 46392337 ps
CPU time 0.64 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:27 PM PDT 24
Peak memory 203716 kb
Host smart-3f312d41-9ba8-4d57-8f5b-5d6ed492a7d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853292409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3853292409
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.31096404
Short name T665
Test name
Test status
Simulation time 275224994 ps
CPU time 1.4 seconds
Started Apr 02 03:37:17 PM PDT 24
Finished Apr 02 03:37:20 PM PDT 24
Peak memory 212028 kb
Host smart-e6641cac-e9c4-4751-a3dd-f90e29b1fd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31096404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.31096404
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1865293626
Short name T701
Test name
Test status
Simulation time 1354779118 ps
CPU time 10.58 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:37:38 PM PDT 24
Peak memory 240604 kb
Host smart-298b4774-00e0-4162-8f0e-5191413ca459
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865293626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1865293626
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3547120095
Short name T70
Test name
Test status
Simulation time 2619901325 ps
CPU time 87.22 seconds
Started Apr 02 03:37:30 PM PDT 24
Finished Apr 02 03:38:57 PM PDT 24
Peak memory 727004 kb
Host smart-ff47f86d-1385-4694-9707-772e101112b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547120095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3547120095
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3808342579
Short name T19
Test name
Test status
Simulation time 4380261177 ps
CPU time 64.27 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:38:32 PM PDT 24
Peak memory 384584 kb
Host smart-e4ebcafd-2bab-42f9-96f6-e25eb560046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808342579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3808342579
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3098991039
Short name T680
Test name
Test status
Simulation time 177109186 ps
CPU time 1.2 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:27 PM PDT 24
Peak memory 203812 kb
Host smart-685a0eb1-e6b7-4e45-8156-b81a0f53ff92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098991039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3098991039
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3178169934
Short name T538
Test name
Test status
Simulation time 549930604 ps
CPU time 3.77 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 226432 kb
Host smart-9c4a9b97-1f30-458d-9219-729d44def18b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178169934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3178169934
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1662809348
Short name T304
Test name
Test status
Simulation time 6982769542 ps
CPU time 206.77 seconds
Started Apr 02 03:37:30 PM PDT 24
Finished Apr 02 03:40:57 PM PDT 24
Peak memory 949228 kb
Host smart-7ea1c3e6-1b33-45a6-8803-7e616142217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662809348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1662809348
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.718423119
Short name T414
Test name
Test status
Simulation time 3821643273 ps
CPU time 19.33 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:46 PM PDT 24
Peak memory 325332 kb
Host smart-4e241017-77f6-4c70-a572-958c1cd915e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718423119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.718423119
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2830250276
Short name T173
Test name
Test status
Simulation time 4379919688 ps
CPU time 17.31 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:43 PM PDT 24
Peak memory 382728 kb
Host smart-4d04ed8e-b345-4003-a4c0-bc9914bc8a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830250276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2830250276
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.351613536
Short name T547
Test name
Test status
Simulation time 6693639070 ps
CPU time 30.23 seconds
Started Apr 02 03:37:21 PM PDT 24
Finished Apr 02 03:37:52 PM PDT 24
Peak memory 368836 kb
Host smart-59b8ba85-9241-4a37-9953-d7c9cba82ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351613536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.351613536
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2209839963
Short name T81
Test name
Test status
Simulation time 10123290019 ps
CPU time 32.39 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:58 PM PDT 24
Peak memory 397268 kb
Host smart-833963d6-4526-4330-866c-4b554083b03d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209839963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2209839963
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3533539902
Short name T828
Test name
Test status
Simulation time 10046752513 ps
CPU time 86.63 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:38:53 PM PDT 24
Peak memory 729584 kb
Host smart-bf117293-e528-4fbf-980d-688ccf7a6439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533539902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3533539902
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.129517986
Short name T1045
Test name
Test status
Simulation time 907488286 ps
CPU time 2.53 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 203820 kb
Host smart-8b8eef3d-fe1b-44a9-834c-518afee03ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129517986 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_hrst.129517986
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.724219712
Short name T769
Test name
Test status
Simulation time 2046843026 ps
CPU time 5.53 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:32 PM PDT 24
Peak memory 207436 kb
Host smart-c6067142-54ac-4e29-a734-585122b13f74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724219712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.724219712
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.363967019
Short name T22
Test name
Test status
Simulation time 16434670154 ps
CPU time 17.42 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:44 PM PDT 24
Peak memory 203752 kb
Host smart-2dcf5634-d4dc-43ae-a395-98cafc7470dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363967019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.363967019
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1196307663
Short name T898
Test name
Test status
Simulation time 2014085209 ps
CPU time 24.16 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:49 PM PDT 24
Peak memory 203840 kb
Host smart-07bcec5d-8759-40dd-a87c-0ebb52dca008
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196307663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1196307663
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1161964513
Short name T435
Test name
Test status
Simulation time 9570349526 ps
CPU time 1029.96 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:54:38 PM PDT 24
Peak memory 2422592 kb
Host smart-6edf5df0-395e-4ab6-91d8-85711c715cf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161964513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1161964513
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2825082023
Short name T1027
Test name
Test status
Simulation time 1331780984 ps
CPU time 6.51 seconds
Started Apr 02 03:37:22 PM PDT 24
Finished Apr 02 03:37:29 PM PDT 24
Peak memory 220016 kb
Host smart-18a55c93-57f4-4ef0-982c-a94070fede59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825082023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2825082023
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.1948541303
Short name T846
Test name
Test status
Simulation time 653738970 ps
CPU time 4.79 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 203788 kb
Host smart-3e0d2490-9b71-4246-874f-5d45311b7d74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948541303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.1948541303
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.896657926
Short name T526
Test name
Test status
Simulation time 17115356 ps
CPU time 0.65 seconds
Started Apr 02 03:37:23 PM PDT 24
Finished Apr 02 03:37:24 PM PDT 24
Peak memory 203496 kb
Host smart-a27a0aa3-190b-422b-86b3-34796e7cd220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896657926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.896657926
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1421063231
Short name T630
Test name
Test status
Simulation time 250895307 ps
CPU time 1.23 seconds
Started Apr 02 03:37:33 PM PDT 24
Finished Apr 02 03:37:35 PM PDT 24
Peak memory 212028 kb
Host smart-f279e0f4-e788-4d07-aac9-942632f25e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421063231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1421063231
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1990555533
Short name T393
Test name
Test status
Simulation time 814423209 ps
CPU time 4.27 seconds
Started Apr 02 03:37:31 PM PDT 24
Finished Apr 02 03:37:36 PM PDT 24
Peak memory 249756 kb
Host smart-f8d7c365-5b8b-436f-8cba-e321c1e7be31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990555533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1990555533
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.312947494
Short name T391
Test name
Test status
Simulation time 5375460008 ps
CPU time 64.26 seconds
Started Apr 02 03:37:31 PM PDT 24
Finished Apr 02 03:38:35 PM PDT 24
Peak memory 671540 kb
Host smart-bf77006b-08bb-4f2e-a95c-43419b22e3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312947494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.312947494
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.13169402
Short name T303
Test name
Test status
Simulation time 7935115962 ps
CPU time 57.68 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:38:26 PM PDT 24
Peak memory 644724 kb
Host smart-22b15a83-d5d9-4739-a5b6-7f11a7379818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13169402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.13169402
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2442821944
Short name T499
Test name
Test status
Simulation time 571861106 ps
CPU time 1.25 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:27 PM PDT 24
Peak memory 203796 kb
Host smart-0b1092c1-f633-4ea8-b05e-3064a5ec5177
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442821944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2442821944
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2902206619
Short name T90
Test name
Test status
Simulation time 541967854 ps
CPU time 3.03 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:29 PM PDT 24
Peak memory 203800 kb
Host smart-aab4bf60-301e-4748-a5ba-d3b3fc9f3d9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902206619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2902206619
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.4208036198
Short name T215
Test name
Test status
Simulation time 468400583 ps
CPU time 19.6 seconds
Started Apr 02 03:37:29 PM PDT 24
Finished Apr 02 03:37:49 PM PDT 24
Peak memory 203788 kb
Host smart-75550ffc-6bef-402c-8e37-095d64d83d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208036198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.4208036198
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.355779571
Short name T1091
Test name
Test status
Simulation time 3870113435 ps
CPU time 105.23 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:39:11 PM PDT 24
Peak memory 462776 kb
Host smart-d35a3dcd-82de-4488-bd2b-71751f28b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355779571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.355779571
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1605508462
Short name T1117
Test name
Test status
Simulation time 65392738 ps
CPU time 0.66 seconds
Started Apr 02 03:37:29 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 203644 kb
Host smart-fb4025c8-4ba3-496a-8256-927cde821fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605508462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1605508462
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3930463120
Short name T410
Test name
Test status
Simulation time 9843654770 ps
CPU time 219.98 seconds
Started Apr 02 03:37:32 PM PDT 24
Finished Apr 02 03:41:13 PM PDT 24
Peak memory 1100388 kb
Host smart-aca2c7ab-a141-466a-b09f-b3d1c58b5d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930463120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3930463120
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.654703433
Short name T876
Test name
Test status
Simulation time 971963204 ps
CPU time 45.45 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:38:14 PM PDT 24
Peak memory 312220 kb
Host smart-9c3247d1-3cfd-41cb-9425-c109958d3ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654703433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.654703433
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1877775878
Short name T78
Test name
Test status
Simulation time 22711298514 ps
CPU time 2069.31 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 04:11:55 PM PDT 24
Peak memory 1250860 kb
Host smart-ee608030-c479-4774-8019-a873be7b0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877775878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1877775878
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.60503325
Short name T804
Test name
Test status
Simulation time 1324718474 ps
CPU time 3.59 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 203772 kb
Host smart-270f0424-6477-4fbd-a6e9-3ecb60c180b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60503325 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_bad_addr.60503325
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.1862769538
Short name T1112
Test name
Test status
Simulation time 10162981603 ps
CPU time 15.46 seconds
Started Apr 02 03:37:34 PM PDT 24
Finished Apr 02 03:37:49 PM PDT 24
Peak memory 297692 kb
Host smart-ead773c0-066f-44a1-83a1-c41e8731b44e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862769538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.1862769538
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2604821513
Short name T1095
Test name
Test status
Simulation time 10444915678 ps
CPU time 16.29 seconds
Started Apr 02 03:37:23 PM PDT 24
Finished Apr 02 03:37:40 PM PDT 24
Peak memory 336972 kb
Host smart-e4c44f43-afc0-4736-bf76-02a4528507a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604821513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2604821513
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1041167702
Short name T918
Test name
Test status
Simulation time 1200490803 ps
CPU time 4.83 seconds
Started Apr 02 03:37:31 PM PDT 24
Finished Apr 02 03:37:36 PM PDT 24
Peak memory 211868 kb
Host smart-10b7632a-04bc-4c2a-a2e7-6bf8ac61d46f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041167702 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1041167702
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.83196343
Short name T924
Test name
Test status
Simulation time 1330804391 ps
CPU time 14.56 seconds
Started Apr 02 03:37:29 PM PDT 24
Finished Apr 02 03:37:44 PM PDT 24
Peak memory 203796 kb
Host smart-994ebace-266e-4677-9015-72739ecda9fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83196343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_targ
et_smoke.83196343
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1333938119
Short name T816
Test name
Test status
Simulation time 3780677106 ps
CPU time 41.34 seconds
Started Apr 02 03:37:34 PM PDT 24
Finished Apr 02 03:38:15 PM PDT 24
Peak memory 203824 kb
Host smart-7d391a22-b484-491e-8e75-f2423761d17f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333938119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1333938119
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.621957945
Short name T1025
Test name
Test status
Simulation time 24279912827 ps
CPU time 639.95 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:48:04 PM PDT 24
Peak memory 2895604 kb
Host smart-0d36bf6e-cd86-46ad-af1e-4ebe94a67228
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621957945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.621957945
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2872922461
Short name T875
Test name
Test status
Simulation time 1463022387 ps
CPU time 7.32 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:37:35 PM PDT 24
Peak memory 219932 kb
Host smart-deb261d7-596d-4597-82d1-26b12e5de96f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872922461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2872922461
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1790313867
Short name T461
Test name
Test status
Simulation time 23812033 ps
CPU time 0.6 seconds
Started Apr 02 03:37:34 PM PDT 24
Finished Apr 02 03:37:35 PM PDT 24
Peak memory 203628 kb
Host smart-26288b71-2508-4168-98cb-af70e0a4ed9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790313867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1790313867
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2684411734
Short name T663
Test name
Test status
Simulation time 288247278 ps
CPU time 1.45 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 212040 kb
Host smart-2899a938-e029-4665-b11b-9a68c859dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684411734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2684411734
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3184948701
Short name T678
Test name
Test status
Simulation time 348467880 ps
CPU time 6.77 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:37:35 PM PDT 24
Peak memory 273140 kb
Host smart-605368af-ae60-4303-a1da-9d02e115385a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184948701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3184948701
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3026009741
Short name T440
Test name
Test status
Simulation time 2635433700 ps
CPU time 42.18 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:38:10 PM PDT 24
Peak memory 525356 kb
Host smart-fac8b0c8-b3f0-4a4c-8631-cdaaf0fb3e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026009741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3026009741
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3630252449
Short name T540
Test name
Test status
Simulation time 2095891288 ps
CPU time 60.45 seconds
Started Apr 02 03:37:30 PM PDT 24
Finished Apr 02 03:38:31 PM PDT 24
Peak memory 589472 kb
Host smart-4d63af2e-03bd-455e-8466-9faed6cd35f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630252449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3630252449
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1683237848
Short name T458
Test name
Test status
Simulation time 69036251 ps
CPU time 0.91 seconds
Started Apr 02 03:37:35 PM PDT 24
Finished Apr 02 03:37:36 PM PDT 24
Peak memory 203640 kb
Host smart-dcdf18de-0397-41ef-bfdd-bddf06791358
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683237848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1683237848
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3940295654
Short name T1064
Test name
Test status
Simulation time 794401458 ps
CPU time 4.17 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:37:29 PM PDT 24
Peak memory 203804 kb
Host smart-53faf8cd-556b-47f9-801b-bc2c66def9ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940295654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3940295654
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2842523508
Short name T808
Test name
Test status
Simulation time 11571927699 ps
CPU time 195.35 seconds
Started Apr 02 03:37:30 PM PDT 24
Finished Apr 02 03:40:46 PM PDT 24
Peak memory 896128 kb
Host smart-fcf2496d-56e9-401a-97fd-965f67ac57d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842523508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2842523508
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.4279007772
Short name T1120
Test name
Test status
Simulation time 511138338 ps
CPU time 7.48 seconds
Started Apr 02 03:37:32 PM PDT 24
Finished Apr 02 03:37:40 PM PDT 24
Peak memory 203824 kb
Host smart-f4e72311-af70-4e98-a928-9b7d8854a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279007772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.4279007772
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.458659925
Short name T275
Test name
Test status
Simulation time 1053968724 ps
CPU time 22.37 seconds
Started Apr 02 03:37:38 PM PDT 24
Finished Apr 02 03:38:00 PM PDT 24
Peak memory 360608 kb
Host smart-50757e0a-3bea-4f1f-a05a-e79b4040bc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458659925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.458659925
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.3323132216
Short name T392
Test name
Test status
Simulation time 74657738 ps
CPU time 0.67 seconds
Started Apr 02 03:37:35 PM PDT 24
Finished Apr 02 03:37:36 PM PDT 24
Peak memory 203620 kb
Host smart-94025407-966b-4bfd-91b8-6a7b2a94634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323132216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3323132216
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3561802204
Short name T859
Test name
Test status
Simulation time 19219636990 ps
CPU time 48.97 seconds
Started Apr 02 03:37:27 PM PDT 24
Finished Apr 02 03:38:16 PM PDT 24
Peak memory 203816 kb
Host smart-5be533dd-6acc-4a3b-af64-c5267e5e4ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561802204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3561802204
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3978748545
Short name T17
Test name
Test status
Simulation time 1097058392 ps
CPU time 21.19 seconds
Started Apr 02 03:37:25 PM PDT 24
Finished Apr 02 03:37:47 PM PDT 24
Peak memory 339512 kb
Host smart-1fbf137d-4289-44ae-a866-26b0f1c192b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978748545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3978748545
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2038664079
Short name T38
Test name
Test status
Simulation time 2659950580 ps
CPU time 3.5 seconds
Started Apr 02 03:37:35 PM PDT 24
Finished Apr 02 03:37:39 PM PDT 24
Peak memory 203852 kb
Host smart-16a18e28-5ae5-4ca4-bec4-13ccef941c86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038664079 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2038664079
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.717973541
Short name T993
Test name
Test status
Simulation time 10474604694 ps
CPU time 12.79 seconds
Started Apr 02 03:37:36 PM PDT 24
Finished Apr 02 03:37:49 PM PDT 24
Peak memory 286796 kb
Host smart-0e0e3e8c-b93e-4702-a392-094a79722ff3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717973541 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.717973541
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3486931766
Short name T253
Test name
Test status
Simulation time 10791401887 ps
CPU time 3.51 seconds
Started Apr 02 03:37:31 PM PDT 24
Finished Apr 02 03:37:34 PM PDT 24
Peak memory 224904 kb
Host smart-ac91cf0d-61ca-4328-966f-f36421be5f39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486931766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3486931766
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.3107311044
Short name T848
Test name
Test status
Simulation time 2452199952 ps
CPU time 2.85 seconds
Started Apr 02 03:37:35 PM PDT 24
Finished Apr 02 03:37:37 PM PDT 24
Peak memory 203892 kb
Host smart-06941236-8939-4cb0-9557-a0cfad0aad33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107311044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.3107311044
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1580275063
Short name T306
Test name
Test status
Simulation time 758290601 ps
CPU time 4.32 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:37:33 PM PDT 24
Peak memory 203848 kb
Host smart-26235b19-a56e-469f-a670-6f5ea20c0fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580275063 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1580275063
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.937800888
Short name T1015
Test name
Test status
Simulation time 3002101423 ps
CPU time 26.22 seconds
Started Apr 02 03:37:26 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 203808 kb
Host smart-00fcdf07-c4b5-4796-94ac-f5b0f7bace57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937800888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.937800888
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2113859670
Short name T747
Test name
Test status
Simulation time 1427395748 ps
CPU time 11.41 seconds
Started Apr 02 03:37:33 PM PDT 24
Finished Apr 02 03:37:45 PM PDT 24
Peak memory 212032 kb
Host smart-00eb349d-7186-48b5-9545-5348f7d5af4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113859670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2113859670
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2149575528
Short name T688
Test name
Test status
Simulation time 5677235487 ps
CPU time 7.48 seconds
Started Apr 02 03:37:37 PM PDT 24
Finished Apr 02 03:37:44 PM PDT 24
Peak memory 219676 kb
Host smart-f406ffe5-dea4-4d57-8678-a2259a0a28e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149575528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2149575528
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.4119285754
Short name T535
Test name
Test status
Simulation time 17668852 ps
CPU time 0.63 seconds
Started Apr 02 03:37:44 PM PDT 24
Finished Apr 02 03:37:45 PM PDT 24
Peak memory 203660 kb
Host smart-8585a76d-7f88-4bf6-b6d6-e868a9940bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119285754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.4119285754
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2855518971
Short name T1088
Test name
Test status
Simulation time 99128374 ps
CPU time 1.17 seconds
Started Apr 02 03:37:39 PM PDT 24
Finished Apr 02 03:37:40 PM PDT 24
Peak memory 212056 kb
Host smart-61878213-c7df-474f-a1e1-daa4d868d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855518971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2855518971
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.438661216
Short name T867
Test name
Test status
Simulation time 345469257 ps
CPU time 3.26 seconds
Started Apr 02 03:37:36 PM PDT 24
Finished Apr 02 03:37:39 PM PDT 24
Peak memory 234484 kb
Host smart-9eea9c48-5f42-4f58-9829-6ac0de32cffb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438661216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.438661216
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1579862777
Short name T851
Test name
Test status
Simulation time 2755021527 ps
CPU time 63.23 seconds
Started Apr 02 03:37:37 PM PDT 24
Finished Apr 02 03:38:41 PM PDT 24
Peak memory 629464 kb
Host smart-49af22d4-d75e-4b4e-b538-14a146cfce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579862777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1579862777
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3020447144
Short name T573
Test name
Test status
Simulation time 7552331812 ps
CPU time 137.82 seconds
Started Apr 02 03:37:38 PM PDT 24
Finished Apr 02 03:39:56 PM PDT 24
Peak memory 629948 kb
Host smart-3745dee5-0926-4005-890f-ec75a30796fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020447144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3020447144
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1771463201
Short name T14
Test name
Test status
Simulation time 422788995 ps
CPU time 1.03 seconds
Started Apr 02 03:37:39 PM PDT 24
Finished Apr 02 03:37:40 PM PDT 24
Peak memory 203808 kb
Host smart-d58c263b-84ba-4d3d-a581-11a6aa28834c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771463201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1771463201
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1478763271
Short name T313
Test name
Test status
Simulation time 457395125 ps
CPU time 7.29 seconds
Started Apr 02 03:37:35 PM PDT 24
Finished Apr 02 03:37:43 PM PDT 24
Peak memory 223896 kb
Host smart-7ceb8e0f-8de8-43a0-93a8-0e3757cd041b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478763271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1478763271
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.857555504
Short name T156
Test name
Test status
Simulation time 4120603671 ps
CPU time 114.14 seconds
Started Apr 02 03:37:37 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 1219184 kb
Host smart-cee5f0cb-f0bc-463b-a7ea-8cd6a47593dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857555504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.857555504
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3825293323
Short name T636
Test name
Test status
Simulation time 433115313 ps
CPU time 16.05 seconds
Started Apr 02 03:37:42 PM PDT 24
Finished Apr 02 03:37:59 PM PDT 24
Peak memory 203776 kb
Host smart-88c2402d-8472-45b4-90e1-67cce9e4a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825293323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3825293323
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.4188055642
Short name T757
Test name
Test status
Simulation time 1437631310 ps
CPU time 77.12 seconds
Started Apr 02 03:37:43 PM PDT 24
Finished Apr 02 03:39:01 PM PDT 24
Peak memory 416528 kb
Host smart-a7adb294-b8a2-48b8-af0c-ec31efa38006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188055642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.4188055642
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1931271660
Short name T629
Test name
Test status
Simulation time 28319214 ps
CPU time 0.7 seconds
Started Apr 02 03:37:42 PM PDT 24
Finished Apr 02 03:37:44 PM PDT 24
Peak memory 203580 kb
Host smart-b6ff1121-180e-4ead-937f-5321014767af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931271660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1931271660
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3836087469
Short name T33
Test name
Test status
Simulation time 49606501892 ps
CPU time 1953.05 seconds
Started Apr 02 03:37:39 PM PDT 24
Finished Apr 02 04:10:13 PM PDT 24
Peak memory 252476 kb
Host smart-f998150f-1f27-44e3-bb9a-137aff6988f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836087469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3836087469
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3867161443
Short name T1013
Test name
Test status
Simulation time 1289850340 ps
CPU time 30.99 seconds
Started Apr 02 03:37:31 PM PDT 24
Finished Apr 02 03:38:02 PM PDT 24
Peak memory 411152 kb
Host smart-ad1b401f-9b50-4fc7-9faf-71b1ad44ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867161443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3867161443
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3153062701
Short name T841
Test name
Test status
Simulation time 1533175979 ps
CPU time 3.92 seconds
Started Apr 02 03:37:43 PM PDT 24
Finished Apr 02 03:37:47 PM PDT 24
Peak memory 212052 kb
Host smart-891f7c80-f77a-4920-9784-b3fa4910cdd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153062701 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3153062701
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.464714528
Short name T975
Test name
Test status
Simulation time 13168882838 ps
CPU time 4.85 seconds
Started Apr 02 03:37:40 PM PDT 24
Finished Apr 02 03:37:45 PM PDT 24
Peak memory 243824 kb
Host smart-510e95ed-8601-459a-ae4e-4b0635645844
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464714528 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.464714528
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.3012591082
Short name T951
Test name
Test status
Simulation time 331232742 ps
CPU time 2.26 seconds
Started Apr 02 03:37:44 PM PDT 24
Finished Apr 02 03:37:46 PM PDT 24
Peak memory 203780 kb
Host smart-0a78b8b8-3f42-4093-9e30-2378a52e70ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012591082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.3012591082
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.411715620
Short name T476
Test name
Test status
Simulation time 2453894759 ps
CPU time 6.62 seconds
Started Apr 02 03:37:36 PM PDT 24
Finished Apr 02 03:37:43 PM PDT 24
Peak memory 220036 kb
Host smart-8e069b28-9ed2-4a53-b433-4bc228e63752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411715620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.411715620
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.1604892618
Short name T931
Test name
Test status
Simulation time 4621933500 ps
CPU time 3.14 seconds
Started Apr 02 03:37:38 PM PDT 24
Finished Apr 02 03:37:42 PM PDT 24
Peak memory 203816 kb
Host smart-64943807-399b-4c27-9300-a0ca0e7ee2aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604892618 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1604892618
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3134595941
Short name T523
Test name
Test status
Simulation time 2281765627 ps
CPU time 18.72 seconds
Started Apr 02 03:37:36 PM PDT 24
Finished Apr 02 03:37:55 PM PDT 24
Peak memory 203884 kb
Host smart-25647ce2-f112-4fce-a7c7-50c51bfd095a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134595941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3134595941
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2478279
Short name T1173
Test name
Test status
Simulation time 19642179051 ps
CPU time 12.24 seconds
Started Apr 02 03:37:39 PM PDT 24
Finished Apr 02 03:37:52 PM PDT 24
Peak memory 203884 kb
Host smart-d97c460d-bb33-44e2-9bd3-3006b031b76d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stress_wr.2478279
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3804400047
Short name T389
Test name
Test status
Simulation time 27073935843 ps
CPU time 503.56 seconds
Started Apr 02 03:37:40 PM PDT 24
Finished Apr 02 03:46:03 PM PDT 24
Peak memory 1482700 kb
Host smart-abae5a87-4425-4c60-9473-b722daa488a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804400047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3804400047
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1220290310
Short name T1040
Test name
Test status
Simulation time 7192050114 ps
CPU time 7.01 seconds
Started Apr 02 03:37:43 PM PDT 24
Finished Apr 02 03:37:50 PM PDT 24
Peak memory 218600 kb
Host smart-4dad4b8f-c1fb-4314-b965-fad96b2cae35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220290310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1220290310
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2521690858
Short name T1190
Test name
Test status
Simulation time 110401320 ps
CPU time 0.58 seconds
Started Apr 02 03:37:47 PM PDT 24
Finished Apr 02 03:37:48 PM PDT 24
Peak memory 203688 kb
Host smart-f09d3933-2655-4e27-b42a-b0a2698ecd15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521690858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2521690858
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2275353974
Short name T812
Test name
Test status
Simulation time 1069100170 ps
CPU time 1.72 seconds
Started Apr 02 03:37:42 PM PDT 24
Finished Apr 02 03:37:45 PM PDT 24
Peak memory 212008 kb
Host smart-adc1d1fc-3948-4b01-bbf6-9b07edcdbdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275353974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2275353974
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3514129976
Short name T1180
Test name
Test status
Simulation time 454903047 ps
CPU time 4.67 seconds
Started Apr 02 03:37:42 PM PDT 24
Finished Apr 02 03:37:48 PM PDT 24
Peak memory 250492 kb
Host smart-d02980c4-485f-4994-a450-0464c0999f01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514129976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3514129976
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2009590598
Short name T1128
Test name
Test status
Simulation time 2591468122 ps
CPU time 37.9 seconds
Started Apr 02 03:37:43 PM PDT 24
Finished Apr 02 03:38:21 PM PDT 24
Peak memory 524140 kb
Host smart-e35c66bb-9f23-4423-8274-e92e6ef8dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009590598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2009590598
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2360329047
Short name T501
Test name
Test status
Simulation time 1771975891 ps
CPU time 135.23 seconds
Started Apr 02 03:37:41 PM PDT 24
Finished Apr 02 03:39:56 PM PDT 24
Peak memory 644472 kb
Host smart-377f5f26-4aa9-44a3-bbba-186ca1510525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360329047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2360329047
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2895278628
Short name T1176
Test name
Test status
Simulation time 301008004 ps
CPU time 0.85 seconds
Started Apr 02 03:37:42 PM PDT 24
Finished Apr 02 03:37:44 PM PDT 24
Peak memory 203692 kb
Host smart-cf02680d-4148-4b91-b3d0-50385004feb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895278628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2895278628
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2542322137
Short name T89
Test name
Test status
Simulation time 1226767334 ps
CPU time 9.86 seconds
Started Apr 02 03:37:43 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 203824 kb
Host smart-d74bf6da-c14c-4179-8e1d-ec76280d8658
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542322137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2542322137
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.974783686
Short name T296
Test name
Test status
Simulation time 2812798996 ps
CPU time 75.83 seconds
Started Apr 02 03:37:39 PM PDT 24
Finished Apr 02 03:38:55 PM PDT 24
Peak memory 872088 kb
Host smart-433b24aa-4483-43ec-967d-896727ed920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974783686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.974783686
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.15271856
Short name T429
Test name
Test status
Simulation time 284122897 ps
CPU time 10.62 seconds
Started Apr 02 03:37:49 PM PDT 24
Finished Apr 02 03:38:00 PM PDT 24
Peak memory 203888 kb
Host smart-ea83bd9e-8b77-4516-be01-6e97a1d0930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15271856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.15271856
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.1074565560
Short name T818
Test name
Test status
Simulation time 64553728 ps
CPU time 0.67 seconds
Started Apr 02 03:37:45 PM PDT 24
Finished Apr 02 03:37:46 PM PDT 24
Peak memory 203592 kb
Host smart-e8785040-81d8-4b19-862d-720c5b438363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074565560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1074565560
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2320742454
Short name T860
Test name
Test status
Simulation time 12981384437 ps
CPU time 251.5 seconds
Started Apr 02 03:37:41 PM PDT 24
Finished Apr 02 03:41:53 PM PDT 24
Peak memory 969408 kb
Host smart-447a23c4-e64f-4052-87e1-30eea3c99c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320742454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2320742454
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.2356771210
Short name T250
Test name
Test status
Simulation time 1102702190 ps
CPU time 52.68 seconds
Started Apr 02 03:37:43 PM PDT 24
Finished Apr 02 03:38:36 PM PDT 24
Peak memory 330828 kb
Host smart-a8cbdd9a-9da7-485f-bbd2-297c79d65db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356771210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2356771210
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1325021033
Short name T830
Test name
Test status
Simulation time 637418626 ps
CPU time 3.42 seconds
Started Apr 02 03:37:48 PM PDT 24
Finished Apr 02 03:37:52 PM PDT 24
Peak memory 203844 kb
Host smart-3eac2672-7136-4a6f-bc86-040be66be163
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325021033 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1325021033
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.547111163
Short name T325
Test name
Test status
Simulation time 10028378036 ps
CPU time 72 seconds
Started Apr 02 03:37:44 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 559844 kb
Host smart-9fd4d316-0fb4-497d-bfc9-715f9994349b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547111163 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.547111163
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2015398654
Short name T475
Test name
Test status
Simulation time 10074635058 ps
CPU time 125.39 seconds
Started Apr 02 03:37:44 PM PDT 24
Finished Apr 02 03:39:50 PM PDT 24
Peak memory 745176 kb
Host smart-6523484d-8dae-48b6-8be7-d6d84d36d44b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015398654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2015398654
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.4246494178
Short name T671
Test name
Test status
Simulation time 568690735 ps
CPU time 3.03 seconds
Started Apr 02 03:37:48 PM PDT 24
Finished Apr 02 03:37:52 PM PDT 24
Peak memory 203796 kb
Host smart-0e6e6904-e561-451f-b5d5-26a078471110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246494178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.4246494178
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2020604079
Short name T56
Test name
Test status
Simulation time 1141017685 ps
CPU time 5.5 seconds
Started Apr 02 03:37:48 PM PDT 24
Finished Apr 02 03:37:54 PM PDT 24
Peak memory 203804 kb
Host smart-99b5d383-4eba-48ee-9f39-f07cebdc3604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020604079 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2020604079
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2219317468
Short name T686
Test name
Test status
Simulation time 1267721882 ps
CPU time 34.59 seconds
Started Apr 02 03:37:44 PM PDT 24
Finished Apr 02 03:38:18 PM PDT 24
Peak memory 203760 kb
Host smart-8d26c94d-7811-4bcf-8b7d-92bd010bea40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219317468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2219317468
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.534268463
Short name T270
Test name
Test status
Simulation time 564810583 ps
CPU time 22.29 seconds
Started Apr 02 03:37:48 PM PDT 24
Finished Apr 02 03:38:10 PM PDT 24
Peak memory 203840 kb
Host smart-77421052-fd66-4378-b006-aaf1019d82e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534268463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.534268463
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.416010838
Short name T592
Test name
Test status
Simulation time 6345329627 ps
CPU time 148.41 seconds
Started Apr 02 03:37:47 PM PDT 24
Finished Apr 02 03:40:16 PM PDT 24
Peak memory 1583416 kb
Host smart-b28b7a6a-9af9-49af-8930-b8c86f90a5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416010838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_t
arget_stretch.416010838
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3373861934
Short name T344
Test name
Test status
Simulation time 1572105764 ps
CPU time 6.64 seconds
Started Apr 02 03:37:46 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 212040 kb
Host smart-368e1322-0e4e-45a0-8758-a495b9b66157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373861934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3373861934
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.417215127
Short name T1021
Test name
Test status
Simulation time 26213354 ps
CPU time 0.63 seconds
Started Apr 02 03:37:56 PM PDT 24
Finished Apr 02 03:37:57 PM PDT 24
Peak memory 203632 kb
Host smart-7ece57eb-2be0-4323-87f7-9d9477464487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417215127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.417215127
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3044809225
Short name T463
Test name
Test status
Simulation time 249132327 ps
CPU time 1.8 seconds
Started Apr 02 03:37:52 PM PDT 24
Finished Apr 02 03:37:54 PM PDT 24
Peak memory 212000 kb
Host smart-9f26c37f-4670-49fb-a6f8-6e58f2eff26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044809225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3044809225
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2708305897
Short name T953
Test name
Test status
Simulation time 516451986 ps
CPU time 26.67 seconds
Started Apr 02 03:37:50 PM PDT 24
Finished Apr 02 03:38:17 PM PDT 24
Peak memory 317860 kb
Host smart-94225eb2-2121-4616-91a3-4e4a495480e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708305897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2708305897
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1850649507
Short name T631
Test name
Test status
Simulation time 2699815581 ps
CPU time 44.57 seconds
Started Apr 02 03:37:48 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 526664 kb
Host smart-1756a888-7a1b-45e1-a8da-5b35b0f80076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850649507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1850649507
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2150147913
Short name T372
Test name
Test status
Simulation time 389470077 ps
CPU time 0.96 seconds
Started Apr 02 03:37:49 PM PDT 24
Finished Apr 02 03:37:51 PM PDT 24
Peak memory 203728 kb
Host smart-4fdddee9-a28e-4210-ab91-a855b25b8ef8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150147913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2150147913
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3582913756
Short name T1147
Test name
Test status
Simulation time 100095759 ps
CPU time 5.81 seconds
Started Apr 02 03:37:49 PM PDT 24
Finished Apr 02 03:37:56 PM PDT 24
Peak memory 217012 kb
Host smart-ab03fd77-8cab-4e99-beac-96ae4ad7eb8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582913756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3582913756
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.4257583599
Short name T284
Test name
Test status
Simulation time 2145481765 ps
CPU time 8.47 seconds
Started Apr 02 03:37:52 PM PDT 24
Finished Apr 02 03:38:01 PM PDT 24
Peak memory 203788 kb
Host smart-279a5a4f-aad5-4fd7-a3ed-1930cbff1efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257583599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.4257583599
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.327829459
Short name T1077
Test name
Test status
Simulation time 10730855829 ps
CPU time 76.16 seconds
Started Apr 02 03:38:00 PM PDT 24
Finished Apr 02 03:39:17 PM PDT 24
Peak memory 411236 kb
Host smart-b862de7b-1326-466c-80b2-4e7d20b8709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327829459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.327829459
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2679846021
Short name T1132
Test name
Test status
Simulation time 45218653 ps
CPU time 0.67 seconds
Started Apr 02 03:37:49 PM PDT 24
Finished Apr 02 03:37:50 PM PDT 24
Peak memory 203536 kb
Host smart-0d109f36-f472-446b-85b8-13f2edfa646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679846021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2679846021
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.4143593366
Short name T824
Test name
Test status
Simulation time 5021495845 ps
CPU time 267.19 seconds
Started Apr 02 03:37:52 PM PDT 24
Finished Apr 02 03:42:19 PM PDT 24
Peak memory 783600 kb
Host smart-d3a03551-9b53-4369-ae5f-9f4ea7df6255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143593366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.4143593366
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1551902687
Short name T1041
Test name
Test status
Simulation time 6114204816 ps
CPU time 73.82 seconds
Started Apr 02 03:37:48 PM PDT 24
Finished Apr 02 03:39:02 PM PDT 24
Peak memory 406632 kb
Host smart-a893aacd-f274-4513-a346-536ff152b602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551902687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1551902687
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2422229845
Short name T852
Test name
Test status
Simulation time 3577154725 ps
CPU time 4.41 seconds
Started Apr 02 03:37:53 PM PDT 24
Finished Apr 02 03:37:57 PM PDT 24
Peak memory 203920 kb
Host smart-25c02cc7-1545-402e-b9ad-d85232d679df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422229845 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2422229845
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3199377077
Short name T432
Test name
Test status
Simulation time 10330436255 ps
CPU time 11.49 seconds
Started Apr 02 03:37:55 PM PDT 24
Finished Apr 02 03:38:07 PM PDT 24
Peak memory 303744 kb
Host smart-116c7df5-1ba7-477f-b0c9-59b19d533419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199377077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3199377077
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2541212404
Short name T64
Test name
Test status
Simulation time 10216424963 ps
CPU time 19.37 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:38:22 PM PDT 24
Peak memory 335180 kb
Host smart-7967d506-d4d8-4944-a17f-98d1d9a2f37c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541212404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2541212404
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1039215484
Short name T644
Test name
Test status
Simulation time 271767256 ps
CPU time 2.12 seconds
Started Apr 02 03:37:54 PM PDT 24
Finished Apr 02 03:37:56 PM PDT 24
Peak memory 203852 kb
Host smart-53199a36-2c9b-42fa-9663-47270198cf6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039215484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1039215484
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1346757430
Short name T557
Test name
Test status
Simulation time 6010044712 ps
CPU time 7.25 seconds
Started Apr 02 03:37:51 PM PDT 24
Finished Apr 02 03:37:59 PM PDT 24
Peak memory 211196 kb
Host smart-6bcd08bd-49a6-4f1a-a34b-9da88f72c699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346757430 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1346757430
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2213423663
Short name T854
Test name
Test status
Simulation time 1227431261 ps
CPU time 15.09 seconds
Started Apr 02 03:37:52 PM PDT 24
Finished Apr 02 03:38:07 PM PDT 24
Peak memory 203808 kb
Host smart-4268634f-feb9-4ce8-8926-96067d4aec6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213423663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2213423663
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3163308783
Short name T608
Test name
Test status
Simulation time 301812701 ps
CPU time 12.33 seconds
Started Apr 02 03:37:52 PM PDT 24
Finished Apr 02 03:38:05 PM PDT 24
Peak memory 203772 kb
Host smart-4f7124aa-c3a1-4929-b770-02043f326a2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163308783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3163308783
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1759235096
Short name T781
Test name
Test status
Simulation time 42455609932 ps
CPU time 1412.4 seconds
Started Apr 02 03:38:00 PM PDT 24
Finished Apr 02 04:01:33 PM PDT 24
Peak memory 4908540 kb
Host smart-6951a38f-042f-4d77-88cb-18d8279e1570
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759235096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1759235096
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.133968725
Short name T353
Test name
Test status
Simulation time 6690008328 ps
CPU time 7.76 seconds
Started Apr 02 03:37:52 PM PDT 24
Finished Apr 02 03:38:00 PM PDT 24
Peak memory 212052 kb
Host smart-5766f442-e23a-453c-97cf-14626b9f42e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133968725 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.133968725
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3087993073
Short name T646
Test name
Test status
Simulation time 16834810 ps
CPU time 0.64 seconds
Started Apr 02 03:38:05 PM PDT 24
Finished Apr 02 03:38:06 PM PDT 24
Peak memory 203672 kb
Host smart-7191d15e-1891-4e6f-b530-a2a6aa4fc8d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087993073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3087993073
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1777388694
Short name T460
Test name
Test status
Simulation time 293058295 ps
CPU time 1.9 seconds
Started Apr 02 03:37:55 PM PDT 24
Finished Apr 02 03:37:57 PM PDT 24
Peak memory 212016 kb
Host smart-6eb05957-87fd-4128-b0f8-f2373502a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777388694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1777388694
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.522673860
Short name T318
Test name
Test status
Simulation time 2746401481 ps
CPU time 13.88 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:38:16 PM PDT 24
Peak memory 252060 kb
Host smart-bfcf8965-d940-40bf-b5c8-5f9689191b8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522673860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.522673860
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3385845739
Short name T1097
Test name
Test status
Simulation time 20785683800 ps
CPU time 136.23 seconds
Started Apr 02 03:38:07 PM PDT 24
Finished Apr 02 03:40:23 PM PDT 24
Peak memory 671796 kb
Host smart-bbe0257c-0407-43ba-b56a-79268a53f25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385845739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3385845739
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1157076468
Short name T1018
Test name
Test status
Simulation time 1155406048 ps
CPU time 72.06 seconds
Started Apr 02 03:37:57 PM PDT 24
Finished Apr 02 03:39:10 PM PDT 24
Peak memory 448200 kb
Host smart-70ba07ea-2a9e-4c12-ab29-52d435c59a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157076468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1157076468
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.917095676
Short name T1170
Test name
Test status
Simulation time 548330362 ps
CPU time 1.05 seconds
Started Apr 02 03:37:57 PM PDT 24
Finished Apr 02 03:37:59 PM PDT 24
Peak memory 203828 kb
Host smart-f5dc80f5-898f-494e-8fae-b96b3ad973bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917095676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fm
t.917095676
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1928304985
Short name T1108
Test name
Test status
Simulation time 362200429 ps
CPU time 5.03 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:38:09 PM PDT 24
Peak memory 236188 kb
Host smart-503bc342-35d1-455a-8c72-e78e7bd814ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928304985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1928304985
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3496098196
Short name T716
Test name
Test status
Simulation time 14695021479 ps
CPU time 123.85 seconds
Started Apr 02 03:37:57 PM PDT 24
Finished Apr 02 03:40:02 PM PDT 24
Peak memory 1279004 kb
Host smart-f7e61440-deee-425c-a4b0-f4b670fcf51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496098196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3496098196
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.880139272
Short name T909
Test name
Test status
Simulation time 165379285 ps
CPU time 2.86 seconds
Started Apr 02 03:38:05 PM PDT 24
Finished Apr 02 03:38:08 PM PDT 24
Peak memory 203800 kb
Host smart-f28e6884-632f-4c85-ae00-b2a030439742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880139272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.880139272
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3275562256
Short name T163
Test name
Test status
Simulation time 5023494251 ps
CPU time 17.78 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:38:20 PM PDT 24
Peak memory 298148 kb
Host smart-e0d74bc5-e6fc-4926-ad5c-842baabc40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275562256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3275562256
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.427934399
Short name T329
Test name
Test status
Simulation time 80136731 ps
CPU time 0.69 seconds
Started Apr 02 03:37:57 PM PDT 24
Finished Apr 02 03:37:59 PM PDT 24
Peak memory 203592 kb
Host smart-208000d9-888f-4c4c-9801-1edef06730ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427934399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.427934399
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2139138927
Short name T586
Test name
Test status
Simulation time 2547220030 ps
CPU time 104.8 seconds
Started Apr 02 03:38:04 PM PDT 24
Finished Apr 02 03:39:49 PM PDT 24
Peak memory 219620 kb
Host smart-3c57d0df-62ec-4e0a-9c1b-34885bcc83e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139138927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2139138927
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1350057426
Short name T505
Test name
Test status
Simulation time 3142720122 ps
CPU time 39.98 seconds
Started Apr 02 03:37:57 PM PDT 24
Finished Apr 02 03:38:38 PM PDT 24
Peak memory 466684 kb
Host smart-6d05fc9e-7f91-4e0e-bfde-31db13687690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350057426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1350057426
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3654281296
Short name T929
Test name
Test status
Simulation time 3033789500 ps
CPU time 3.93 seconds
Started Apr 02 03:38:05 PM PDT 24
Finished Apr 02 03:38:09 PM PDT 24
Peak memory 203856 kb
Host smart-63836a5d-d398-403f-8b95-8de4cefa7c49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654281296 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3654281296
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2203091035
Short name T324
Test name
Test status
Simulation time 10142504385 ps
CPU time 78.3 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 603300 kb
Host smart-41338df2-7f53-4130-a275-705b0406dc41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203091035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2203091035
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3705493730
Short name T1195
Test name
Test status
Simulation time 11003081376 ps
CPU time 8.01 seconds
Started Apr 02 03:37:57 PM PDT 24
Finished Apr 02 03:38:06 PM PDT 24
Peak memory 279860 kb
Host smart-02d0e9d2-24c6-4332-a23c-0feb0f242412
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705493730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3705493730
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1559438002
Short name T314
Test name
Test status
Simulation time 6848767831 ps
CPU time 2.84 seconds
Started Apr 02 03:38:07 PM PDT 24
Finished Apr 02 03:38:12 PM PDT 24
Peak memory 203840 kb
Host smart-336c6f4a-d83b-4c61-bf7a-189b03f65625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559438002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1559438002
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.1090390262
Short name T271
Test name
Test status
Simulation time 885790828 ps
CPU time 3.55 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:38:06 PM PDT 24
Peak memory 203840 kb
Host smart-fffa8a3e-aabc-4a92-8a4d-bd348bba6b77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090390262 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.1090390262
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.356946289
Short name T1028
Test name
Test status
Simulation time 5977966802 ps
CPU time 31.96 seconds
Started Apr 02 03:38:05 PM PDT 24
Finished Apr 02 03:38:37 PM PDT 24
Peak memory 203852 kb
Host smart-7eefd725-b7fe-420d-a42d-dc22bc4fdc13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356946289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.356946289
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.111714882
Short name T244
Test name
Test status
Simulation time 965445600 ps
CPU time 9.01 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:18 PM PDT 24
Peak memory 205028 kb
Host smart-70fc7ea6-8dff-46e0-b52c-f468ce4409db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111714882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.111714882
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.748300260
Short name T820
Test name
Test status
Simulation time 12127469724 ps
CPU time 6.85 seconds
Started Apr 02 03:38:04 PM PDT 24
Finished Apr 02 03:38:11 PM PDT 24
Peak memory 203876 kb
Host smart-b5460e79-cd76-4e13-ac7e-1120a719ad3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748300260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_wr.748300260
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3065519214
Short name T1188
Test name
Test status
Simulation time 28705344614 ps
CPU time 218.37 seconds
Started Apr 02 03:38:01 PM PDT 24
Finished Apr 02 03:41:39 PM PDT 24
Peak memory 1593480 kb
Host smart-61ea9a85-f9a7-4383-b5aa-71eefb530e40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065519214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3065519214
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3902515774
Short name T950
Test name
Test status
Simulation time 2693717311 ps
CPU time 7.05 seconds
Started Apr 02 03:37:57 PM PDT 24
Finished Apr 02 03:38:05 PM PDT 24
Peak memory 220092 kb
Host smart-f1094936-bbdf-4742-a429-3e2a80c14217
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902515774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3902515774
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1261906875
Short name T5
Test name
Test status
Simulation time 38460912 ps
CPU time 0.61 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:44 PM PDT 24
Peak memory 203668 kb
Host smart-25578abd-3dfc-43d0-bccd-7667a8d85c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261906875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1261906875
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3234823506
Short name T487
Test name
Test status
Simulation time 279369139 ps
CPU time 1.24 seconds
Started Apr 02 03:36:34 PM PDT 24
Finished Apr 02 03:36:35 PM PDT 24
Peak memory 212044 kb
Host smart-560514c0-959a-40c5-94fa-6adeb518a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234823506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3234823506
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2536588019
Short name T1083
Test name
Test status
Simulation time 705926816 ps
CPU time 3.92 seconds
Started Apr 02 03:36:34 PM PDT 24
Finished Apr 02 03:36:38 PM PDT 24
Peak memory 234876 kb
Host smart-90de8d3a-53aa-4f50-a301-0e079ccadeb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536588019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2536588019
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.418883598
Short name T419
Test name
Test status
Simulation time 7232846499 ps
CPU time 47.75 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:37:23 PM PDT 24
Peak memory 483244 kb
Host smart-1ab50502-5376-4582-8cc4-458415996792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418883598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.418883598
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2134410977
Short name T422
Test name
Test status
Simulation time 2727981184 ps
CPU time 40.96 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:37:16 PM PDT 24
Peak memory 465048 kb
Host smart-2fd1fff7-fb30-400d-a360-bf6bdec934a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134410977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2134410977
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1058957003
Short name T1126
Test name
Test status
Simulation time 220078348 ps
CPU time 1.03 seconds
Started Apr 02 03:36:29 PM PDT 24
Finished Apr 02 03:36:30 PM PDT 24
Peak memory 203704 kb
Host smart-758e01a8-11f0-4d73-be1d-b4124585020b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058957003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1058957003
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3813716208
Short name T564
Test name
Test status
Simulation time 569851826 ps
CPU time 3.27 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:36:38 PM PDT 24
Peak memory 224404 kb
Host smart-fcb6e6be-ac67-428e-a523-bceed715f9f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813716208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3813716208
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2863229064
Short name T85
Test name
Test status
Simulation time 25002804889 ps
CPU time 56.56 seconds
Started Apr 02 03:36:32 PM PDT 24
Finished Apr 02 03:37:28 PM PDT 24
Peak memory 736092 kb
Host smart-3ef085ed-7552-4d6c-93f7-37b393f01357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863229064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2863229064
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.338893319
Short name T579
Test name
Test status
Simulation time 541032355 ps
CPU time 6.09 seconds
Started Apr 02 03:36:38 PM PDT 24
Finished Apr 02 03:36:44 PM PDT 24
Peak memory 203820 kb
Host smart-683865d5-b45a-48c8-bd92-ad7ffb0c63c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338893319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.338893319
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2690636901
Short name T405
Test name
Test status
Simulation time 2961491920 ps
CPU time 71.12 seconds
Started Apr 02 03:36:33 PM PDT 24
Finished Apr 02 03:37:44 PM PDT 24
Peak memory 378304 kb
Host smart-1c33fe3a-97a4-4af0-9cdd-0e27474c11ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690636901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2690636901
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.2835932633
Short name T913
Test name
Test status
Simulation time 27668080 ps
CPU time 0.64 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:36 PM PDT 24
Peak memory 203536 kb
Host smart-72c013bd-db03-46c5-85eb-c1b04dc687e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835932633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2835932633
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1555711017
Short name T969
Test name
Test status
Simulation time 3165072507 ps
CPU time 44.15 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:37:20 PM PDT 24
Peak memory 387208 kb
Host smart-04b0c25f-fdbc-4c6f-ac89-ee6ff4b8ecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555711017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1555711017
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3994428886
Short name T810
Test name
Test status
Simulation time 5558057620 ps
CPU time 66.88 seconds
Started Apr 02 03:36:32 PM PDT 24
Finished Apr 02 03:37:39 PM PDT 24
Peak memory 303376 kb
Host smart-e36da280-ff26-4210-9704-0ced26e81abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994428886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3994428886
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3340947796
Short name T101
Test name
Test status
Simulation time 73180220 ps
CPU time 0.83 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:36:36 PM PDT 24
Peak memory 221256 kb
Host smart-ba19085c-945e-4c30-8318-d4986b9c0391
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340947796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3340947796
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2482331660
Short name T559
Test name
Test status
Simulation time 1876045989 ps
CPU time 2.82 seconds
Started Apr 02 03:36:49 PM PDT 24
Finished Apr 02 03:36:53 PM PDT 24
Peak memory 203796 kb
Host smart-4456e891-432a-410d-807a-703f720ecb9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482331660 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2482331660
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3186698366
Short name T195
Test name
Test status
Simulation time 10906142269 ps
CPU time 10.85 seconds
Started Apr 02 03:36:38 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 266936 kb
Host smart-443d285b-633f-4d6d-8f29-1926b8db7530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186698366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3186698366
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.4170421397
Short name T761
Test name
Test status
Simulation time 10818353464 ps
CPU time 6.28 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:36:50 PM PDT 24
Peak memory 257872 kb
Host smart-7c876e26-c988-4a5f-ad6c-5e3f7c175273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170421397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.4170421397
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2851392062
Short name T546
Test name
Test status
Simulation time 457472159 ps
CPU time 2.64 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 203840 kb
Host smart-42af800e-acc0-4318-b6c5-6bf6a2deb6c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851392062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2851392062
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1953399978
Short name T521
Test name
Test status
Simulation time 696841974 ps
CPU time 3.84 seconds
Started Apr 02 03:36:45 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 203816 kb
Host smart-f8f8957a-9180-4c57-97e5-9a952ccf1787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953399978 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1953399978
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2889984123
Short name T1069
Test name
Test status
Simulation time 3202240813 ps
CPU time 13.48 seconds
Started Apr 02 03:36:34 PM PDT 24
Finished Apr 02 03:36:48 PM PDT 24
Peak memory 203836 kb
Host smart-a6d638f7-907c-4899-971b-24e0089632d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889984123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2889984123
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3762749595
Short name T339
Test name
Test status
Simulation time 5610561343 ps
CPU time 23.23 seconds
Started Apr 02 03:36:45 PM PDT 24
Finished Apr 02 03:37:08 PM PDT 24
Peak memory 229308 kb
Host smart-de22a46f-17fa-4716-b86c-d22045eeef46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762749595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3762749595
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.317648548
Short name T430
Test name
Test status
Simulation time 11478169171 ps
CPU time 13.26 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 203856 kb
Host smart-1d60ba81-f753-4222-acbb-0321a71fbc2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317648548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.317648548
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.548323193
Short name T1166
Test name
Test status
Simulation time 4733881131 ps
CPU time 6.6 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:50 PM PDT 24
Peak memory 203944 kb
Host smart-17cf8cd5-ccca-468d-ab7d-99b13170389b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548323193 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.548323193
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2883806114
Short name T1130
Test name
Test status
Simulation time 54116381 ps
CPU time 0.6 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:10 PM PDT 24
Peak memory 203732 kb
Host smart-11e2d218-832c-4ffc-9887-0d1480e7e384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883806114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2883806114
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.658532138
Short name T1051
Test name
Test status
Simulation time 245603530 ps
CPU time 1.62 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:38:04 PM PDT 24
Peak memory 211984 kb
Host smart-52fdb4a2-892f-4293-bd7d-51db46f2497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658532138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.658532138
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2736827679
Short name T474
Test name
Test status
Simulation time 1050668096 ps
CPU time 6 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:38:10 PM PDT 24
Peak memory 257524 kb
Host smart-f15ef4dc-dc1a-425a-9a5c-b24f0150245f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736827679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2736827679
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1545512937
Short name T434
Test name
Test status
Simulation time 4973801568 ps
CPU time 34.93 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:38:51 PM PDT 24
Peak memory 424980 kb
Host smart-e31c7790-6261-4e0b-b505-47fa37bbb2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545512937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1545512937
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3582347934
Short name T1111
Test name
Test status
Simulation time 3162556939 ps
CPU time 107.39 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:39:50 PM PDT 24
Peak memory 580192 kb
Host smart-1548225a-2282-439c-9560-c5a04aca5f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582347934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3582347934
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1190796558
Short name T412
Test name
Test status
Simulation time 375109126 ps
CPU time 1.01 seconds
Started Apr 02 03:38:01 PM PDT 24
Finished Apr 02 03:38:03 PM PDT 24
Peak memory 203744 kb
Host smart-f417701c-5f24-4055-830e-7a0bf4563f5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190796558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1190796558
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1688726266
Short name T888
Test name
Test status
Simulation time 445163233 ps
CPU time 3.4 seconds
Started Apr 02 03:38:14 PM PDT 24
Finished Apr 02 03:38:17 PM PDT 24
Peak memory 222220 kb
Host smart-45c9fb47-1a7e-4daf-a046-202d9fed4b6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688726266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1688726266
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1180556067
Short name T718
Test name
Test status
Simulation time 3276119509 ps
CPU time 216.87 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:41:41 PM PDT 24
Peak memory 953412 kb
Host smart-047840be-9c95-444f-b4e6-266aa36dc9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180556067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1180556067
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.1194340611
Short name T28
Test name
Test status
Simulation time 541643379 ps
CPU time 22.02 seconds
Started Apr 02 03:38:10 PM PDT 24
Finished Apr 02 03:38:32 PM PDT 24
Peak memory 203780 kb
Host smart-4ae3d658-6772-477d-ae2f-c0efebfb7dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194340611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1194340611
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3896845561
Short name T1055
Test name
Test status
Simulation time 2037695182 ps
CPU time 44.7 seconds
Started Apr 02 03:38:05 PM PDT 24
Finished Apr 02 03:38:50 PM PDT 24
Peak memory 534564 kb
Host smart-e622b3de-19d0-4d07-bb2b-0baf6d2eec5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896845561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3896845561
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.790098438
Short name T479
Test name
Test status
Simulation time 28218175 ps
CPU time 0.67 seconds
Started Apr 02 03:38:04 PM PDT 24
Finished Apr 02 03:38:05 PM PDT 24
Peak memory 203560 kb
Host smart-696c4dd3-c897-45d2-b2e6-995c6dcc61fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790098438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.790098438
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2313420704
Short name T387
Test name
Test status
Simulation time 4284727692 ps
CPU time 51.65 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:38:55 PM PDT 24
Peak memory 315768 kb
Host smart-7a112e79-f797-4107-b4f9-6893e820eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313420704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2313420704
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2636464307
Short name T926
Test name
Test status
Simulation time 3757884066 ps
CPU time 5.14 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:38:09 PM PDT 24
Peak memory 212148 kb
Host smart-927b9f7e-7c85-488d-bd7a-5b7cf535e98a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636464307 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2636464307
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.631544160
Short name T69
Test name
Test status
Simulation time 10070895193 ps
CPU time 74.54 seconds
Started Apr 02 03:38:05 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 603388 kb
Host smart-7636bff2-9b50-48f6-986f-a5d23322bdbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631544160 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.631544160
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2328317436
Short name T731
Test name
Test status
Simulation time 10099191007 ps
CPU time 85.53 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:39:28 PM PDT 24
Peak memory 685976 kb
Host smart-a18737c2-5f06-4fb9-ae04-6e955a612625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328317436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2328317436
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3791647292
Short name T381
Test name
Test status
Simulation time 728650038 ps
CPU time 2.43 seconds
Started Apr 02 03:38:05 PM PDT 24
Finished Apr 02 03:38:08 PM PDT 24
Peak memory 203812 kb
Host smart-1cf0e5c0-6c7d-478c-b107-ef1609ee6c47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791647292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3791647292
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.321164795
Short name T104
Test name
Test status
Simulation time 1295753138 ps
CPU time 6.03 seconds
Started Apr 02 03:38:10 PM PDT 24
Finished Apr 02 03:38:16 PM PDT 24
Peak memory 214920 kb
Host smart-fdef930f-daf8-4258-bd98-5437fac7ccb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321164795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.321164795
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3929457424
Short name T465
Test name
Test status
Simulation time 5878226407 ps
CPU time 4.72 seconds
Started Apr 02 03:38:10 PM PDT 24
Finished Apr 02 03:38:15 PM PDT 24
Peak memory 203836 kb
Host smart-afaba3ae-8cb2-4ba9-bb6d-051f1d518a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929457424 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3929457424
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1504596647
Short name T937
Test name
Test status
Simulation time 2465694217 ps
CPU time 49.75 seconds
Started Apr 02 03:38:06 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 203872 kb
Host smart-38537d99-1c0b-4fe1-971d-a46619d630b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504596647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1504596647
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1556438106
Short name T536
Test name
Test status
Simulation time 7624778794 ps
CPU time 23.98 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:38:28 PM PDT 24
Peak memory 222036 kb
Host smart-75943552-c1c2-4af4-9dba-67373d27a612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556438106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1556438106
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3206729618
Short name T301
Test name
Test status
Simulation time 4722546789 ps
CPU time 6.96 seconds
Started Apr 02 03:38:03 PM PDT 24
Finished Apr 02 03:38:10 PM PDT 24
Peak memory 209944 kb
Host smart-186ecaed-6e58-4ecb-8ac8-100675528645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206729618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3206729618
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.4193087709
Short name T652
Test name
Test status
Simulation time 12141576500 ps
CPU time 4.98 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:38:07 PM PDT 24
Peak memory 206744 kb
Host smart-abe9a359-e402-4f3b-89cb-6b858738516d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193087709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.4193087709
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1913012587
Short name T612
Test name
Test status
Simulation time 30925755 ps
CPU time 0.62 seconds
Started Apr 02 03:38:13 PM PDT 24
Finished Apr 02 03:38:14 PM PDT 24
Peak memory 203632 kb
Host smart-c82c91d8-4e7b-4c1b-a88f-d16c3fca4d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913012587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1913012587
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2964284542
Short name T436
Test name
Test status
Simulation time 383819347 ps
CPU time 1.93 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:38:18 PM PDT 24
Peak memory 212092 kb
Host smart-9d4c7874-7cfc-4df4-8976-a2cba1f9c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964284542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2964284542
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.4109919244
Short name T495
Test name
Test status
Simulation time 856338527 ps
CPU time 4.46 seconds
Started Apr 02 03:38:06 PM PDT 24
Finished Apr 02 03:38:11 PM PDT 24
Peak memory 251256 kb
Host smart-28947f4c-7427-4621-9ff2-251a28fe76b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109919244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.4109919244
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.627368613
Short name T1046
Test name
Test status
Simulation time 1984111506 ps
CPU time 73.18 seconds
Started Apr 02 03:38:04 PM PDT 24
Finished Apr 02 03:39:18 PM PDT 24
Peak memory 692368 kb
Host smart-b84cf355-60b2-460c-be0a-88ae39ac7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627368613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.627368613
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3058825144
Short name T299
Test name
Test status
Simulation time 10513826044 ps
CPU time 139.66 seconds
Started Apr 02 03:38:08 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 617704 kb
Host smart-bf78ab2a-1420-4309-bfa7-cde14f518d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058825144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3058825144
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3233592175
Short name T1096
Test name
Test status
Simulation time 489046579 ps
CPU time 0.91 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:10 PM PDT 24
Peak memory 203684 kb
Host smart-600fb175-8cfb-425f-91be-b8b562385e44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233592175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3233592175
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2108211214
Short name T537
Test name
Test status
Simulation time 132176564 ps
CPU time 7.21 seconds
Started Apr 02 03:38:20 PM PDT 24
Finished Apr 02 03:38:28 PM PDT 24
Peak memory 203852 kb
Host smart-97d9ad0b-4218-48e2-af9e-c60095bde50d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108211214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2108211214
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3145683644
Short name T887
Test name
Test status
Simulation time 6802418158 ps
CPU time 101.47 seconds
Started Apr 02 03:38:08 PM PDT 24
Finished Apr 02 03:39:50 PM PDT 24
Peak memory 1014556 kb
Host smart-18a705b8-9f67-4377-9390-c8742bd35125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145683644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3145683644
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2759356295
Short name T940
Test name
Test status
Simulation time 797931814 ps
CPU time 2.72 seconds
Started Apr 02 03:38:15 PM PDT 24
Finished Apr 02 03:38:18 PM PDT 24
Peak memory 203888 kb
Host smart-d2944947-40f4-4bc2-b049-10bb3951cca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759356295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2759356295
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.1748276008
Short name T637
Test name
Test status
Simulation time 5498310718 ps
CPU time 60.16 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:39:19 PM PDT 24
Peak memory 293232 kb
Host smart-c57f2347-4970-4296-8a22-ec15e82f5803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748276008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1748276008
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2431148652
Short name T845
Test name
Test status
Simulation time 21157877 ps
CPU time 0.62 seconds
Started Apr 02 03:38:15 PM PDT 24
Finished Apr 02 03:38:15 PM PDT 24
Peak memory 203616 kb
Host smart-c40fded4-aeb3-464e-a11e-45bc61a399e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431148652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2431148652
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.490829772
Short name T907
Test name
Test status
Simulation time 4953092651 ps
CPU time 25.42 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:34 PM PDT 24
Peak memory 349556 kb
Host smart-9998d6eb-d144-40be-974b-662e10b82901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490829772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.490829772
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3228887424
Short name T107
Test name
Test status
Simulation time 3826220649 ps
CPU time 46.95 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 478724 kb
Host smart-302b3b9a-ff18-47dd-ba39-06dde372ec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228887424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3228887424
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.4011943819
Short name T2
Test name
Test status
Simulation time 1218133272 ps
CPU time 3.17 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:38:22 PM PDT 24
Peak memory 203808 kb
Host smart-12d164e8-2c88-4faf-8bdf-2601ba8f94f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011943819 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.4011943819
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3604225142
Short name T1065
Test name
Test status
Simulation time 10297309424 ps
CPU time 32.92 seconds
Started Apr 02 03:38:12 PM PDT 24
Finished Apr 02 03:38:45 PM PDT 24
Peak memory 401748 kb
Host smart-7c1f4690-0f9b-42fd-ac77-032342c914e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604225142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3604225142
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1485456129
Short name T1044
Test name
Test status
Simulation time 10187482612 ps
CPU time 36.97 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 469056 kb
Host smart-b2e46765-e846-4394-b10d-ebb620775059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485456129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1485456129
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1504648260
Short name T1140
Test name
Test status
Simulation time 1141927807 ps
CPU time 1.95 seconds
Started Apr 02 03:38:14 PM PDT 24
Finished Apr 02 03:38:16 PM PDT 24
Peak memory 203800 kb
Host smart-00043641-ad68-4199-94e3-d1a8dec4296f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504648260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1504648260
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.772904952
Short name T401
Test name
Test status
Simulation time 3392807567 ps
CPU time 4.75 seconds
Started Apr 02 03:38:10 PM PDT 24
Finished Apr 02 03:38:15 PM PDT 24
Peak memory 203836 kb
Host smart-b24fc673-d2fc-4e0d-8462-cf0b625d7b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772904952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.772904952
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.2990411184
Short name T819
Test name
Test status
Simulation time 1824550369 ps
CPU time 35.1 seconds
Started Apr 02 03:38:02 PM PDT 24
Finished Apr 02 03:38:37 PM PDT 24
Peak memory 203788 kb
Host smart-bdaca341-d0a9-4c0e-8578-cc257b211cb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990411184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.2990411184
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2278830877
Short name T554
Test name
Test status
Simulation time 8657655921 ps
CPU time 25.71 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:35 PM PDT 24
Peak memory 228396 kb
Host smart-dddf669e-2cbc-4ed6-9e98-e286a6da5bf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278830877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2278830877
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.745295810
Short name T967
Test name
Test status
Simulation time 16313771713 ps
CPU time 4.42 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:14 PM PDT 24
Peak memory 203788 kb
Host smart-74055767-5261-4e66-aef4-534a152f642c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745295810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.745295810
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3989528180
Short name T776
Test name
Test status
Simulation time 10901998117 ps
CPU time 1188.44 seconds
Started Apr 02 03:38:10 PM PDT 24
Finished Apr 02 03:57:59 PM PDT 24
Peak memory 2765812 kb
Host smart-8dccaf09-7c73-40be-a4a2-dda926aa579c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989528180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3989528180
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2439885064
Short name T286
Test name
Test status
Simulation time 21959107144 ps
CPU time 5.72 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:15 PM PDT 24
Peak memory 212064 kb
Host smart-6ec3df91-43b4-4f4b-89a7-1c9b47f5e399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439885064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2439885064
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2119936783
Short name T1005
Test name
Test status
Simulation time 24557157 ps
CPU time 0.64 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:38:17 PM PDT 24
Peak memory 203712 kb
Host smart-1cb46630-5e2e-41b4-bd4e-c78453fb37e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119936783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2119936783
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.331792529
Short name T726
Test name
Test status
Simulation time 251302627 ps
CPU time 1.39 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:38:18 PM PDT 24
Peak memory 220284 kb
Host smart-6ae4fb69-03bf-419a-97ee-853d1037a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331792529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.331792529
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1776599017
Short name T527
Test name
Test status
Simulation time 595211643 ps
CPU time 14.06 seconds
Started Apr 02 03:38:06 PM PDT 24
Finished Apr 02 03:38:21 PM PDT 24
Peak memory 253052 kb
Host smart-acedd57b-5377-4e9e-af92-d49106dfd4f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776599017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1776599017
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2585064381
Short name T802
Test name
Test status
Simulation time 1936009894 ps
CPU time 50.64 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:39:00 PM PDT 24
Peak memory 373776 kb
Host smart-657cd0a4-04eb-4fe9-b4d3-9354bf22b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585064381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2585064381
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2117119999
Short name T782
Test name
Test status
Simulation time 3063525709 ps
CPU time 45.31 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:55 PM PDT 24
Peak memory 482932 kb
Host smart-e5b543a2-0719-4570-9588-ea75fbe7c98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117119999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2117119999
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3954187236
Short name T1037
Test name
Test status
Simulation time 146160235 ps
CPU time 1.12 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:10 PM PDT 24
Peak memory 203744 kb
Host smart-c5514bd6-0dee-4b36-b95a-380f20975644
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954187236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3954187236
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1538449721
Short name T1048
Test name
Test status
Simulation time 195525761 ps
CPU time 5.55 seconds
Started Apr 02 03:38:10 PM PDT 24
Finished Apr 02 03:38:16 PM PDT 24
Peak memory 239420 kb
Host smart-9eba1811-f848-4a1c-866b-a335efee9b1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538449721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1538449721
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2037778766
Short name T154
Test name
Test status
Simulation time 4445509372 ps
CPU time 124.64 seconds
Started Apr 02 03:38:11 PM PDT 24
Finished Apr 02 03:40:16 PM PDT 24
Peak memory 1307804 kb
Host smart-3089ad1e-84ba-4afb-8997-f092f674c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037778766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2037778766
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2490204896
Short name T448
Test name
Test status
Simulation time 350278599 ps
CPU time 5.57 seconds
Started Apr 02 03:38:20 PM PDT 24
Finished Apr 02 03:38:26 PM PDT 24
Peak memory 203828 kb
Host smart-9c54cb89-3044-4cea-9a07-20fb2e8d5b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490204896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2490204896
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.306625311
Short name T1047
Test name
Test status
Simulation time 10102371041 ps
CPU time 82.37 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:39:42 PM PDT 24
Peak memory 404204 kb
Host smart-87bb2e4b-253b-4392-9517-54622499d7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306625311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.306625311
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.248010410
Short name T1105
Test name
Test status
Simulation time 88388974 ps
CPU time 0.7 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:38:19 PM PDT 24
Peak memory 203604 kb
Host smart-f9739387-71f4-4dae-8b85-0c744866140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248010410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.248010410
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1750258839
Short name T88
Test name
Test status
Simulation time 5267220282 ps
CPU time 31.39 seconds
Started Apr 02 03:38:11 PM PDT 24
Finished Apr 02 03:38:43 PM PDT 24
Peak memory 424504 kb
Host smart-1fe4fbf6-4f6f-4556-b5d0-891d4aa71e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750258839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1750258839
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.4045829093
Short name T1125
Test name
Test status
Simulation time 2671104115 ps
CPU time 34.06 seconds
Started Apr 02 03:38:09 PM PDT 24
Finished Apr 02 03:38:43 PM PDT 24
Peak memory 446692 kb
Host smart-c099be59-a571-4f4c-a41b-f6e220150497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045829093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.4045829093
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.157695836
Short name T111
Test name
Test status
Simulation time 1642077107 ps
CPU time 3.86 seconds
Started Apr 02 03:38:18 PM PDT 24
Finished Apr 02 03:38:22 PM PDT 24
Peak memory 211996 kb
Host smart-f668a731-1355-4064-ae90-dd77a661165b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157695836 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.157695836
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.469779223
Short name T971
Test name
Test status
Simulation time 10804127677 ps
CPU time 7.84 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:38:27 PM PDT 24
Peak memory 254088 kb
Host smart-55e32ae0-24b0-4c3e-ac16-6a4f3da3dce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469779223 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_acq.469779223
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2749795798
Short name T725
Test name
Test status
Simulation time 10104601619 ps
CPU time 94.36 seconds
Started Apr 02 03:38:14 PM PDT 24
Finished Apr 02 03:39:48 PM PDT 24
Peak memory 700028 kb
Host smart-3ca505f1-7548-4f71-868f-0ad1d8ac19ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749795798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2749795798
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.3082768673
Short name T935
Test name
Test status
Simulation time 1709623176 ps
CPU time 2.44 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:38:19 PM PDT 24
Peak memory 203700 kb
Host smart-6e071f55-12d6-4165-9b3f-95286e6a3bdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082768673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.3082768673
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2899829150
Short name T777
Test name
Test status
Simulation time 934683949 ps
CPU time 4.94 seconds
Started Apr 02 03:38:14 PM PDT 24
Finished Apr 02 03:38:19 PM PDT 24
Peak memory 205516 kb
Host smart-0ceafb46-4e1c-49b0-8659-58588ccd97a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899829150 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2899829150
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.694960203
Short name T598
Test name
Test status
Simulation time 7865611280 ps
CPU time 5.49 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:38:22 PM PDT 24
Peak memory 203820 kb
Host smart-64e24b81-d29f-4b41-947b-c637047bc54f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694960203 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.694960203
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.343292265
Short name T83
Test name
Test status
Simulation time 3575936212 ps
CPU time 31.56 seconds
Started Apr 02 03:38:10 PM PDT 24
Finished Apr 02 03:38:42 PM PDT 24
Peak memory 203764 kb
Host smart-00f5c09a-3577-421c-838a-4fb2e4a264c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343292265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.343292265
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.36993006
Short name T517
Test name
Test status
Simulation time 300380444 ps
CPU time 11.25 seconds
Started Apr 02 03:38:15 PM PDT 24
Finished Apr 02 03:38:27 PM PDT 24
Peak memory 203792 kb
Host smart-03fd829d-4b7a-4b6c-a068-0aea53e59bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stress_rd.36993006
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.47323900
Short name T728
Test name
Test status
Simulation time 24142427839 ps
CPU time 501.6 seconds
Started Apr 02 03:38:21 PM PDT 24
Finished Apr 02 03:46:42 PM PDT 24
Peak memory 1551796 kb
Host smart-2f81f663-81c5-498d-aa5a-f95379b45ac7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47323900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_stretch.47323900
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.237723986
Short name T1043
Test name
Test status
Simulation time 4965308779 ps
CPU time 6.06 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:38:25 PM PDT 24
Peak memory 203924 kb
Host smart-d4131c5f-e50d-4bb7-81db-f2d24f87d188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237723986 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.237723986
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2733193094
Short name T373
Test name
Test status
Simulation time 32493344 ps
CPU time 0.63 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:32 PM PDT 24
Peak memory 203524 kb
Host smart-685f954e-4800-4ba2-9996-14e0c0754ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733193094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2733193094
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.366388268
Short name T53
Test name
Test status
Simulation time 202467586 ps
CPU time 1.72 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 215656 kb
Host smart-ec62c698-0f21-4638-814e-b2694f33b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366388268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.366388268
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.1857145093
Short name T472
Test name
Test status
Simulation time 1539132366 ps
CPU time 19.83 seconds
Started Apr 02 03:38:15 PM PDT 24
Finished Apr 02 03:38:35 PM PDT 24
Peak memory 261624 kb
Host smart-81b3bd79-be5d-4ed1-aa1f-f978d35e569c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857145093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.1857145093
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1528478877
Short name T955
Test name
Test status
Simulation time 1183765711 ps
CPU time 29.46 seconds
Started Apr 02 03:38:14 PM PDT 24
Finished Apr 02 03:38:43 PM PDT 24
Peak memory 344564 kb
Host smart-af6b11b0-fbe3-46a6-b8bd-d678d1c38b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528478877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1528478877
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3918566263
Short name T737
Test name
Test status
Simulation time 8228858538 ps
CPU time 59.13 seconds
Started Apr 02 03:38:18 PM PDT 24
Finished Apr 02 03:39:17 PM PDT 24
Peak memory 657576 kb
Host smart-07bd0aa6-838e-4f36-a8cf-cac3b55121cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918566263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3918566263
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2782219243
Short name T247
Test name
Test status
Simulation time 260337362 ps
CPU time 0.83 seconds
Started Apr 02 03:38:18 PM PDT 24
Finished Apr 02 03:38:18 PM PDT 24
Peak memory 203696 kb
Host smart-bb5087f2-b743-4994-9db4-14369dfe3dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782219243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2782219243
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1342906041
Short name T7
Test name
Test status
Simulation time 192501097 ps
CPU time 9.72 seconds
Started Apr 02 03:38:21 PM PDT 24
Finished Apr 02 03:38:30 PM PDT 24
Peak memory 203844 kb
Host smart-23114325-0046-4b9a-a495-d841a61df74a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342906041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1342906041
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.775435883
Short name T991
Test name
Test status
Simulation time 10219470168 ps
CPU time 103.49 seconds
Started Apr 02 03:38:18 PM PDT 24
Finished Apr 02 03:40:02 PM PDT 24
Peak memory 1118496 kb
Host smart-f776b3c7-4fdd-40f7-95d6-a513be0c72ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775435883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.775435883
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.4061188622
Short name T262
Test name
Test status
Simulation time 1538498277 ps
CPU time 14.5 seconds
Started Apr 02 03:38:29 PM PDT 24
Finished Apr 02 03:38:45 PM PDT 24
Peak memory 203860 kb
Host smart-b3ae1ef6-bb23-4998-a7f2-99d411977d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061188622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.4061188622
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.179905863
Short name T645
Test name
Test status
Simulation time 1654264326 ps
CPU time 36.21 seconds
Started Apr 02 03:38:29 PM PDT 24
Finished Apr 02 03:39:07 PM PDT 24
Peak memory 458176 kb
Host smart-f055879e-b1d4-4301-8d7b-9e3c5be3904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179905863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.179905863
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.1897909010
Short name T297
Test name
Test status
Simulation time 26396429 ps
CPU time 0.69 seconds
Started Apr 02 03:38:14 PM PDT 24
Finished Apr 02 03:38:15 PM PDT 24
Peak memory 203608 kb
Host smart-42ef6aac-aa7e-4eb4-b310-bb98aab4ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897909010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1897909010
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3000639903
Short name T1101
Test name
Test status
Simulation time 24962445333 ps
CPU time 84.49 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:39:44 PM PDT 24
Peak memory 291032 kb
Host smart-a20abb3b-c74c-4c6f-b28f-46d0670b1476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000639903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3000639903
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3947795155
Short name T672
Test name
Test status
Simulation time 1461874189 ps
CPU time 75.38 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 400844 kb
Host smart-188daa93-4ff5-4e66-86b6-eb8b2c43fcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947795155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3947795155
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1897918711
Short name T689
Test name
Test status
Simulation time 2008287774 ps
CPU time 4.62 seconds
Started Apr 02 03:38:19 PM PDT 24
Finished Apr 02 03:38:23 PM PDT 24
Peak memory 211988 kb
Host smart-db55320c-a1a6-4556-a736-65577c4ed72d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897918711 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1897918711
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2261249321
Short name T63
Test name
Test status
Simulation time 10040381570 ps
CPU time 68.27 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:39:40 PM PDT 24
Peak memory 585460 kb
Host smart-de775ee1-0562-451e-ad4b-ed6ed0804c6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261249321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2261249321
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1209498130
Short name T172
Test name
Test status
Simulation time 10506117212 ps
CPU time 10.87 seconds
Started Apr 02 03:38:20 PM PDT 24
Finished Apr 02 03:38:31 PM PDT 24
Peak memory 297488 kb
Host smart-c1efa1f7-b0ae-4e0b-92d7-d4c50dee88f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209498130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1209498130
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3723889237
Short name T709
Test name
Test status
Simulation time 696105332 ps
CPU time 2.52 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:38:34 PM PDT 24
Peak memory 203688 kb
Host smart-aa3e4c72-1be7-4ddb-9406-e83dc8d8b369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723889237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3723889237
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2652568307
Short name T1159
Test name
Test status
Simulation time 3009438489 ps
CPU time 4.62 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:38:36 PM PDT 24
Peak memory 207708 kb
Host smart-63f02cc9-7ab5-449b-a4f6-926304a3d477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652568307 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2652568307
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2002668808
Short name T651
Test name
Test status
Simulation time 6163685434 ps
CPU time 14.51 seconds
Started Apr 02 03:38:18 PM PDT 24
Finished Apr 02 03:38:32 PM PDT 24
Peak memory 203872 kb
Host smart-09022d46-1649-4669-9ce8-d2addde90892
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002668808 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2002668808
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.267866845
Short name T901
Test name
Test status
Simulation time 1354815103 ps
CPU time 10.83 seconds
Started Apr 02 03:38:17 PM PDT 24
Finished Apr 02 03:38:28 PM PDT 24
Peak memory 203760 kb
Host smart-d2edf3d6-6da1-41db-bcfd-a4e0ab89d39b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267866845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_tar
get_smoke.267866845
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2301748927
Short name T961
Test name
Test status
Simulation time 2380096858 ps
CPU time 18.13 seconds
Started Apr 02 03:38:16 PM PDT 24
Finished Apr 02 03:38:34 PM PDT 24
Peak memory 225072 kb
Host smart-8dd33af6-40c0-4d4b-bfb6-6a7e13dc3110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301748927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2301748927
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3775006111
Short name T879
Test name
Test status
Simulation time 26225438269 ps
CPU time 4.93 seconds
Started Apr 02 03:38:24 PM PDT 24
Finished Apr 02 03:38:29 PM PDT 24
Peak memory 203916 kb
Host smart-bce64d69-d8fd-41b9-9bab-b6d96a99455b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775006111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3775006111
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.768608002
Short name T355
Test name
Test status
Simulation time 1403220510 ps
CPU time 6.39 seconds
Started Apr 02 03:38:20 PM PDT 24
Finished Apr 02 03:38:27 PM PDT 24
Peak memory 220028 kb
Host smart-ae6a33f5-7585-4f5a-9d35-76399e03a3b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768608002 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.768608002
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.264599980
Short name T1019
Test name
Test status
Simulation time 18951457 ps
CPU time 0.63 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 203704 kb
Host smart-e2807ab8-d74d-48a9-871f-40d4fd8c7a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264599980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.264599980
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.4127251854
Short name T793
Test name
Test status
Simulation time 419211498 ps
CPU time 1.52 seconds
Started Apr 02 03:38:21 PM PDT 24
Finished Apr 02 03:38:23 PM PDT 24
Peak memory 212000 kb
Host smart-b7039c8e-2d1a-4b2d-8d68-d45ca66af82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127251854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.4127251854
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.359605428
Short name T669
Test name
Test status
Simulation time 1208765295 ps
CPU time 15.11 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 03:38:41 PM PDT 24
Peak memory 264720 kb
Host smart-ebbc6e8a-48f2-4cb8-bc34-a706e205aa29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359605428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.359605428
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.3347671002
Short name T503
Test name
Test status
Simulation time 1827269215 ps
CPU time 54.35 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 580500 kb
Host smart-6e1ee614-3371-43a1-b174-6e0613015515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347671002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.3347671002
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2474867558
Short name T641
Test name
Test status
Simulation time 1976223314 ps
CPU time 40.34 seconds
Started Apr 02 03:38:28 PM PDT 24
Finished Apr 02 03:39:09 PM PDT 24
Peak memory 517176 kb
Host smart-276fccb3-8990-4a57-b76e-502dcb705fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474867558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2474867558
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1575495845
Short name T45
Test name
Test status
Simulation time 248756116 ps
CPU time 1.02 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 203656 kb
Host smart-51df69ef-37a7-4d86-b983-3148f6143f09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575495845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1575495845
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2683921738
Short name T385
Test name
Test status
Simulation time 529876789 ps
CPU time 3.43 seconds
Started Apr 02 03:38:18 PM PDT 24
Finished Apr 02 03:38:22 PM PDT 24
Peak memory 223832 kb
Host smart-bdb6b777-2191-4d8c-9a1b-0733d01bdce7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683921738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2683921738
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1140191298
Short name T745
Test name
Test status
Simulation time 8985700183 ps
CPU time 60.73 seconds
Started Apr 02 03:38:29 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 714712 kb
Host smart-39784045-b5ee-4096-892f-994b28b39126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140191298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1140191298
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1291525063
Short name T869
Test name
Test status
Simulation time 2045115841 ps
CPU time 7.98 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 203824 kb
Host smart-be602aea-3fcf-4bed-9878-18c0183db61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291525063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1291525063
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1739584003
Short name T1089
Test name
Test status
Simulation time 4576007949 ps
CPU time 23.96 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:55 PM PDT 24
Peak memory 318808 kb
Host smart-223159a5-f638-4fde-a87e-866cd7bd93fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739584003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1739584003
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3453485487
Short name T768
Test name
Test status
Simulation time 24813009 ps
CPU time 0.63 seconds
Started Apr 02 03:38:17 PM PDT 24
Finished Apr 02 03:38:18 PM PDT 24
Peak memory 203592 kb
Host smart-73d067e1-c5c0-41d8-ad51-845a38eef73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453485487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3453485487
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2980933468
Short name T539
Test name
Test status
Simulation time 48037780189 ps
CPU time 341.5 seconds
Started Apr 02 03:38:28 PM PDT 24
Finished Apr 02 03:44:10 PM PDT 24
Peak memory 1580628 kb
Host smart-c02cd0da-3618-47aa-83f5-1cd08866fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980933468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2980933468
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3690182754
Short name T704
Test name
Test status
Simulation time 921702803 ps
CPU time 17.9 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:49 PM PDT 24
Peak memory 294252 kb
Host smart-4282e5fa-2993-4f0d-ad67-6e70806268e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690182754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3690182754
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4199856622
Short name T1110
Test name
Test status
Simulation time 850523977 ps
CPU time 4.48 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:38:36 PM PDT 24
Peak memory 203844 kb
Host smart-dbd7477a-e2e0-4820-a07f-126d6d26f661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199856622 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4199856622
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.2844420808
Short name T959
Test name
Test status
Simulation time 10074643761 ps
CPU time 91.82 seconds
Started Apr 02 03:38:21 PM PDT 24
Finished Apr 02 03:39:53 PM PDT 24
Peak memory 595484 kb
Host smart-6b2fdbad-dfc6-46a2-847c-29b2b466e91f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844420808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.2844420808
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3372669900
Short name T746
Test name
Test status
Simulation time 10109481594 ps
CPU time 36.89 seconds
Started Apr 02 03:38:21 PM PDT 24
Finished Apr 02 03:38:58 PM PDT 24
Peak memory 447668 kb
Host smart-df2429a4-473d-4151-82e7-66f8f46a179d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372669900 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3372669900
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2000951939
Short name T927
Test name
Test status
Simulation time 1615710775 ps
CPU time 2.39 seconds
Started Apr 02 03:38:27 PM PDT 24
Finished Apr 02 03:38:30 PM PDT 24
Peak memory 203824 kb
Host smart-3c341c5f-5964-4a1e-9f3c-bce608404b56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000951939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2000951939
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.4211934007
Short name T10
Test name
Test status
Simulation time 1462326068 ps
CPU time 7.43 seconds
Started Apr 02 03:38:27 PM PDT 24
Finished Apr 02 03:38:35 PM PDT 24
Peak memory 212080 kb
Host smart-e6114f1b-8ab6-4126-910d-9e7d08fd3782
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211934007 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.4211934007
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2087028348
Short name T520
Test name
Test status
Simulation time 6617316169 ps
CPU time 18.8 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 03:38:44 PM PDT 24
Peak memory 203832 kb
Host smart-891f0f3b-56e7-4e66-84c8-5e539dc2ba59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087028348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2087028348
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.4228684914
Short name T667
Test name
Test status
Simulation time 604954652 ps
CPU time 9.25 seconds
Started Apr 02 03:38:21 PM PDT 24
Finished Apr 02 03:38:31 PM PDT 24
Peak memory 207824 kb
Host smart-ecc9a922-672a-4baf-9b35-04e570dfdfeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228684914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.4228684914
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1911467343
Short name T1081
Test name
Test status
Simulation time 6124430641 ps
CPU time 5.81 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 03:38:31 PM PDT 24
Peak memory 249368 kb
Host smart-19613358-d603-43d2-bbbd-aee343ba504f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911467343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1911467343
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1597015870
Short name T703
Test name
Test status
Simulation time 1876761173 ps
CPU time 7.58 seconds
Started Apr 02 03:38:23 PM PDT 24
Finished Apr 02 03:38:30 PM PDT 24
Peak memory 216244 kb
Host smart-2566cc36-99da-4dba-b23b-ff45cd6498ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597015870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1597015870
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.528220768
Short name T1192
Test name
Test status
Simulation time 16975873 ps
CPU time 0.59 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 203696 kb
Host smart-93c0d6da-306c-4d7f-a5aa-f91eb3189652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528220768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.528220768
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3496800782
Short name T54
Test name
Test status
Simulation time 287443932 ps
CPU time 1.79 seconds
Started Apr 02 03:38:29 PM PDT 24
Finished Apr 02 03:38:31 PM PDT 24
Peak memory 212008 kb
Host smart-0b9f1295-2fda-41bf-8f8d-fa0ce8947033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496800782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3496800782
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.1321488540
Short name T920
Test name
Test status
Simulation time 670061540 ps
CPU time 8.54 seconds
Started Apr 02 03:38:24 PM PDT 24
Finished Apr 02 03:38:32 PM PDT 24
Peak memory 234652 kb
Host smart-0a54e41d-c33d-4ea7-b6d7-c9f465b96057
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321488540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.1321488540
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2865347630
Short name T1003
Test name
Test status
Simulation time 2094753544 ps
CPU time 68.54 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 03:39:34 PM PDT 24
Peak memory 704464 kb
Host smart-9a1f9a3d-8f6f-41e3-b1b2-34a376a942f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865347630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2865347630
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1409990758
Short name T928
Test name
Test status
Simulation time 5091725132 ps
CPU time 35.56 seconds
Started Apr 02 03:38:26 PM PDT 24
Finished Apr 02 03:39:02 PM PDT 24
Peak memory 518500 kb
Host smart-0564ad17-7f05-4130-8b23-1759431ebe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409990758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1409990758
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2667643305
Short name T311
Test name
Test status
Simulation time 385600339 ps
CPU time 1 seconds
Started Apr 02 03:38:24 PM PDT 24
Finished Apr 02 03:38:25 PM PDT 24
Peak memory 203732 kb
Host smart-29053523-b3ba-42bd-b49c-9fb02f5a4b24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667643305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2667643305
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2278029570
Short name T417
Test name
Test status
Simulation time 1158329415 ps
CPU time 2.7 seconds
Started Apr 02 03:38:22 PM PDT 24
Finished Apr 02 03:38:25 PM PDT 24
Peak memory 218068 kb
Host smart-9482d77d-84a0-4eeb-86f9-0ce51f322ba1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278029570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2278029570
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2048163694
Short name T1035
Test name
Test status
Simulation time 6294891318 ps
CPU time 72.33 seconds
Started Apr 02 03:38:24 PM PDT 24
Finished Apr 02 03:39:36 PM PDT 24
Peak memory 942000 kb
Host smart-5aef4b03-1b21-4780-9af6-00efa51a7a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048163694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2048163694
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.369493203
Short name T616
Test name
Test status
Simulation time 3325291667 ps
CPU time 4.81 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:36 PM PDT 24
Peak memory 203920 kb
Host smart-4df783bc-0ec7-4080-9826-f02a65eec97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369493203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.369493203
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1434893541
Short name T1139
Test name
Test status
Simulation time 6674619853 ps
CPU time 44.81 seconds
Started Apr 02 03:38:32 PM PDT 24
Finished Apr 02 03:39:17 PM PDT 24
Peak memory 486160 kb
Host smart-27721938-0510-4c87-a31c-658dc9874e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434893541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1434893541
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.3238114773
Short name T455
Test name
Test status
Simulation time 49597787 ps
CPU time 0.72 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 03:38:26 PM PDT 24
Peak memory 203580 kb
Host smart-e29e7ab3-afa6-4675-a699-2585f67078d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238114773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3238114773
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3654450050
Short name T190
Test name
Test status
Simulation time 53443643802 ps
CPU time 2998.47 seconds
Started Apr 02 03:38:25 PM PDT 24
Finished Apr 02 04:28:24 PM PDT 24
Peak memory 5724456 kb
Host smart-59bf66f9-f565-4393-80ff-29a2f2d514dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654450050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3654450050
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1560130035
Short name T416
Test name
Test status
Simulation time 2773216491 ps
CPU time 35.01 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:39:06 PM PDT 24
Peak memory 409076 kb
Host smart-703e6d02-bd54-483c-a8a0-7e2e70b02302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560130035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1560130035
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.945022503
Short name T624
Test name
Test status
Simulation time 802088835 ps
CPU time 3.23 seconds
Started Apr 02 03:38:29 PM PDT 24
Finished Apr 02 03:38:34 PM PDT 24
Peak memory 203824 kb
Host smart-e81ee895-a4f8-4aff-9cfe-72560dc93e61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945022503 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.945022503
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2800224829
Short name T82
Test name
Test status
Simulation time 10318912330 ps
CPU time 8.8 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:40 PM PDT 24
Peak memory 245540 kb
Host smart-270cc9d0-092e-41ae-9f99-d6977d6f5830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800224829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2800224829
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2702598365
Short name T193
Test name
Test status
Simulation time 10059230162 ps
CPU time 114.05 seconds
Started Apr 02 03:38:28 PM PDT 24
Finished Apr 02 03:40:23 PM PDT 24
Peak memory 748776 kb
Host smart-5b542c6f-65cd-43dc-b06d-6362edf2eeda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702598365 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2702598365
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1545919543
Short name T801
Test name
Test status
Simulation time 778968678 ps
CPU time 2.54 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:33 PM PDT 24
Peak memory 203688 kb
Host smart-f910d638-52f7-4bfa-bcbd-ce41e1c7c17a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545919543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1545919543
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3409338021
Short name T908
Test name
Test status
Simulation time 12593091022 ps
CPU time 6.91 seconds
Started Apr 02 03:38:27 PM PDT 24
Finished Apr 02 03:38:34 PM PDT 24
Peak memory 220068 kb
Host smart-e561543b-ba2f-4cc0-b5db-425aa1c60092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409338021 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3409338021
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.4166356585
Short name T878
Test name
Test status
Simulation time 5765336468 ps
CPU time 13.02 seconds
Started Apr 02 03:38:27 PM PDT 24
Finished Apr 02 03:38:41 PM PDT 24
Peak memory 203872 kb
Host smart-4b3e0222-f275-48df-898e-2765e138c7df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166356585 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.4166356585
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2481007285
Short name T532
Test name
Test status
Simulation time 5200698383 ps
CPU time 13.13 seconds
Started Apr 02 03:38:28 PM PDT 24
Finished Apr 02 03:38:41 PM PDT 24
Peak memory 203824 kb
Host smart-2195bab3-1123-4b98-9aaa-47a03da657e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481007285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2481007285
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.977784437
Short name T611
Test name
Test status
Simulation time 681236529 ps
CPU time 10 seconds
Started Apr 02 03:38:28 PM PDT 24
Finished Apr 02 03:38:38 PM PDT 24
Peak memory 208736 kb
Host smart-308bcce8-1691-4014-887d-afc87cdf97c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977784437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.977784437
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.319733832
Short name T1008
Test name
Test status
Simulation time 6612526390 ps
CPU time 7.95 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:39 PM PDT 24
Peak memory 218096 kb
Host smart-a118b657-b6a4-42be-82ae-e30862e3299c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319733832 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.319733832
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.325459448
Short name T1131
Test name
Test status
Simulation time 4400562138 ps
CPU time 5.96 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:37 PM PDT 24
Peak memory 203792 kb
Host smart-4788a894-f526-4b34-9e2a-0cc9ed390c97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325459448 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_unexp_stop.325459448
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.640553391
Short name T9
Test name
Test status
Simulation time 65753202 ps
CPU time 0.63 seconds
Started Apr 02 03:38:39 PM PDT 24
Finished Apr 02 03:38:40 PM PDT 24
Peak memory 203688 kb
Host smart-80a1657b-137b-47a1-b138-9db9ff173548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640553391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.640553391
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3040782635
Short name T569
Test name
Test status
Simulation time 88581183 ps
CPU time 1.56 seconds
Started Apr 02 03:38:35 PM PDT 24
Finished Apr 02 03:38:36 PM PDT 24
Peak memory 212088 kb
Host smart-f3836819-9105-40fe-b52c-d54fee57cab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040782635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3040782635
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2358003844
Short name T319
Test name
Test status
Simulation time 1234193279 ps
CPU time 5.83 seconds
Started Apr 02 03:38:30 PM PDT 24
Finished Apr 02 03:38:36 PM PDT 24
Peak memory 271172 kb
Host smart-dd3fade4-9aa3-4a8a-a408-dcebedd234a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358003844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2358003844
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1259270047
Short name T903
Test name
Test status
Simulation time 12071954637 ps
CPU time 77.03 seconds
Started Apr 02 03:38:35 PM PDT 24
Finished Apr 02 03:39:52 PM PDT 24
Peak memory 731444 kb
Host smart-bf1a7030-979e-4930-a011-75e664061b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259270047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1259270047
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1101163735
Short name T328
Test name
Test status
Simulation time 1370065840 ps
CPU time 42.46 seconds
Started Apr 02 03:38:34 PM PDT 24
Finished Apr 02 03:39:16 PM PDT 24
Peak memory 508820 kb
Host smart-f3cdfcd3-15c1-4fc2-95bb-fce4b1b4079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101163735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1101163735
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.535842423
Short name T315
Test name
Test status
Simulation time 696969551 ps
CPU time 1.21 seconds
Started Apr 02 03:38:34 PM PDT 24
Finished Apr 02 03:38:35 PM PDT 24
Peak memory 203804 kb
Host smart-329621fd-657b-452f-8e76-d580d8854eb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535842423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.535842423
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1524284150
Short name T459
Test name
Test status
Simulation time 273845834 ps
CPU time 3.84 seconds
Started Apr 02 03:38:33 PM PDT 24
Finished Apr 02 03:38:37 PM PDT 24
Peak memory 224988 kb
Host smart-1675648d-0c3f-45da-943d-0a96b3ad0e16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524284150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1524284150
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.766382368
Short name T164
Test name
Test status
Simulation time 17955179560 ps
CPU time 344.99 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:44:16 PM PDT 24
Peak memory 1277776 kb
Host smart-6a04df12-06f8-464f-b114-4bcdec7dcf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766382368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.766382368
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.1777079939
Short name T649
Test name
Test status
Simulation time 790637455 ps
CPU time 2.94 seconds
Started Apr 02 03:38:38 PM PDT 24
Finished Apr 02 03:38:41 PM PDT 24
Peak memory 203844 kb
Host smart-8492ef89-e4c2-4399-9659-0e8bb8e7a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777079939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1777079939
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3686313533
Short name T201
Test name
Test status
Simulation time 5160422885 ps
CPU time 65.95 seconds
Started Apr 02 03:38:37 PM PDT 24
Finished Apr 02 03:39:43 PM PDT 24
Peak memory 398736 kb
Host smart-b946debb-f9c7-4bec-94be-c8da2058aa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686313533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3686313533
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2687618901
Short name T12
Test name
Test status
Simulation time 53375427 ps
CPU time 0.62 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:38:32 PM PDT 24
Peak memory 203608 kb
Host smart-a1528929-5ffc-4d11-bcce-aa6c429cf283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687618901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2687618901
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1295478234
Short name T191
Test name
Test status
Simulation time 6367394942 ps
CPU time 65.51 seconds
Started Apr 02 03:38:33 PM PDT 24
Finished Apr 02 03:39:38 PM PDT 24
Peak memory 316252 kb
Host smart-a4437c81-9870-4d93-9b7d-c5a46c6fb022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295478234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1295478234
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.717745660
Short name T925
Test name
Test status
Simulation time 22356656592 ps
CPU time 55.54 seconds
Started Apr 02 03:38:33 PM PDT 24
Finished Apr 02 03:39:28 PM PDT 24
Peak memory 325528 kb
Host smart-3b786530-179e-460d-9106-c997b3b1029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717745660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.717745660
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.515814161
Short name T112
Test name
Test status
Simulation time 18806617783 ps
CPU time 318.42 seconds
Started Apr 02 03:38:31 PM PDT 24
Finished Apr 02 03:43:49 PM PDT 24
Peak memory 1407732 kb
Host smart-ff97f1d7-73d4-4b9d-82ad-a25a9a5e5b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515814161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.515814161
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3530924815
Short name T1059
Test name
Test status
Simulation time 2813233240 ps
CPU time 3.33 seconds
Started Apr 02 03:38:38 PM PDT 24
Finished Apr 02 03:38:41 PM PDT 24
Peak memory 203852 kb
Host smart-1f9f9473-2ad5-460c-9f76-484def1f8f6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530924815 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3530924815
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3903003506
Short name T62
Test name
Test status
Simulation time 10308017938 ps
CPU time 28.53 seconds
Started Apr 02 03:38:40 PM PDT 24
Finished Apr 02 03:39:08 PM PDT 24
Peak memory 381032 kb
Host smart-c6e13580-5779-4fad-a45e-b9bd39dc6944
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903003506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3903003506
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3311503785
Short name T817
Test name
Test status
Simulation time 10201700326 ps
CPU time 8.03 seconds
Started Apr 02 03:38:36 PM PDT 24
Finished Apr 02 03:38:44 PM PDT 24
Peak memory 267468 kb
Host smart-bc197bbb-55d6-4557-b3a3-bd3e1ff9cc56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311503785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3311503785
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1924078650
Short name T1104
Test name
Test status
Simulation time 1838631545 ps
CPU time 2.5 seconds
Started Apr 02 03:38:38 PM PDT 24
Finished Apr 02 03:38:41 PM PDT 24
Peak memory 203772 kb
Host smart-bcbc268e-f58d-4a55-907c-99496ccdd217
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924078650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1924078650
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2387194371
Short name T842
Test name
Test status
Simulation time 876196260 ps
CPU time 5.11 seconds
Started Apr 02 03:38:33 PM PDT 24
Finished Apr 02 03:38:38 PM PDT 24
Peak memory 211916 kb
Host smart-42e338bc-1080-4f1c-a5d4-36e2418d087a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387194371 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2387194371
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2088570856
Short name T337
Test name
Test status
Simulation time 1314170399 ps
CPU time 21.25 seconds
Started Apr 02 03:38:38 PM PDT 24
Finished Apr 02 03:38:59 PM PDT 24
Peak memory 203776 kb
Host smart-b7afd1b3-de9a-408a-ba98-e02014796fa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088570856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2088570856
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.150791679
Short name T243
Test name
Test status
Simulation time 821155426 ps
CPU time 6.98 seconds
Started Apr 02 03:38:36 PM PDT 24
Finished Apr 02 03:38:44 PM PDT 24
Peak memory 205704 kb
Host smart-72749e8e-ab29-4580-a3e0-245a6e0dce8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150791679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_rd.150791679
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3025940734
Short name T1063
Test name
Test status
Simulation time 29105986042 ps
CPU time 2092.64 seconds
Started Apr 02 03:38:37 PM PDT 24
Finished Apr 02 04:13:30 PM PDT 24
Peak memory 3698920 kb
Host smart-5576043e-45dd-4912-9b72-b7662e42a539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025940734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3025940734
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2925123839
Short name T386
Test name
Test status
Simulation time 3739414984 ps
CPU time 5.8 seconds
Started Apr 02 03:38:41 PM PDT 24
Finished Apr 02 03:38:47 PM PDT 24
Peak memory 218760 kb
Host smart-558d7655-cb80-416c-8e81-18b586f056e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925123839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2925123839
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3658440781
Short name T805
Test name
Test status
Simulation time 165789883 ps
CPU time 0.6 seconds
Started Apr 02 03:38:46 PM PDT 24
Finished Apr 02 03:38:47 PM PDT 24
Peak memory 203648 kb
Host smart-e2429a18-1ab0-4d3b-984d-d27cbdf0fc39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658440781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3658440781
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3371480100
Short name T771
Test name
Test status
Simulation time 128761593 ps
CPU time 1.13 seconds
Started Apr 02 03:38:44 PM PDT 24
Finished Apr 02 03:38:45 PM PDT 24
Peak memory 212040 kb
Host smart-8fd68e3e-79fe-42c0-bcf5-769baa006564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371480100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3371480100
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1678607771
Short name T377
Test name
Test status
Simulation time 957558046 ps
CPU time 3.57 seconds
Started Apr 02 03:38:39 PM PDT 24
Finished Apr 02 03:38:42 PM PDT 24
Peak memory 229844 kb
Host smart-73905b6e-44aa-407a-a73d-383e8994a42b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678607771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1678607771
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3553495072
Short name T963
Test name
Test status
Simulation time 30515879488 ps
CPU time 53.72 seconds
Started Apr 02 03:38:39 PM PDT 24
Finished Apr 02 03:39:33 PM PDT 24
Peak memory 574888 kb
Host smart-8e37c19c-d052-46a7-8c1b-71d7cb91ac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553495072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3553495072
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2576054455
Short name T872
Test name
Test status
Simulation time 462541983 ps
CPU time 1.05 seconds
Started Apr 02 03:38:37 PM PDT 24
Finished Apr 02 03:38:39 PM PDT 24
Peak memory 203744 kb
Host smart-3f1480b5-72db-4718-97d6-6bf358bb5c5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576054455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2576054455
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2353648019
Short name T1038
Test name
Test status
Simulation time 264245368 ps
CPU time 7.14 seconds
Started Apr 02 03:38:38 PM PDT 24
Finished Apr 02 03:38:45 PM PDT 24
Peak memory 223908 kb
Host smart-673021d6-ff82-4c92-81e2-e441b283837e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353648019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2353648019
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2472960070
Short name T796
Test name
Test status
Simulation time 3055268191 ps
CPU time 81.65 seconds
Started Apr 02 03:38:37 PM PDT 24
Finished Apr 02 03:39:59 PM PDT 24
Peak memory 930720 kb
Host smart-454010ce-dccf-4c6b-b663-1ee31dcc781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472960070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2472960070
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3002666288
Short name T214
Test name
Test status
Simulation time 10384632210 ps
CPU time 20.99 seconds
Started Apr 02 03:38:49 PM PDT 24
Finished Apr 02 03:39:10 PM PDT 24
Peak memory 203856 kb
Host smart-038ef506-7e2c-49ff-9a58-65b1b4cc3131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002666288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3002666288
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.3449523233
Short name T565
Test name
Test status
Simulation time 4970379576 ps
CPU time 29.41 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:39:19 PM PDT 24
Peak memory 417348 kb
Host smart-356aa425-6ab0-4137-b54c-53007cfe05f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449523233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.3449523233
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.593061868
Short name T806
Test name
Test status
Simulation time 50016896 ps
CPU time 0.66 seconds
Started Apr 02 03:38:39 PM PDT 24
Finished Apr 02 03:38:40 PM PDT 24
Peak memory 203636 kb
Host smart-5c773593-b58c-44e8-af53-36e151f1c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593061868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.593061868
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3143758601
Short name T643
Test name
Test status
Simulation time 632197380 ps
CPU time 26.03 seconds
Started Apr 02 03:38:37 PM PDT 24
Finished Apr 02 03:39:03 PM PDT 24
Peak memory 228456 kb
Host smart-a0d3e86a-430a-4769-b2a9-e96d9b10edd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143758601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3143758601
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.91673522
Short name T524
Test name
Test status
Simulation time 1265161136 ps
CPU time 64.09 seconds
Started Apr 02 03:38:40 PM PDT 24
Finished Apr 02 03:39:45 PM PDT 24
Peak memory 352612 kb
Host smart-6d76418b-56d0-4cde-a151-c4903fc9a8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91673522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.91673522
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3383880037
Short name T625
Test name
Test status
Simulation time 2145503785 ps
CPU time 2.79 seconds
Started Apr 02 03:39:01 PM PDT 24
Finished Apr 02 03:39:04 PM PDT 24
Peak memory 203808 kb
Host smart-4a8633d0-478a-4b33-8890-a4d9311af73e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383880037 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3383880037
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1102166204
Short name T239
Test name
Test status
Simulation time 10090268440 ps
CPU time 98.2 seconds
Started Apr 02 03:38:41 PM PDT 24
Finished Apr 02 03:40:19 PM PDT 24
Peak memory 614240 kb
Host smart-9ccac53b-9dac-4f10-b32d-39a28f85862b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102166204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1102166204
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1048478810
Short name T759
Test name
Test status
Simulation time 10027533019 ps
CPU time 104.31 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:40:34 PM PDT 24
Peak memory 758380 kb
Host smart-039a497f-b165-4e1d-b4fd-0e178cf6e4a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048478810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.1048478810
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2316943013
Short name T356
Test name
Test status
Simulation time 350274573 ps
CPU time 2.4 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:38:52 PM PDT 24
Peak memory 203756 kb
Host smart-9915fce0-94e5-42ad-9bba-b4df51611512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316943013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2316943013
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3899808587
Short name T1022
Test name
Test status
Simulation time 2332932434 ps
CPU time 3.13 seconds
Started Apr 02 03:38:42 PM PDT 24
Finished Apr 02 03:38:45 PM PDT 24
Peak memory 204916 kb
Host smart-83f77f37-e716-4f67-b635-67f5be5ad874
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899808587 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3899808587
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1252838496
Short name T921
Test name
Test status
Simulation time 9930317552 ps
CPU time 5.71 seconds
Started Apr 02 03:38:47 PM PDT 24
Finished Apr 02 03:38:53 PM PDT 24
Peak memory 203820 kb
Host smart-f5269a5d-d725-4829-8bf3-6f74b2bda75a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252838496 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1252838496
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3581913258
Short name T1090
Test name
Test status
Simulation time 657230653 ps
CPU time 9.02 seconds
Started Apr 02 03:38:44 PM PDT 24
Finished Apr 02 03:38:53 PM PDT 24
Peak memory 203792 kb
Host smart-f5e2bfc7-1208-410c-bcf4-56f676f7169e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581913258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3581913258
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2744605317
Short name T749
Test name
Test status
Simulation time 5168115102 ps
CPU time 54.53 seconds
Started Apr 02 03:38:41 PM PDT 24
Finished Apr 02 03:39:36 PM PDT 24
Peak memory 205876 kb
Host smart-11b9350a-e23e-4ccb-8824-a2def9ef0c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744605317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2744605317
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3575217974
Short name T288
Test name
Test status
Simulation time 5693101855 ps
CPU time 27.9 seconds
Started Apr 02 03:38:43 PM PDT 24
Finished Apr 02 03:39:11 PM PDT 24
Peak memory 295744 kb
Host smart-f75e25fb-38ca-4d4f-874d-61b678b23b73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575217974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3575217974
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2108694477
Short name T504
Test name
Test status
Simulation time 7851505653 ps
CPU time 6.94 seconds
Started Apr 02 03:38:43 PM PDT 24
Finished Apr 02 03:38:51 PM PDT 24
Peak memory 220116 kb
Host smart-d358f188-bb77-4445-b08d-329b688afc81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108694477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2108694477
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.10627303
Short name T1075
Test name
Test status
Simulation time 168361804 ps
CPU time 0.62 seconds
Started Apr 02 03:38:53 PM PDT 24
Finished Apr 02 03:38:54 PM PDT 24
Peak memory 203628 kb
Host smart-f7894791-c30f-4a18-bcfa-6346272d9da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10627303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.10627303
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1094760867
Short name T997
Test name
Test status
Simulation time 177912335 ps
CPU time 1.37 seconds
Started Apr 02 03:38:49 PM PDT 24
Finished Apr 02 03:38:51 PM PDT 24
Peak memory 212036 kb
Host smart-e862869e-0995-4f39-b1c4-0eef0816276a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094760867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1094760867
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1408173090
Short name T710
Test name
Test status
Simulation time 392907237 ps
CPU time 5.2 seconds
Started Apr 02 03:38:49 PM PDT 24
Finished Apr 02 03:38:55 PM PDT 24
Peak memory 250024 kb
Host smart-0788d3b4-890d-4370-9bbf-f49b6acc71b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408173090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1408173090
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3759929519
Short name T217
Test name
Test status
Simulation time 1574542355 ps
CPU time 47.08 seconds
Started Apr 02 03:38:46 PM PDT 24
Finished Apr 02 03:39:34 PM PDT 24
Peak memory 584296 kb
Host smart-47438644-3994-4b43-a3be-7e1fd4ba099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759929519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3759929519
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1822737346
Short name T962
Test name
Test status
Simulation time 2682163204 ps
CPU time 84.4 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:40:14 PM PDT 24
Peak memory 481108 kb
Host smart-ab29e2dd-fa87-44dd-ba5a-a7b374e4cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822737346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1822737346
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1844375052
Short name T431
Test name
Test status
Simulation time 816116772 ps
CPU time 9.78 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:38:59 PM PDT 24
Peak memory 203880 kb
Host smart-b3a95f4b-aca3-458b-b31a-00c2707da985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844375052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1844375052
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1324067537
Short name T676
Test name
Test status
Simulation time 4097501247 ps
CPU time 99.14 seconds
Started Apr 02 03:38:46 PM PDT 24
Finished Apr 02 03:40:26 PM PDT 24
Peak memory 1152136 kb
Host smart-d8a07ccd-1fc2-4934-b993-2c38b8d5a720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324067537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1324067537
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.1592528155
Short name T742
Test name
Test status
Simulation time 1147880877 ps
CPU time 11.93 seconds
Started Apr 02 03:38:51 PM PDT 24
Finished Apr 02 03:39:03 PM PDT 24
Peak memory 203800 kb
Host smart-794a36b8-6e3b-4af7-9408-2e4e11fd4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592528155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1592528155
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2112125575
Short name T266
Test name
Test status
Simulation time 1026034287 ps
CPU time 49.3 seconds
Started Apr 02 03:38:48 PM PDT 24
Finished Apr 02 03:39:39 PM PDT 24
Peak memory 325156 kb
Host smart-d5f52261-811a-4bdd-bfc1-905ddac2055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112125575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2112125575
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2517187194
Short name T358
Test name
Test status
Simulation time 40211473 ps
CPU time 0.68 seconds
Started Apr 02 03:38:47 PM PDT 24
Finished Apr 02 03:38:48 PM PDT 24
Peak memory 203580 kb
Host smart-1ff55e1e-101c-42fe-b3c2-9da02734f10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517187194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2517187194
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3694535629
Short name T34
Test name
Test status
Simulation time 3001052297 ps
CPU time 40.99 seconds
Started Apr 02 03:38:46 PM PDT 24
Finished Apr 02 03:39:28 PM PDT 24
Peak memory 377104 kb
Host smart-78b984c5-7576-4415-8d16-db6ce5ba5103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694535629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3694535629
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1508620221
Short name T359
Test name
Test status
Simulation time 1387149467 ps
CPU time 75.95 seconds
Started Apr 02 03:38:46 PM PDT 24
Finished Apr 02 03:40:03 PM PDT 24
Peak memory 423324 kb
Host smart-2ca6ce41-7f50-469d-9625-3dac24b55bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508620221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1508620221
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1556805735
Short name T32
Test name
Test status
Simulation time 66655208823 ps
CPU time 372.21 seconds
Started Apr 02 03:38:47 PM PDT 24
Finished Apr 02 03:44:59 PM PDT 24
Peak memory 2177380 kb
Host smart-aa60c6ff-ef1b-47c2-a81d-de1e10d6a151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556805735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1556805735
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.589470340
Short name T1016
Test name
Test status
Simulation time 3112316869 ps
CPU time 3.73 seconds
Started Apr 02 03:38:50 PM PDT 24
Finished Apr 02 03:38:54 PM PDT 24
Peak memory 203856 kb
Host smart-6dfdf23f-a94b-485a-bcdd-e37511615129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589470340 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.589470340
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.4265971031
Short name T988
Test name
Test status
Simulation time 10276995179 ps
CPU time 13.57 seconds
Started Apr 02 03:38:50 PM PDT 24
Finished Apr 02 03:39:04 PM PDT 24
Peak memory 295228 kb
Host smart-f2fb08ea-05d6-470c-a856-ec8ab153e884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265971031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.4265971031
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3370426929
Short name T986
Test name
Test status
Simulation time 1849931356 ps
CPU time 2.7 seconds
Started Apr 02 03:38:50 PM PDT 24
Finished Apr 02 03:38:53 PM PDT 24
Peak memory 203724 kb
Host smart-ddb2e4d8-2f73-4790-98d4-c0dba3f4c7ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370426929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3370426929
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.3889514961
Short name T834
Test name
Test status
Simulation time 3559609851 ps
CPU time 5.31 seconds
Started Apr 02 03:38:45 PM PDT 24
Finished Apr 02 03:38:51 PM PDT 24
Peak memory 210892 kb
Host smart-ed69876e-8640-4795-b29a-2edc142ffee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889514961 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.3889514961
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2309812709
Short name T360
Test name
Test status
Simulation time 2390456026 ps
CPU time 47.32 seconds
Started Apr 02 03:39:04 PM PDT 24
Finished Apr 02 03:39:51 PM PDT 24
Peak memory 203920 kb
Host smart-e346ce32-7afd-46ee-8ed7-056be2b80490
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309812709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2309812709
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1707414064
Short name T990
Test name
Test status
Simulation time 3799697465 ps
CPU time 13.01 seconds
Started Apr 02 03:38:47 PM PDT 24
Finished Apr 02 03:39:00 PM PDT 24
Peak memory 212660 kb
Host smart-2e2e6daa-53ca-4d9f-8106-9b31e3d40ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707414064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1707414064
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1448499371
Short name T899
Test name
Test status
Simulation time 6017417467 ps
CPU time 6.87 seconds
Started Apr 02 03:38:49 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 220092 kb
Host smart-bbe31f37-0316-4511-87f7-7b1ad0dccc06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448499371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1448499371
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.3848206366
Short name T600
Test name
Test status
Simulation time 4112658053 ps
CPU time 3.51 seconds
Started Apr 02 03:38:52 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 205036 kb
Host smart-84f7a63b-825e-46ba-84ef-e046ee7b0505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848206366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.3848206366
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1467721037
Short name T580
Test name
Test status
Simulation time 21428232 ps
CPU time 0.6 seconds
Started Apr 02 03:38:55 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 203408 kb
Host smart-a97b5f44-de2f-4639-b769-42a103b5bc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467721037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1467721037
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.556952135
Short name T409
Test name
Test status
Simulation time 542109576 ps
CPU time 1.8 seconds
Started Apr 02 03:38:55 PM PDT 24
Finished Apr 02 03:38:57 PM PDT 24
Peak memory 212116 kb
Host smart-87d713e9-889f-49b3-83dd-19de298f5be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556952135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.556952135
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1745600284
Short name T1014
Test name
Test status
Simulation time 231654898 ps
CPU time 10.46 seconds
Started Apr 02 03:38:52 PM PDT 24
Finished Apr 02 03:39:02 PM PDT 24
Peak memory 229116 kb
Host smart-7cd68238-aa0f-479e-be87-41a85a857618
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745600284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1745600284
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3291337781
Short name T58
Test name
Test status
Simulation time 1678651594 ps
CPU time 55.34 seconds
Started Apr 02 03:38:53 PM PDT 24
Finished Apr 02 03:39:48 PM PDT 24
Peak memory 601612 kb
Host smart-2411fd16-0598-4f19-b311-146e07b7fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291337781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3291337781
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.362433968
Short name T1142
Test name
Test status
Simulation time 4940746799 ps
CPU time 34.06 seconds
Started Apr 02 03:38:50 PM PDT 24
Finished Apr 02 03:39:25 PM PDT 24
Peak memory 498396 kb
Host smart-13dbec68-0a03-4149-94b7-61fe87cd3a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362433968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.362433968
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1040156751
Short name T606
Test name
Test status
Simulation time 121229811 ps
CPU time 0.95 seconds
Started Apr 02 03:38:53 PM PDT 24
Finished Apr 02 03:38:54 PM PDT 24
Peak memory 203644 kb
Host smart-774d4643-976d-4095-80bf-fc90352a167b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040156751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1040156751
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.306826553
Short name T292
Test name
Test status
Simulation time 749829892 ps
CPU time 4.7 seconds
Started Apr 02 03:38:50 PM PDT 24
Finished Apr 02 03:38:55 PM PDT 24
Peak memory 203800 kb
Host smart-a4b77ff4-114c-4c65-b2c2-78c73476986c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306826553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
306826553
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2350594506
Short name T219
Test name
Test status
Simulation time 14768593173 ps
CPU time 275.44 seconds
Started Apr 02 03:38:51 PM PDT 24
Finished Apr 02 03:43:26 PM PDT 24
Peak memory 1124056 kb
Host smart-7720481b-ff65-4b40-8365-76cd2889d75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350594506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2350594506
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.1324975216
Short name T982
Test name
Test status
Simulation time 411383396 ps
CPU time 5.01 seconds
Started Apr 02 03:38:55 PM PDT 24
Finished Apr 02 03:39:01 PM PDT 24
Peak memory 203760 kb
Host smart-23178dcf-595a-4d7b-827b-fe9f8d34a8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324975216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1324975216
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.2068313523
Short name T1099
Test name
Test status
Simulation time 31651765 ps
CPU time 0.66 seconds
Started Apr 02 03:38:51 PM PDT 24
Finished Apr 02 03:38:52 PM PDT 24
Peak memory 203596 kb
Host smart-6132ff24-20b5-4759-87db-9d2f792780b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068313523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2068313523
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.181278395
Short name T37
Test name
Test status
Simulation time 1216737896 ps
CPU time 4.99 seconds
Started Apr 02 03:38:55 PM PDT 24
Finished Apr 02 03:39:01 PM PDT 24
Peak memory 203900 kb
Host smart-cf5a554a-7ae7-471d-a8e9-a7869cd36d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181278395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.181278395
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.430406184
Short name T426
Test name
Test status
Simulation time 5165746896 ps
CPU time 63.9 seconds
Started Apr 02 03:38:52 PM PDT 24
Finished Apr 02 03:39:57 PM PDT 24
Peak memory 309720 kb
Host smart-b453b345-e73b-498d-897e-2964c44042b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430406184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.430406184
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.950546133
Short name T281
Test name
Test status
Simulation time 1462548934 ps
CPU time 3.51 seconds
Started Apr 02 03:38:53 PM PDT 24
Finished Apr 02 03:38:57 PM PDT 24
Peak memory 211960 kb
Host smart-d1195c0c-550f-4037-ba85-aad53e7b7b28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950546133 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.950546133
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1333235956
Short name T654
Test name
Test status
Simulation time 10257349280 ps
CPU time 19.71 seconds
Started Apr 02 03:38:52 PM PDT 24
Finished Apr 02 03:39:12 PM PDT 24
Peak memory 305628 kb
Host smart-373013b2-0a21-4fef-bf0d-6f14de26b1ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333235956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1333235956
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1492347602
Short name T1116
Test name
Test status
Simulation time 10226104251 ps
CPU time 93.9 seconds
Started Apr 02 03:38:55 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 715700 kb
Host smart-93b299d8-985f-4d71-a254-6bf24d46c3b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492347602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1492347602
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3628104496
Short name T1141
Test name
Test status
Simulation time 481132627 ps
CPU time 1.89 seconds
Started Apr 02 03:38:52 PM PDT 24
Finished Apr 02 03:38:54 PM PDT 24
Peak memory 203744 kb
Host smart-2740cb7e-eb32-4426-b6ec-ae5c21fb4421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628104496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3628104496
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3725218606
Short name T853
Test name
Test status
Simulation time 1264915824 ps
CPU time 6.2 seconds
Started Apr 02 03:38:54 PM PDT 24
Finished Apr 02 03:39:01 PM PDT 24
Peak memory 212208 kb
Host smart-d4c798e5-eca2-4edd-beba-809b37b1408e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725218606 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3725218606
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.4052546679
Short name T263
Test name
Test status
Simulation time 10716818026 ps
CPU time 3.32 seconds
Started Apr 02 03:38:53 PM PDT 24
Finished Apr 02 03:38:56 PM PDT 24
Peak memory 203852 kb
Host smart-eb1124f0-aaea-477b-af31-e6b9136194b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052546679 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.4052546679
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3822878124
Short name T1087
Test name
Test status
Simulation time 1038648311 ps
CPU time 16.61 seconds
Started Apr 02 03:38:54 PM PDT 24
Finished Apr 02 03:39:11 PM PDT 24
Peak memory 203784 kb
Host smart-51e5828e-4b91-4675-b720-e7f4845fa6f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822878124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3822878124
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.2263911493
Short name T1154
Test name
Test status
Simulation time 1666729469 ps
CPU time 15.55 seconds
Started Apr 02 03:38:54 PM PDT 24
Finished Apr 02 03:39:10 PM PDT 24
Peak memory 209272 kb
Host smart-aa5fbeb1-0331-4917-ab26-7b49a7e53d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263911493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.2263911493
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.297216524
Short name T471
Test name
Test status
Simulation time 18985812553 ps
CPU time 139.91 seconds
Started Apr 02 03:38:53 PM PDT 24
Finished Apr 02 03:41:13 PM PDT 24
Peak memory 1215884 kb
Host smart-c1783df7-5391-4682-9ffc-d72ea1d7b9e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297216524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.297216524
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.722060288
Short name T664
Test name
Test status
Simulation time 6059574792 ps
CPU time 6.43 seconds
Started Apr 02 03:38:55 PM PDT 24
Finished Apr 02 03:39:02 PM PDT 24
Peak memory 203888 kb
Host smart-96fc9477-4606-4f2c-afa3-94c19232e297
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722060288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.722060288
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2309207301
Short name T884
Test name
Test status
Simulation time 23143381 ps
CPU time 0.65 seconds
Started Apr 02 03:36:50 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 203688 kb
Host smart-67f18436-6c7f-46e2-81d2-89cc5f7361a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309207301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2309207301
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3459444017
Short name T1143
Test name
Test status
Simulation time 102379442 ps
CPU time 1.5 seconds
Started Apr 02 03:36:39 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 212080 kb
Host smart-2da5e482-2b7d-4848-a1d8-595169a6082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459444017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3459444017
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1026057983
Short name T942
Test name
Test status
Simulation time 590629610 ps
CPU time 13.67 seconds
Started Apr 02 03:36:38 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 244828 kb
Host smart-10002db2-e7d2-4df6-a27a-803cc2b1cf40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026057983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1026057983
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1292810918
Short name T494
Test name
Test status
Simulation time 9570534394 ps
CPU time 38.54 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:37:25 PM PDT 24
Peak memory 212064 kb
Host smart-15753c2e-2114-4b99-98cd-e4d0adbf50fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292810918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1292810918
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.219145670
Short name T161
Test name
Test status
Simulation time 2741330360 ps
CPU time 41.2 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 497828 kb
Host smart-4348b073-8466-4f1b-a574-63ba54afc1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219145670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.219145670
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3963300218
Short name T376
Test name
Test status
Simulation time 144580484 ps
CPU time 1.11 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:45 PM PDT 24
Peak memory 203764 kb
Host smart-ae6438df-8458-4bf2-a700-b62a5a1f6d3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963300218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3963300218
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.919004303
Short name T300
Test name
Test status
Simulation time 226051583 ps
CPU time 2.86 seconds
Started Apr 02 03:36:34 PM PDT 24
Finished Apr 02 03:36:36 PM PDT 24
Peak memory 218760 kb
Host smart-96756fce-090b-4f5e-807b-d766aac84ea5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919004303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.919004303
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.514928902
Short name T155
Test name
Test status
Simulation time 3173335832 ps
CPU time 71.87 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:37:49 PM PDT 24
Peak memory 958696 kb
Host smart-1d30b315-4242-4164-bbc8-45607439606a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514928902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.514928902
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.4208764386
Short name T421
Test name
Test status
Simulation time 1376347395 ps
CPU time 5.33 seconds
Started Apr 02 03:36:30 PM PDT 24
Finished Apr 02 03:36:36 PM PDT 24
Peak memory 203836 kb
Host smart-ec9d86e6-68df-43e2-8494-6393af717440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208764386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.4208764386
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3153659047
Short name T482
Test name
Test status
Simulation time 6466900112 ps
CPU time 31.11 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:37:08 PM PDT 24
Peak memory 446376 kb
Host smart-9f1b356f-772d-420f-b3ec-587721565e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153659047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3153659047
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2484832539
Short name T352
Test name
Test status
Simulation time 74906585 ps
CPU time 0.66 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:36:36 PM PDT 24
Peak memory 203604 kb
Host smart-6fa15cb6-27e3-4dec-8b80-7accc3b18ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484832539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2484832539
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.243834659
Short name T47
Test name
Test status
Simulation time 28776976165 ps
CPU time 132.84 seconds
Started Apr 02 03:36:35 PM PDT 24
Finished Apr 02 03:38:48 PM PDT 24
Peak memory 365620 kb
Host smart-269fda3c-1864-4a19-93e0-15f479b2a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243834659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.243834659
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1313236478
Short name T615
Test name
Test status
Simulation time 720658760 ps
CPU time 11.55 seconds
Started Apr 02 03:36:45 PM PDT 24
Finished Apr 02 03:36:56 PM PDT 24
Peak memory 284396 kb
Host smart-2374bb35-189a-480c-876d-6d936bc6274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313236478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1313236478
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1937715270
Short name T100
Test name
Test status
Simulation time 308193628 ps
CPU time 0.89 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:44 PM PDT 24
Peak memory 222396 kb
Host smart-666f95df-6f2b-42de-aa67-bc90785b05c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937715270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1937715270
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1734391822
Short name T574
Test name
Test status
Simulation time 3937601064 ps
CPU time 4.51 seconds
Started Apr 02 03:36:39 PM PDT 24
Finished Apr 02 03:36:43 PM PDT 24
Peak memory 203856 kb
Host smart-60dd4a4d-da9d-4c51-bde8-0f24b113baa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734391822 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1734391822
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2776674142
Short name T751
Test name
Test status
Simulation time 10482915754 ps
CPU time 5.43 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:42 PM PDT 24
Peak memory 239464 kb
Host smart-a4044a7d-4dc3-47e3-8fe6-4dd2d55c8be4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776674142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2776674142
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2549838332
Short name T1100
Test name
Test status
Simulation time 10471635479 ps
CPU time 31.45 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:37:15 PM PDT 24
Peak memory 454236 kb
Host smart-a8d0ff51-715b-4d65-b43c-14005fa69698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549838332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2549838332
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.749644625
Short name T1152
Test name
Test status
Simulation time 2083660312 ps
CPU time 3.13 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:36:34 PM PDT 24
Peak memory 203680 kb
Host smart-aee9f0ff-e0f9-4019-982a-1b26db632880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749644625 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.749644625
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.984494038
Short name T954
Test name
Test status
Simulation time 1633952429 ps
CPU time 4.33 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 204392 kb
Host smart-17c380ed-de6a-4307-a7c3-4b7cb58f98f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984494038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.984494038
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3490553860
Short name T1066
Test name
Test status
Simulation time 6717966687 ps
CPU time 5.14 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 203856 kb
Host smart-a1a735e6-1ea6-4ae7-83c3-6130a66a380c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490553860 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3490553860
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2898260652
Short name T171
Test name
Test status
Simulation time 1230946440 ps
CPU time 46.9 seconds
Started Apr 02 03:36:32 PM PDT 24
Finished Apr 02 03:37:19 PM PDT 24
Peak memory 203812 kb
Host smart-625fc728-69bc-4022-b60d-004fdceea47d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898260652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2898260652
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2602386745
Short name T727
Test name
Test status
Simulation time 5817842514 ps
CPU time 26.62 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:37:08 PM PDT 24
Peak memory 223368 kb
Host smart-4fa04eb0-8691-41c6-aa0d-28ef2a21b4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602386745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2602386745
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3839041023
Short name T255
Test name
Test status
Simulation time 2750963859 ps
CPU time 49.83 seconds
Started Apr 02 03:36:39 PM PDT 24
Finished Apr 02 03:37:29 PM PDT 24
Peak memory 796708 kb
Host smart-4ceff69c-5695-4dc8-ae0f-579186c5c0ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839041023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3839041023
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.485738430
Short name T1032
Test name
Test status
Simulation time 2288574090 ps
CPU time 5.99 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:48 PM PDT 24
Peak memory 203872 kb
Host smart-1af65d76-ed5e-478b-bfe5-c12652139275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485738430 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.485738430
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1480552745
Short name T905
Test name
Test status
Simulation time 22254470 ps
CPU time 0.66 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:39:13 PM PDT 24
Peak memory 203660 kb
Host smart-f39df7fe-d10f-4420-ad70-0cea7cdc1461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480552745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1480552745
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.4216828321
Short name T550
Test name
Test status
Simulation time 368369917 ps
CPU time 1.5 seconds
Started Apr 02 03:38:54 PM PDT 24
Finished Apr 02 03:38:55 PM PDT 24
Peak memory 212092 kb
Host smart-b6947b7b-af6d-44ab-9a17-302c5dc0da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216828321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.4216828321
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3656730444
Short name T49
Test name
Test status
Simulation time 761766441 ps
CPU time 7.43 seconds
Started Apr 02 03:38:57 PM PDT 24
Finished Apr 02 03:39:05 PM PDT 24
Peak memory 283180 kb
Host smart-9b352e67-4b71-4bb4-8c83-d29b75126478
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656730444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3656730444
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.285836183
Short name T1134
Test name
Test status
Simulation time 2303303141 ps
CPU time 72.06 seconds
Started Apr 02 03:38:57 PM PDT 24
Finished Apr 02 03:40:10 PM PDT 24
Peak memory 408964 kb
Host smart-40f34f05-1b16-4176-88da-ea88e21e623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285836183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.285836183
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.4062569939
Short name T850
Test name
Test status
Simulation time 4244448516 ps
CPU time 163.83 seconds
Started Apr 02 03:38:58 PM PDT 24
Finished Apr 02 03:41:42 PM PDT 24
Peak memory 733312 kb
Host smart-3109b79d-1aef-4621-832e-846c9a0cd1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062569939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.4062569939
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.865507438
Short name T900
Test name
Test status
Simulation time 76782907 ps
CPU time 0.92 seconds
Started Apr 02 03:38:58 PM PDT 24
Finished Apr 02 03:39:00 PM PDT 24
Peak memory 203708 kb
Host smart-80b50341-a272-4a2f-a312-f1a65e592cbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865507438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.865507438
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.58309968
Short name T87
Test name
Test status
Simulation time 614068052 ps
CPU time 8 seconds
Started Apr 02 03:38:56 PM PDT 24
Finished Apr 02 03:39:05 PM PDT 24
Peak memory 203832 kb
Host smart-55044db8-893f-4e92-a683-849a539e29c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58309968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.58309968
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.841411656
Short name T1156
Test name
Test status
Simulation time 11282772376 ps
CPU time 132.3 seconds
Started Apr 02 03:38:59 PM PDT 24
Finished Apr 02 03:41:13 PM PDT 24
Peak memory 710668 kb
Host smart-21177508-890e-4331-af34-299a5b775aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841411656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.841411656
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2375053938
Short name T321
Test name
Test status
Simulation time 1327567463 ps
CPU time 13.9 seconds
Started Apr 02 03:39:04 PM PDT 24
Finished Apr 02 03:39:18 PM PDT 24
Peak memory 203776 kb
Host smart-45b0aaa3-cf7d-4321-bbca-425a6341d8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375053938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2375053938
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1955708985
Short name T633
Test name
Test status
Simulation time 1251558234 ps
CPU time 27.36 seconds
Started Apr 02 03:39:05 PM PDT 24
Finished Apr 02 03:39:34 PM PDT 24
Peak memory 382132 kb
Host smart-44b6b96e-22a2-48d9-ba01-590f10965089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955708985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1955708985
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3526521382
Short name T182
Test name
Test status
Simulation time 32462668 ps
CPU time 0.68 seconds
Started Apr 02 03:39:00 PM PDT 24
Finished Apr 02 03:39:01 PM PDT 24
Peak memory 203580 kb
Host smart-00ff8bda-b376-419d-9a00-eccd768cea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526521382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3526521382
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3500579299
Short name T979
Test name
Test status
Simulation time 28296520954 ps
CPU time 55 seconds
Started Apr 02 03:38:59 PM PDT 24
Finished Apr 02 03:39:55 PM PDT 24
Peak memory 644288 kb
Host smart-ce855635-2ce2-4631-bc78-232fe3a3795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500579299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3500579299
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2306229506
Short name T258
Test name
Test status
Simulation time 2139947603 ps
CPU time 19.47 seconds
Started Apr 02 03:38:59 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 328776 kb
Host smart-f78cbd2d-0f8b-4cbb-8dda-1f3e6538f339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306229506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2306229506
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.4030638631
Short name T519
Test name
Test status
Simulation time 874946802 ps
CPU time 4.35 seconds
Started Apr 02 03:39:02 PM PDT 24
Finished Apr 02 03:39:06 PM PDT 24
Peak memory 211988 kb
Host smart-84aaff3d-f9d0-499b-af4e-3646510b22a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030638631 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.4030638631
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1516329958
Short name T577
Test name
Test status
Simulation time 10061130773 ps
CPU time 81.12 seconds
Started Apr 02 03:39:00 PM PDT 24
Finished Apr 02 03:40:22 PM PDT 24
Peak memory 601072 kb
Host smart-e22c6e4a-a7b6-4862-871d-9d8a79f79096
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516329958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1516329958
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.4170513423
Short name T910
Test name
Test status
Simulation time 10169220809 ps
CPU time 13.58 seconds
Started Apr 02 03:38:59 PM PDT 24
Finished Apr 02 03:39:14 PM PDT 24
Peak memory 303900 kb
Host smart-4afc9d50-2d8c-4beb-950a-e42b2172897f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170513423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.4170513423
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2661795804
Short name T835
Test name
Test status
Simulation time 317629013 ps
CPU time 2.16 seconds
Started Apr 02 03:39:02 PM PDT 24
Finished Apr 02 03:39:04 PM PDT 24
Peak memory 203816 kb
Host smart-4682bc4e-ea2e-401c-a5ff-52f363ddadd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661795804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2661795804
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1632046930
Short name T73
Test name
Test status
Simulation time 737249763 ps
CPU time 4.46 seconds
Started Apr 02 03:39:03 PM PDT 24
Finished Apr 02 03:39:08 PM PDT 24
Peak memory 206556 kb
Host smart-d5f97184-34f1-4136-a003-79e27f5af655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632046930 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1632046930
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.134456975
Short name T609
Test name
Test status
Simulation time 2107643184 ps
CPU time 33.99 seconds
Started Apr 02 03:38:57 PM PDT 24
Finished Apr 02 03:39:32 PM PDT 24
Peak memory 203676 kb
Host smart-2695bbe6-7251-4bfd-b089-1eef1e040df5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134456975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.134456975
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3630725881
Short name T783
Test name
Test status
Simulation time 1293564197 ps
CPU time 20.63 seconds
Started Apr 02 03:38:58 PM PDT 24
Finished Apr 02 03:39:19 PM PDT 24
Peak memory 225212 kb
Host smart-f4d207b5-b86a-462e-a4fc-ef11fbc41938
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630725881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3630725881
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.650946320
Short name T1129
Test name
Test status
Simulation time 21458859401 ps
CPU time 112.96 seconds
Started Apr 02 03:38:59 PM PDT 24
Finished Apr 02 03:40:54 PM PDT 24
Peak memory 1098860 kb
Host smart-30a242c3-3809-47e6-bb88-c73ddb4482b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650946320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_t
arget_stretch.650946320
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.731007529
Short name T364
Test name
Test status
Simulation time 1651452470 ps
CPU time 8.38 seconds
Started Apr 02 03:39:00 PM PDT 24
Finished Apr 02 03:39:09 PM PDT 24
Peak memory 215012 kb
Host smart-ebb261f0-c222-49da-a7d6-e692b99baa13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731007529 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.731007529
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.355223535
Short name T1183
Test name
Test status
Simulation time 16466940 ps
CPU time 0.6 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:39:13 PM PDT 24
Peak memory 203644 kb
Host smart-e13a0c0b-ff31-4ae5-839e-39722c248506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355223535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.355223535
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1919298005
Short name T591
Test name
Test status
Simulation time 237279680 ps
CPU time 1.1 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:39:12 PM PDT 24
Peak memory 211996 kb
Host smart-765eaf14-ed7f-46ea-80a0-696690b5071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919298005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1919298005
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.27960015
Short name T338
Test name
Test status
Simulation time 1070248211 ps
CPU time 7.47 seconds
Started Apr 02 03:39:01 PM PDT 24
Finished Apr 02 03:39:09 PM PDT 24
Peak memory 226692 kb
Host smart-c1d7f44b-72f3-4768-9df2-758f08c94820
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27960015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty
.27960015
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1668429810
Short name T379
Test name
Test status
Simulation time 10945424617 ps
CPU time 66.88 seconds
Started Apr 02 03:39:03 PM PDT 24
Finished Apr 02 03:40:10 PM PDT 24
Peak memory 694244 kb
Host smart-4c38d75d-8b10-4790-ab24-e467125243eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668429810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1668429810
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3004133209
Short name T260
Test name
Test status
Simulation time 7753023330 ps
CPU time 115.37 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:41:06 PM PDT 24
Peak memory 608324 kb
Host smart-0d509bcc-0d1c-49fd-b0d2-973fbec9adf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004133209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3004133209
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1075469339
Short name T923
Test name
Test status
Simulation time 393728578 ps
CPU time 0.88 seconds
Started Apr 02 03:39:04 PM PDT 24
Finished Apr 02 03:39:05 PM PDT 24
Peak memory 203656 kb
Host smart-fce3717b-5869-40c9-b1f4-67c350a69555
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075469339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1075469339
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2927717082
Short name T1012
Test name
Test status
Simulation time 633897120 ps
CPU time 7.71 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 203744 kb
Host smart-2cadf12d-658c-44fc-824c-c9c268c1c6f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927717082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2927717082
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.318591578
Short name T446
Test name
Test status
Simulation time 4121377361 ps
CPU time 328.11 seconds
Started Apr 02 03:39:03 PM PDT 24
Finished Apr 02 03:44:31 PM PDT 24
Peak memory 1226800 kb
Host smart-703f6675-30be-4220-a2e7-a07bee82222d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318591578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.318591578
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.4007293263
Short name T1150
Test name
Test status
Simulation time 4188309298 ps
CPU time 7.67 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:39:19 PM PDT 24
Peak memory 203864 kb
Host smart-7cda13e2-8777-46b9-9f61-b2bc5cc4206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007293263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.4007293263
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1870333335
Short name T1000
Test name
Test status
Simulation time 6220112360 ps
CPU time 22.73 seconds
Started Apr 02 03:39:14 PM PDT 24
Finished Apr 02 03:39:39 PM PDT 24
Peak memory 325932 kb
Host smart-77955031-3ead-4ab0-a8f8-3120f31b6426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870333335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1870333335
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.3715009785
Short name T322
Test name
Test status
Simulation time 29779212 ps
CPU time 0.7 seconds
Started Apr 02 03:39:04 PM PDT 24
Finished Apr 02 03:39:05 PM PDT 24
Peak memory 203576 kb
Host smart-e7d8acb4-3a32-4067-b566-f6c9bec98b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715009785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3715009785
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2954564376
Short name T249
Test name
Test status
Simulation time 1565952157 ps
CPU time 35.99 seconds
Started Apr 02 03:39:04 PM PDT 24
Finished Apr 02 03:39:40 PM PDT 24
Peak memory 285188 kb
Host smart-7a1ecca0-c94e-4f4b-8a59-edea7eef89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954564376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2954564376
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2188869267
Short name T1085
Test name
Test status
Simulation time 2025157544 ps
CPU time 21.47 seconds
Started Apr 02 03:39:04 PM PDT 24
Finished Apr 02 03:39:26 PM PDT 24
Peak memory 343040 kb
Host smart-efb5676b-2a18-4bfe-8087-8f4aaedb7501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188869267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2188869267
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.4189949689
Short name T348
Test name
Test status
Simulation time 695344480 ps
CPU time 3.04 seconds
Started Apr 02 03:39:06 PM PDT 24
Finished Apr 02 03:39:10 PM PDT 24
Peak memory 203776 kb
Host smart-d3ce2325-20b1-43da-8331-7f676ddf4e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189949689 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.4189949689
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3468100038
Short name T1113
Test name
Test status
Simulation time 10070088187 ps
CPU time 30.79 seconds
Started Apr 02 03:39:07 PM PDT 24
Finished Apr 02 03:39:38 PM PDT 24
Peak memory 399904 kb
Host smart-1542e20a-59f2-4b25-87ae-091acbcd43ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468100038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3468100038
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1882151507
Short name T345
Test name
Test status
Simulation time 10067262544 ps
CPU time 99.44 seconds
Started Apr 02 03:39:07 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 759416 kb
Host smart-7b8d31ae-5914-4b93-a3b4-66e3c581c812
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882151507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1882151507
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2450085123
Short name T1007
Test name
Test status
Simulation time 557803002 ps
CPU time 2.98 seconds
Started Apr 02 03:39:14 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 203844 kb
Host smart-653298fb-85c0-4044-8fbc-c22823c6a48c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450085123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2450085123
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3586596691
Short name T693
Test name
Test status
Simulation time 2565396076 ps
CPU time 4.59 seconds
Started Apr 02 03:39:06 PM PDT 24
Finished Apr 02 03:39:12 PM PDT 24
Peak memory 203904 kb
Host smart-ed43487c-d5a8-46f1-aff2-ee36e477c2ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586596691 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3586596691
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3002639494
Short name T272
Test name
Test status
Simulation time 1139230213 ps
CPU time 33.8 seconds
Started Apr 02 03:39:02 PM PDT 24
Finished Apr 02 03:39:36 PM PDT 24
Peak memory 203804 kb
Host smart-faf74f23-8072-4556-a464-abae687684e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002639494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3002639494
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2856858788
Short name T1076
Test name
Test status
Simulation time 3091914616 ps
CPU time 10.35 seconds
Started Apr 02 03:39:03 PM PDT 24
Finished Apr 02 03:39:14 PM PDT 24
Peak memory 212636 kb
Host smart-24cfebdf-0b93-4a7a-843c-b33e8ae870ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856858788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2856858788
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.676001876
Short name T483
Test name
Test status
Simulation time 32657901356 ps
CPU time 2454.83 seconds
Started Apr 02 03:39:03 PM PDT 24
Finished Apr 02 04:19:59 PM PDT 24
Peak memory 7852436 kb
Host smart-f84ac411-b12e-424a-9034-e4e3e33fa6ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676001876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.676001876
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3600196456
Short name T865
Test name
Test status
Simulation time 2347046427 ps
CPU time 6.83 seconds
Started Apr 02 03:39:09 PM PDT 24
Finished Apr 02 03:39:16 PM PDT 24
Peak memory 220124 kb
Host smart-2f9118f5-5046-4ea5-92e6-9f679c290002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600196456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3600196456
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2229032162
Short name T105
Test name
Test status
Simulation time 53643988 ps
CPU time 0.59 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:39:13 PM PDT 24
Peak memory 203724 kb
Host smart-c018b1ed-5cff-4ecd-8b02-7ff2e28f70ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229032162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2229032162
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3114440093
Short name T614
Test name
Test status
Simulation time 102265120 ps
CPU time 1.31 seconds
Started Apr 02 03:39:09 PM PDT 24
Finished Apr 02 03:39:10 PM PDT 24
Peak memory 212024 kb
Host smart-7f7cbf2a-6792-4ac7-b07b-641a4efde5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114440093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3114440093
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.56909091
Short name T932
Test name
Test status
Simulation time 1758380274 ps
CPU time 6.55 seconds
Started Apr 02 03:39:09 PM PDT 24
Finished Apr 02 03:39:15 PM PDT 24
Peak memory 265364 kb
Host smart-432771e0-9472-471a-b912-071090b7a4a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56909091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty
.56909091
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.866620832
Short name T403
Test name
Test status
Simulation time 1812535405 ps
CPU time 124.34 seconds
Started Apr 02 03:39:08 PM PDT 24
Finished Apr 02 03:41:12 PM PDT 24
Peak memory 633880 kb
Host smart-ed30b70d-93b3-498f-8b9e-bd1fe65a7a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866620832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.866620832
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3676848028
Short name T340
Test name
Test status
Simulation time 7003366105 ps
CPU time 54.44 seconds
Started Apr 02 03:39:07 PM PDT 24
Finished Apr 02 03:40:01 PM PDT 24
Peak memory 640496 kb
Host smart-b7e00d68-70b4-4026-a0be-388c41c3034f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676848028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3676848028
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2141861297
Short name T411
Test name
Test status
Simulation time 462659352 ps
CPU time 1.15 seconds
Started Apr 02 03:39:08 PM PDT 24
Finished Apr 02 03:39:09 PM PDT 24
Peak memory 203844 kb
Host smart-802d5104-9c30-4fdf-9308-cedfcb599280
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141861297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2141861297
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.798766663
Short name T1070
Test name
Test status
Simulation time 133190918 ps
CPU time 3.58 seconds
Started Apr 02 03:39:06 PM PDT 24
Finished Apr 02 03:39:11 PM PDT 24
Peak memory 203744 kb
Host smart-511898ae-a2f3-472e-802c-149700e62c77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798766663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
798766663
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2479198330
Short name T153
Test name
Test status
Simulation time 12901416120 ps
CPU time 56.57 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:40:09 PM PDT 24
Peak memory 844296 kb
Host smart-559c01f9-4e04-4a1e-985c-baef3df895c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479198330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2479198330
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2584513816
Short name T1121
Test name
Test status
Simulation time 1001081867 ps
CPU time 20.81 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:39:32 PM PDT 24
Peak memory 203828 kb
Host smart-e229c83e-e4b8-404d-8aa5-f2b96b78adb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584513816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2584513816
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.2470351669
Short name T25
Test name
Test status
Simulation time 2991095561 ps
CPU time 76.96 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:40:28 PM PDT 24
Peak memory 417792 kb
Host smart-664ff757-cec0-4ce1-a433-3201ba7af2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470351669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2470351669
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3467783622
Short name T674
Test name
Test status
Simulation time 17826380 ps
CPU time 0.63 seconds
Started Apr 02 03:39:09 PM PDT 24
Finished Apr 02 03:39:09 PM PDT 24
Peak memory 203584 kb
Host smart-c2096a50-94a8-41f5-b974-a0a0bc45e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467783622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3467783622
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2770384268
Short name T1157
Test name
Test status
Simulation time 25409791395 ps
CPU time 1044.95 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:56:39 PM PDT 24
Peak memory 238548 kb
Host smart-89f1ac7d-3d29-4bf4-a84a-a5fd76ed9ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770384268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2770384268
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2963857850
Short name T621
Test name
Test status
Simulation time 1079869058 ps
CPU time 22.06 seconds
Started Apr 02 03:39:14 PM PDT 24
Finished Apr 02 03:39:39 PM PDT 24
Peak memory 317340 kb
Host smart-3c6f2d17-2dd3-483d-bca1-bc357f8e8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963857850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2963857850
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1051402173
Short name T655
Test name
Test status
Simulation time 3211867845 ps
CPU time 5.06 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:39:17 PM PDT 24
Peak memory 203876 kb
Host smart-97e2f912-f051-4d78-a039-0c2cf2386020
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051402173 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1051402173
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1159104829
Short name T1189
Test name
Test status
Simulation time 10193473163 ps
CPU time 14.36 seconds
Started Apr 02 03:39:10 PM PDT 24
Finished Apr 02 03:39:25 PM PDT 24
Peak memory 275092 kb
Host smart-04f0182d-5344-4938-a62d-650316059683
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159104829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1159104829
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3512903588
Short name T251
Test name
Test status
Simulation time 10283191015 ps
CPU time 18.08 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:39:32 PM PDT 24
Peak memory 340320 kb
Host smart-370c6526-211e-4ef8-aee3-248aa257499a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512903588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3512903588
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3295045383
Short name T868
Test name
Test status
Simulation time 582550509 ps
CPU time 3.26 seconds
Started Apr 02 03:39:11 PM PDT 24
Finished Apr 02 03:39:14 PM PDT 24
Peak memory 203716 kb
Host smart-152d3ae2-e3b4-4e7f-8390-6deff00896dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295045383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3295045383
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.4074943138
Short name T815
Test name
Test status
Simulation time 5009981136 ps
CPU time 6.4 seconds
Started Apr 02 03:39:14 PM PDT 24
Finished Apr 02 03:39:23 PM PDT 24
Peak memory 211976 kb
Host smart-cf3b0221-c416-4054-8549-d0c50bdb31e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074943138 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.4074943138
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3165159009
Short name T712
Test name
Test status
Simulation time 5343025676 ps
CPU time 20.51 seconds
Started Apr 02 03:39:08 PM PDT 24
Finished Apr 02 03:39:28 PM PDT 24
Peak memory 203864 kb
Host smart-202783b4-feee-4fff-89e9-1551b8023930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165159009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3165159009
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2272771084
Short name T972
Test name
Test status
Simulation time 4950417734 ps
CPU time 23.92 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:39:36 PM PDT 24
Peak memory 237276 kb
Host smart-2695740c-aa23-45fd-a8c5-5a4d80cb0c4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272771084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2272771084
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1311320577
Short name T55
Test name
Test status
Simulation time 36041759655 ps
CPU time 884 seconds
Started Apr 02 03:39:10 PM PDT 24
Finished Apr 02 03:53:54 PM PDT 24
Peak memory 4302752 kb
Host smart-af2eb31a-b2d4-47d3-8f73-28274b77f34d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311320577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1311320577
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1396714025
Short name T720
Test name
Test status
Simulation time 4531212784 ps
CPU time 6.99 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:39:19 PM PDT 24
Peak memory 211708 kb
Host smart-d5ca5dbf-f502-4eec-9d85-53976f68c877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396714025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1396714025
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.4248292140
Short name T1052
Test name
Test status
Simulation time 309343244 ps
CPU time 0.65 seconds
Started Apr 02 03:39:17 PM PDT 24
Finished Apr 02 03:39:19 PM PDT 24
Peak memory 203684 kb
Host smart-6e7e039c-0187-4110-8d6b-2353a69974f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248292140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.4248292140
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1584523626
Short name T280
Test name
Test status
Simulation time 149293459 ps
CPU time 1.39 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:39:18 PM PDT 24
Peak memory 212092 kb
Host smart-1b666bbf-c238-442e-9159-f287e0cca59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584523626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1584523626
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3203862261
Short name T792
Test name
Test status
Simulation time 770910763 ps
CPU time 8.45 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:39:21 PM PDT 24
Peak memory 279812 kb
Host smart-ace7470b-5386-4822-9b11-618d700b2f1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203862261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3203862261
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3532511823
Short name T84
Test name
Test status
Simulation time 9957506639 ps
CPU time 70.04 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:40:24 PM PDT 24
Peak memory 402120 kb
Host smart-d47554c5-a1b7-4cbe-81d5-8f116b6277c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532511823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3532511823
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3196777720
Short name T883
Test name
Test status
Simulation time 1515399025 ps
CPU time 41.74 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 525408 kb
Host smart-04bd1497-a82e-4a4c-be09-4bba4ffa61a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196777720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3196777720
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.4021438943
Short name T418
Test name
Test status
Simulation time 127551413 ps
CPU time 1.01 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:39:18 PM PDT 24
Peak memory 203696 kb
Host smart-2d4b46af-c088-4724-ac57-a44b7fa2eb0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021438943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.4021438943
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1746858557
Short name T607
Test name
Test status
Simulation time 128191430 ps
CPU time 3.2 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:39:17 PM PDT 24
Peak memory 223840 kb
Host smart-a445af46-8730-43b1-9344-995ede258327
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746858557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1746858557
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2581154614
Short name T1067
Test name
Test status
Simulation time 4828103983 ps
CPU time 130.78 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:41:24 PM PDT 24
Peak memory 1286300 kb
Host smart-b45cb3a9-ed51-4667-b04d-32a5ca01fbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581154614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2581154614
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2733186907
Short name T1178
Test name
Test status
Simulation time 148814680 ps
CPU time 2.52 seconds
Started Apr 02 03:39:18 PM PDT 24
Finished Apr 02 03:39:21 PM PDT 24
Peak memory 203840 kb
Host smart-e223372e-463d-4629-bdc3-f748a51e7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733186907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2733186907
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.76308507
Short name T160
Test name
Test status
Simulation time 3269951882 ps
CPU time 27.96 seconds
Started Apr 02 03:39:20 PM PDT 24
Finished Apr 02 03:39:48 PM PDT 24
Peak memory 388492 kb
Host smart-e6b8dcd0-3726-45d0-9de6-bee01ef5cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76308507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.76308507
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2410868704
Short name T647
Test name
Test status
Simulation time 25174394 ps
CPU time 0.67 seconds
Started Apr 02 03:39:12 PM PDT 24
Finished Apr 02 03:39:13 PM PDT 24
Peak memory 203608 kb
Host smart-30784f9b-f2b4-4d2c-b892-18edb9dfba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410868704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2410868704
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3785438601
Short name T186
Test name
Test status
Simulation time 17925744433 ps
CPU time 665.97 seconds
Started Apr 02 03:39:16 PM PDT 24
Finished Apr 02 03:50:23 PM PDT 24
Peak memory 203856 kb
Host smart-4cf1c793-3d05-4a31-b5e5-9b60504ff2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785438601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3785438601
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3904760539
Short name T843
Test name
Test status
Simulation time 871809562 ps
CPU time 41.92 seconds
Started Apr 02 03:39:10 PM PDT 24
Finished Apr 02 03:39:52 PM PDT 24
Peak memory 297840 kb
Host smart-33950016-44fb-49b2-a5d8-eb1300004895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904760539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3904760539
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1545485386
Short name T398
Test name
Test status
Simulation time 1877477164 ps
CPU time 4.59 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:39:21 PM PDT 24
Peak memory 203784 kb
Host smart-de33125a-6b90-41c3-aea7-a5ed23d25ca0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545485386 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1545485386
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.588639957
Short name T788
Test name
Test status
Simulation time 10384354116 ps
CPU time 14.78 seconds
Started Apr 02 03:39:15 PM PDT 24
Finished Apr 02 03:39:32 PM PDT 24
Peak memory 305604 kb
Host smart-00393e5d-5e51-4dd1-aa81-5c40c22074e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588639957 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.588639957
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.4006196002
Short name T941
Test name
Test status
Simulation time 2140409131 ps
CPU time 3.07 seconds
Started Apr 02 03:39:14 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 203844 kb
Host smart-b6129ed4-3771-4068-b21f-907a4de6e4c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006196002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.4006196002
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.119348060
Short name T330
Test name
Test status
Simulation time 1074441842 ps
CPU time 5.54 seconds
Started Apr 02 03:39:14 PM PDT 24
Finished Apr 02 03:39:22 PM PDT 24
Peak memory 212036 kb
Host smart-926fb486-a431-49e2-9604-fc2e8ab70c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119348060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.119348060
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.107980261
Short name T106
Test name
Test status
Simulation time 818560430 ps
CPU time 31.83 seconds
Started Apr 02 03:39:13 PM PDT 24
Finished Apr 02 03:39:46 PM PDT 24
Peak memory 203764 kb
Host smart-167dbc69-e09f-4cc3-ab10-d4f7973f076e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107980261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.107980261
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1616071015
Short name T1179
Test name
Test status
Simulation time 12142698652 ps
CPU time 11.81 seconds
Started Apr 02 03:39:16 PM PDT 24
Finished Apr 02 03:39:30 PM PDT 24
Peak memory 208172 kb
Host smart-2344e569-dee2-4729-87fb-223c2e02d9f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616071015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1616071015
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1854272041
Short name T383
Test name
Test status
Simulation time 15194605237 ps
CPU time 573.02 seconds
Started Apr 02 03:39:15 PM PDT 24
Finished Apr 02 03:48:50 PM PDT 24
Peak memory 3321168 kb
Host smart-bec3d21b-a440-418f-979d-d7bc3f77f0b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854272041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1854272041
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2373057263
Short name T241
Test name
Test status
Simulation time 15720386190 ps
CPU time 6.49 seconds
Started Apr 02 03:39:15 PM PDT 24
Finished Apr 02 03:39:23 PM PDT 24
Peak memory 212088 kb
Host smart-3d997e8e-b5e2-4d79-9591-4e0a75dd76ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373057263 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2373057263
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.1806291239
Short name T442
Test name
Test status
Simulation time 1631680651 ps
CPU time 7.08 seconds
Started Apr 02 03:39:16 PM PDT 24
Finished Apr 02 03:39:24 PM PDT 24
Peak memory 203812 kb
Host smart-a62d868b-6d03-421a-aabd-4ea5c3139ee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806291239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.i2c_target_unexp_stop.1806291239
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2491930247
Short name T561
Test name
Test status
Simulation time 59189599 ps
CPU time 0.65 seconds
Started Apr 02 03:39:24 PM PDT 24
Finished Apr 02 03:39:25 PM PDT 24
Peak memory 203704 kb
Host smart-297bb88a-32b8-4d93-8818-2e83efc8d288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491930247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2491930247
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1598038674
Short name T397
Test name
Test status
Simulation time 171516974 ps
CPU time 1.88 seconds
Started Apr 02 03:39:23 PM PDT 24
Finished Apr 02 03:39:25 PM PDT 24
Peak memory 212052 kb
Host smart-dc87e155-22df-4234-925b-a0bf1c3419f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598038674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1598038674
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1356064080
Short name T361
Test name
Test status
Simulation time 1158657828 ps
CPU time 12.58 seconds
Started Apr 02 03:39:19 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 247556 kb
Host smart-1c8f1d68-0d84-45bc-a6a7-31168d9f4313
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356064080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1356064080
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.4179607548
Short name T685
Test name
Test status
Simulation time 2608506288 ps
CPU time 38.98 seconds
Started Apr 02 03:39:19 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 513512 kb
Host smart-67117a7f-2bf3-41dc-aff2-f8a3238fde56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179607548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.4179607548
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1377842319
Short name T837
Test name
Test status
Simulation time 2348586762 ps
CPU time 73.97 seconds
Started Apr 02 03:39:18 PM PDT 24
Finished Apr 02 03:40:32 PM PDT 24
Peak memory 699444 kb
Host smart-83b2a5ce-f375-49e0-ad5e-e35f662c7daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377842319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1377842319
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2850309407
Short name T197
Test name
Test status
Simulation time 139202168 ps
CPU time 1.06 seconds
Started Apr 02 03:39:22 PM PDT 24
Finished Apr 02 03:39:23 PM PDT 24
Peak memory 203712 kb
Host smart-daeb9518-c90d-4c7a-bf46-8060bdcdbe6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850309407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2850309407
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1839875194
Short name T15
Test name
Test status
Simulation time 694223041 ps
CPU time 3.34 seconds
Started Apr 02 03:39:17 PM PDT 24
Finished Apr 02 03:39:20 PM PDT 24
Peak memory 223264 kb
Host smart-079d9f26-a2b5-43ae-b27e-233e085a3d13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839875194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1839875194
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2955061811
Short name T911
Test name
Test status
Simulation time 3323233288 ps
CPU time 75.22 seconds
Started Apr 02 03:39:16 PM PDT 24
Finished Apr 02 03:40:32 PM PDT 24
Peak memory 885156 kb
Host smart-b2964934-8a44-411a-ac0b-04d10a1a8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955061811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2955061811
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2140911180
Short name T977
Test name
Test status
Simulation time 829322867 ps
CPU time 16.53 seconds
Started Apr 02 03:39:29 PM PDT 24
Finished Apr 02 03:39:45 PM PDT 24
Peak memory 203844 kb
Host smart-a7f8f4dd-b36c-47a2-83e1-c9fa6c9c7ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140911180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2140911180
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1595533909
Short name T447
Test name
Test status
Simulation time 6669989164 ps
CPU time 88.6 seconds
Started Apr 02 03:39:24 PM PDT 24
Finished Apr 02 03:40:53 PM PDT 24
Peak memory 429720 kb
Host smart-e43e4397-3ba2-4077-a7ff-291002359064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595533909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1595533909
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.4235125924
Short name T13
Test name
Test status
Simulation time 31563888 ps
CPU time 0.7 seconds
Started Apr 02 03:39:18 PM PDT 24
Finished Apr 02 03:39:19 PM PDT 24
Peak memory 203524 kb
Host smart-4fdb1ddc-17f4-4fb3-96aa-5e36ab6583db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235125924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.4235125924
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2023848470
Short name T1106
Test name
Test status
Simulation time 5318639313 ps
CPU time 34.37 seconds
Started Apr 02 03:39:25 PM PDT 24
Finished Apr 02 03:40:00 PM PDT 24
Peak memory 529684 kb
Host smart-adbec3dc-2401-4fd4-bb0a-d41c9ebf1917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023848470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2023848470
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3539861568
Short name T1181
Test name
Test status
Simulation time 5558343667 ps
CPU time 16.75 seconds
Started Apr 02 03:39:19 PM PDT 24
Finished Apr 02 03:39:35 PM PDT 24
Peak memory 302924 kb
Host smart-2ab69bd1-26d4-45b7-a4a1-5d848e732b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539861568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3539861568
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1022296401
Short name T248
Test name
Test status
Simulation time 619024145 ps
CPU time 3.01 seconds
Started Apr 02 03:39:28 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 203856 kb
Host smart-e6f8fc67-15b9-49f9-aea9-c25fdbd1a8eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022296401 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1022296401
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.593547900
Short name T1182
Test name
Test status
Simulation time 10190978677 ps
CPU time 33.06 seconds
Started Apr 02 03:39:24 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 396736 kb
Host smart-ff1c45c2-7d07-413c-9f4b-49d4e55385aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593547900 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.593547900
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2595600281
Short name T530
Test name
Test status
Simulation time 10171947017 ps
CPU time 40.73 seconds
Started Apr 02 03:39:30 PM PDT 24
Finished Apr 02 03:40:11 PM PDT 24
Peak memory 459132 kb
Host smart-7b1b103c-cd86-4970-8cc1-b3e7a4b8c438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595600281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2595600281
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1400423517
Short name T205
Test name
Test status
Simulation time 313637640 ps
CPU time 2.28 seconds
Started Apr 02 03:39:25 PM PDT 24
Finished Apr 02 03:39:28 PM PDT 24
Peak memory 203756 kb
Host smart-4087ccdd-ebc9-4c16-91ba-24b7dc28b39e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400423517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1400423517
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.4211324092
Short name T424
Test name
Test status
Simulation time 1209946938 ps
CPU time 4.92 seconds
Started Apr 02 03:39:23 PM PDT 24
Finished Apr 02 03:39:28 PM PDT 24
Peak memory 216960 kb
Host smart-c574a890-305b-44dd-852e-a489ac2c678d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211324092 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.4211324092
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1232732956
Short name T653
Test name
Test status
Simulation time 1731483279 ps
CPU time 29.6 seconds
Started Apr 02 03:39:24 PM PDT 24
Finished Apr 02 03:39:54 PM PDT 24
Peak memory 203772 kb
Host smart-730e8848-b93a-4f43-8832-9c46f8554fc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232732956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1232732956
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3571509811
Short name T814
Test name
Test status
Simulation time 914793306 ps
CPU time 40.34 seconds
Started Apr 02 03:39:26 PM PDT 24
Finished Apr 02 03:40:06 PM PDT 24
Peak memory 203844 kb
Host smart-da61fa07-a4bf-4827-a6ce-4362693c66b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571509811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3571509811
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.2237884912
Short name T619
Test name
Test status
Simulation time 22800365157 ps
CPU time 134.13 seconds
Started Apr 02 03:39:23 PM PDT 24
Finished Apr 02 03:41:38 PM PDT 24
Peak memory 1297764 kb
Host smart-0614d11d-e4c8-4f08-809b-5db5c89ec2fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237884912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.2237884912
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.4159483110
Short name T516
Test name
Test status
Simulation time 1467559740 ps
CPU time 6.95 seconds
Started Apr 02 03:39:26 PM PDT 24
Finished Apr 02 03:39:33 PM PDT 24
Peak memory 219756 kb
Host smart-8b78197b-8a4b-47d0-95cb-68bec87b4550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159483110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.4159483110
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2213470671
Short name T791
Test name
Test status
Simulation time 21847971 ps
CPU time 0.64 seconds
Started Apr 02 03:39:32 PM PDT 24
Finished Apr 02 03:39:34 PM PDT 24
Peak memory 203656 kb
Host smart-74c1ece6-c60c-4531-bb66-952259a5d51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213470671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2213470671
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1473278766
Short name T74
Test name
Test status
Simulation time 301356871 ps
CPU time 1.19 seconds
Started Apr 02 03:39:24 PM PDT 24
Finished Apr 02 03:39:25 PM PDT 24
Peak memory 212068 kb
Host smart-6e9f91ea-8b7d-4165-9082-03a4af3f4636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473278766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1473278766
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1657915913
Short name T298
Test name
Test status
Simulation time 702984188 ps
CPU time 7.92 seconds
Started Apr 02 03:39:26 PM PDT 24
Finished Apr 02 03:39:34 PM PDT 24
Peak memory 277824 kb
Host smart-55bfeec2-ca42-4a1a-aae6-0fdf41bd9486
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657915913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1657915913
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.421674295
Short name T513
Test name
Test status
Simulation time 3215841392 ps
CPU time 43.7 seconds
Started Apr 02 03:39:26 PM PDT 24
Finished Apr 02 03:40:10 PM PDT 24
Peak memory 557004 kb
Host smart-241ae6e8-1f6a-4d9e-8b68-3f127ec6cfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421674295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.421674295
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3499134823
Short name T267
Test name
Test status
Simulation time 1818814859 ps
CPU time 121.32 seconds
Started Apr 02 03:39:25 PM PDT 24
Finished Apr 02 03:41:27 PM PDT 24
Peak memory 601400 kb
Host smart-7b6aafe7-1770-4ee6-80b1-2ec50121ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499134823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3499134823
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2655319569
Short name T829
Test name
Test status
Simulation time 580427333 ps
CPU time 1.04 seconds
Started Apr 02 03:39:27 PM PDT 24
Finished Apr 02 03:39:29 PM PDT 24
Peak memory 203668 kb
Host smart-2f3baf72-52fc-4543-9996-d3500679a6b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655319569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2655319569
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3390748861
Short name T1168
Test name
Test status
Simulation time 118070351 ps
CPU time 3.04 seconds
Started Apr 02 03:39:29 PM PDT 24
Finished Apr 02 03:39:33 PM PDT 24
Peak memory 222080 kb
Host smart-ba357d3a-5b23-4ec9-85ab-719272c3e4c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390748861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3390748861
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.738430837
Short name T593
Test name
Test status
Simulation time 23943822332 ps
CPU time 252.69 seconds
Started Apr 02 03:39:30 PM PDT 24
Finished Apr 02 03:43:43 PM PDT 24
Peak memory 1036012 kb
Host smart-3a2f07e6-5679-42bc-ab45-041e72d12615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738430837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.738430837
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.991596761
Short name T758
Test name
Test status
Simulation time 823704315 ps
CPU time 3.56 seconds
Started Apr 02 03:39:27 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 203824 kb
Host smart-f5b2781f-3af6-4780-9ade-83cfb4d63088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991596761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.991596761
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.752045789
Short name T1167
Test name
Test status
Simulation time 1517004612 ps
CPU time 76.63 seconds
Started Apr 02 03:39:28 PM PDT 24
Finished Apr 02 03:40:44 PM PDT 24
Peak memory 410504 kb
Host smart-f5053120-0cda-44c4-acfc-2e13806bd9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752045789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.752045789
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3122703555
Short name T508
Test name
Test status
Simulation time 19956755 ps
CPU time 0.65 seconds
Started Apr 02 03:39:30 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 203628 kb
Host smart-fb9e8770-0ec7-4961-be29-17892fffcdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122703555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3122703555
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2499541904
Short name T1148
Test name
Test status
Simulation time 8237584127 ps
CPU time 422.4 seconds
Started Apr 02 03:39:28 PM PDT 24
Finished Apr 02 03:46:31 PM PDT 24
Peak memory 1949112 kb
Host smart-e8c1326c-af77-4c06-8183-6edafb9875a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499541904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2499541904
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.212870132
Short name T744
Test name
Test status
Simulation time 1122368242 ps
CPU time 20.05 seconds
Started Apr 02 03:39:25 PM PDT 24
Finished Apr 02 03:39:45 PM PDT 24
Peak memory 299308 kb
Host smart-f3fa206d-277e-4f6f-aa89-c453aec1e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212870132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.212870132
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1972026540
Short name T291
Test name
Test status
Simulation time 744745870 ps
CPU time 3.72 seconds
Started Apr 02 03:39:25 PM PDT 24
Finished Apr 02 03:39:29 PM PDT 24
Peak memory 203820 kb
Host smart-c91f8c0d-3eb6-4852-a6f5-6e8d4d0c7b85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972026540 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1972026540
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1457975551
Short name T779
Test name
Test status
Simulation time 10195326096 ps
CPU time 32.59 seconds
Started Apr 02 03:39:27 PM PDT 24
Finished Apr 02 03:40:00 PM PDT 24
Peak memory 417796 kb
Host smart-8b7e6b2f-e4e9-4aa8-b4fe-133b231eab3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457975551 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1457975551
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.206065848
Short name T543
Test name
Test status
Simulation time 10141571805 ps
CPU time 32.85 seconds
Started Apr 02 03:39:31 PM PDT 24
Finished Apr 02 03:40:05 PM PDT 24
Peak memory 438336 kb
Host smart-bfb308fb-5f86-4b1a-90cc-ae56019c5887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206065848 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.206065848
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2928035605
Short name T159
Test name
Test status
Simulation time 2385827892 ps
CPU time 2.71 seconds
Started Apr 02 03:39:28 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 203876 kb
Host smart-8aa6fe9f-e523-47a2-b98e-c002114b4d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928035605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2928035605
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3448040406
Short name T740
Test name
Test status
Simulation time 1284725838 ps
CPU time 5.65 seconds
Started Apr 02 03:39:28 PM PDT 24
Finished Apr 02 03:39:34 PM PDT 24
Peak memory 213832 kb
Host smart-b92d07db-fa68-456f-b714-3973052eda44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448040406 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3448040406
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.336606177
Short name T989
Test name
Test status
Simulation time 496607872 ps
CPU time 15.4 seconds
Started Apr 02 03:39:26 PM PDT 24
Finished Apr 02 03:39:41 PM PDT 24
Peak memory 203872 kb
Host smart-d67bcc88-3dbf-4f98-9546-351aef31fc50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336606177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.336606177
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3534125963
Short name T390
Test name
Test status
Simulation time 1817816914 ps
CPU time 16.27 seconds
Started Apr 02 03:39:26 PM PDT 24
Finished Apr 02 03:39:43 PM PDT 24
Peak memory 210364 kb
Host smart-7f500e27-d66c-4856-abaa-89137e609f88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534125963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3534125963
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2173999823
Short name T1175
Test name
Test status
Simulation time 9587005076 ps
CPU time 1015.23 seconds
Started Apr 02 03:39:28 PM PDT 24
Finished Apr 02 03:56:23 PM PDT 24
Peak memory 2457020 kb
Host smart-ff2f4086-f273-4668-b51a-8c823755591a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173999823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2173999823
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3257776930
Short name T8
Test name
Test status
Simulation time 8650741180 ps
CPU time 6.83 seconds
Started Apr 02 03:39:30 PM PDT 24
Finished Apr 02 03:39:37 PM PDT 24
Peak memory 217580 kb
Host smart-543fd324-3f48-4c29-9254-11152bc3677a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257776930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3257776930
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3901154563
Short name T310
Test name
Test status
Simulation time 20631533 ps
CPU time 0.62 seconds
Started Apr 02 03:39:39 PM PDT 24
Finished Apr 02 03:39:40 PM PDT 24
Peak memory 203640 kb
Host smart-48c6243b-7f36-4b35-bc6e-6317b4214abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901154563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3901154563
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2929799187
Short name T203
Test name
Test status
Simulation time 105971144 ps
CPU time 1.49 seconds
Started Apr 02 03:39:32 PM PDT 24
Finished Apr 02 03:39:35 PM PDT 24
Peak memory 211952 kb
Host smart-67666eab-3a2b-4456-8033-3cf71a83f4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929799187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2929799187
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2616141573
Short name T732
Test name
Test status
Simulation time 3603266205 ps
CPU time 17.68 seconds
Started Apr 02 03:39:31 PM PDT 24
Finished Apr 02 03:39:50 PM PDT 24
Peak memory 276468 kb
Host smart-7fdd9cea-ae95-4b47-9bad-5f4af7265735
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616141573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2616141573
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2449495284
Short name T1124
Test name
Test status
Simulation time 1191525612 ps
CPU time 77.16 seconds
Started Apr 02 03:39:33 PM PDT 24
Finished Apr 02 03:40:50 PM PDT 24
Peak memory 490800 kb
Host smart-b2136c86-93c6-4437-a4c9-c91ad8cd50e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449495284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2449495284
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.383889949
Short name T309
Test name
Test status
Simulation time 7703294516 ps
CPU time 66.51 seconds
Started Apr 02 03:39:31 PM PDT 24
Finished Apr 02 03:40:37 PM PDT 24
Peak memory 701896 kb
Host smart-bf859106-2a2f-4b55-b962-c82ad1e7ba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383889949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.383889949
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1212128349
Short name T1004
Test name
Test status
Simulation time 128031098 ps
CPU time 0.91 seconds
Started Apr 02 03:39:27 PM PDT 24
Finished Apr 02 03:39:29 PM PDT 24
Peak memory 203712 kb
Host smart-b1d11704-fb61-45aa-92c3-0e948a9ecf77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212128349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1212128349
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3273084286
Short name T560
Test name
Test status
Simulation time 148780366 ps
CPU time 3.5 seconds
Started Apr 02 03:39:26 PM PDT 24
Finished Apr 02 03:39:29 PM PDT 24
Peak memory 225472 kb
Host smart-4fe5fbbc-7c85-4ab8-afd1-63870243695c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273084286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3273084286
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1437147382
Short name T404
Test name
Test status
Simulation time 13613347531 ps
CPU time 93.84 seconds
Started Apr 02 03:39:28 PM PDT 24
Finished Apr 02 03:41:03 PM PDT 24
Peak memory 984256 kb
Host smart-c158f397-4dd9-4521-8654-33d4285cc1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437147382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1437147382
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.4084713846
Short name T677
Test name
Test status
Simulation time 673510656 ps
CPU time 5.65 seconds
Started Apr 02 03:39:37 PM PDT 24
Finished Apr 02 03:39:43 PM PDT 24
Peak memory 203828 kb
Host smart-e93d1e57-691a-458a-8197-d143ca3c4e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084713846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.4084713846
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.595043492
Short name T870
Test name
Test status
Simulation time 20055940 ps
CPU time 0.65 seconds
Started Apr 02 03:39:30 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 203636 kb
Host smart-954d2a4b-0e72-455e-b38d-0716d2d72ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595043492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.595043492
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2159888865
Short name T382
Test name
Test status
Simulation time 1732227065 ps
CPU time 42.03 seconds
Started Apr 02 03:39:33 PM PDT 24
Finished Apr 02 03:40:15 PM PDT 24
Peak memory 293092 kb
Host smart-a12bcddd-cbe6-4142-8d78-2b27a5371f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159888865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2159888865
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2052750731
Short name T695
Test name
Test status
Simulation time 3644101139 ps
CPU time 3.89 seconds
Started Apr 02 03:39:36 PM PDT 24
Finished Apr 02 03:39:40 PM PDT 24
Peak memory 212080 kb
Host smart-ce2373f2-6a37-483a-98a6-d93c8a8b7fe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052750731 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2052750731
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1464054083
Short name T237
Test name
Test status
Simulation time 10117085230 ps
CPU time 37.55 seconds
Started Apr 02 03:39:36 PM PDT 24
Finished Apr 02 03:40:15 PM PDT 24
Peak memory 442868 kb
Host smart-b2ebad87-624c-44eb-b6e0-25ca4b59f69a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464054083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1464054083
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.4095900273
Short name T1010
Test name
Test status
Simulation time 10131472235 ps
CPU time 41.57 seconds
Started Apr 02 03:39:39 PM PDT 24
Finished Apr 02 03:40:20 PM PDT 24
Peak memory 477900 kb
Host smart-6a3c8047-1d30-441c-929e-f674ce9c3cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095900273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.4095900273
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1243744246
Short name T882
Test name
Test status
Simulation time 11770251296 ps
CPU time 6 seconds
Started Apr 02 03:39:33 PM PDT 24
Finished Apr 02 03:39:40 PM PDT 24
Peak memory 203812 kb
Host smart-b9db5298-e132-442d-b2ca-cfe9d841c61a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243744246 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1243744246
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1196050639
Short name T256
Test name
Test status
Simulation time 3594959680 ps
CPU time 11.23 seconds
Started Apr 02 03:39:31 PM PDT 24
Finished Apr 02 03:39:43 PM PDT 24
Peak memory 203920 kb
Host smart-0ff9ed3f-1f61-4a03-8f10-15ce0d1c1657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196050639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1196050639
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3096731963
Short name T544
Test name
Test status
Simulation time 542380537 ps
CPU time 8.26 seconds
Started Apr 02 03:39:31 PM PDT 24
Finished Apr 02 03:39:40 PM PDT 24
Peak memory 204384 kb
Host smart-4b5cfee6-f24b-4106-b12d-cca7a722c96e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096731963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3096731963
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2369216641
Short name T285
Test name
Test status
Simulation time 29839353929 ps
CPU time 224.05 seconds
Started Apr 02 03:39:31 PM PDT 24
Finished Apr 02 03:43:16 PM PDT 24
Peak memory 1777732 kb
Host smart-9dcd595c-f880-4036-9fc1-b7bbdb5a16ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369216641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2369216641
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.930407883
Short name T514
Test name
Test status
Simulation time 1269298228 ps
CPU time 6.55 seconds
Started Apr 02 03:39:30 PM PDT 24
Finished Apr 02 03:39:37 PM PDT 24
Peak memory 212052 kb
Host smart-dae61664-4829-41ee-b713-b08fb92281fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930407883 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_timeout.930407883
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3192337288
Short name T327
Test name
Test status
Simulation time 17649136 ps
CPU time 0.62 seconds
Started Apr 02 03:39:42 PM PDT 24
Finished Apr 02 03:39:42 PM PDT 24
Peak memory 203704 kb
Host smart-0e4bb5d8-91eb-43ea-9b09-b713086234eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192337288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3192337288
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.92655310
Short name T627
Test name
Test status
Simulation time 158188186 ps
CPU time 1.35 seconds
Started Apr 02 03:39:39 PM PDT 24
Finished Apr 02 03:39:41 PM PDT 24
Peak memory 211972 kb
Host smart-79df6b4f-e7e9-4550-a814-919db6b7028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92655310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.92655310
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3244509234
Short name T367
Test name
Test status
Simulation time 933253529 ps
CPU time 5.22 seconds
Started Apr 02 03:39:37 PM PDT 24
Finished Apr 02 03:39:42 PM PDT 24
Peak memory 249352 kb
Host smart-c507eb0d-1c36-42e7-8090-5b4ce0800850
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244509234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3244509234
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1882057365
Short name T992
Test name
Test status
Simulation time 3022692633 ps
CPU time 43.55 seconds
Started Apr 02 03:39:40 PM PDT 24
Finished Apr 02 03:40:24 PM PDT 24
Peak memory 562940 kb
Host smart-1e6eb928-dc1b-4f2e-8bf4-608145c2d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882057365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1882057365
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1798363884
Short name T457
Test name
Test status
Simulation time 1317849359 ps
CPU time 75.75 seconds
Started Apr 02 03:39:35 PM PDT 24
Finished Apr 02 03:40:51 PM PDT 24
Peak memory 471428 kb
Host smart-022f3c99-3f1a-44c9-8f18-1327c7adfe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798363884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1798363884
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3610993603
Short name T831
Test name
Test status
Simulation time 163724101 ps
CPU time 0.86 seconds
Started Apr 02 03:39:33 PM PDT 24
Finished Apr 02 03:39:34 PM PDT 24
Peak memory 203720 kb
Host smart-db76f93a-f9f3-4d29-8544-869b2b85c394
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610993603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3610993603
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.274468611
Short name T587
Test name
Test status
Simulation time 474508762 ps
CPU time 2.56 seconds
Started Apr 02 03:39:40 PM PDT 24
Finished Apr 02 03:39:43 PM PDT 24
Peak memory 203712 kb
Host smart-0bc43cc4-4903-40ed-9952-fa37840d1bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274468611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
274468611
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2593272149
Short name T648
Test name
Test status
Simulation time 3602503340 ps
CPU time 86.89 seconds
Started Apr 02 03:39:35 PM PDT 24
Finished Apr 02 03:41:02 PM PDT 24
Peak memory 1035576 kb
Host smart-3e837efc-4954-47a0-a368-4c7074dcfad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593272149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2593272149
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3317455266
Short name T775
Test name
Test status
Simulation time 726534684 ps
CPU time 14.56 seconds
Started Apr 02 03:39:41 PM PDT 24
Finished Apr 02 03:39:56 PM PDT 24
Peak memory 203784 kb
Host smart-2d6706bd-d3bb-497f-aa53-15a3ef36d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317455266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3317455266
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1340967957
Short name T750
Test name
Test status
Simulation time 24607435378 ps
CPU time 62.53 seconds
Started Apr 02 03:39:44 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 405716 kb
Host smart-671eaea5-c76f-4e42-ab52-b54cbb97eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340967957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1340967957
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1583372427
Short name T179
Test name
Test status
Simulation time 45888898 ps
CPU time 0.68 seconds
Started Apr 02 03:39:35 PM PDT 24
Finished Apr 02 03:39:36 PM PDT 24
Peak memory 203596 kb
Host smart-1159e31b-dd00-4887-8ef3-0854876fa996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583372427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1583372427
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2382702721
Short name T187
Test name
Test status
Simulation time 13113091264 ps
CPU time 207.84 seconds
Started Apr 02 03:39:40 PM PDT 24
Finished Apr 02 03:43:08 PM PDT 24
Peak memory 645868 kb
Host smart-a5070ebd-9ce4-4835-b784-1c7b35f12704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382702721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2382702721
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.817850510
Short name T438
Test name
Test status
Simulation time 11170197541 ps
CPU time 61.1 seconds
Started Apr 02 03:39:35 PM PDT 24
Finished Apr 02 03:40:37 PM PDT 24
Peak memory 336668 kb
Host smart-7ddd53ab-5e64-4115-968d-d70492b85b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817850510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.817850510
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.239503208
Short name T384
Test name
Test status
Simulation time 3182815629 ps
CPU time 3.01 seconds
Started Apr 02 03:39:37 PM PDT 24
Finished Apr 02 03:39:40 PM PDT 24
Peak memory 203792 kb
Host smart-535a3484-6ece-4cce-9094-c28d0190b04c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239503208 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.239503208
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1732950370
Short name T294
Test name
Test status
Simulation time 10457419505 ps
CPU time 12.53 seconds
Started Apr 02 03:39:41 PM PDT 24
Finished Apr 02 03:39:53 PM PDT 24
Peak memory 257160 kb
Host smart-6baf1aeb-a24a-43e7-aa8b-2d7f1169831a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732950370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1732950370
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3729805537
Short name T576
Test name
Test status
Simulation time 10274779978 ps
CPU time 6.18 seconds
Started Apr 02 03:39:40 PM PDT 24
Finished Apr 02 03:39:47 PM PDT 24
Peak memory 250932 kb
Host smart-c03cfa73-105e-4868-9080-9640d10d8814
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729805537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3729805537
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1138796470
Short name T613
Test name
Test status
Simulation time 619771550 ps
CPU time 2.48 seconds
Started Apr 02 03:39:45 PM PDT 24
Finished Apr 02 03:39:48 PM PDT 24
Peak memory 203876 kb
Host smart-af77cf25-54a9-4b4c-ad51-439a4ba44955
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138796470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1138796470
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3693476960
Short name T362
Test name
Test status
Simulation time 787080306 ps
CPU time 4.74 seconds
Started Apr 02 03:39:40 PM PDT 24
Finished Apr 02 03:39:45 PM PDT 24
Peak memory 209248 kb
Host smart-2259cce3-693b-4493-afc4-b13c8a2fee26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693476960 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3693476960
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.745976927
Short name T1086
Test name
Test status
Simulation time 1066617570 ps
CPU time 40.54 seconds
Started Apr 02 03:39:37 PM PDT 24
Finished Apr 02 03:40:18 PM PDT 24
Peak memory 203824 kb
Host smart-5bdd5788-ec5e-49bb-a29a-f7ec166be7c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745976927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_tar
get_smoke.745976927
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3682977083
Short name T618
Test name
Test status
Simulation time 861819117 ps
CPU time 13.54 seconds
Started Apr 02 03:39:38 PM PDT 24
Finished Apr 02 03:39:52 PM PDT 24
Peak memory 214580 kb
Host smart-b825c7a8-1482-44ba-8013-8c5a83cc6552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682977083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3682977083
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.2119015496
Short name T433
Test name
Test status
Simulation time 9233738472 ps
CPU time 19.1 seconds
Started Apr 02 03:39:40 PM PDT 24
Finished Apr 02 03:39:59 PM PDT 24
Peak memory 203856 kb
Host smart-cdd97861-5c1c-4a6c-af74-d356cb74ff3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119015496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.2119015496
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1165075805
Short name T175
Test name
Test status
Simulation time 5183625639 ps
CPU time 6.73 seconds
Started Apr 02 03:39:38 PM PDT 24
Finished Apr 02 03:39:45 PM PDT 24
Peak memory 203920 kb
Host smart-454f2382-9885-49a1-b598-7cc9b19a9d39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165075805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1165075805
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.85503082
Short name T656
Test name
Test status
Simulation time 38202872 ps
CPU time 0.59 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:39:54 PM PDT 24
Peak memory 203684 kb
Host smart-5d1ea211-33f5-4ca6-95fe-badc9b79ad21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85503082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.85503082
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2524330636
Short name T1093
Test name
Test status
Simulation time 93104024 ps
CPU time 1.49 seconds
Started Apr 02 03:39:43 PM PDT 24
Finished Apr 02 03:39:44 PM PDT 24
Peak memory 211968 kb
Host smart-147eefad-bbe3-4062-bac1-9106a0a75fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524330636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2524330636
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3355785053
Short name T1001
Test name
Test status
Simulation time 1302988052 ps
CPU time 5.85 seconds
Started Apr 02 03:39:43 PM PDT 24
Finished Apr 02 03:39:49 PM PDT 24
Peak memory 270584 kb
Host smart-ee2159ff-5dce-41d1-9c48-8b702d7cf017
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355785053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3355785053
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2540928126
Short name T756
Test name
Test status
Simulation time 7343200110 ps
CPU time 55.04 seconds
Started Apr 02 03:39:42 PM PDT 24
Finished Apr 02 03:40:37 PM PDT 24
Peak memory 662988 kb
Host smart-af798131-4e52-444d-aadf-f9be7cd0f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540928126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2540928126
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1087651696
Short name T697
Test name
Test status
Simulation time 1352100726 ps
CPU time 43.87 seconds
Started Apr 02 03:39:43 PM PDT 24
Finished Apr 02 03:40:27 PM PDT 24
Peak memory 529924 kb
Host smart-c8272b1e-efe4-467c-89eb-f37775b3e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087651696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1087651696
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3264699377
Short name T470
Test name
Test status
Simulation time 761024712 ps
CPU time 1.19 seconds
Started Apr 02 03:39:41 PM PDT 24
Finished Apr 02 03:39:42 PM PDT 24
Peak memory 203800 kb
Host smart-6273555c-3118-4ea9-b481-74085fdd26c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264699377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3264699377
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.639575979
Short name T437
Test name
Test status
Simulation time 112215883 ps
CPU time 3.38 seconds
Started Apr 02 03:39:45 PM PDT 24
Finished Apr 02 03:39:49 PM PDT 24
Peak memory 220572 kb
Host smart-37734091-48d8-48f8-ae54-7eab62500951
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639575979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
639575979
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1824470415
Short name T57
Test name
Test status
Simulation time 13716747319 ps
CPU time 99.48 seconds
Started Apr 02 03:39:43 PM PDT 24
Finished Apr 02 03:41:22 PM PDT 24
Peak memory 1024628 kb
Host smart-0ab90a3c-6dfb-4504-afb3-12538b56419c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824470415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1824470415
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.4027680004
Short name T1080
Test name
Test status
Simulation time 322673431 ps
CPU time 13.32 seconds
Started Apr 02 03:39:50 PM PDT 24
Finished Apr 02 03:40:04 PM PDT 24
Peak memory 203808 kb
Host smart-c5df1ca2-998a-4f9f-b4bf-63f03e3df4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027680004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.4027680004
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1493793023
Short name T177
Test name
Test status
Simulation time 1842856990 ps
CPU time 36.91 seconds
Started Apr 02 03:39:50 PM PDT 24
Finished Apr 02 03:40:27 PM PDT 24
Peak memory 444308 kb
Host smart-313ac064-11b1-45dc-ac8e-907798317fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493793023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1493793023
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3193361499
Short name T180
Test name
Test status
Simulation time 38635160 ps
CPU time 0.66 seconds
Started Apr 02 03:39:44 PM PDT 24
Finished Apr 02 03:39:45 PM PDT 24
Peak memory 203592 kb
Host smart-73868b2f-3383-4064-88b0-ccbfdb7073c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193361499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3193361499
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1177609141
Short name T675
Test name
Test status
Simulation time 1259735012 ps
CPU time 18.29 seconds
Started Apr 02 03:39:42 PM PDT 24
Finished Apr 02 03:40:00 PM PDT 24
Peak memory 243420 kb
Host smart-5ba788f4-956b-4d55-b4c6-c25f3fb04828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177609141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1177609141
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1287420936
Short name T658
Test name
Test status
Simulation time 905729395 ps
CPU time 42.69 seconds
Started Apr 02 03:39:41 PM PDT 24
Finished Apr 02 03:40:24 PM PDT 24
Peak memory 282856 kb
Host smart-1d5b77cd-e2ed-4d11-974f-e4e9d5096135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287420936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1287420936
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1609396794
Short name T736
Test name
Test status
Simulation time 6667413801 ps
CPU time 4.87 seconds
Started Apr 02 03:39:54 PM PDT 24
Finished Apr 02 03:39:59 PM PDT 24
Peak memory 212096 kb
Host smart-92726a3e-f99d-4f4e-b9f1-95706de09838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609396794 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1609396794
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1712090528
Short name T170
Test name
Test status
Simulation time 10227557123 ps
CPU time 14.09 seconds
Started Apr 02 03:39:51 PM PDT 24
Finished Apr 02 03:40:06 PM PDT 24
Peak memory 281780 kb
Host smart-87c31ea9-0e15-4b3e-8872-b20736f791b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712090528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1712090528
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1999422766
Short name T594
Test name
Test status
Simulation time 10622807486 ps
CPU time 17.89 seconds
Started Apr 02 03:39:49 PM PDT 24
Finished Apr 02 03:40:07 PM PDT 24
Peak memory 322864 kb
Host smart-a452e628-6ee7-494b-8eac-14d02c4f5ff7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999422766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1999422766
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.4085172878
Short name T50
Test name
Test status
Simulation time 269695770 ps
CPU time 1.91 seconds
Started Apr 02 03:39:45 PM PDT 24
Finished Apr 02 03:39:47 PM PDT 24
Peak memory 203776 kb
Host smart-36c75588-fe27-4db8-935b-38f5c6273920
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085172878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.4085172878
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.424635694
Short name T628
Test name
Test status
Simulation time 728781638 ps
CPU time 4.18 seconds
Started Apr 02 03:39:49 PM PDT 24
Finished Apr 02 03:39:54 PM PDT 24
Peak memory 205188 kb
Host smart-5aa71d39-4668-4aef-a6d6-9c8c34e3f221
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424635694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.424635694
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1956820392
Short name T439
Test name
Test status
Simulation time 678167634 ps
CPU time 11.01 seconds
Started Apr 02 03:39:43 PM PDT 24
Finished Apr 02 03:39:54 PM PDT 24
Peak memory 203772 kb
Host smart-34e948b1-4512-40d7-addd-3cb790b801de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956820392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1956820392
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2723363636
Short name T208
Test name
Test status
Simulation time 11425669733 ps
CPU time 44.84 seconds
Started Apr 02 03:39:45 PM PDT 24
Finished Apr 02 03:40:30 PM PDT 24
Peak memory 205132 kb
Host smart-58510d65-e09b-4e8c-b0b6-48b8f8c3148b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723363636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2723363636
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3079020864
Short name T1079
Test name
Test status
Simulation time 16323459378 ps
CPU time 116.74 seconds
Started Apr 02 03:39:46 PM PDT 24
Finished Apr 02 03:41:43 PM PDT 24
Peak memory 1051684 kb
Host smart-e023dd68-0ac3-439d-a4fe-f7e6194c32e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079020864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3079020864
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3955835426
Short name T240
Test name
Test status
Simulation time 2060959999 ps
CPU time 6.38 seconds
Started Apr 02 03:39:46 PM PDT 24
Finished Apr 02 03:39:52 PM PDT 24
Peak memory 220004 kb
Host smart-eb65c95b-2950-411d-9f29-89d232e5d39c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955835426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3955835426
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.4201263110
Short name T797
Test name
Test status
Simulation time 9728669920 ps
CPU time 5.84 seconds
Started Apr 02 03:39:45 PM PDT 24
Finished Apr 02 03:39:51 PM PDT 24
Peak memory 203808 kb
Host smart-50107562-0ada-4d1c-b89c-fb0ed9c34062
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201263110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.4201263110
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3115687869
Short name T316
Test name
Test status
Simulation time 63561301 ps
CPU time 0.62 seconds
Started Apr 02 03:39:57 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 203668 kb
Host smart-1ec8a912-568f-4c08-ae9f-9e4e301731eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115687869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3115687869
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2942257143
Short name T402
Test name
Test status
Simulation time 103139515 ps
CPU time 1.98 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:39:54 PM PDT 24
Peak memory 212112 kb
Host smart-5f78f102-3d25-4059-a569-9d02bacf3618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942257143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2942257143
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2130402583
Short name T468
Test name
Test status
Simulation time 987734566 ps
CPU time 9.36 seconds
Started Apr 02 03:39:50 PM PDT 24
Finished Apr 02 03:39:59 PM PDT 24
Peak memory 312636 kb
Host smart-22742a0f-8610-4641-b426-98599c111d62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130402583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2130402583
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.165202278
Short name T774
Test name
Test status
Simulation time 2331566174 ps
CPU time 169.92 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:42:42 PM PDT 24
Peak memory 762300 kb
Host smart-3887064a-f035-4331-b1cc-e1525fb580af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165202278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.165202278
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1926802576
Short name T721
Test name
Test status
Simulation time 4821921520 ps
CPU time 30.27 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:40:23 PM PDT 24
Peak memory 437824 kb
Host smart-ac2a8b34-664a-4245-adfe-726220ba7704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926802576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1926802576
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.541487020
Short name T522
Test name
Test status
Simulation time 899893011 ps
CPU time 1.08 seconds
Started Apr 02 03:39:51 PM PDT 24
Finished Apr 02 03:39:52 PM PDT 24
Peak memory 203756 kb
Host smart-54492726-9873-4522-9120-57a406e241c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541487020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.541487020
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.682135975
Short name T374
Test name
Test status
Simulation time 166849059 ps
CPU time 4.75 seconds
Started Apr 02 03:39:53 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 232228 kb
Host smart-5c353174-87a0-4906-9e4d-44852c72b5c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682135975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
682135975
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.562275707
Short name T150
Test name
Test status
Simulation time 7534872657 ps
CPU time 91.5 seconds
Started Apr 02 03:39:49 PM PDT 24
Finished Apr 02 03:41:21 PM PDT 24
Peak memory 1102352 kb
Host smart-091c0bb8-3f7a-4970-8ade-96291b4b4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562275707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.562275707
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.371608215
Short name T27
Test name
Test status
Simulation time 1667372145 ps
CPU time 18.28 seconds
Started Apr 02 03:39:58 PM PDT 24
Finished Apr 02 03:40:16 PM PDT 24
Peak memory 203792 kb
Host smart-d55cfad9-2faf-460b-b071-ff17b093f89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371608215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.371608215
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3028447475
Short name T502
Test name
Test status
Simulation time 6313753633 ps
CPU time 78.99 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:41:12 PM PDT 24
Peak memory 381348 kb
Host smart-2cb69d93-111e-46dc-9b2b-3472a96c063d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028447475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3028447475
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2399393348
Short name T894
Test name
Test status
Simulation time 45896610 ps
CPU time 0.74 seconds
Started Apr 02 03:39:51 PM PDT 24
Finished Apr 02 03:39:52 PM PDT 24
Peak memory 203564 kb
Host smart-1f52cf18-98d0-4496-9334-9694d7f289f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399393348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2399393348
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1992265885
Short name T48
Test name
Test status
Simulation time 6091605482 ps
CPU time 30.07 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:40:22 PM PDT 24
Peak memory 377124 kb
Host smart-747ae6d1-edf9-436a-ad6d-eb72d3cb4743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992265885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1992265885
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.793342397
Short name T985
Test name
Test status
Simulation time 803173683 ps
CPU time 14.13 seconds
Started Apr 02 03:39:50 PM PDT 24
Finished Apr 02 03:40:04 PM PDT 24
Peak memory 301120 kb
Host smart-1d0e4882-b127-4b19-8410-25f8fe4f3b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793342397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.793342397
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3079417862
Short name T660
Test name
Test status
Simulation time 3806248945 ps
CPU time 4.26 seconds
Started Apr 02 03:39:54 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 203440 kb
Host smart-a3991f66-98b4-4da3-b6e5-863d8b26e07d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079417862 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3079417862
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3715699055
Short name T752
Test name
Test status
Simulation time 10103875389 ps
CPU time 29.19 seconds
Started Apr 02 03:39:53 PM PDT 24
Finished Apr 02 03:40:22 PM PDT 24
Peak memory 400644 kb
Host smart-1cd32726-ead6-4bf3-9594-da76279edb30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715699055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3715699055
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.694605620
Short name T67
Test name
Test status
Simulation time 10111674648 ps
CPU time 106.52 seconds
Started Apr 02 03:40:01 PM PDT 24
Finished Apr 02 03:41:48 PM PDT 24
Peak memory 727188 kb
Host smart-924de958-54a2-4ec3-8e54-2ab606f8ff70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694605620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.694605620
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1475168290
Short name T1137
Test name
Test status
Simulation time 300400035 ps
CPU time 2.13 seconds
Started Apr 02 03:39:54 PM PDT 24
Finished Apr 02 03:39:56 PM PDT 24
Peak memory 203744 kb
Host smart-e5bfafc0-14b7-4275-bc00-c63724da42ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475168290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1475168290
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2181196694
Short name T488
Test name
Test status
Simulation time 1304242257 ps
CPU time 7.48 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:40:00 PM PDT 24
Peak memory 209060 kb
Host smart-0f49a17d-f8fa-4961-95bd-bda2751f59b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181196694 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2181196694
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2696570188
Short name T871
Test name
Test status
Simulation time 4485385768 ps
CPU time 40.6 seconds
Started Apr 02 03:39:51 PM PDT 24
Finished Apr 02 03:40:32 PM PDT 24
Peak memory 203872 kb
Host smart-006c68b1-2eec-4885-9bd9-079317f74729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696570188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2696570188
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2824366518
Short name T1068
Test name
Test status
Simulation time 4605613277 ps
CPU time 17.52 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:40:10 PM PDT 24
Peak memory 219924 kb
Host smart-dc724733-eea1-4bed-8ae7-54ff937ec781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824366518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2824366518
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.473165135
Short name T1074
Test name
Test status
Simulation time 44731234060 ps
CPU time 108.23 seconds
Started Apr 02 03:39:49 PM PDT 24
Finished Apr 02 03:41:37 PM PDT 24
Peak memory 426316 kb
Host smart-fa85e193-c8ef-4fc4-8af2-546036bc9dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473165135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.473165135
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.727282857
Short name T1036
Test name
Test status
Simulation time 1095661753 ps
CPU time 6.35 seconds
Started Apr 02 03:39:51 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 203852 kb
Host smart-e1715fcf-ac1c-4383-98ed-e185a83f546e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727282857 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.727282857
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.4028772434
Short name T1196
Test name
Test status
Simulation time 16101646 ps
CPU time 0.61 seconds
Started Apr 02 03:36:39 PM PDT 24
Finished Apr 02 03:36:39 PM PDT 24
Peak memory 203632 kb
Host smart-42690534-5c3c-4713-b118-05a11c3f469e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028772434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.4028772434
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3068793462
Short name T261
Test name
Test status
Simulation time 700548342 ps
CPU time 1.68 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:36:42 PM PDT 24
Peak memory 212056 kb
Host smart-4e3fac75-bd1b-4bb7-a18d-c5a05d53c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068793462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3068793462
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3125349146
Short name T375
Test name
Test status
Simulation time 466545485 ps
CPU time 5.15 seconds
Started Apr 02 03:36:56 PM PDT 24
Finished Apr 02 03:37:02 PM PDT 24
Peak memory 249360 kb
Host smart-8ff92682-322a-4fb9-bba2-d0320451a30a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125349146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3125349146
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1761953442
Short name T1177
Test name
Test status
Simulation time 6859710238 ps
CPU time 34.02 seconds
Started Apr 02 03:36:51 PM PDT 24
Finished Apr 02 03:37:25 PM PDT 24
Peak memory 360792 kb
Host smart-29a9e5cd-7496-44e1-8d30-9114b361fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761953442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1761953442
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.565240177
Short name T289
Test name
Test status
Simulation time 2970019375 ps
CPU time 71.3 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 682568 kb
Host smart-ba171791-1dd3-48fa-aca2-8dac88ca0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565240177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.565240177
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.87807068
Short name T799
Test name
Test status
Simulation time 96599791 ps
CPU time 0.84 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:43 PM PDT 24
Peak memory 203708 kb
Host smart-285bf309-1644-477e-bf71-bed4dda7d18a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87807068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.87807068
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1329747607
Short name T605
Test name
Test status
Simulation time 494955254 ps
CPU time 6.66 seconds
Started Apr 02 03:36:37 PM PDT 24
Finished Apr 02 03:36:44 PM PDT 24
Peak memory 222680 kb
Host smart-ec6f9ea7-bf0f-402e-be19-f79198a9fc81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329747607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1329747607
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3038670087
Short name T158
Test name
Test status
Simulation time 55397230624 ps
CPU time 127.48 seconds
Started Apr 02 03:36:31 PM PDT 24
Finished Apr 02 03:38:39 PM PDT 24
Peak memory 1306736 kb
Host smart-7d77e3e0-56c4-4468-bd6d-1b3dea59b725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038670087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3038670087
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2750602500
Short name T500
Test name
Test status
Simulation time 1219659116 ps
CPU time 9.49 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 203844 kb
Host smart-7379378b-fed9-4a84-a839-32537508f66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750602500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2750602500
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.162092511
Short name T570
Test name
Test status
Simulation time 6075773953 ps
CPU time 37.76 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:37:24 PM PDT 24
Peak memory 416092 kb
Host smart-a7c2823e-76b6-4277-943a-d7b2792ee926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162092511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.162092511
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.130473363
Short name T1056
Test name
Test status
Simulation time 50014022 ps
CPU time 0.65 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:42 PM PDT 24
Peak memory 203616 kb
Host smart-0c7733b1-7d36-4e53-aca7-750fb2b7364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130473363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.130473363
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1546875411
Short name T541
Test name
Test status
Simulation time 3141752756 ps
CPU time 79.49 seconds
Started Apr 02 03:36:56 PM PDT 24
Finished Apr 02 03:38:16 PM PDT 24
Peak memory 420184 kb
Host smart-3a62874d-3f73-47b1-91c5-5294eba54a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546875411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1546875411
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.623564665
Short name T946
Test name
Test status
Simulation time 3074250734 ps
CPU time 4.1 seconds
Started Apr 02 03:36:36 PM PDT 24
Finished Apr 02 03:36:41 PM PDT 24
Peak memory 212128 kb
Host smart-6b28bf79-aea0-441a-9814-4c447aadabd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623564665 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.623564665
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3436673468
Short name T91
Test name
Test status
Simulation time 10178067922 ps
CPU time 11.78 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:36:58 PM PDT 24
Peak memory 256808 kb
Host smart-ccb141f0-a114-4e7c-b3cb-abd1c9f449c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436673468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3436673468
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2265830846
Short name T998
Test name
Test status
Simulation time 10295029142 ps
CPU time 11.33 seconds
Started Apr 02 03:36:40 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 287608 kb
Host smart-9c169ae3-e6e9-4ee7-b453-306d3cfb91ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265830846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2265830846
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3163125484
Short name T204
Test name
Test status
Simulation time 456487852 ps
CPU time 2.59 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:47 PM PDT 24
Peak memory 203768 kb
Host smart-b9f3ad35-2089-4c3b-854d-e831e4670ad2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163125484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3163125484
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1755019690
Short name T491
Test name
Test status
Simulation time 4194214093 ps
CPU time 5.73 seconds
Started Apr 02 03:36:53 PM PDT 24
Finished Apr 02 03:36:59 PM PDT 24
Peak memory 212048 kb
Host smart-c39774c6-4cf0-43ac-bd41-0f947ccdadbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755019690 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1755019690
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.787502969
Short name T705
Test name
Test status
Simulation time 5214506761 ps
CPU time 40.4 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:37:24 PM PDT 24
Peak memory 203856 kb
Host smart-836c8acc-f2cc-405f-8651-04bfdfc2fbcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787502969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.787502969
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1942676619
Short name T743
Test name
Test status
Simulation time 7486694951 ps
CPU time 26.99 seconds
Started Apr 02 03:36:40 PM PDT 24
Finished Apr 02 03:37:07 PM PDT 24
Peak memory 220804 kb
Host smart-3e485568-0fc6-4147-abda-7586368a699f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942676619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1942676619
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2143479050
Short name T906
Test name
Test status
Simulation time 14769631436 ps
CPU time 6.99 seconds
Started Apr 02 03:36:33 PM PDT 24
Finished Apr 02 03:36:40 PM PDT 24
Peak memory 203812 kb
Host smart-07f591ce-33a9-4dcc-bff0-673046ebfc5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143479050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2143479050
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3297889342
Short name T582
Test name
Test status
Simulation time 4854377970 ps
CPU time 7.66 seconds
Started Apr 02 03:36:47 PM PDT 24
Finished Apr 02 03:36:55 PM PDT 24
Peak memory 213096 kb
Host smart-2ce7df4a-5f61-4292-9bbf-84504d9bb19e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297889342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3297889342
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2384819006
Short name T1098
Test name
Test status
Simulation time 45418152 ps
CPU time 0.63 seconds
Started Apr 02 03:39:59 PM PDT 24
Finished Apr 02 03:39:59 PM PDT 24
Peak memory 203704 kb
Host smart-2b580f88-8661-469b-bfe9-8572a1be4374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384819006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2384819006
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1887150087
Short name T584
Test name
Test status
Simulation time 300537718 ps
CPU time 1.2 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:39:53 PM PDT 24
Peak memory 212076 kb
Host smart-3b8c4099-fe85-4aba-bdec-c16aa68f581e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887150087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1887150087
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1398808754
Short name T849
Test name
Test status
Simulation time 279729264 ps
CPU time 6.43 seconds
Started Apr 02 03:39:54 PM PDT 24
Finished Apr 02 03:40:00 PM PDT 24
Peak memory 259760 kb
Host smart-b1b1fd6d-36c6-4417-a5e4-640e66b0bd9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398808754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1398808754
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1726273442
Short name T915
Test name
Test status
Simulation time 2113117497 ps
CPU time 61.49 seconds
Started Apr 02 03:39:58 PM PDT 24
Finished Apr 02 03:41:00 PM PDT 24
Peak memory 685572 kb
Host smart-54ca0d74-2bde-46e8-8d45-19b00ec2ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726273442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1726273442
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2694132792
Short name T511
Test name
Test status
Simulation time 2245274079 ps
CPU time 80.01 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:41:22 PM PDT 24
Peak memory 710340 kb
Host smart-4f206cfd-47b8-4970-bdad-72c3d32de62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694132792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2694132792
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3350460229
Short name T1092
Test name
Test status
Simulation time 199150256 ps
CPU time 1.06 seconds
Started Apr 02 03:39:53 PM PDT 24
Finished Apr 02 03:39:55 PM PDT 24
Peak memory 203796 kb
Host smart-3c627cef-fddd-423a-8fce-ca9bdb8edc48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350460229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3350460229
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.4061230667
Short name T862
Test name
Test status
Simulation time 813560383 ps
CPU time 4.36 seconds
Started Apr 02 03:39:54 PM PDT 24
Finished Apr 02 03:39:58 PM PDT 24
Peak memory 203748 kb
Host smart-97cf9331-45cd-42c5-997a-ce4299d3c6cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061230667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.4061230667
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2030065067
Short name T666
Test name
Test status
Simulation time 24354362383 ps
CPU time 71.9 seconds
Started Apr 02 03:39:53 PM PDT 24
Finished Apr 02 03:41:05 PM PDT 24
Peak memory 929848 kb
Host smart-0f265aa7-6bb5-44f6-ba3f-a1d11ac7837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030065067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2030065067
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2452716408
Short name T273
Test name
Test status
Simulation time 413568559 ps
CPU time 12.89 seconds
Started Apr 02 03:40:00 PM PDT 24
Finished Apr 02 03:40:13 PM PDT 24
Peak memory 203732 kb
Host smart-563d56d0-e5dd-4faf-9333-a3144479c39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452716408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2452716408
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3350105981
Short name T498
Test name
Test status
Simulation time 5610655235 ps
CPU time 29.03 seconds
Started Apr 02 03:39:58 PM PDT 24
Finished Apr 02 03:40:27 PM PDT 24
Peak memory 425352 kb
Host smart-f4723d2b-c41b-4434-bcd9-215c61b36c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350105981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3350105981
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.295269363
Short name T1122
Test name
Test status
Simulation time 49169381 ps
CPU time 0.71 seconds
Started Apr 02 03:39:54 PM PDT 24
Finished Apr 02 03:39:55 PM PDT 24
Peak memory 203620 kb
Host smart-f31e50a2-8e45-41c0-9dda-9d8b53c2cc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295269363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.295269363
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1616568001
Short name T790
Test name
Test status
Simulation time 9020756139 ps
CPU time 75.46 seconds
Started Apr 02 03:39:52 PM PDT 24
Finished Apr 02 03:41:08 PM PDT 24
Peak memory 399380 kb
Host smart-2b8f9b6e-39c6-4966-8f1e-31da8f30d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616568001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1616568001
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3533457550
Short name T722
Test name
Test status
Simulation time 476410885 ps
CPU time 2.8 seconds
Started Apr 02 03:39:58 PM PDT 24
Finished Apr 02 03:40:01 PM PDT 24
Peak memory 203792 kb
Host smart-ff3b253a-4049-4b16-a404-e3ee0ac77862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533457550 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3533457550
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.4164187483
Short name T452
Test name
Test status
Simulation time 10281115121 ps
CPU time 15.1 seconds
Started Apr 02 03:39:56 PM PDT 24
Finished Apr 02 03:40:12 PM PDT 24
Peak memory 281184 kb
Host smart-826d5fca-9cfa-44ae-9ac7-0d90ae4ddc59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164187483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.4164187483
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.495823824
Short name T904
Test name
Test status
Simulation time 10694261149 ps
CPU time 17.66 seconds
Started Apr 02 03:39:59 PM PDT 24
Finished Apr 02 03:40:17 PM PDT 24
Peak memory 342296 kb
Host smart-df3eb006-3826-4b49-b78a-6a22cc821c29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495823824 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.495823824
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1348271057
Short name T276
Test name
Test status
Simulation time 742079299 ps
CPU time 2.41 seconds
Started Apr 02 03:39:57 PM PDT 24
Finished Apr 02 03:39:59 PM PDT 24
Peak memory 203752 kb
Host smart-9db937b5-1008-4abe-8cd1-9307c743e27a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348271057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1348271057
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2796196255
Short name T995
Test name
Test status
Simulation time 5617731796 ps
CPU time 6.64 seconds
Started Apr 02 03:39:56 PM PDT 24
Finished Apr 02 03:40:03 PM PDT 24
Peak memory 212104 kb
Host smart-899fc5de-6137-48da-a6f0-0cb980b8d56d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796196255 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2796196255
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2114497730
Short name T889
Test name
Test status
Simulation time 729497575 ps
CPU time 28.61 seconds
Started Apr 02 03:40:01 PM PDT 24
Finished Apr 02 03:40:30 PM PDT 24
Peak memory 203744 kb
Host smart-6ab7365d-ec1f-49ff-9b8a-4a39b02e8c96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114497730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2114497730
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1346285834
Short name T765
Test name
Test status
Simulation time 2430272224 ps
CPU time 6.37 seconds
Started Apr 02 03:39:57 PM PDT 24
Finished Apr 02 03:40:04 PM PDT 24
Peak memory 203824 kb
Host smart-9b71c89e-c6cf-431b-b972-2444fba66589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346285834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1346285834
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3377360042
Short name T754
Test name
Test status
Simulation time 44872757807 ps
CPU time 105.54 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:41:48 PM PDT 24
Peak memory 997732 kb
Host smart-71349753-9aa0-471c-9731-7f53912b7f3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377360042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3377360042
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.617692517
Short name T109
Test name
Test status
Simulation time 1083781009 ps
CPU time 6.47 seconds
Started Apr 02 03:40:00 PM PDT 24
Finished Apr 02 03:40:07 PM PDT 24
Peak memory 213284 kb
Host smart-8ce66f28-5caa-41b0-9734-c57b1d4c6d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617692517 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.617692517
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3393935714
Short name T96
Test name
Test status
Simulation time 163455344 ps
CPU time 0.59 seconds
Started Apr 02 03:40:07 PM PDT 24
Finished Apr 02 03:40:08 PM PDT 24
Peak memory 203692 kb
Host smart-5f73db92-c2aa-47e4-8676-1a8dbfc736a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393935714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3393935714
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.845463132
Short name T525
Test name
Test status
Simulation time 144626984 ps
CPU time 1.65 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:40:04 PM PDT 24
Peak memory 212024 kb
Host smart-b9a6ef7c-bb92-43a5-a08e-10620f8b5d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845463132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.845463132
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3723628092
Short name T713
Test name
Test status
Simulation time 1478455664 ps
CPU time 16.76 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 271184 kb
Host smart-bdae4d4a-af7b-4a24-a616-46ebb4ea8f36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723628092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3723628092
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3882610129
Short name T947
Test name
Test status
Simulation time 27550972830 ps
CPU time 51.94 seconds
Started Apr 02 03:39:59 PM PDT 24
Finished Apr 02 03:40:52 PM PDT 24
Peak memory 569008 kb
Host smart-bc9da581-4160-4939-bb8b-0936635a76dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882610129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3882610129
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.353862474
Short name T469
Test name
Test status
Simulation time 6781612304 ps
CPU time 119.15 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:42:01 PM PDT 24
Peak memory 608152 kb
Host smart-176be55b-01ef-42f6-9129-9ed592b8c60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353862474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.353862474
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.4066519623
Short name T346
Test name
Test status
Simulation time 3608775414 ps
CPU time 4.12 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:40:07 PM PDT 24
Peak memory 203896 kb
Host smart-391a42be-2820-4ff4-bd47-27f1eec33047
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066519623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.4066519623
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1876924058
Short name T278
Test name
Test status
Simulation time 12775916078 ps
CPU time 209.17 seconds
Started Apr 02 03:40:00 PM PDT 24
Finished Apr 02 03:43:29 PM PDT 24
Peak memory 869768 kb
Host smart-444a4a94-aee5-41f8-8070-fd151cfe6e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876924058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1876924058
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2460973648
Short name T1187
Test name
Test status
Simulation time 1005787432 ps
CPU time 3.6 seconds
Started Apr 02 03:40:04 PM PDT 24
Finished Apr 02 03:40:07 PM PDT 24
Peak memory 203812 kb
Host smart-ea0171db-52a3-421a-9598-6327e01302a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460973648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2460973648
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2892254070
Short name T24
Test name
Test status
Simulation time 6096962672 ps
CPU time 26.08 seconds
Started Apr 02 03:40:03 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 346464 kb
Host smart-fd5df2d7-05eb-4255-9654-048017615e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892254070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2892254070
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.1285808990
Short name T698
Test name
Test status
Simulation time 214498488 ps
CPU time 0.66 seconds
Started Apr 02 03:40:00 PM PDT 24
Finished Apr 02 03:40:01 PM PDT 24
Peak memory 203532 kb
Host smart-c511b44c-72b6-42fd-88fd-c2939ec386c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285808990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1285808990
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3564331075
Short name T1020
Test name
Test status
Simulation time 8652480508 ps
CPU time 20.81 seconds
Started Apr 02 03:39:59 PM PDT 24
Finished Apr 02 03:40:21 PM PDT 24
Peak memory 320900 kb
Host smart-e4aafaa0-4869-437b-8ac8-76fd271113ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564331075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3564331075
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.838680393
Short name T785
Test name
Test status
Simulation time 435199782 ps
CPU time 2.7 seconds
Started Apr 02 03:40:05 PM PDT 24
Finished Apr 02 03:40:08 PM PDT 24
Peak memory 203808 kb
Host smart-ccd87441-105d-43de-ba35-1634c80abe37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838680393 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.838680393
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1908444180
Short name T1039
Test name
Test status
Simulation time 10043896775 ps
CPU time 76.19 seconds
Started Apr 02 03:40:06 PM PDT 24
Finished Apr 02 03:41:22 PM PDT 24
Peak memory 543004 kb
Host smart-0ca6e1db-5043-4bc7-9e0a-ece7e8d7f6ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908444180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1908444180
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1268112537
Short name T807
Test name
Test status
Simulation time 10159530767 ps
CPU time 89.41 seconds
Started Apr 02 03:40:06 PM PDT 24
Finished Apr 02 03:41:35 PM PDT 24
Peak memory 723584 kb
Host smart-ece6817b-0bae-42c2-bcb1-562fdca9e6d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268112537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1268112537
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3140312093
Short name T588
Test name
Test status
Simulation time 5113739856 ps
CPU time 1.89 seconds
Started Apr 02 03:40:02 PM PDT 24
Finished Apr 02 03:40:04 PM PDT 24
Peak memory 203932 kb
Host smart-35800c9e-ab77-43c1-8418-84762621bab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140312093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3140312093
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.161167969
Short name T1138
Test name
Test status
Simulation time 2955141086 ps
CPU time 4.23 seconds
Started Apr 02 03:40:04 PM PDT 24
Finished Apr 02 03:40:08 PM PDT 24
Peak memory 203924 kb
Host smart-d5905533-bb19-46e8-949c-f97503fdcced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161167969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.161167969
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2978981189
Short name T1078
Test name
Test status
Simulation time 1016162509 ps
CPU time 39.95 seconds
Started Apr 02 03:40:08 PM PDT 24
Finished Apr 02 03:40:48 PM PDT 24
Peak memory 203756 kb
Host smart-d7348e68-8188-4fa4-9825-386b137af3b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978981189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2978981189
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3756242843
Short name T400
Test name
Test status
Simulation time 3398176769 ps
CPU time 33.36 seconds
Started Apr 02 03:40:03 PM PDT 24
Finished Apr 02 03:40:36 PM PDT 24
Peak memory 203896 kb
Host smart-7ab0632e-13e5-448d-b137-9fb44aa2036a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756242843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3756242843
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1348516075
Short name T1115
Test name
Test status
Simulation time 18373343061 ps
CPU time 1895.84 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 04:11:49 PM PDT 24
Peak memory 4431152 kb
Host smart-0bc75d22-2930-4ad5-aec3-bb48e41a22b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348516075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1348516075
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3833047863
Short name T847
Test name
Test status
Simulation time 1505510327 ps
CPU time 7.32 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:40:20 PM PDT 24
Peak memory 219868 kb
Host smart-319ad80c-2bb7-446d-807a-a5f09d3f7be1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833047863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3833047863
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3228720755
Short name T1144
Test name
Test status
Simulation time 19048327 ps
CPU time 0.61 seconds
Started Apr 02 03:40:11 PM PDT 24
Finished Apr 02 03:40:12 PM PDT 24
Peak memory 203652 kb
Host smart-cc8c1e4a-37c1-42a0-ac8c-6e21778aaefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228720755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3228720755
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1289592638
Short name T708
Test name
Test status
Simulation time 74606527 ps
CPU time 1.33 seconds
Started Apr 02 03:40:14 PM PDT 24
Finished Apr 02 03:40:15 PM PDT 24
Peak memory 203844 kb
Host smart-c34279ad-280c-4657-93e1-06d1194b4b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289592638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1289592638
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3980015271
Short name T784
Test name
Test status
Simulation time 2752576392 ps
CPU time 7.69 seconds
Started Apr 02 03:40:05 PM PDT 24
Finished Apr 02 03:40:13 PM PDT 24
Peak memory 256680 kb
Host smart-1cfe44fd-54ac-4f63-ba21-f24e64c4fe73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980015271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3980015271
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3521104295
Short name T444
Test name
Test status
Simulation time 1086048909 ps
CPU time 71.61 seconds
Started Apr 02 03:40:06 PM PDT 24
Finished Apr 02 03:41:18 PM PDT 24
Peak memory 467848 kb
Host smart-6a48d6b7-b817-4659-9df6-2658594d6dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521104295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3521104295
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.812721973
Short name T351
Test name
Test status
Simulation time 8891713205 ps
CPU time 58.44 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:41:11 PM PDT 24
Peak memory 620472 kb
Host smart-2365065e-4466-4b88-9cf9-d69865c06c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812721973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.812721973
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3339343492
Short name T780
Test name
Test status
Simulation time 225784025 ps
CPU time 1.01 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:40:13 PM PDT 24
Peak memory 203564 kb
Host smart-a087793d-406a-435f-9486-6b980d7ab933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339343492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3339343492
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1087786213
Short name T1034
Test name
Test status
Simulation time 1088688894 ps
CPU time 4.68 seconds
Started Apr 02 03:40:03 PM PDT 24
Finished Apr 02 03:40:08 PM PDT 24
Peak memory 229864 kb
Host smart-9ebd5ab6-45d5-4468-bf00-9fdb19c1de61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087786213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1087786213
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3985054762
Short name T949
Test name
Test status
Simulation time 4468788886 ps
CPU time 145.2 seconds
Started Apr 02 03:40:04 PM PDT 24
Finished Apr 02 03:42:30 PM PDT 24
Peak memory 1280040 kb
Host smart-44437296-961e-46bc-9032-598c19448881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985054762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3985054762
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3552093975
Short name T252
Test name
Test status
Simulation time 1692423996 ps
CPU time 17.22 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 203876 kb
Host smart-6c2fa809-9e7b-4d82-83e2-8c7fc208025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552093975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3552093975
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.226054837
Short name T873
Test name
Test status
Simulation time 6899973312 ps
CPU time 78.76 seconds
Started Apr 02 03:40:11 PM PDT 24
Finished Apr 02 03:41:30 PM PDT 24
Peak memory 396904 kb
Host smart-a5c43c00-c23f-45bf-a8a5-28e8d0cda56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226054837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.226054837
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.66825896
Short name T934
Test name
Test status
Simulation time 17763549 ps
CPU time 0.62 seconds
Started Apr 02 03:40:03 PM PDT 24
Finished Apr 02 03:40:04 PM PDT 24
Peak memory 203608 kb
Host smart-5c6ea3db-37ab-4d47-be09-b091bb59363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66825896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.66825896
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.1066115510
Short name T966
Test name
Test status
Simulation time 5153696730 ps
CPU time 38.87 seconds
Started Apr 02 03:40:08 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 520812 kb
Host smart-3adf04ba-59d5-4dd9-aaad-f05b91822a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066115510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1066115510
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.491504057
Short name T308
Test name
Test status
Simulation time 2983978782 ps
CPU time 24.5 seconds
Started Apr 02 03:40:06 PM PDT 24
Finished Apr 02 03:40:31 PM PDT 24
Peak memory 364456 kb
Host smart-7d695898-381e-4c9b-b46c-0c58ceb03d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491504057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.491504057
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2752279164
Short name T567
Test name
Test status
Simulation time 1848943791 ps
CPU time 3.43 seconds
Started Apr 02 03:40:08 PM PDT 24
Finished Apr 02 03:40:11 PM PDT 24
Peak memory 203748 kb
Host smart-b788ea4e-dcb6-4a5b-93cf-bea73d4e98d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752279164 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2752279164
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1215676001
Short name T484
Test name
Test status
Simulation time 10049687904 ps
CPU time 79.38 seconds
Started Apr 02 03:40:05 PM PDT 24
Finished Apr 02 03:41:25 PM PDT 24
Peak memory 587248 kb
Host smart-9893fc5f-fe0b-4f19-a822-8f055aef13b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215676001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1215676001
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.2592157035
Short name T825
Test name
Test status
Simulation time 10134027480 ps
CPU time 42.72 seconds
Started Apr 02 03:40:14 PM PDT 24
Finished Apr 02 03:40:57 PM PDT 24
Peak memory 447040 kb
Host smart-fa3204f4-cef3-4353-9d83-5d8f05bbd6ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592157035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.2592157035
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1026086858
Short name T877
Test name
Test status
Simulation time 568149283 ps
CPU time 2.92 seconds
Started Apr 02 03:40:07 PM PDT 24
Finished Apr 02 03:40:10 PM PDT 24
Peak memory 203844 kb
Host smart-c59aef39-fec0-4dde-a2d2-dff2f0db5c73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026086858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1026086858
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1557232699
Short name T464
Test name
Test status
Simulation time 4717393716 ps
CPU time 6.27 seconds
Started Apr 02 03:40:08 PM PDT 24
Finished Apr 02 03:40:14 PM PDT 24
Peak memory 203936 kb
Host smart-81f7a511-eb41-4ec1-bc1a-e0a58dbcc148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557232699 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1557232699
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.4261737877
Short name T1054
Test name
Test status
Simulation time 10562573245 ps
CPU time 3.7 seconds
Started Apr 02 03:40:10 PM PDT 24
Finished Apr 02 03:40:14 PM PDT 24
Peak memory 203880 kb
Host smart-9d5c8964-9c0f-4984-8376-ddd456ec0d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261737877 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.4261737877
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3391643610
Short name T1119
Test name
Test status
Simulation time 17690342351 ps
CPU time 49.34 seconds
Started Apr 02 03:40:11 PM PDT 24
Finished Apr 02 03:41:01 PM PDT 24
Peak memory 203904 kb
Host smart-3bb1033e-aba5-4d1a-954f-e8db62afa2cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391643610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3391643610
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2771393596
Short name T326
Test name
Test status
Simulation time 1130523402 ps
CPU time 48.55 seconds
Started Apr 02 03:40:06 PM PDT 24
Finished Apr 02 03:40:55 PM PDT 24
Peak memory 203852 kb
Host smart-a7aa0d30-5a9d-4dc5-9205-96fd858a7808
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771393596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2771393596
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.166775346
Short name T1161
Test name
Test status
Simulation time 14058369244 ps
CPU time 2024.85 seconds
Started Apr 02 03:40:10 PM PDT 24
Finished Apr 02 04:13:55 PM PDT 24
Peak memory 3434036 kb
Host smart-9fdb077b-e428-4937-91d2-8ba50f4fb98f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166775346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.166775346
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.230453753
Short name T575
Test name
Test status
Simulation time 1262489511 ps
CPU time 6.43 seconds
Started Apr 02 03:40:08 PM PDT 24
Finished Apr 02 03:40:15 PM PDT 24
Peak memory 212080 kb
Host smart-85f351e5-d02b-4dcb-957e-d54d2a239bb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230453753 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.230453753
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2064919334
Short name T413
Test name
Test status
Simulation time 81093960 ps
CPU time 0.58 seconds
Started Apr 02 03:40:15 PM PDT 24
Finished Apr 02 03:40:16 PM PDT 24
Peak memory 203604 kb
Host smart-ac8ea621-575e-4e92-95bb-02a57bcec3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064919334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2064919334
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1220562629
Short name T453
Test name
Test status
Simulation time 242431043 ps
CPU time 1.17 seconds
Started Apr 02 03:40:10 PM PDT 24
Finished Apr 02 03:40:11 PM PDT 24
Peak memory 212048 kb
Host smart-6ec290d6-c248-4ecd-bb09-6d96ae0b6e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220562629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1220562629
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.127542574
Short name T760
Test name
Test status
Simulation time 243216325 ps
CPU time 12.29 seconds
Started Apr 02 03:40:10 PM PDT 24
Finished Apr 02 03:40:23 PM PDT 24
Peak memory 251080 kb
Host smart-8e4faa5e-407b-4237-98a7-dffe5fe6b8e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127542574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.127542574
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2800882650
Short name T691
Test name
Test status
Simulation time 3146047186 ps
CPU time 52.38 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:41:04 PM PDT 24
Peak memory 572540 kb
Host smart-91aa8910-a312-4d76-a05e-6e5cdf1b900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800882650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2800882650
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.4293689418
Short name T94
Test name
Test status
Simulation time 2162324889 ps
CPU time 174.68 seconds
Started Apr 02 03:40:14 PM PDT 24
Finished Apr 02 03:43:09 PM PDT 24
Peak memory 741668 kb
Host smart-b98d8e00-86b7-476a-b876-10d093d5e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293689418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.4293689418
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3353888235
Short name T366
Test name
Test status
Simulation time 615853443 ps
CPU time 0.99 seconds
Started Apr 02 03:40:14 PM PDT 24
Finished Apr 02 03:40:15 PM PDT 24
Peak memory 203696 kb
Host smart-e6c3eceb-e4ac-403b-8d52-76a1a35604c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353888235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3353888235
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2158622798
Short name T729
Test name
Test status
Simulation time 1522159781 ps
CPU time 2.89 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:40:15 PM PDT 24
Peak memory 203832 kb
Host smart-9337203a-e395-4153-b9b1-0d7946139917
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158622798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2158622798
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.636251076
Short name T973
Test name
Test status
Simulation time 12796051644 ps
CPU time 194 seconds
Started Apr 02 03:40:10 PM PDT 24
Finished Apr 02 03:43:24 PM PDT 24
Peak memory 903024 kb
Host smart-6dd3be57-6084-47cc-b0de-abbd848af151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636251076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.636251076
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.4266014490
Short name T635
Test name
Test status
Simulation time 315173934 ps
CPU time 4.32 seconds
Started Apr 02 03:40:13 PM PDT 24
Finished Apr 02 03:40:18 PM PDT 24
Peak memory 203892 kb
Host smart-20f8dca0-35da-44c9-bfb9-20621e353222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266014490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.4266014490
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.159050487
Short name T507
Test name
Test status
Simulation time 7542711613 ps
CPU time 33.43 seconds
Started Apr 02 03:40:19 PM PDT 24
Finished Apr 02 03:40:53 PM PDT 24
Peak memory 445716 kb
Host smart-a374f05b-e49d-4980-baca-12c1457b5b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159050487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.159050487
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2142684156
Short name T1185
Test name
Test status
Simulation time 19100942 ps
CPU time 0.7 seconds
Started Apr 02 03:40:14 PM PDT 24
Finished Apr 02 03:40:14 PM PDT 24
Peak memory 203620 kb
Host smart-b3a8467f-3c33-4e7e-8f0c-faa2feb37f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142684156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2142684156
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1759487511
Short name T681
Test name
Test status
Simulation time 6573759392 ps
CPU time 70.25 seconds
Started Apr 02 03:40:11 PM PDT 24
Finished Apr 02 03:41:21 PM PDT 24
Peak memory 228280 kb
Host smart-45b8ada3-18d2-485d-9f71-2aab3c7a62da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759487511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1759487511
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3614899273
Short name T496
Test name
Test status
Simulation time 5511851168 ps
CPU time 26.37 seconds
Started Apr 02 03:40:10 PM PDT 24
Finished Apr 02 03:40:37 PM PDT 24
Peak memory 333356 kb
Host smart-f5b0062b-022e-4580-b391-88f049eb1380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614899273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3614899273
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.241398543
Short name T1146
Test name
Test status
Simulation time 446102631 ps
CPU time 2.79 seconds
Started Apr 02 03:40:13 PM PDT 24
Finished Apr 02 03:40:16 PM PDT 24
Peak memory 203812 kb
Host smart-33e08056-6588-4db7-807d-9d91439a53eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241398543 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.241398543
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2356374429
Short name T638
Test name
Test status
Simulation time 10027338540 ps
CPU time 83.34 seconds
Started Apr 02 03:40:13 PM PDT 24
Finished Apr 02 03:41:37 PM PDT 24
Peak memory 582784 kb
Host smart-b56c0281-6fa1-4095-99c1-a5341cfeb169
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356374429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2356374429
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3517460374
Short name T68
Test name
Test status
Simulation time 10124159419 ps
CPU time 16.09 seconds
Started Apr 02 03:40:20 PM PDT 24
Finished Apr 02 03:40:36 PM PDT 24
Peak memory 315824 kb
Host smart-b25f0413-51e9-4972-a817-e0aa234faf29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517460374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3517460374
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2282096380
Short name T866
Test name
Test status
Simulation time 373430207 ps
CPU time 2.39 seconds
Started Apr 02 03:40:16 PM PDT 24
Finished Apr 02 03:40:19 PM PDT 24
Peak memory 203732 kb
Host smart-b4a1dc0b-17df-41ee-932c-357c4584a1d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282096380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2282096380
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2763034100
Short name T368
Test name
Test status
Simulation time 5137048192 ps
CPU time 6.7 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:40:19 PM PDT 24
Peak memory 220056 kb
Host smart-b8a11035-110b-48de-bfc2-5e5fe371413f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763034100 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2763034100
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2077050694
Short name T1158
Test name
Test status
Simulation time 3564493433 ps
CPU time 14.17 seconds
Started Apr 02 03:40:12 PM PDT 24
Finished Apr 02 03:40:26 PM PDT 24
Peak memory 203896 kb
Host smart-69487837-3ab9-4c85-868e-c5c62cf56f7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077050694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2077050694
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2985347760
Short name T1162
Test name
Test status
Simulation time 13555762340 ps
CPU time 27.21 seconds
Started Apr 02 03:40:17 PM PDT 24
Finished Apr 02 03:40:44 PM PDT 24
Peak memory 221084 kb
Host smart-9ad8a9e2-56a5-484c-ace4-109481679eaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985347760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2985347760
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2660557538
Short name T766
Test name
Test status
Simulation time 42789272846 ps
CPU time 327.67 seconds
Started Apr 02 03:40:14 PM PDT 24
Finished Apr 02 03:45:42 PM PDT 24
Peak memory 2096152 kb
Host smart-d8c32fc7-70c5-4dfc-84da-a77a83db9a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660557538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2660557538
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2026350106
Short name T707
Test name
Test status
Simulation time 6016416768 ps
CPU time 7.19 seconds
Started Apr 02 03:40:15 PM PDT 24
Finished Apr 02 03:40:23 PM PDT 24
Peak memory 219972 kb
Host smart-892a7cf1-6aee-4dd1-8844-ea09a7e50f00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026350106 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2026350106
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3752680709
Short name T763
Test name
Test status
Simulation time 109244020 ps
CPU time 0.6 seconds
Started Apr 02 03:40:24 PM PDT 24
Finished Apr 02 03:40:25 PM PDT 24
Peak memory 203632 kb
Host smart-0b65e1a8-b4b3-4f92-99df-259b3613c1f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752680709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3752680709
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3698732584
Short name T886
Test name
Test status
Simulation time 238127561 ps
CPU time 1.92 seconds
Started Apr 02 03:40:20 PM PDT 24
Finished Apr 02 03:40:22 PM PDT 24
Peak memory 212124 kb
Host smart-75e9401c-aae7-416b-8bfb-463c18db0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698732584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3698732584
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1348772376
Short name T610
Test name
Test status
Simulation time 1045792224 ps
CPU time 14.07 seconds
Started Apr 02 03:40:21 PM PDT 24
Finished Apr 02 03:40:35 PM PDT 24
Peak memory 259940 kb
Host smart-f390f70e-92be-4115-b8e4-e921782a38ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348772376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1348772376
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2334927887
Short name T406
Test name
Test status
Simulation time 3251835429 ps
CPU time 58.46 seconds
Started Apr 02 03:40:19 PM PDT 24
Finished Apr 02 03:41:17 PM PDT 24
Peak memory 598552 kb
Host smart-985f3633-b2f9-43e9-921e-fdea47c167a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334927887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2334927887
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3569457931
Short name T880
Test name
Test status
Simulation time 2225844323 ps
CPU time 83.27 seconds
Started Apr 02 03:40:17 PM PDT 24
Finished Apr 02 03:41:41 PM PDT 24
Peak memory 730888 kb
Host smart-435720cf-241a-49f1-a652-108a43073b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569457931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3569457931
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1523641525
Short name T1123
Test name
Test status
Simulation time 90256678 ps
CPU time 1.02 seconds
Started Apr 02 03:40:21 PM PDT 24
Finished Apr 02 03:40:22 PM PDT 24
Peak memory 203688 kb
Host smart-ba2a8c9c-db11-4df4-ab93-f0c016b03b70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523641525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1523641525
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.2827360769
Short name T719
Test name
Test status
Simulation time 181502790 ps
CPU time 4.61 seconds
Started Apr 02 03:40:19 PM PDT 24
Finished Apr 02 03:40:24 PM PDT 24
Peak memory 203816 kb
Host smart-91a56a79-6f65-422e-9f7e-da65610186d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827360769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.2827360769
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3259068297
Short name T176
Test name
Test status
Simulation time 13398452489 ps
CPU time 124.07 seconds
Started Apr 02 03:40:16 PM PDT 24
Finished Apr 02 03:42:21 PM PDT 24
Peak memory 1114108 kb
Host smart-356fd90a-8d01-41ef-aa6f-b262a3eb3394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259068297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3259068297
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2567008377
Short name T1030
Test name
Test status
Simulation time 339935051 ps
CPU time 5.76 seconds
Started Apr 02 03:40:27 PM PDT 24
Finished Apr 02 03:40:32 PM PDT 24
Peak memory 203828 kb
Host smart-256111f9-2f01-4a94-845a-353ab73aa233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567008377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2567008377
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.990236262
Short name T661
Test name
Test status
Simulation time 5032351881 ps
CPU time 60.48 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:41:26 PM PDT 24
Peak memory 346616 kb
Host smart-9708c4ea-07a4-420a-a9d1-5ed538dee0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990236262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.990236262
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.1786646804
Short name T185
Test name
Test status
Simulation time 28003519 ps
CPU time 0.66 seconds
Started Apr 02 03:40:15 PM PDT 24
Finished Apr 02 03:40:16 PM PDT 24
Peak memory 203520 kb
Host smart-4bb743f6-d0bc-47ad-8463-ab09f01a5e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786646804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1786646804
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.279712660
Short name T1193
Test name
Test status
Simulation time 6333483291 ps
CPU time 243.76 seconds
Started Apr 02 03:40:21 PM PDT 24
Finished Apr 02 03:44:25 PM PDT 24
Peak memory 931684 kb
Host smart-6533ec2f-9f1a-498f-b9dc-ea26f6416538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279712660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.279712660
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2058638139
Short name T597
Test name
Test status
Simulation time 1438362005 ps
CPU time 30.59 seconds
Started Apr 02 03:40:13 PM PDT 24
Finished Apr 02 03:40:44 PM PDT 24
Peak memory 421932 kb
Host smart-304caf5c-7c37-4f4a-9765-e49f125df01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058638139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2058638139
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3001499857
Short name T388
Test name
Test status
Simulation time 3207983911 ps
CPU time 3.15 seconds
Started Apr 02 03:40:22 PM PDT 24
Finished Apr 02 03:40:26 PM PDT 24
Peak memory 203868 kb
Host smart-cc92e711-da4c-4132-9127-ecd8cb7318c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001499857 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3001499857
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2151991816
Short name T65
Test name
Test status
Simulation time 10321168600 ps
CPU time 33.7 seconds
Started Apr 02 03:40:20 PM PDT 24
Finished Apr 02 03:40:54 PM PDT 24
Peak memory 437584 kb
Host smart-bd849a8b-d38a-459a-a04a-8b0b2819243b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151991816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2151991816
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1084030171
Short name T553
Test name
Test status
Simulation time 10121368645 ps
CPU time 85.54 seconds
Started Apr 02 03:40:21 PM PDT 24
Finished Apr 02 03:41:47 PM PDT 24
Peak memory 689672 kb
Host smart-6e72f450-5e77-4b80-ac2a-e1918675bade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084030171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1084030171
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3258230766
Short name T735
Test name
Test status
Simulation time 432343723 ps
CPU time 2.5 seconds
Started Apr 02 03:40:20 PM PDT 24
Finished Apr 02 03:40:23 PM PDT 24
Peak memory 203804 kb
Host smart-21184c5f-a310-4747-8089-acae56736f7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258230766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3258230766
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1600858595
Short name T945
Test name
Test status
Simulation time 1087249657 ps
CPU time 5.34 seconds
Started Apr 02 03:40:17 PM PDT 24
Finished Apr 02 03:40:22 PM PDT 24
Peak memory 211928 kb
Host smart-9861c890-b684-4592-aa8b-3a30f814ee00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600858595 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1600858595
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.2280227175
Short name T212
Test name
Test status
Simulation time 6267016664 ps
CPU time 4.65 seconds
Started Apr 02 03:40:21 PM PDT 24
Finished Apr 02 03:40:27 PM PDT 24
Peak memory 203764 kb
Host smart-17e07a81-ab36-4cf7-b500-a82307cb59db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280227175 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.2280227175
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2856472225
Short name T110
Test name
Test status
Simulation time 7118048191 ps
CPU time 11.52 seconds
Started Apr 02 03:40:18 PM PDT 24
Finished Apr 02 03:40:30 PM PDT 24
Peak memory 208292 kb
Host smart-13e71de5-854f-4a38-9f9d-412a6265fc04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856472225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2856472225
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.857270478
Short name T770
Test name
Test status
Simulation time 5012200727 ps
CPU time 348.52 seconds
Started Apr 02 03:40:18 PM PDT 24
Finished Apr 02 03:46:07 PM PDT 24
Peak memory 1336892 kb
Host smart-be7c9759-5627-4ba9-9f6c-6f84bf6254a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857270478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.857270478
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.761764795
Short name T380
Test name
Test status
Simulation time 5420553826 ps
CPU time 6.58 seconds
Started Apr 02 03:40:23 PM PDT 24
Finished Apr 02 03:40:30 PM PDT 24
Peak memory 203948 kb
Host smart-6305ff15-031f-4220-a8e9-fbe98042b65e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761764795 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.761764795
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1024806728
Short name T302
Test name
Test status
Simulation time 59827452 ps
CPU time 0.61 seconds
Started Apr 02 03:40:31 PM PDT 24
Finished Apr 02 03:40:32 PM PDT 24
Peak memory 203620 kb
Host smart-ff7e396b-3d05-41b4-ac92-96a23e31d1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024806728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1024806728
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2385743006
Short name T778
Test name
Test status
Simulation time 90229820 ps
CPU time 1.28 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:40:28 PM PDT 24
Peak memory 211992 kb
Host smart-8f93af14-1ccf-4e16-8df9-ed9e4d52d791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385743006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2385743006
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1610618092
Short name T682
Test name
Test status
Simulation time 1013432051 ps
CPU time 6.6 seconds
Started Apr 02 03:40:28 PM PDT 24
Finished Apr 02 03:40:35 PM PDT 24
Peak memory 260856 kb
Host smart-7cad8317-c15c-4a08-838c-7c61c091fc8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610618092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1610618092
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1023520486
Short name T956
Test name
Test status
Simulation time 1890036519 ps
CPU time 139.61 seconds
Started Apr 02 03:40:27 PM PDT 24
Finished Apr 02 03:42:47 PM PDT 24
Peak memory 673788 kb
Host smart-f8849b34-b652-4125-989f-15986c7380ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023520486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1023520486
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.644821706
Short name T531
Test name
Test status
Simulation time 8338849818 ps
CPU time 54.98 seconds
Started Apr 02 03:40:24 PM PDT 24
Finished Apr 02 03:41:20 PM PDT 24
Peak memory 590068 kb
Host smart-d8928cbb-338c-4912-9d55-ab68d745134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644821706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.644821706
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1304577172
Short name T449
Test name
Test status
Simulation time 1243742295 ps
CPU time 1.07 seconds
Started Apr 02 03:40:27 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 203704 kb
Host smart-cc70ff63-7eda-472c-ba57-9aaed7be6fe1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304577172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1304577172
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2732478944
Short name T662
Test name
Test status
Simulation time 104554319 ps
CPU time 5.56 seconds
Started Apr 02 03:40:23 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 203848 kb
Host smart-171665c1-3dad-456b-98ef-3b69b1c27032
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732478944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2732478944
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2300451783
Short name T407
Test name
Test status
Simulation time 12815211895 ps
CPU time 234.67 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:44:21 PM PDT 24
Peak memory 1002440 kb
Host smart-f55690a4-c264-44df-a569-ab2bf80630d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300451783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2300451783
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2560752538
Short name T1163
Test name
Test status
Simulation time 514951533 ps
CPU time 17.42 seconds
Started Apr 02 03:40:28 PM PDT 24
Finished Apr 02 03:40:46 PM PDT 24
Peak memory 203832 kb
Host smart-58884e8a-ae8f-4ca6-8241-e52148a1fcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560752538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2560752538
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.1534629380
Short name T938
Test name
Test status
Simulation time 1074638905 ps
CPU time 22.91 seconds
Started Apr 02 03:40:29 PM PDT 24
Finished Apr 02 03:40:52 PM PDT 24
Peak memory 347660 kb
Host smart-1acadc46-baf4-4a7a-b71c-964cbd9d307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534629380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.1534629380
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3572882096
Short name T456
Test name
Test status
Simulation time 88884034 ps
CPU time 0.69 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:40:27 PM PDT 24
Peak memory 203604 kb
Host smart-ce1a593f-183b-4e00-8c70-a98db9367b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572882096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3572882096
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1587669110
Short name T264
Test name
Test status
Simulation time 1171331703 ps
CPU time 58.13 seconds
Started Apr 02 03:40:25 PM PDT 24
Finished Apr 02 03:41:23 PM PDT 24
Peak memory 333700 kb
Host smart-5838f21e-ab2c-49c7-a981-d7d18839a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587669110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1587669110
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1379518956
Short name T803
Test name
Test status
Simulation time 1997432466 ps
CPU time 2.65 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:40:29 PM PDT 24
Peak memory 203736 kb
Host smart-50db51fe-d83e-4bab-b59e-e1501a7db4fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379518956 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1379518956
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2604956289
Short name T1191
Test name
Test status
Simulation time 10123163521 ps
CPU time 33.41 seconds
Started Apr 02 03:40:31 PM PDT 24
Finished Apr 02 03:41:05 PM PDT 24
Peak memory 370332 kb
Host smart-32af2d8e-9a55-499e-888b-fd109701d549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604956289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2604956289
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2845905352
Short name T485
Test name
Test status
Simulation time 11195850310 ps
CPU time 7.86 seconds
Started Apr 02 03:40:28 PM PDT 24
Finished Apr 02 03:40:36 PM PDT 24
Peak memory 269140 kb
Host smart-d8c9fb87-e367-46d3-93ef-012a0ef5563b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845905352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2845905352
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1270321348
Short name T51
Test name
Test status
Simulation time 786177782 ps
CPU time 2.62 seconds
Started Apr 02 03:40:28 PM PDT 24
Finished Apr 02 03:40:30 PM PDT 24
Peak memory 203788 kb
Host smart-155adda7-ac15-4681-8361-63162a949ae0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270321348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1270321348
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2474557419
Short name T533
Test name
Test status
Simulation time 2636607457 ps
CPU time 3.46 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:40:30 PM PDT 24
Peak memory 203920 kb
Host smart-cb334f85-1c7d-4a3c-abf4-160163af9072
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474557419 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2474557419
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1901206287
Short name T79
Test name
Test status
Simulation time 25117331886 ps
CPU time 8.01 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:40:34 PM PDT 24
Peak memory 203944 kb
Host smart-a8d19986-2f18-4f40-b680-9d5394348079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901206287 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1901206287
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.3789529262
Short name T378
Test name
Test status
Simulation time 2277137729 ps
CPU time 15.67 seconds
Started Apr 02 03:40:23 PM PDT 24
Finished Apr 02 03:40:39 PM PDT 24
Peak memory 203904 kb
Host smart-2b06f240-9d83-4b91-83a9-bbac41dfe223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789529262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.3789529262
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.800657790
Short name T254
Test name
Test status
Simulation time 1243793388 ps
CPU time 11.66 seconds
Started Apr 02 03:40:28 PM PDT 24
Finished Apr 02 03:40:39 PM PDT 24
Peak memory 203764 kb
Host smart-35ea0150-cc30-4729-8f33-5ee1ee3408a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800657790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.800657790
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.594361633
Short name T755
Test name
Test status
Simulation time 26014466956 ps
CPU time 7.44 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:40:34 PM PDT 24
Peak memory 203876 kb
Host smart-b002f6b5-8f9d-4816-b5ba-c883ef61940b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594361633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.594361633
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2855544395
Short name T684
Test name
Test status
Simulation time 9743584605 ps
CPU time 116.04 seconds
Started Apr 02 03:40:26 PM PDT 24
Finished Apr 02 03:42:22 PM PDT 24
Peak memory 1289712 kb
Host smart-4532d6a2-32c4-4389-8af6-3efd4bcefc77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855544395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2855544395
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1225640599
Short name T800
Test name
Test status
Simulation time 2790379877 ps
CPU time 7.71 seconds
Started Apr 02 03:40:29 PM PDT 24
Finished Apr 02 03:40:37 PM PDT 24
Peak memory 212144 kb
Host smart-a04d2a95-7908-40be-b96a-71b0600f965c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225640599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1225640599
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1476906032
Short name T293
Test name
Test status
Simulation time 27173011 ps
CPU time 0.64 seconds
Started Apr 02 03:40:37 PM PDT 24
Finished Apr 02 03:40:37 PM PDT 24
Peak memory 203696 kb
Host smart-322e1ae6-9813-4b13-871f-f974735b8b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476906032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1476906032
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3010294401
Short name T268
Test name
Test status
Simulation time 85851999 ps
CPU time 1.43 seconds
Started Apr 02 03:40:32 PM PDT 24
Finished Apr 02 03:40:34 PM PDT 24
Peak memory 220232 kb
Host smart-018b92eb-cf91-4a53-ad91-24e71ab8badd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010294401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3010294401
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.128298877
Short name T1050
Test name
Test status
Simulation time 331433675 ps
CPU time 17.64 seconds
Started Apr 02 03:40:32 PM PDT 24
Finished Apr 02 03:40:50 PM PDT 24
Peak memory 267572 kb
Host smart-fe27845e-54f5-4251-a64e-5c08b9278721
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128298877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.128298877
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.4238904210
Short name T428
Test name
Test status
Simulation time 4109660306 ps
CPU time 122.23 seconds
Started Apr 02 03:40:31 PM PDT 24
Finished Apr 02 03:42:34 PM PDT 24
Peak memory 561156 kb
Host smart-bfcdb356-10db-4e13-9a25-89a394d50049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238904210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.4238904210
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1897318889
Short name T902
Test name
Test status
Simulation time 1695254003 ps
CPU time 58.61 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:41:33 PM PDT 24
Peak memory 607940 kb
Host smart-edf4e9b6-0039-4904-9849-03d6e5577eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897318889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1897318889
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3220016034
Short name T473
Test name
Test status
Simulation time 133161381 ps
CPU time 0.84 seconds
Started Apr 02 03:40:32 PM PDT 24
Finished Apr 02 03:40:33 PM PDT 24
Peak memory 203672 kb
Host smart-189703d3-7c77-452f-8612-3e4ba24624d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220016034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3220016034
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2054919122
Short name T983
Test name
Test status
Simulation time 3969868409 ps
CPU time 11.65 seconds
Started Apr 02 03:40:33 PM PDT 24
Finished Apr 02 03:40:45 PM PDT 24
Peak memory 245916 kb
Host smart-d7eea73e-8c9b-4638-9064-72958f15a323
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054919122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2054919122
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.941272690
Short name T549
Test name
Test status
Simulation time 10846640494 ps
CPU time 71.05 seconds
Started Apr 02 03:40:32 PM PDT 24
Finished Apr 02 03:41:44 PM PDT 24
Peak memory 849960 kb
Host smart-e4070587-f9f6-4c7a-a7d2-90f21b56218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941272690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.941272690
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3808712849
Short name T916
Test name
Test status
Simulation time 296876252 ps
CPU time 12.41 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 203832 kb
Host smart-392e0b19-1eaf-4220-b8ee-3f17e6ac2e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808712849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3808712849
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.699233960
Short name T948
Test name
Test status
Simulation time 43735747 ps
CPU time 0.68 seconds
Started Apr 02 03:40:29 PM PDT 24
Finished Apr 02 03:40:30 PM PDT 24
Peak memory 203588 kb
Host smart-9b73d435-7fef-46ae-9653-7ae959265d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699233960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.699233960
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1308396564
Short name T396
Test name
Test status
Simulation time 6244143665 ps
CPU time 121.36 seconds
Started Apr 02 03:40:32 PM PDT 24
Finished Apr 02 03:42:34 PM PDT 24
Peak memory 666040 kb
Host smart-7406445d-f661-4fbb-bb56-f1dc05da3eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308396564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1308396564
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3881892593
Short name T1057
Test name
Test status
Simulation time 5461713802 ps
CPU time 22.35 seconds
Started Apr 02 03:40:33 PM PDT 24
Finished Apr 02 03:40:56 PM PDT 24
Peak memory 330576 kb
Host smart-4d1361cc-3c36-4cf3-a529-339eb6cc75c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881892593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3881892593
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.895191144
Short name T39
Test name
Test status
Simulation time 886923613 ps
CPU time 4.34 seconds
Started Apr 02 03:40:38 PM PDT 24
Finished Apr 02 03:40:42 PM PDT 24
Peak memory 203792 kb
Host smart-fffda494-a910-4735-8452-f1b9b2d45237
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895191144 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.895191144
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1135752075
Short name T994
Test name
Test status
Simulation time 11010069281 ps
CPU time 4.24 seconds
Started Apr 02 03:40:33 PM PDT 24
Finished Apr 02 03:40:38 PM PDT 24
Peak memory 221516 kb
Host smart-d07b234a-18bf-4301-81d2-bf42808bb597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135752075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1135752075
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1756161829
Short name T512
Test name
Test status
Simulation time 10059507338 ps
CPU time 97.19 seconds
Started Apr 02 03:40:32 PM PDT 24
Finished Apr 02 03:42:10 PM PDT 24
Peak memory 720992 kb
Host smart-1fc6de50-0f18-427e-a54f-3137d81a25fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756161829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1756161829
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.814137060
Short name T1118
Test name
Test status
Simulation time 5345853892 ps
CPU time 2.41 seconds
Started Apr 02 03:40:35 PM PDT 24
Finished Apr 02 03:40:38 PM PDT 24
Peak memory 203840 kb
Host smart-7b6382f1-6908-452c-9051-bf9f0a6be07c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814137060 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.814137060
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2209275792
Short name T72
Test name
Test status
Simulation time 902614701 ps
CPU time 4.79 seconds
Started Apr 02 03:40:31 PM PDT 24
Finished Apr 02 03:40:36 PM PDT 24
Peak memory 213232 kb
Host smart-8b8ee112-58bc-43e7-b257-340b0db5a155
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209275792 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2209275792
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2397609682
Short name T670
Test name
Test status
Simulation time 14704299281 ps
CPU time 6.25 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:40:40 PM PDT 24
Peak memory 203880 kb
Host smart-205e587b-1084-453e-8c30-4d498f46417d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397609682 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2397609682
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2324755908
Short name T467
Test name
Test status
Simulation time 2078762934 ps
CPU time 17.91 seconds
Started Apr 02 03:40:32 PM PDT 24
Finished Apr 02 03:40:50 PM PDT 24
Peak memory 203808 kb
Host smart-9571c027-3d75-45a7-8715-cc2034fb9f18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324755908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2324755908
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1252302030
Short name T335
Test name
Test status
Simulation time 1058304027 ps
CPU time 43.1 seconds
Started Apr 02 03:40:31 PM PDT 24
Finished Apr 02 03:41:15 PM PDT 24
Peak memory 203788 kb
Host smart-6a3ac92c-ac37-4bfd-94c6-900836955103
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252302030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1252302030
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3665377098
Short name T265
Test name
Test status
Simulation time 23481840755 ps
CPU time 1422.68 seconds
Started Apr 02 03:40:31 PM PDT 24
Finished Apr 02 04:04:15 PM PDT 24
Peak memory 5236884 kb
Host smart-969fbc72-a370-4e33-8f92-6e09c5e0b4bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665377098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3665377098
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2641729295
Short name T26
Test name
Test status
Simulation time 3952590949 ps
CPU time 5.61 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:40:40 PM PDT 24
Peak memory 203928 kb
Host smart-3ea4392c-d2c8-42dd-8d88-e7b6758803d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641729295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2641729295
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.4085683388
Short name T42
Test name
Test status
Simulation time 3830639632 ps
CPU time 4.72 seconds
Started Apr 02 03:40:36 PM PDT 24
Finished Apr 02 03:40:41 PM PDT 24
Peak memory 204088 kb
Host smart-a4cdcca5-b825-4e2b-84af-9f9759a055fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085683388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.4085683388
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1587321272
Short name T601
Test name
Test status
Simulation time 44149150 ps
CPU time 0.61 seconds
Started Apr 02 03:40:43 PM PDT 24
Finished Apr 02 03:40:43 PM PDT 24
Peak memory 203700 kb
Host smart-63d75589-f79c-4c4b-b348-8742c8772a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587321272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1587321272
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.902770338
Short name T933
Test name
Test status
Simulation time 58021711 ps
CPU time 1.31 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:40:36 PM PDT 24
Peak memory 212020 kb
Host smart-e5c1ff19-b34b-4e87-8dde-212b95cd988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902770338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.902770338
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1459185843
Short name T922
Test name
Test status
Simulation time 665703621 ps
CPU time 5.74 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:40:40 PM PDT 24
Peak memory 249280 kb
Host smart-c000eed0-2b11-4139-ae75-ba65bec9f5bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459185843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1459185843
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3399040401
Short name T420
Test name
Test status
Simulation time 2859879352 ps
CPU time 92.89 seconds
Started Apr 02 03:40:38 PM PDT 24
Finished Apr 02 03:42:11 PM PDT 24
Peak memory 550332 kb
Host smart-48197621-c25a-47be-ab66-fd48edd3f98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399040401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3399040401
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1619093638
Short name T558
Test name
Test status
Simulation time 7538755418 ps
CPU time 52.14 seconds
Started Apr 02 03:40:38 PM PDT 24
Finished Apr 02 03:41:31 PM PDT 24
Peak memory 653548 kb
Host smart-58ee61e9-079c-4738-adaa-b2cbf6078dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619093638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1619093638
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2039697495
Short name T454
Test name
Test status
Simulation time 86501130 ps
CPU time 0.83 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:40:35 PM PDT 24
Peak memory 203624 kb
Host smart-463d64a5-b0f9-4468-aff6-901e11739948
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039697495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2039697495
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3728141033
Short name T451
Test name
Test status
Simulation time 434773687 ps
CPU time 6.97 seconds
Started Apr 02 03:40:33 PM PDT 24
Finished Apr 02 03:40:40 PM PDT 24
Peak memory 203752 kb
Host smart-a002d0d6-f91b-4f81-9459-4c1cb978261e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728141033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3728141033
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.465018605
Short name T724
Test name
Test status
Simulation time 2655344021 ps
CPU time 176.05 seconds
Started Apr 02 03:40:35 PM PDT 24
Finished Apr 02 03:43:31 PM PDT 24
Peak memory 850308 kb
Host smart-42004521-4712-4ce4-8c90-ab2e19c6daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465018605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.465018605
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.80923942
Short name T269
Test name
Test status
Simulation time 348032393 ps
CPU time 5.73 seconds
Started Apr 02 03:40:41 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 203748 kb
Host smart-244a933f-59c6-4c00-9b3b-eecf0fb262fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80923942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.80923942
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.3427119466
Short name T823
Test name
Test status
Simulation time 15647547677 ps
CPU time 79.65 seconds
Started Apr 02 03:40:45 PM PDT 24
Finished Apr 02 03:42:05 PM PDT 24
Peak memory 373404 kb
Host smart-4b88ef22-df12-4a3d-9adf-20bb73178638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427119466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3427119466
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.1767920715
Short name T332
Test name
Test status
Simulation time 252985616 ps
CPU time 0.66 seconds
Started Apr 02 03:40:34 PM PDT 24
Finished Apr 02 03:40:36 PM PDT 24
Peak memory 203604 kb
Host smart-503d4598-64e3-4924-9b2b-597097109b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767920715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1767920715
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2564652168
Short name T510
Test name
Test status
Simulation time 4945942309 ps
CPU time 58.13 seconds
Started Apr 02 03:40:36 PM PDT 24
Finished Apr 02 03:41:34 PM PDT 24
Peak memory 355436 kb
Host smart-a0f8ee17-4f9e-4221-9515-44c104f1e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564652168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2564652168
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.130603036
Short name T1071
Test name
Test status
Simulation time 2404465004 ps
CPU time 26.63 seconds
Started Apr 02 03:40:38 PM PDT 24
Finished Apr 02 03:41:05 PM PDT 24
Peak memory 350188 kb
Host smart-a0ea1566-fd2d-4e57-b133-65a7b72ee0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130603036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.130603036
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2141146854
Short name T1172
Test name
Test status
Simulation time 689845470 ps
CPU time 3.62 seconds
Started Apr 02 03:40:43 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 212032 kb
Host smart-4ae5f0e9-7575-40d7-a8d5-22dc1dc39fe4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141146854 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2141146854
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.4125419518
Short name T976
Test name
Test status
Simulation time 10484173575 ps
CPU time 14.92 seconds
Started Apr 02 03:40:37 PM PDT 24
Finished Apr 02 03:40:52 PM PDT 24
Peak memory 301908 kb
Host smart-7c03618b-7857-4220-9e5d-2039d7cc0d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125419518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.4125419518
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.664792495
Short name T981
Test name
Test status
Simulation time 10399518461 ps
CPU time 15.35 seconds
Started Apr 02 03:40:38 PM PDT 24
Finished Apr 02 03:40:54 PM PDT 24
Peak memory 314128 kb
Host smart-4f0dfec6-bc7f-4221-87fc-90554324637f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664792495 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.664792495
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.2100440576
Short name T222
Test name
Test status
Simulation time 346116268 ps
CPU time 2.33 seconds
Started Apr 02 03:40:43 PM PDT 24
Finished Apr 02 03:40:45 PM PDT 24
Peak memory 203804 kb
Host smart-da808ffb-15dd-4c76-80f4-9cff19d5d043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100440576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.2100440576
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2520805954
Short name T885
Test name
Test status
Simulation time 2040854245 ps
CPU time 4.69 seconds
Started Apr 02 03:40:36 PM PDT 24
Finished Apr 02 03:40:41 PM PDT 24
Peak memory 203792 kb
Host smart-fc96bf11-1170-475d-b70f-6e318be271d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520805954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2520805954
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2375125214
Short name T892
Test name
Test status
Simulation time 8733659064 ps
CPU time 14.47 seconds
Started Apr 02 03:40:35 PM PDT 24
Finished Apr 02 03:40:50 PM PDT 24
Peak memory 203844 kb
Host smart-57f16f69-fc3c-4e97-bf96-d4715b1074d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375125214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2375125214
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.4101081849
Short name T1023
Test name
Test status
Simulation time 5392269978 ps
CPU time 21.81 seconds
Started Apr 02 03:40:39 PM PDT 24
Finished Apr 02 03:41:01 PM PDT 24
Peak memory 222372 kb
Host smart-6d9b08ee-7ce7-4d0e-9b60-3d502a077c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101081849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.4101081849
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.37706419
Short name T1061
Test name
Test status
Simulation time 14732619220 ps
CPU time 8.37 seconds
Started Apr 02 03:40:39 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 203756 kb
Host smart-57c4b743-b0d1-4f18-98e2-cc47180ed53b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37706419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stress_wr.37706419
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3037550967
Short name T210
Test name
Test status
Simulation time 34518639252 ps
CPU time 601.37 seconds
Started Apr 02 03:40:41 PM PDT 24
Finished Apr 02 03:50:42 PM PDT 24
Peak memory 2972672 kb
Host smart-78760d2d-ceb1-4552-ba13-96ddf6c48ca6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037550967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3037550967
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.38656123
Short name T864
Test name
Test status
Simulation time 4382519328 ps
CPU time 6.96 seconds
Started Apr 02 03:40:42 PM PDT 24
Finished Apr 02 03:40:50 PM PDT 24
Peak memory 220140 kb
Host smart-a8732fa9-81fe-434f-aa2b-fc685f8bd04f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38656123 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_timeout.38656123
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3668947458
Short name T679
Test name
Test status
Simulation time 32217535 ps
CPU time 0.61 seconds
Started Apr 02 03:40:50 PM PDT 24
Finished Apr 02 03:40:51 PM PDT 24
Peak memory 203704 kb
Host smart-edf1ae56-e4db-4644-9c06-936013c5ce03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668947458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3668947458
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3264833363
Short name T696
Test name
Test status
Simulation time 75190821 ps
CPU time 1.24 seconds
Started Apr 02 03:40:44 PM PDT 24
Finished Apr 02 03:40:45 PM PDT 24
Peak memory 203788 kb
Host smart-66e093f0-205d-40bc-a6be-e4326b74b9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264833363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3264833363
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3046933615
Short name T914
Test name
Test status
Simulation time 226705281 ps
CPU time 5.66 seconds
Started Apr 02 03:40:41 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 246668 kb
Host smart-4ad47082-37e5-4d7b-8844-96ee6230f087
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046933615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3046933615
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2534096930
Short name T1029
Test name
Test status
Simulation time 8287153328 ps
CPU time 59.02 seconds
Started Apr 02 03:40:41 PM PDT 24
Finished Apr 02 03:41:41 PM PDT 24
Peak memory 594828 kb
Host smart-46cbacb4-368e-4b23-b1bb-9d3b0e8882b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534096930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2534096930
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2612553830
Short name T492
Test name
Test status
Simulation time 4434724746 ps
CPU time 165.37 seconds
Started Apr 02 03:40:42 PM PDT 24
Finished Apr 02 03:43:28 PM PDT 24
Peak memory 713428 kb
Host smart-5e772634-beda-4c42-a3fc-ea6b02da750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612553830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2612553830
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.409901307
Short name T1072
Test name
Test status
Simulation time 879119639 ps
CPU time 0.85 seconds
Started Apr 02 03:40:43 PM PDT 24
Finished Apr 02 03:40:44 PM PDT 24
Peak memory 203676 kb
Host smart-e9d5a857-db15-4f62-b917-4014135cacc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409901307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.409901307
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.4055015185
Short name T1165
Test name
Test status
Simulation time 161226313 ps
CPU time 4.83 seconds
Started Apr 02 03:40:44 PM PDT 24
Finished Apr 02 03:40:49 PM PDT 24
Peak memory 232016 kb
Host smart-3b80d919-6694-4ee4-a72a-3c1bc21b71ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055015185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.4055015185
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4231323722
Short name T952
Test name
Test status
Simulation time 31963193935 ps
CPU time 56.15 seconds
Started Apr 02 03:40:42 PM PDT 24
Finished Apr 02 03:41:38 PM PDT 24
Peak memory 841500 kb
Host smart-0112ec6d-e6b9-45e1-a221-d44a8c097599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231323722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4231323722
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3427279198
Short name T626
Test name
Test status
Simulation time 693826447 ps
CPU time 13.97 seconds
Started Apr 02 03:40:50 PM PDT 24
Finished Apr 02 03:41:05 PM PDT 24
Peak memory 203868 kb
Host smart-c12bcfb9-c723-4525-8358-3263f9920337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427279198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3427279198
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2809861729
Short name T290
Test name
Test status
Simulation time 6616538723 ps
CPU time 91.04 seconds
Started Apr 02 03:40:45 PM PDT 24
Finished Apr 02 03:42:17 PM PDT 24
Peak memory 445068 kb
Host smart-7eb60611-640e-499d-b734-b072d702af97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809861729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2809861729
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2539620460
Short name T184
Test name
Test status
Simulation time 19584607 ps
CPU time 0.67 seconds
Started Apr 02 03:40:41 PM PDT 24
Finished Apr 02 03:40:42 PM PDT 24
Peak memory 203592 kb
Host smart-d6bfdd21-cbc0-4885-8c0a-98e6e21e3fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539620460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2539620460
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2120640275
Short name T581
Test name
Test status
Simulation time 12224994465 ps
CPU time 160.66 seconds
Started Apr 02 03:40:41 PM PDT 24
Finished Apr 02 03:43:22 PM PDT 24
Peak memory 203864 kb
Host smart-f82d7659-ffed-4f51-9c39-238c39177de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120640275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2120640275
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3243984158
Short name T1109
Test name
Test status
Simulation time 1307899666 ps
CPU time 67.63 seconds
Started Apr 02 03:40:42 PM PDT 24
Finished Apr 02 03:41:50 PM PDT 24
Peak memory 357692 kb
Host smart-08507014-81a8-41e3-b6c2-827a0a0c5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243984158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3243984158
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3842372595
Short name T509
Test name
Test status
Simulation time 2179827396 ps
CPU time 2.87 seconds
Started Apr 02 03:40:45 PM PDT 24
Finished Apr 02 03:40:47 PM PDT 24
Peak memory 203868 kb
Host smart-9ea0ee7c-f4c6-4ede-a982-47b065252309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842372595 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3842372595
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2293707492
Short name T341
Test name
Test status
Simulation time 10155931657 ps
CPU time 13.79 seconds
Started Apr 02 03:40:47 PM PDT 24
Finished Apr 02 03:41:01 PM PDT 24
Peak memory 291716 kb
Host smart-80313951-e3b7-48bd-9a35-c07825cdd68b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293707492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2293707492
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3334775872
Short name T486
Test name
Test status
Simulation time 10088808355 ps
CPU time 95.68 seconds
Started Apr 02 03:40:56 PM PDT 24
Finished Apr 02 03:42:32 PM PDT 24
Peak memory 735004 kb
Host smart-550834d1-b7fc-42ee-8428-d2ce6dd3a2de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334775872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3334775872
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.764379558
Short name T423
Test name
Test status
Simulation time 2245452275 ps
CPU time 2.29 seconds
Started Apr 02 03:40:51 PM PDT 24
Finished Apr 02 03:40:53 PM PDT 24
Peak memory 203840 kb
Host smart-e1d5df7d-757b-41b0-b058-0c1a609b5d95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764379558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.764379558
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1021417586
Short name T839
Test name
Test status
Simulation time 13421738564 ps
CPU time 5.94 seconds
Started Apr 02 03:40:44 PM PDT 24
Finished Apr 02 03:40:50 PM PDT 24
Peak memory 212112 kb
Host smart-8bc0c02d-701f-4dd3-8d98-eded3fc3e3e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021417586 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1021417586
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1655419943
Short name T1002
Test name
Test status
Simulation time 875943517 ps
CPU time 14.63 seconds
Started Apr 02 03:41:01 PM PDT 24
Finished Apr 02 03:41:16 PM PDT 24
Peak memory 203812 kb
Host smart-420d7d17-2d84-4f0b-9ea0-d2bcc6feb0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655419943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1655419943
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2402105471
Short name T347
Test name
Test status
Simulation time 14410945052 ps
CPU time 17.05 seconds
Started Apr 02 03:40:48 PM PDT 24
Finished Apr 02 03:41:05 PM PDT 24
Peak memory 216056 kb
Host smart-ebae6c84-a854-4bbb-8e59-a34eb002a2cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402105471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2402105471
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2598824913
Short name T462
Test name
Test status
Simulation time 20470483620 ps
CPU time 1302 seconds
Started Apr 02 03:40:47 PM PDT 24
Finished Apr 02 04:02:30 PM PDT 24
Peak memory 4772968 kb
Host smart-e9d48847-6959-4f75-8871-3af213356da0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598824913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2598824913
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3313048851
Short name T855
Test name
Test status
Simulation time 1552462105 ps
CPU time 7.1 seconds
Started Apr 02 03:40:45 PM PDT 24
Finished Apr 02 03:40:53 PM PDT 24
Peak memory 218808 kb
Host smart-3eec65fd-5fbf-4340-9fb6-6b3d19907ecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313048851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3313048851
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3087448636
Short name T1017
Test name
Test status
Simulation time 28807645 ps
CPU time 0.65 seconds
Started Apr 02 03:40:52 PM PDT 24
Finished Apr 02 03:40:53 PM PDT 24
Peak memory 203700 kb
Host smart-6931315b-66c3-4bc4-aa0e-4c5ed303f44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087448636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3087448636
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.942656957
Short name T350
Test name
Test status
Simulation time 49304862 ps
CPU time 1.39 seconds
Started Apr 02 03:40:50 PM PDT 24
Finished Apr 02 03:40:51 PM PDT 24
Peak memory 212036 kb
Host smart-c8e58116-4f77-4da1-93f5-691896304f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942656957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.942656957
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3378895202
Short name T733
Test name
Test status
Simulation time 764997903 ps
CPU time 4.17 seconds
Started Apr 02 03:40:49 PM PDT 24
Finished Apr 02 03:40:53 PM PDT 24
Peak memory 233664 kb
Host smart-719ee9c2-89e3-44bf-ab74-ef24fb48c7e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378895202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3378895202
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.4219992931
Short name T279
Test name
Test status
Simulation time 2332867124 ps
CPU time 64.99 seconds
Started Apr 02 03:40:55 PM PDT 24
Finished Apr 02 03:42:00 PM PDT 24
Peak memory 701012 kb
Host smart-4bee2135-d9c6-48f5-b416-ee39fc5c85a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219992931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.4219992931
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1263061148
Short name T1164
Test name
Test status
Simulation time 1832019046 ps
CPU time 54.07 seconds
Started Apr 02 03:40:47 PM PDT 24
Finished Apr 02 03:41:41 PM PDT 24
Peak memory 651728 kb
Host smart-55ccaba0-fe7f-4e45-900c-596e56214135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263061148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1263061148
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2667244952
Short name T480
Test name
Test status
Simulation time 903702036 ps
CPU time 1.07 seconds
Started Apr 02 03:40:50 PM PDT 24
Finished Apr 02 03:40:51 PM PDT 24
Peak memory 203824 kb
Host smart-d32d3a9a-3d6f-4193-9cac-78a8d3849dfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667244952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2667244952
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3334832138
Short name T822
Test name
Test status
Simulation time 207278718 ps
CPU time 10.9 seconds
Started Apr 02 03:40:49 PM PDT 24
Finished Apr 02 03:41:00 PM PDT 24
Peak memory 241324 kb
Host smart-00a5af03-fa04-4e9b-af81-7fc4d605f7c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334832138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3334832138
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3931198725
Short name T787
Test name
Test status
Simulation time 11143116781 ps
CPU time 183.05 seconds
Started Apr 02 03:40:49 PM PDT 24
Finished Apr 02 03:43:52 PM PDT 24
Peak memory 870436 kb
Host smart-f05fbef0-d30e-453f-bc5a-d66f3885fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931198725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3931198725
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.999981862
Short name T295
Test name
Test status
Simulation time 238650575 ps
CPU time 3.43 seconds
Started Apr 02 03:40:50 PM PDT 24
Finished Apr 02 03:40:54 PM PDT 24
Peak memory 203828 kb
Host smart-bd529002-0ffd-46de-93f2-bff3d2b2d0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999981862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.999981862
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.2177579038
Short name T1169
Test name
Test status
Simulation time 3732503368 ps
CPU time 90.12 seconds
Started Apr 02 03:40:51 PM PDT 24
Finished Apr 02 03:42:21 PM PDT 24
Peak memory 406912 kb
Host smart-8b25bcc7-2012-4dba-80ec-775f0b60feab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177579038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2177579038
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3058952234
Short name T202
Test name
Test status
Simulation time 44795446 ps
CPU time 0.68 seconds
Started Apr 02 03:40:49 PM PDT 24
Finished Apr 02 03:40:49 PM PDT 24
Peak memory 203608 kb
Host smart-01981e34-75e6-4096-a5ab-e161bba28950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058952234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3058952234
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1616446122
Short name T970
Test name
Test status
Simulation time 32983395668 ps
CPU time 91.15 seconds
Started Apr 02 03:40:48 PM PDT 24
Finished Apr 02 03:42:19 PM PDT 24
Peak memory 203908 kb
Host smart-1d2569d3-8c53-41c6-a97c-c02cbd4bf49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616446122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1616446122
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4229015688
Short name T357
Test name
Test status
Simulation time 1376464822 ps
CPU time 66.75 seconds
Started Apr 02 03:40:50 PM PDT 24
Finished Apr 02 03:41:57 PM PDT 24
Peak memory 378824 kb
Host smart-57766a03-47fd-4128-bb2a-579edd24c1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229015688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4229015688
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2263204977
Short name T893
Test name
Test status
Simulation time 997573189 ps
CPU time 3.01 seconds
Started Apr 02 03:40:56 PM PDT 24
Finished Apr 02 03:41:00 PM PDT 24
Peak memory 203672 kb
Host smart-3da2ad5c-9c8c-4201-8357-090c670146f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263204977 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2263204977
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2850884269
Short name T965
Test name
Test status
Simulation time 10157841926 ps
CPU time 14.4 seconds
Started Apr 02 03:40:53 PM PDT 24
Finished Apr 02 03:41:08 PM PDT 24
Peak memory 289920 kb
Host smart-4f1d2e59-6076-4bf2-b980-7e75daf6b08c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850884269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2850884269
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2261655361
Short name T590
Test name
Test status
Simulation time 10376037606 ps
CPU time 3.83 seconds
Started Apr 02 03:40:56 PM PDT 24
Finished Apr 02 03:41:00 PM PDT 24
Peak memory 229732 kb
Host smart-2a0f1f5d-0b59-4d2c-9796-3c39880c41f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261655361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2261655361
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.9095571
Short name T874
Test name
Test status
Simulation time 1616062185 ps
CPU time 2.49 seconds
Started Apr 02 03:40:58 PM PDT 24
Finished Apr 02 03:41:01 PM PDT 24
Peak memory 203704 kb
Host smart-0b804bfe-7a15-44ea-ae38-7b20b75fc398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9095571 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.i2c_target_hrst.9095571
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1964059147
Short name T283
Test name
Test status
Simulation time 4255888529 ps
CPU time 5.25 seconds
Started Apr 02 03:40:54 PM PDT 24
Finished Apr 02 03:41:00 PM PDT 24
Peak memory 210176 kb
Host smart-c9950ba4-4846-4a2b-9939-d599ba6c7f12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964059147 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1964059147
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2187448883
Short name T571
Test name
Test status
Simulation time 4045437807 ps
CPU time 12.51 seconds
Started Apr 02 03:40:50 PM PDT 24
Finished Apr 02 03:41:02 PM PDT 24
Peak memory 203872 kb
Host smart-b327fdba-f93a-42f1-b95a-c3e63f3bebf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187448883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2187448883
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.952376638
Short name T960
Test name
Test status
Simulation time 1683963450 ps
CPU time 25.23 seconds
Started Apr 02 03:40:52 PM PDT 24
Finished Apr 02 03:41:18 PM PDT 24
Peak memory 236212 kb
Host smart-d6244dba-fdff-4dd1-a2e8-61180cdc1f8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952376638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.952376638
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.710422149
Short name T1042
Test name
Test status
Simulation time 27976261869 ps
CPU time 335.96 seconds
Started Apr 02 03:40:54 PM PDT 24
Finished Apr 02 03:46:31 PM PDT 24
Peak memory 2482584 kb
Host smart-9f5b360f-ac31-4077-817e-92b41612776a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710422149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.710422149
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3823026194
Short name T692
Test name
Test status
Simulation time 16663155012 ps
CPU time 6.72 seconds
Started Apr 02 03:40:53 PM PDT 24
Finished Apr 02 03:41:00 PM PDT 24
Peak memory 220140 kb
Host smart-532df350-197a-4f9d-b104-3af25bad0120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823026194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3823026194
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.2266997213
Short name T912
Test name
Test status
Simulation time 3196553643 ps
CPU time 5.49 seconds
Started Apr 02 03:40:53 PM PDT 24
Finished Apr 02 03:40:58 PM PDT 24
Peak memory 203856 kb
Host smart-2e4148fc-8f3f-4cbc-b511-35b883336ccc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266997213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.2266997213
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3046188370
Short name T738
Test name
Test status
Simulation time 50688291 ps
CPU time 0.63 seconds
Started Apr 02 03:36:55 PM PDT 24
Finished Apr 02 03:36:55 PM PDT 24
Peak memory 203720 kb
Host smart-a96337b0-8ebd-4779-94bf-9289d70984ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046188370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3046188370
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3366009025
Short name T683
Test name
Test status
Simulation time 46900042 ps
CPU time 1.29 seconds
Started Apr 02 03:36:52 PM PDT 24
Finished Apr 02 03:36:54 PM PDT 24
Peak memory 211880 kb
Host smart-a42ed4c9-f652-4eb7-9283-c91a3e66a0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366009025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3366009025
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.596629120
Short name T659
Test name
Test status
Simulation time 241171045 ps
CPU time 12.12 seconds
Started Apr 02 03:36:48 PM PDT 24
Finished Apr 02 03:37:00 PM PDT 24
Peak memory 248156 kb
Host smart-e2e53953-98cd-489a-ab14-0d8ff28877d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596629120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.596629120
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2141413162
Short name T36
Test name
Test status
Simulation time 2095835159 ps
CPU time 71.43 seconds
Started Apr 02 03:36:49 PM PDT 24
Finished Apr 02 03:38:02 PM PDT 24
Peak memory 648308 kb
Host smart-ec84b45e-b7f9-4571-b945-994cb026f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141413162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2141413162
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.2886439819
Short name T773
Test name
Test status
Simulation time 9552754971 ps
CPU time 159.1 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:39:25 PM PDT 24
Peak memory 729100 kb
Host smart-18841af8-42e7-41bc-96c1-879505c99b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886439819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2886439819
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1091037991
Short name T734
Test name
Test status
Simulation time 313431034 ps
CPU time 0.85 seconds
Started Apr 02 03:36:45 PM PDT 24
Finished Apr 02 03:36:46 PM PDT 24
Peak memory 203676 kb
Host smart-6637299f-e358-4076-9eb8-3fd9528f1f3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091037991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1091037991
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3703475295
Short name T844
Test name
Test status
Simulation time 2177958512 ps
CPU time 7.22 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:36:53 PM PDT 24
Peak memory 225756 kb
Host smart-f948930b-50f8-4662-b02a-7eef6a4c2622
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703475295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3703475295
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.389301286
Short name T599
Test name
Test status
Simulation time 47996077898 ps
CPU time 101.41 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:38:22 PM PDT 24
Peak memory 1039136 kb
Host smart-ce839178-f9fc-4241-aba1-139991852efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389301286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.389301286
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2312542009
Short name T1084
Test name
Test status
Simulation time 2689136142 ps
CPU time 7.61 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 203912 kb
Host smart-0c8628e6-08c7-483d-9cb7-57ffbadc652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312542009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2312542009
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.512373549
Short name T320
Test name
Test status
Simulation time 1013911920 ps
CPU time 21.35 seconds
Started Apr 02 03:37:07 PM PDT 24
Finished Apr 02 03:37:28 PM PDT 24
Peak memory 333732 kb
Host smart-2aafd9c4-88cb-41f6-933d-a0fb047c61a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512373549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.512373549
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3348647739
Short name T108
Test name
Test status
Simulation time 45757619 ps
CPU time 0.66 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:42 PM PDT 24
Peak memory 203624 kb
Host smart-3c666e80-28e9-484f-8cf4-b6dfebc8f9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348647739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3348647739
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1871628764
Short name T1073
Test name
Test status
Simulation time 8181829269 ps
CPU time 39.2 seconds
Started Apr 02 03:36:41 PM PDT 24
Finished Apr 02 03:37:21 PM PDT 24
Peak memory 544628 kb
Host smart-47c5eea6-2501-4b05-94dc-6dd4f7a70662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871628764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1871628764
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.4173126986
Short name T838
Test name
Test status
Simulation time 4932617359 ps
CPU time 33.02 seconds
Started Apr 02 03:36:38 PM PDT 24
Finished Apr 02 03:37:11 PM PDT 24
Peak memory 277096 kb
Host smart-94dc5847-ee84-4481-b851-4237892f08e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173126986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.4173126986
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3246754976
Short name T857
Test name
Test status
Simulation time 2303057999 ps
CPU time 3.21 seconds
Started Apr 02 03:36:52 PM PDT 24
Finished Apr 02 03:36:56 PM PDT 24
Peak memory 203760 kb
Host smart-589f3305-7b7b-460b-a71b-b42845911f64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246754976 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3246754976
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.158598530
Short name T890
Test name
Test status
Simulation time 10025918075 ps
CPU time 72.67 seconds
Started Apr 02 03:36:51 PM PDT 24
Finished Apr 02 03:38:03 PM PDT 24
Peak memory 598772 kb
Host smart-bf170dcd-69e9-4197-a214-0ad81d9c6b35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158598530 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.158598530
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.97061580
Short name T1062
Test name
Test status
Simulation time 10034609763 ps
CPU time 80.36 seconds
Started Apr 02 03:36:49 PM PDT 24
Finished Apr 02 03:38:09 PM PDT 24
Peak memory 671212 kb
Host smart-035e7f59-323d-4ea5-a0bc-5d3c5543480e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97061580 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_fifo_reset_tx.97061580
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.916114614
Short name T863
Test name
Test status
Simulation time 470383439 ps
CPU time 2.6 seconds
Started Apr 02 03:36:49 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 203760 kb
Host smart-99f96c1b-ae22-4d44-911e-a09002fbab52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916114614 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.916114614
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3004312031
Short name T1024
Test name
Test status
Simulation time 680489699 ps
CPU time 3.58 seconds
Started Apr 02 03:36:38 PM PDT 24
Finished Apr 02 03:36:42 PM PDT 24
Peak memory 203752 kb
Host smart-f96158c0-3c8d-4420-85da-ed5f968320e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004312031 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3004312031
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1432163309
Short name T919
Test name
Test status
Simulation time 3156055836 ps
CPU time 9.85 seconds
Started Apr 02 03:36:56 PM PDT 24
Finished Apr 02 03:37:06 PM PDT 24
Peak memory 203788 kb
Host smart-051eef13-a0ba-4f19-80b7-ab4097a691e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432163309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1432163309
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.4150126720
Short name T668
Test name
Test status
Simulation time 994522374 ps
CPU time 18.24 seconds
Started Apr 02 03:36:49 PM PDT 24
Finished Apr 02 03:37:07 PM PDT 24
Peak memory 210600 kb
Host smart-871a6105-2fd1-4177-8540-e5603cbff614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150126720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.4150126720
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3896158873
Short name T896
Test name
Test status
Simulation time 42195288183 ps
CPU time 443.36 seconds
Started Apr 02 03:37:00 PM PDT 24
Finished Apr 02 03:44:25 PM PDT 24
Peak memory 2423836 kb
Host smart-33dbdcbd-2778-494d-aec8-3d302697e046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896158873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3896158873
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2568639563
Short name T987
Test name
Test status
Simulation time 1197682229 ps
CPU time 6.82 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 219996 kb
Host smart-6c452d23-d4fb-460e-b4f0-b0adf70ef834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568639563 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2568639563
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1466617149
Short name T545
Test name
Test status
Simulation time 61932442 ps
CPU time 0.63 seconds
Started Apr 02 03:36:50 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 203652 kb
Host smart-46d094a0-2b7d-49bc-b8b4-2cbc5d727c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466617149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1466617149
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2565932652
Short name T1160
Test name
Test status
Simulation time 168494935 ps
CPU time 1.62 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:46 PM PDT 24
Peak memory 212064 kb
Host smart-bec7a488-ccda-4b00-a374-e4d07e4ca6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565932652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2565932652
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1953920722
Short name T563
Test name
Test status
Simulation time 1014364920 ps
CPU time 4.54 seconds
Started Apr 02 03:36:47 PM PDT 24
Finished Apr 02 03:36:52 PM PDT 24
Peak memory 252836 kb
Host smart-68d14913-08d7-4bf1-a3fa-8f9111e3ecd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953920722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1953920722
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1891311996
Short name T858
Test name
Test status
Simulation time 7814651844 ps
CPU time 59.15 seconds
Started Apr 02 03:36:54 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 651592 kb
Host smart-67f795b5-8a79-45af-9d55-54050f4eb60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891311996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1891311996
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2552644508
Short name T1049
Test name
Test status
Simulation time 7195713415 ps
CPU time 124.33 seconds
Started Apr 02 03:36:47 PM PDT 24
Finished Apr 02 03:38:52 PM PDT 24
Peak memory 581780 kb
Host smart-68ab29c5-a31f-445b-86af-983344332afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552644508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2552644508
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3958113978
Short name T200
Test name
Test status
Simulation time 212847320 ps
CPU time 0.95 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:43 PM PDT 24
Peak memory 203740 kb
Host smart-0abeb644-918a-422f-862d-49eaa34b92fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958113978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3958113978
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.780754646
Short name T706
Test name
Test status
Simulation time 148759241 ps
CPU time 7.45 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:36:54 PM PDT 24
Peak memory 203796 kb
Host smart-fe2f8767-b974-4a1c-9781-ebfeecdedfb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780754646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.780754646
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.163259914
Short name T317
Test name
Test status
Simulation time 11533507261 ps
CPU time 167.04 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:39:31 PM PDT 24
Peak memory 778100 kb
Host smart-e0485065-f04f-41d8-972d-917df2ac7ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163259914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.163259914
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1025938492
Short name T595
Test name
Test status
Simulation time 1335729858 ps
CPU time 5.47 seconds
Started Apr 02 03:36:53 PM PDT 24
Finished Apr 02 03:36:59 PM PDT 24
Peak memory 203772 kb
Host smart-af673a21-5aef-465d-b582-bac90ed05a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025938492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1025938492
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.69089722
Short name T35
Test name
Test status
Simulation time 1143139978 ps
CPU time 20.66 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:37:04 PM PDT 24
Peak memory 353052 kb
Host smart-ea4632ce-1530-4152-8526-88c039156a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69089722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.69089722
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.247599756
Short name T551
Test name
Test status
Simulation time 28039330 ps
CPU time 0.67 seconds
Started Apr 02 03:36:48 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 203556 kb
Host smart-fb2508b5-6b14-4864-8e29-e43e95d0d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247599756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.247599756
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2507668090
Short name T369
Test name
Test status
Simulation time 28012077738 ps
CPU time 764.23 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:49:28 PM PDT 24
Peak memory 1848184 kb
Host smart-9bf5e036-5d9f-4d21-8e5d-a10ba311d987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507668090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2507668090
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.640000578
Short name T764
Test name
Test status
Simulation time 1474513218 ps
CPU time 35.46 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:37:20 PM PDT 24
Peak memory 419976 kb
Host smart-73d42821-16c6-4e8c-8edc-fcf033885338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640000578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.640000578
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3865432984
Short name T277
Test name
Test status
Simulation time 7999113463 ps
CPU time 4.97 seconds
Started Apr 02 03:36:52 PM PDT 24
Finished Apr 02 03:36:57 PM PDT 24
Peak memory 203920 kb
Host smart-fd13133f-d060-43cb-9513-0354cd50c768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865432984 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3865432984
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1165107727
Short name T336
Test name
Test status
Simulation time 10106542546 ps
CPU time 76.66 seconds
Started Apr 02 03:36:47 PM PDT 24
Finished Apr 02 03:38:03 PM PDT 24
Peak memory 578940 kb
Host smart-30ebd031-234c-4ad7-b867-a03984654fc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165107727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1165107727
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.4155524424
Short name T583
Test name
Test status
Simulation time 10353618895 ps
CPU time 12.6 seconds
Started Apr 02 03:36:48 PM PDT 24
Finished Apr 02 03:37:01 PM PDT 24
Peak memory 306520 kb
Host smart-72b59d58-8ad8-4524-a2ad-5cce605873a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155524424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.4155524424
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1954694485
Short name T1135
Test name
Test status
Simulation time 431461263 ps
CPU time 2.83 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:47 PM PDT 24
Peak memory 203820 kb
Host smart-7c3591ce-bb6a-4e39-b694-d5887a8bb1ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954694485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1954694485
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3837296023
Short name T589
Test name
Test status
Simulation time 2971028296 ps
CPU time 4.47 seconds
Started Apr 02 03:36:54 PM PDT 24
Finished Apr 02 03:36:58 PM PDT 24
Peak memory 205008 kb
Host smart-35541835-c790-4856-a82d-d70f58a4ab61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837296023 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3837296023
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2621259859
Short name T529
Test name
Test status
Simulation time 6243625869 ps
CPU time 14.55 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:37:00 PM PDT 24
Peak memory 203804 kb
Host smart-73df25eb-81b6-428b-8f86-e5f0a76a36e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621259859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2621259859
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1068455571
Short name T209
Test name
Test status
Simulation time 1630865056 ps
CPU time 36.38 seconds
Started Apr 02 03:36:40 PM PDT 24
Finished Apr 02 03:37:16 PM PDT 24
Peak memory 203772 kb
Host smart-9d6ea4c6-1c50-40ed-9e55-5926b0c1d513
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068455571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1068455571
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1498181965
Short name T657
Test name
Test status
Simulation time 16456805746 ps
CPU time 114.37 seconds
Started Apr 02 03:36:50 PM PDT 24
Finished Apr 02 03:38:45 PM PDT 24
Peak memory 1047104 kb
Host smart-aea3cb3b-ee04-4b58-b0cb-017e2c63e5d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498181965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1498181965
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.4008358703
Short name T1009
Test name
Test status
Simulation time 1291408260 ps
CPU time 7.11 seconds
Started Apr 02 03:36:51 PM PDT 24
Finished Apr 02 03:36:59 PM PDT 24
Peak memory 219940 kb
Host smart-470d30b2-791f-4e8a-a85d-d067cc41153f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008358703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.4008358703
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.190901070
Short name T958
Test name
Test status
Simulation time 1415837822 ps
CPU time 5.48 seconds
Started Apr 02 03:36:42 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 203804 kb
Host smart-89060618-5305-4a55-9911-05b296b39f70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190901070 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_unexp_stop.190901070
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.4255383537
Short name T980
Test name
Test status
Simulation time 59890969 ps
CPU time 0.64 seconds
Started Apr 02 03:37:03 PM PDT 24
Finished Apr 02 03:37:04 PM PDT 24
Peak memory 203704 kb
Host smart-5602e033-f468-454e-ab63-b347388f1927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255383537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.4255383537
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2904530267
Short name T603
Test name
Test status
Simulation time 297047914 ps
CPU time 1.4 seconds
Started Apr 02 03:36:47 PM PDT 24
Finished Apr 02 03:36:49 PM PDT 24
Peak memory 212044 kb
Host smart-87a7f87b-6a50-443e-a832-73a363eab98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904530267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2904530267
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.4207091109
Short name T939
Test name
Test status
Simulation time 1376637156 ps
CPU time 17.28 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:37:01 PM PDT 24
Peak memory 262568 kb
Host smart-17d70688-95c1-48c5-8e95-d9b47d28134e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207091109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.4207091109
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3640915575
Short name T711
Test name
Test status
Simulation time 9310979859 ps
CPU time 90.55 seconds
Started Apr 02 03:36:48 PM PDT 24
Finished Apr 02 03:38:19 PM PDT 24
Peak memory 339816 kb
Host smart-702b4713-69ea-499f-b03e-667589c128a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640915575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3640915575
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3418458525
Short name T349
Test name
Test status
Simulation time 1728333615 ps
CPU time 87.49 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:38:14 PM PDT 24
Peak memory 517292 kb
Host smart-309acf60-8d8a-491d-bd53-015835b51e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418458525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3418458525
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.832464253
Short name T895
Test name
Test status
Simulation time 433496912 ps
CPU time 0.84 seconds
Started Apr 02 03:36:47 PM PDT 24
Finished Apr 02 03:36:47 PM PDT 24
Peak memory 203696 kb
Host smart-c3083615-ddad-4edd-a840-28ab9feb6db8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832464253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.832464253
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2692450994
Short name T425
Test name
Test status
Simulation time 1161124701 ps
CPU time 4.18 seconds
Started Apr 02 03:37:00 PM PDT 24
Finished Apr 02 03:37:06 PM PDT 24
Peak memory 226232 kb
Host smart-0564cfab-07cd-4f2e-be70-40f770dad5c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692450994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2692450994
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2381130744
Short name T236
Test name
Test status
Simulation time 2354706964 ps
CPU time 144.69 seconds
Started Apr 02 03:36:43 PM PDT 24
Finished Apr 02 03:39:08 PM PDT 24
Peak memory 722480 kb
Host smart-bf1a8902-01c3-4756-a0b7-7ca394a1be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381130744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2381130744
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.516006601
Short name T178
Test name
Test status
Simulation time 372969738 ps
CPU time 15.01 seconds
Started Apr 02 03:36:56 PM PDT 24
Finished Apr 02 03:37:12 PM PDT 24
Peak memory 203892 kb
Host smart-6bbfa4a8-515d-4b91-8bf3-990946bc60f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516006601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.516006601
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3633520080
Short name T1151
Test name
Test status
Simulation time 3621942471 ps
CPU time 12.4 seconds
Started Apr 02 03:37:07 PM PDT 24
Finished Apr 02 03:37:19 PM PDT 24
Peak memory 261256 kb
Host smart-c2b00a74-c472-41ea-ad2a-da29b961e707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633520080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3633520080
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1331277346
Short name T978
Test name
Test status
Simulation time 43534377 ps
CPU time 0.62 seconds
Started Apr 02 03:36:46 PM PDT 24
Finished Apr 02 03:36:47 PM PDT 24
Peak memory 203608 kb
Host smart-5c725703-9264-4b12-80e1-9d9bcd00b440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331277346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1331277346
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3882178410
Short name T408
Test name
Test status
Simulation time 2928058388 ps
CPU time 10.62 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:55 PM PDT 24
Peak memory 220676 kb
Host smart-76103200-fba0-4d23-afac-dfd2713cf4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882178410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3882178410
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2370218369
Short name T162
Test name
Test status
Simulation time 6788289237 ps
CPU time 51.71 seconds
Started Apr 02 03:36:50 PM PDT 24
Finished Apr 02 03:37:42 PM PDT 24
Peak memory 309872 kb
Host smart-b3687d82-6162-4ce5-9143-1b919bba6c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370218369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2370218369
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3747815924
Short name T441
Test name
Test status
Simulation time 407005468 ps
CPU time 2.69 seconds
Started Apr 02 03:37:11 PM PDT 24
Finished Apr 02 03:37:14 PM PDT 24
Peak memory 203820 kb
Host smart-88712702-c491-47e7-804b-a4024472779c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747815924 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3747815924
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2965869280
Short name T238
Test name
Test status
Simulation time 10325681659 ps
CPU time 13.23 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:58 PM PDT 24
Peak memory 272528 kb
Host smart-dc5aaa12-8a6e-41f3-be38-2e31b82d3aa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965869280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2965869280
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3041416713
Short name T1058
Test name
Test status
Simulation time 10659423536 ps
CPU time 13.7 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:57 PM PDT 24
Peak memory 332200 kb
Host smart-3344bc3a-582b-4576-91f3-5b30fa92f70f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041416713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3041416713
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.597697724
Short name T52
Test name
Test status
Simulation time 356727594 ps
CPU time 2.23 seconds
Started Apr 02 03:37:01 PM PDT 24
Finished Apr 02 03:37:04 PM PDT 24
Peak memory 203800 kb
Host smart-a6498c17-323a-421c-b314-57101df99636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597697724 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.597697724
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2432357119
Short name T343
Test name
Test status
Simulation time 4445166880 ps
CPU time 4.69 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:48 PM PDT 24
Peak memory 205224 kb
Host smart-8c4f869a-16ff-4d9a-8d85-ac2e6b39b782
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432357119 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2432357119
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.499785598
Short name T856
Test name
Test status
Simulation time 1891974627 ps
CPU time 15.55 seconds
Started Apr 02 03:36:52 PM PDT 24
Finished Apr 02 03:37:08 PM PDT 24
Peak memory 203824 kb
Host smart-2666c185-4d5c-40dc-9378-14a5bbfa2824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499785598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.499785598
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3769296326
Short name T702
Test name
Test status
Simulation time 6215844557 ps
CPU time 67.7 seconds
Started Apr 02 03:36:53 PM PDT 24
Finished Apr 02 03:38:01 PM PDT 24
Peak memory 208624 kb
Host smart-9f7d0300-6e13-4afd-b214-702975c4fb97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769296326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3769296326
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.1741110994
Short name T259
Test name
Test status
Simulation time 17934301214 ps
CPU time 31.93 seconds
Started Apr 02 03:36:50 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 436156 kb
Host smart-0f05da05-fe00-4ba0-9525-3dcce8692612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741110994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.1741110994
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1463725676
Short name T1094
Test name
Test status
Simulation time 11989963043 ps
CPU time 6.91 seconds
Started Apr 02 03:36:44 PM PDT 24
Finished Apr 02 03:36:51 PM PDT 24
Peak memory 212176 kb
Host smart-6c4767ff-e19f-4c57-ac81-394634fc1eb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463725676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1463725676
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2354864740
Short name T739
Test name
Test status
Simulation time 40136162 ps
CPU time 0.61 seconds
Started Apr 02 03:36:58 PM PDT 24
Finished Apr 02 03:36:59 PM PDT 24
Peak memory 203736 kb
Host smart-04f58924-82be-4bb6-afbd-9d4a24aa84c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354864740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2354864740
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2521730412
Short name T333
Test name
Test status
Simulation time 110367171 ps
CPU time 1.73 seconds
Started Apr 02 03:37:09 PM PDT 24
Finished Apr 02 03:37:11 PM PDT 24
Peak memory 211956 kb
Host smart-9863e5ad-4378-46b0-8165-e46cbc51390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521730412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2521730412
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3183378811
Short name T1149
Test name
Test status
Simulation time 367630335 ps
CPU time 8.47 seconds
Started Apr 02 03:37:02 PM PDT 24
Finished Apr 02 03:37:11 PM PDT 24
Peak memory 280444 kb
Host smart-3164abde-424d-4a10-ab6c-2e2f6994c6b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183378811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.3183378811
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2221555774
Short name T1114
Test name
Test status
Simulation time 1973224052 ps
CPU time 73.17 seconds
Started Apr 02 03:37:08 PM PDT 24
Finished Apr 02 03:38:21 PM PDT 24
Peak memory 630024 kb
Host smart-f3810a77-a926-4527-ba38-bf18a3574c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221555774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2221555774
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3812207075
Short name T20
Test name
Test status
Simulation time 2109658684 ps
CPU time 47.74 seconds
Started Apr 02 03:37:03 PM PDT 24
Finished Apr 02 03:37:51 PM PDT 24
Peak memory 631976 kb
Host smart-0e4bd41c-697d-4e7d-963f-5ce7afb3fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812207075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3812207075
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.504212886
Short name T1194
Test name
Test status
Simulation time 144432859 ps
CPU time 1.06 seconds
Started Apr 02 03:36:54 PM PDT 24
Finished Apr 02 03:36:55 PM PDT 24
Peak memory 203684 kb
Host smart-381a7383-3353-42cf-b16c-b000bb8f579e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504212886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.504212886
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1235494329
Short name T1174
Test name
Test status
Simulation time 685959884 ps
CPU time 4.07 seconds
Started Apr 02 03:37:10 PM PDT 24
Finished Apr 02 03:37:14 PM PDT 24
Peak memory 203812 kb
Host smart-0c621b91-bf7d-4346-b847-2501ed197614
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235494329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1235494329
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3806744474
Short name T151
Test name
Test status
Simulation time 5290459485 ps
CPU time 57 seconds
Started Apr 02 03:37:09 PM PDT 24
Finished Apr 02 03:38:06 PM PDT 24
Peak memory 805892 kb
Host smart-6556962b-f26d-42e4-9a7b-6ccefa53078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806744474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3806744474
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2534184439
Short name T556
Test name
Test status
Simulation time 1824360519 ps
CPU time 19.04 seconds
Started Apr 02 03:37:00 PM PDT 24
Finished Apr 02 03:37:21 PM PDT 24
Peak memory 203848 kb
Host smart-2c8e1997-9a47-485d-a852-c78d29c35c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534184439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2534184439
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.463992736
Short name T640
Test name
Test status
Simulation time 998301990 ps
CPU time 17.61 seconds
Started Apr 02 03:37:12 PM PDT 24
Finished Apr 02 03:37:30 PM PDT 24
Peak memory 341832 kb
Host smart-351e06b9-51f5-43cf-b3ad-4dc548ff959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463992736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.463992736
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.555383182
Short name T365
Test name
Test status
Simulation time 30728123 ps
CPU time 0.67 seconds
Started Apr 02 03:37:07 PM PDT 24
Finished Apr 02 03:37:08 PM PDT 24
Peak memory 203600 kb
Host smart-429ba9da-ab16-4ce1-a2a3-afd7674fb19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555383182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.555383182
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2929162720
Short name T1031
Test name
Test status
Simulation time 48189915602 ps
CPU time 1077 seconds
Started Apr 02 03:37:10 PM PDT 24
Finished Apr 02 03:55:07 PM PDT 24
Peak memory 3117168 kb
Host smart-da1bf555-e8a5-425f-a6ba-0c40049e38df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929162720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2929162720
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1202480792
Short name T245
Test name
Test status
Simulation time 1225166220 ps
CPU time 60.91 seconds
Started Apr 02 03:36:52 PM PDT 24
Finished Apr 02 03:37:53 PM PDT 24
Peak memory 357832 kb
Host smart-4eb1a973-44db-4d9b-a351-2cd0078706ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202480792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1202480792
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2107628818
Short name T31
Test name
Test status
Simulation time 12133128038 ps
CPU time 408.07 seconds
Started Apr 02 03:37:08 PM PDT 24
Finished Apr 02 03:43:56 PM PDT 24
Peak memory 1546492 kb
Host smart-828457dd-b7b3-4a7f-92a2-20f15a87ad57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107628818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2107628818
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.205781058
Short name T477
Test name
Test status
Simulation time 2383710435 ps
CPU time 3.84 seconds
Started Apr 02 03:37:17 PM PDT 24
Finished Apr 02 03:37:23 PM PDT 24
Peak memory 212040 kb
Host smart-3c97cea5-4d78-4b38-8f8d-45b285d818ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205781058 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.205781058
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1434382285
Short name T92
Test name
Test status
Simulation time 10790000551 ps
CPU time 5.83 seconds
Started Apr 02 03:36:55 PM PDT 24
Finished Apr 02 03:37:01 PM PDT 24
Peak memory 243116 kb
Host smart-67da238a-ee24-43bc-8dee-a0da82d66b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434382285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1434382285
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.342737925
Short name T555
Test name
Test status
Simulation time 10240611359 ps
CPU time 8.62 seconds
Started Apr 02 03:37:10 PM PDT 24
Finished Apr 02 03:37:19 PM PDT 24
Peak memory 268640 kb
Host smart-3ca50abd-2143-4dfe-8224-ad3f2c60ca13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342737925 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.342737925
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3307293010
Short name T216
Test name
Test status
Simulation time 475534757 ps
CPU time 2.69 seconds
Started Apr 02 03:36:56 PM PDT 24
Finished Apr 02 03:36:58 PM PDT 24
Peak memory 203836 kb
Host smart-638b376f-b9ec-40c5-b3ef-9dc81fb749dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307293010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3307293010
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1475632773
Short name T957
Test name
Test status
Simulation time 13284417572 ps
CPU time 6.48 seconds
Started Apr 02 03:37:15 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 218204 kb
Host smart-f919ddd1-574c-4816-9149-4a598a4cfe6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475632773 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1475632773
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1338079458
Short name T307
Test name
Test status
Simulation time 5935242838 ps
CPU time 14.87 seconds
Started Apr 02 03:37:24 PM PDT 24
Finished Apr 02 03:37:39 PM PDT 24
Peak memory 203808 kb
Host smart-396d20d9-5454-4714-87f2-368b8678add3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338079458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1338079458
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.4132485474
Short name T578
Test name
Test status
Simulation time 2601162567 ps
CPU time 10.87 seconds
Started Apr 02 03:37:11 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 209168 kb
Host smart-ca8befaa-41d2-45b9-a97a-6e453154b35c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132485474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.4132485474
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3293770243
Short name T634
Test name
Test status
Simulation time 14736690728 ps
CPU time 32.73 seconds
Started Apr 02 03:36:54 PM PDT 24
Finished Apr 02 03:37:27 PM PDT 24
Peak memory 286980 kb
Host smart-644680d3-4a65-4292-b42f-15a4e90867e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293770243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3293770243
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2344525762
Short name T518
Test name
Test status
Simulation time 2481272763 ps
CPU time 7.3 seconds
Started Apr 02 03:36:56 PM PDT 24
Finished Apr 02 03:37:03 PM PDT 24
Peak memory 220096 kb
Host smart-9bf3a37e-372e-4bb0-97d9-0be31ba0b34c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344525762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2344525762
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1436401930
Short name T832
Test name
Test status
Simulation time 23599460 ps
CPU time 0.6 seconds
Started Apr 02 03:37:14 PM PDT 24
Finished Apr 02 03:37:17 PM PDT 24
Peak memory 203608 kb
Host smart-b3ab5cb2-a464-476f-aa45-505849839796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436401930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1436401930
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2151319387
Short name T506
Test name
Test status
Simulation time 191917102 ps
CPU time 1.49 seconds
Started Apr 02 03:37:03 PM PDT 24
Finished Apr 02 03:37:05 PM PDT 24
Peak memory 212004 kb
Host smart-4b1c55e1-21ea-41de-9cf8-d40b640dbb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151319387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2151319387
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1070081543
Short name T700
Test name
Test status
Simulation time 135380347 ps
CPU time 3.12 seconds
Started Apr 02 03:37:14 PM PDT 24
Finished Apr 02 03:37:19 PM PDT 24
Peak memory 224600 kb
Host smart-47cd8621-f303-4c21-b13f-bbdf0cbac588
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070081543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1070081543
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3463437456
Short name T699
Test name
Test status
Simulation time 16872197954 ps
CPU time 171.31 seconds
Started Apr 02 03:37:20 PM PDT 24
Finished Apr 02 03:40:11 PM PDT 24
Peak memory 750184 kb
Host smart-f5291ce2-2f7d-4075-97d8-905feaba8d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463437456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3463437456
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3344407784
Short name T257
Test name
Test status
Simulation time 4442809163 ps
CPU time 83.42 seconds
Started Apr 02 03:37:14 PM PDT 24
Finished Apr 02 03:38:39 PM PDT 24
Peak memory 703008 kb
Host smart-c6be43b8-86e3-4195-8eb3-10977698a0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344407784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3344407784
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1483970233
Short name T602
Test name
Test status
Simulation time 514545373 ps
CPU time 1.02 seconds
Started Apr 02 03:37:03 PM PDT 24
Finished Apr 02 03:37:04 PM PDT 24
Peak memory 203740 kb
Host smart-fb324f46-bce1-4cf9-a1cf-6dc756f97f0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483970233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1483970233
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2933400608
Short name T974
Test name
Test status
Simulation time 222128932 ps
CPU time 3.01 seconds
Started Apr 02 03:37:18 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 220504 kb
Host smart-10ad7310-29b2-48d4-97cc-95bba556a401
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933400608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2933400608
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2099671662
Short name T157
Test name
Test status
Simulation time 8723553986 ps
CPU time 73.7 seconds
Started Apr 02 03:37:01 PM PDT 24
Finished Apr 02 03:38:15 PM PDT 24
Peak memory 897404 kb
Host smart-b991218b-b52d-487a-baa2-64ac37611f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099671662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2099671662
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.759958244
Short name T29
Test name
Test status
Simulation time 991630799 ps
CPU time 3.68 seconds
Started Apr 02 03:37:13 PM PDT 24
Finished Apr 02 03:37:17 PM PDT 24
Peak memory 203800 kb
Host smart-4e2ac063-564a-4653-b56d-2cbd77f794e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759958244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.759958244
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.3415632902
Short name T772
Test name
Test status
Simulation time 2633189890 ps
CPU time 22.42 seconds
Started Apr 02 03:37:15 PM PDT 24
Finished Apr 02 03:37:38 PM PDT 24
Peak memory 333624 kb
Host smart-2ae07520-e133-4d00-bea0-afdd8383c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415632902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.3415632902
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.1966005936
Short name T1155
Test name
Test status
Simulation time 52469706 ps
CPU time 0.66 seconds
Started Apr 02 03:37:15 PM PDT 24
Finished Apr 02 03:37:17 PM PDT 24
Peak memory 203588 kb
Host smart-80d27000-e42f-47ff-ab39-1413186c74b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966005936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1966005936
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3357865126
Short name T478
Test name
Test status
Simulation time 3131066347 ps
CPU time 11.65 seconds
Started Apr 02 03:37:14 PM PDT 24
Finished Apr 02 03:37:28 PM PDT 24
Peak memory 228436 kb
Host smart-403a145a-6632-4f4c-b82d-c5cd66f45d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357865126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3357865126
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1038146597
Short name T585
Test name
Test status
Simulation time 3181664584 ps
CPU time 82.54 seconds
Started Apr 02 03:37:00 PM PDT 24
Finished Apr 02 03:38:24 PM PDT 24
Peak memory 415052 kb
Host smart-b1209cc0-ed40-45fd-ae1a-fd54cd81cddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038146597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1038146597
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2372333254
Short name T312
Test name
Test status
Simulation time 783747816 ps
CPU time 4.33 seconds
Started Apr 02 03:37:20 PM PDT 24
Finished Apr 02 03:37:24 PM PDT 24
Peak memory 213452 kb
Host smart-4befe44d-9779-47a2-ab7e-774d3c245739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372333254 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2372333254
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.683795187
Short name T415
Test name
Test status
Simulation time 10493320446 ps
CPU time 17.21 seconds
Started Apr 02 03:37:05 PM PDT 24
Finished Apr 02 03:37:22 PM PDT 24
Peak memory 327060 kb
Host smart-f3bfbd23-957e-46f5-8ee5-e80776170196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683795187 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.683795187
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2789725716
Short name T1011
Test name
Test status
Simulation time 10296707267 ps
CPU time 14.88 seconds
Started Apr 02 03:37:03 PM PDT 24
Finished Apr 02 03:37:20 PM PDT 24
Peak memory 314620 kb
Host smart-7a60f40b-a455-44c0-b605-47d1bc1f9e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789725716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2789725716
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.4268681624
Short name T246
Test name
Test status
Simulation time 6840704479 ps
CPU time 6.08 seconds
Started Apr 02 03:37:28 PM PDT 24
Finished Apr 02 03:37:34 PM PDT 24
Peak memory 220024 kb
Host smart-6337c452-4dd1-4d11-9f63-6378a86ffd19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268681624 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.4268681624
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.227147844
Short name T23
Test name
Test status
Simulation time 4758984713 ps
CPU time 17.41 seconds
Started Apr 02 03:37:02 PM PDT 24
Finished Apr 02 03:37:20 PM PDT 24
Peak memory 203816 kb
Host smart-f46fc38f-0a4d-444c-ad0f-304a3a700f63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227147844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ
et_smoke.227147844
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.3479630592
Short name T207
Test name
Test status
Simulation time 1029096306 ps
CPU time 20.77 seconds
Started Apr 02 03:37:06 PM PDT 24
Finished Apr 02 03:37:27 PM PDT 24
Peak memory 215984 kb
Host smart-e97f3297-7b11-4eac-8ae1-9a08bc5540ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479630592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.3479630592
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.809655200
Short name T481
Test name
Test status
Simulation time 15215818045 ps
CPU time 33.24 seconds
Started Apr 02 03:37:02 PM PDT 24
Finished Apr 02 03:37:36 PM PDT 24
Peak memory 203844 kb
Host smart-cfa49fec-d8eb-4540-9f27-f3c13f9bc1f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809655200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.809655200
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.4259575861
Short name T748
Test name
Test status
Simulation time 6088680727 ps
CPU time 7.71 seconds
Started Apr 02 03:37:07 PM PDT 24
Finished Apr 02 03:37:15 PM PDT 24
Peak memory 220104 kb
Host smart-859f5977-6b52-4c4d-bb6e-af1aaaee61d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259575861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.4259575861
Directory /workspace/9.i2c_target_timeout/latest
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