Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

120420

1

T29

459

T17

1

T30

440

ack

9639

1

T4

13

T9

26

T35

56

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	528	1			T29	1		T30	1		T14	3
high	26724	1			T4	1		T9	2		T35	4
med	48598	1			T4	2		T9	4		T35	5
sml	53719	1			T4	10		T9	20		T35	47
all_zero	490	1			T29	1		T14	1		T15	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65110

1

T4

6

T9

13

T35

33

auto[1]

64949

1

T4

7

T9

13

T35

23

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88313

1

T4

13

T9

16

T35

41

auto[1]

41746

1

T9

10

T35

15

T29

144

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124671

1

T4

7

T9

9

T35

21

auto[1]

5388

1

T4

6

T9

17

T35

35

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123866

1

T4

6

T9

17

T35

35

auto[1]

6193

1

T4

7

T9

9

T35

21

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124517

1

T4

7

T9

19

T35

36

auto[1]

5542

1

T4

6

T9

7

T35

20

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65110

1

T4

6

T9

13

T35

33

auto[1]

64949

1

T4

7

T9

13

T35

23

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88313

1

T4

13

T9

16

T35

41

auto[1]

41746

1

T9

10

T35

15

T29

144

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124671

1

T4

7

T9

9

T35

21

auto[1]

5388

1

T4

6

T9

17

T35

35

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123866

1

T4

6

T9

17

T35

35

auto[1]

6193

1

T4

7

T9

9

T35

21

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124517

1

T4

7

T9

19

T35

36

auto[1]

5542

1

T4

6

T9

7

T35

20

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

2

1

T219

1

T220

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T25

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T221

2

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

168

1

T14

1

T78

1

T81

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

86

1

T30

2

T78

1

T80

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

88

1

T30

1

T78

1

T82

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

278

1

T29

1

T15

6

T78

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

138

1

T14

2

T78

2

T82

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

138

1

T29

1

T64

1

T15

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

271

1

T29

1

T30

2

T14

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

137

1

T14

1

T64

1

T15

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

138

1

T29

1

T30

1

T15

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T148

1

T211

1

T222

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T223

1

T224

1

T225

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T226

1

T227

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	38652	1			T29	154		T30	142		T14	231
write_address_byte	6193	1			T4	7		T9	9		T35	21
read_with_ack	1906	1			T9	10		T35	15		T29	11
read_with_nack	3482	1			T4	6		T9	7		T35	20
stop_byte	5542	1			T4	6		T9	7		T35	20
write_address_byte_nak	2670	1			T29	6		T30	11		T14	8
data_byte_nack	120420	1			T29	459		T17	1		T30	440
stop_byte_nack	3186	1			T29	4		T17	1		T30	8
nakok_byte_nack	60174	1			T29	230		T30	225		T14	305
nakok_addr_byte_nack	1355	1			T29	5		T30	5		T14	1