Unified Coverage Report :: Group :: i2c_env_pkg::i2c_interrupts_cg

Group : i2c_env_pkg::i2c_interrupts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.interrupts_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.interrupts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance i2c_env_pkg.interrupts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_full	2	0	2	100.00	100	1	1	2
cp_acq_full_test	1	0	1	100.00	100	1	1	2
cp_acq_threshold	2	0	2	100.00	100	1	1	2
cp_acq_threshold_test	1	0	1	100.00	100	1	1	2
cp_cmd_complete	2	0	2	100.00	100	1	1	2
cp_cmd_complete_test	1	0	1	100.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmt_threshold_test	1	0	1	100.00	100	1	1	2
cp_host_timeout	2	0	2	100.00	100	1	1	2
cp_host_timeout_test	1	0	1	100.00	100	1	1	2
cp_nak	2	0	2	100.00	100	1	1	2
cp_nak_test	1	0	1	100.00	100	1	1	2
cp_rx_overflow	2	0	2	100.00	100	1	1	2
cp_rx_overflow_test	1	0	1	100.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rx_threshold_test	1	0	1	100.00	100	1	1	2
cp_scl_interference	2	0	2	100.00	100	1	1	2
cp_scl_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_interference	2	0	2	100.00	100	1	1	2
cp_sda_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_unstable	2	0	2	100.00	100	1	1	2
cp_sda_unstable_test	1	0	1	100.00	100	1	1	2
cp_stretch_timeout	2	0	2	100.00	100	1	1	2
cp_stretch_timeout_test	1	0	1	100.00	100	1	1	2
cp_tx_stretch	2	0	2	100.00	100	1	1	2
cp_tx_stretch_test	1	0	1	100.00	100	1	1	2
cp_tx_threshold	2	0	2	100.00	100	1	1	2
cp_tx_threshold_test	1	0	1	100.00	100	1	1	2
cp_unexp_stop	2	0	2	100.00	100	1	1	2
cp_unexp_stop_test	1	0	1	100.00	100	1	1	2

Summary for Variable cp_acq_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48181

1

T1

2

T2

2

T4

3

auto[1]

46322

1

T1

1

T2

2

T4

1

---

Summary for Variable cp_acq_full_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_full_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

267

1

T29

7

T14

6

T25

5

---

Summary for Variable cp_acq_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48402

1

T1

1

T2

2

T4

2

auto[1]

46132

1

T1

2

T2

2

T4

2

---

Summary for Variable cp_acq_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

244

1

T29

5

T14

6

T25

4

---

Summary for Variable cp_cmd_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cmd_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48016

1

T1

2

T2

4

T4

2

auto[1]

46472

1

T1

1

T4

2

T5

1

---

Summary for Variable cp_cmd_complete_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

252

1

T29

6

T14

9

T25

4

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46557

1

T1

2

T2

2

T4

2

auto[1]

44659

1

T1

1

T2

2

T4

2

---

Summary for Variable cp_fmt_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

243

1

T29

4

T14

12

T25

2

---

Summary for Variable cp_host_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_host_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48175

1

T1

2

T2

2

T4

2

auto[1]

46325

1

T1

1

T2

2

T4

2

---

Summary for Variable cp_host_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

235

1

T29

5

T14

11

T26

9

---

Summary for Variable cp_nak

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nak

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48232

1

T1

2

T2

3

T4

4

auto[1]

46325

1

T1

1

T2

1

T5

2

---

Summary for Variable cp_nak_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

254

1

T29

9

T14

10

T25

1

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48406

1

T1

3

T2

2

T4

3

auto[1]

46073

1

T2

2

T4

1

T6

1

---

Summary for Variable cp_rx_overflow_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

226

1

T29

9

T14

8

T25

2

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48039

1

T1

3

T2

1

T4

2

auto[1]

46509

1

T2

3

T4

2

T6

2

---

Summary for Variable cp_rx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

255

1

T29

6

T14

6

T25

2

---

Summary for Variable cp_scl_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_scl_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46618

1

T1

1

T2

3

T4

3

auto[1]

44707

1

T1

2

T2

1

T4

1

---

Summary for Variable cp_scl_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

226

1

T29

8

T14

10

T26

9

---

Summary for Variable cp_sda_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46643

1

T1

2

T2

2

T4

2

auto[1]

44608

1

T1

1

T2

2

T4

2

---

Summary for Variable cp_sda_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

257

1

T29

11

T14

13

T25

2

---

Summary for Variable cp_sda_unstable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_unstable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46429

1

T1

2

T2

3

T4

2

auto[1]

44785

1

T1

1

T2

1

T4

2

---

Summary for Variable cp_sda_unstable_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

256

1

T29

7

T14

12

T25

1

---

Summary for Variable cp_stretch_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stretch_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46637

1

T1

3

T2

2

T4

2

auto[1]

44608

1

T2

2

T4

2

T6

1

---

Summary for Variable cp_stretch_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

256

1

T29

10

T14

12

T25

3

---

Summary for Variable cp_tx_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48222

1

T1

1

T2

3

T4

2

auto[1]

46377

1

T1

2

T2

1

T4

2

---

Summary for Variable cp_tx_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

239

1

T29

10

T14

13

T25

1

---

Summary for Variable cp_tx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46668

1

T1

2

T2

2

T4

3

auto[1]

44523

1

T1

1

T2

2

T4

1

---

Summary for Variable cp_tx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

241

1

T29

9

T14

6

T25

3

---

Summary for Variable cp_unexp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unexp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48440

1

T1

2

T2

2

T4

2

auto[1]

46087

1

T1

1

T2

2

T4

2

---

Summary for Variable cp_unexp_stop_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

234

1

T29

9

T14

8

T25

2