Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30823835	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6706109

1

T1

124

T2

2344

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36857712	1			T1	303		T2	4513		T3	1
values[0x0]	336285	1			T1	78		T2	1567		T3	5
values[0x1]	335947	1			T1	63		T2	1436		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22121978	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15407966

1

T1

223

T2

3600

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	152118	1			T7	42		T9	46		T35	102
valid_sources[0x01]	135094	1			T4	1		T7	27		T9	36
valid_sources[0x02]	134471	1			T2	2		T7	25		T9	36
valid_sources[0x03]	144880	1			T2	41		T7	22		T9	43
valid_sources[0x04]	136855	1			T2	87		T7	19		T8	2
valid_sources[0x05]	431225	1			T2	17		T4	1		T7	15
valid_sources[0x06]	139458	1			T7	8		T8	2		T9	43
valid_sources[0x07]	140087	1			T2	19		T7	6		T8	5
valid_sources[0x08]	125319	1			T1	26		T4	2		T7	22
valid_sources[0x09]	137208	1			T7	4		T8	4		T9	43
valid_sources[0x0a]	139749	1			T2	39		T4	2		T7	5
valid_sources[0x0b]	126121	1			T2	14		T4	1		T7	16
valid_sources[0x0c]	146752	1			T2	42		T4	1		T7	19
valid_sources[0x0d]	123994	1			T2	33		T7	14		T9	51
valid_sources[0x0e]	127217	1			T2	26		T7	57		T9	59
valid_sources[0x0f]	212049	1			T2	10		T7	13		T8	1
valid_sources[0x10]	136453	1			T2	47		T9	52		T35	112
valid_sources[0x11]	136082	1			T5	97		T7	3		T8	11
valid_sources[0x12]	149860	1			T7	47		T9	31		T35	134
valid_sources[0x13]	132513	1			T2	4		T5	8		T7	5
valid_sources[0x14]	143185	1			T1	39		T2	37		T7	11
valid_sources[0x15]	138127	1			T2	44		T7	10		T9	51
valid_sources[0x16]	131605	1			T2	17		T7	7		T9	54
valid_sources[0x17]	140926	1			T4	1		T9	63		T35	151
valid_sources[0x18]	132694	1			T2	114		T3	1		T8	8
valid_sources[0x19]	135235	1			T2	17		T4	1		T7	12
valid_sources[0x1a]	139315	1			T2	32		T7	9		T8	2
valid_sources[0x1b]	140111	1			T2	5		T3	1		T7	17
valid_sources[0x1c]	132742	1			T1	28		T2	39		T3	1
valid_sources[0x1d]	137109	1			T2	20		T7	12		T9	54
valid_sources[0x1e]	126629	1			T2	28		T4	1		T5	105
valid_sources[0x1f]	134676	1			T2	15		T7	11		T8	5
valid_sources[0x20]	140136	1			T2	2		T7	12		T9	39
valid_sources[0x21]	146503	1			T2	23		T7	13		T8	4
valid_sources[0x22]	120674	1			T2	34		T3	2		T4	1
valid_sources[0x23]	152395	1			T2	5		T7	5		T9	46
valid_sources[0x24]	142325	1			T2	46		T3	1		T4	1
valid_sources[0x25]	128160	1			T2	15		T7	21		T9	51
valid_sources[0x26]	131529	1			T2	26		T7	18		T8	11
valid_sources[0x27]	124572	1			T1	5		T2	21		T7	25
valid_sources[0x28]	137156	1			T2	8		T5	137		T7	3
valid_sources[0x29]	154259	1			T2	80		T4	1		T7	12
valid_sources[0x2a]	127422	1			T2	134		T7	6		T9	28
valid_sources[0x2b]	128956	1			T2	60		T7	20		T9	66
valid_sources[0x2c]	134529	1			T2	9		T4	1		T7	15
valid_sources[0x2d]	140602	1			T2	40		T7	16		T8	7
valid_sources[0x2e]	151275	1			T2	23		T7	4		T9	47
valid_sources[0x2f]	138599	1			T2	6		T8	2		T9	39
valid_sources[0x30]	127991	1			T2	53		T7	35		T8	11
valid_sources[0x31]	140359	1			T2	39		T7	5		T9	54
valid_sources[0x32]	126141	1			T2	152		T7	2		T9	52
valid_sources[0x33]	131259	1			T2	21		T7	12		T8	27
valid_sources[0x34]	133038	1			T2	21		T7	11		T9	44
valid_sources[0x35]	151762	1			T2	5		T4	1		T7	15
valid_sources[0x36]	135195	1			T2	48		T7	24		T9	52
valid_sources[0x37]	169153	1			T2	13		T7	7		T9	54
valid_sources[0x38]	278209	1			T7	9		T9	42		T35	142
valid_sources[0x39]	170575	1			T2	45		T4	1		T7	19
valid_sources[0x3a]	553805	1			T2	23		T5	78		T7	43
valid_sources[0x3b]	135308	1			T2	2		T7	13		T9	66
valid_sources[0x3c]	142502	1			T2	11		T7	9		T8	2
valid_sources[0x3d]	124783	1			T1	24		T2	27		T4	1
valid_sources[0x3e]	125942	1			T2	44		T6	1		T7	4
valid_sources[0x3f]	142246	1			T1	36		T2	4		T7	6
valid_sources[0x40]	131372	1			T7	12		T9	69		T35	123
valid_sources[0x41]	131522	1			T2	4		T7	17		T9	45
valid_sources[0x42]	130172	1			T2	31		T4	16		T7	20
valid_sources[0x43]	133788	1			T2	41		T7	24		T8	2
valid_sources[0x44]	133650	1			T2	17		T7	16		T9	71
valid_sources[0x45]	135464	1			T2	41		T7	19		T9	42
valid_sources[0x46]	126619	1			T2	13		T7	5		T9	31
valid_sources[0x47]	133053	1			T1	4		T2	9		T4	1
valid_sources[0x48]	147862	1			T2	26		T7	6		T8	9
valid_sources[0x49]	133495	1			T7	5		T8	12		T9	47
valid_sources[0x4a]	133054	1			T2	47		T4	18		T7	24
valid_sources[0x4b]	136373	1			T2	6		T7	24		T8	13
valid_sources[0x4c]	135178	1			T1	29		T2	4		T7	26
valid_sources[0x4d]	141795	1			T2	126		T7	17		T9	54
valid_sources[0x4e]	149432	1			T2	7		T4	1		T7	13
valid_sources[0x4f]	146323	1			T2	40		T7	30		T8	12
valid_sources[0x50]	142227	1			T7	22		T9	53		T35	113
valid_sources[0x51]	301005	1			T2	121		T3	1		T7	25
valid_sources[0x52]	143300	1			T2	7		T6	205		T7	18
valid_sources[0x53]	128792	1			T7	13		T8	2		T9	46
valid_sources[0x54]	150171	1			T2	33		T4	16179		T7	2
valid_sources[0x55]	132700	1			T2	34		T5	5		T7	23
valid_sources[0x56]	131667	1			T2	24		T7	1		T9	51
valid_sources[0x57]	128588	1			T7	37		T8	8		T9	55
valid_sources[0x58]	133517	1			T2	12		T7	19		T9	48
valid_sources[0x59]	128499	1			T2	49		T4	1		T7	34
valid_sources[0x5a]	126500	1			T7	30		T9	71		T35	125
valid_sources[0x5b]	123060	1			T2	94		T7	17		T9	34
valid_sources[0x5c]	122733	1			T2	5		T7	7		T8	16
valid_sources[0x5d]	138468	1			T2	4		T7	19		T9	47
valid_sources[0x5e]	123987	1			T2	5		T7	9		T9	53
valid_sources[0x5f]	142802	1			T2	2		T4	1		T7	34
valid_sources[0x60]	129291	1			T2	9		T4	1		T7	9
valid_sources[0x61]	129882	1			T2	25		T7	12		T9	51
valid_sources[0x62]	158938	1			T2	12		T7	9		T9	35
valid_sources[0x63]	128977	1			T2	25		T7	19		T8	3
valid_sources[0x64]	134640	1			T2	58		T4	1		T7	21
valid_sources[0x65]	136188	1			T2	13		T4	1		T7	13
valid_sources[0x66]	132037	1			T2	22		T7	6		T9	40
valid_sources[0x67]	127556	1			T2	11		T4	1		T7	22
valid_sources[0x68]	143789	1			T2	53		T7	20		T9	44
valid_sources[0x69]	131279	1			T4	1		T7	6		T9	44
valid_sources[0x6a]	152240	1			T2	30		T7	28		T9	42
valid_sources[0x6b]	132834	1			T2	28		T7	16		T9	47
valid_sources[0x6c]	133216	1			T2	50		T4	1		T7	6
valid_sources[0x6d]	133741	1			T2	57		T7	3		T9	68
valid_sources[0x6e]	151990	1			T2	61		T7	43		T9	55
valid_sources[0x6f]	125531	1			T2	12		T7	4		T8	2
valid_sources[0x70]	134588	1			T2	17		T7	6		T9	46
valid_sources[0x71]	143383	1			T1	11		T2	49		T7	1
valid_sources[0x72]	133678	1			T2	27		T3	1		T7	16
valid_sources[0x73]	137674	1			T2	22		T7	37		T8	3
valid_sources[0x74]	127465	1			T1	53		T2	33		T7	21
valid_sources[0x75]	153123	1			T2	11		T7	16		T8	4
valid_sources[0x76]	144507	1			T2	46		T7	17		T8	17
valid_sources[0x77]	137808	1			T2	52		T4	1		T7	7
valid_sources[0x78]	135118	1			T2	20		T4	10980		T7	31
valid_sources[0x79]	249280	1			T5	50		T7	8		T8	1
valid_sources[0x7a]	137180	1			T2	8		T4	2		T5	1
valid_sources[0x7b]	134248	1			T2	58		T7	28		T9	37
valid_sources[0x7c]	132539	1			T2	101		T4	1		T7	7
valid_sources[0x7d]	137236	1			T4	138		T7	36		T9	48
valid_sources[0x7e]	182005	1			T7	20		T8	5		T9	57
valid_sources[0x7f]	130602	1			T2	72		T4	2		T7	10
valid_sources[0x80]	142130	1			T2	30		T7	8		T9	56

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6415804

1

T1

65

T2

1488

T3

1

values[0x0]

all_enables

biggest_size

171705

1

T1

35

T2

601

T3

3

values[0x1]

all_enables

biggest_size

118600

1

T1

24

T2

255

T3

4