Unified Coverage Report :: Module :: i2c_fsm

Module : i2c_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	93.53	85.48		46.79	87.38	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_fsm	82.64	93.53	85.48		46.79	87.38	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	93.53	85.48		46.79	87.38	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	93.53	85.48		46.79	87.38	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.33	97.03	70.73			90.91	66.67	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		665	622	93.53
ALWAYS	181	17	17	100.00
ALWAYS	209	3	3	100.00
ALWAYS	222	9	9	100.00
ALWAYS	240	5	5	100.00
CONT_ASSIGN	262	1	1	100.00
ALWAYS	266	6	6	100.00
ALWAYS	282	9	8	88.89
ALWAYS	301	6	5	83.33
ALWAYS	312	7	7	100.00
ALWAYS	325	6	6	100.00
ALWAYS	336	5	5	100.00
ALWAYS	343	7	7	100.00
ALWAYS	356	5	5	100.00
ALWAYS	370	8	8	100.00
ALWAYS	382	8	7	87.50
ALWAYS	406	6	6	100.00
ALWAYS	416	6	6	100.00
ALWAYS	426	6	6	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
ALWAYS	448	9	9	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
ALWAYS	469	7	7	100.00
ALWAYS	480	5	5	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
ALWAYS	566	6	6	100.00
CONT_ASSIGN	584	1	1	100.00
ALWAYS	589	4	4	100.00
CONT_ASSIGN	606	1	1	100.00
CONT_ASSIGN	610	1	1	100.00
ALWAYS	614	199	179	89.95
CONT_ASSIGN	1018	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
ALWAYS	1041	281	261	92.88
CONT_ASSIGN	1641	1	1	100.00
ALWAYS	1645	3	3	100.00
ALWAYS	1654	5	5	100.00
CONT_ASSIGN	1663	1	1	100.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1670	1	1	100.00
CONT_ASSIGN	1674	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
198	1	1
204	1	1
			MISSING_ELSE
209	1	1
210	1	1
212	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
229	1	1
230	1	1
231	1	1
233	1	1
240	1	1
241	1	1
242	1	1
243	1	1
245	1	1
262	1	1
266	1	1
267	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
282	1	1
283	1	1
284	1	1
285	1	1
287	1	1
288	1	1
289	0	1
			MISSING_ELSE
292	1	1
293	1	1
301	1	1
302	1	1
303	1	1
304	0	1
305	1	1
306	1	1
			MISSING_ELSE
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
319	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
			MISSING_ELSE
336	2	2
337	2	2
338	1	1
343	1	1
344	1	1
345	1	1
346	1	1
347	1	1
348	1	1
350	1	1
356	1	1
357	1	1
358	1	1
360	1	1
361	1	1
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
382	1	1
383	1	1
384	1	1
385	0	1
386	1	1
387	1	1
388	1	1
389	1	1
			MISSING_ELSE
406	1	1
407	1	1
408	1	1
409	1	1
410	1	1
411	1	1
			MISSING_ELSE
416	1	1
417	1	1
418	1	1
419	1	1
420	1	1
421	1	1
			MISSING_ELSE
426	1	1
427	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
436	1	1
437	1	1
440	1	1
441	1	1
444	1	1
448	1	1
449	1	1
450	1	1
451	1	1
452	1	1
455	2	2
456	1	1
458	1	1
463	1	1
464	1	1
465	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	2	2
			MISSING_ELSE
			MISSING_ELSE
480	1	1
481	1	1
482	1	1
483	2	2
			MISSING_ELSE
			MISSING_ELSE
497	1	1
500	1	1
501	1	1
561	1	1
566	1	1
567	1	1
568	1	1
572	1	1
573	1	1
574	1	1
			MISSING_ELSE
584	1	1
589	1	1
590	1	1
591	1	1
592	1	1
			MISSING_ELSE
606	1	1
610	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
620	1	1
621	1	1
622	1	1
623	1	1
624	1	1
625	1	1
626	1	1
627	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
638	1	1
639	1	1
640	0	1
641	0	1
643	1	1
644	1	1
654	1	1
655	1	1
656	1	1
657	2	2
			MISSING_ELSE
661	1	1
662	1	1
663	1	1
667	1	1
668	1	1
669	1	1
672	1	1
673	1	1
674	1	1
676	1	1
678	1	1
682	1	1
683	1	1
684	1	1
685	1	1
686	1	2
			MISSING_ELSE
687	2	2
			MISSING_ELSE
691	1	1
692	1	1
693	1	1
697	1	1
698	1	1
699	1	1
703	1	1
704	1	1
705	1	1
706	2	2
			MISSING_ELSE
707	1	1
708	1	2
			MISSING_ELSE
709	2	2
			MISSING_ELSE
713	1	1
714	1	1
715	1	1
719	1	1
720	1	1
721	1	1
725	1	1
726	1	1
727	1	1
728	1	2
			MISSING_ELSE
729	2	2
			MISSING_ELSE
733	1	1
734	1	1
735	1	1
736	1	1
737	1	1
			MISSING_ELSE
742	1	1
743	1	1
747	2	2
748	2	2
749	1	1
753	1	1
754	2	2
755	2	2
756	1	1
757	1	1
758	1	1
759	1	2
			MISSING_ELSE
760	2	2
			MISSING_ELSE
764	1	1
765	2	2
766	2	2
767	1	1
768	1	1
772	1	1
773	1	1
774	1	1
778	1	1
779	1	1
780	1	1
784	1	1
785	1	1
786	1	1
787	1	1
791	1	1
797	1	1
801	1	1
802	2	2
803	1	1
804	1	1
813	1	1
817	1	1
818	1	1
822	1	1
826	1	1
827	1	1
831	1	1
832	1	1
836	1	1
837	1	1
840	1	1
841	1	1
845	0	1
846	0	1
849	1	1
850	1	1
			==> MISSING_ELSE
856	1	1
860	1	1
861	1	1
865	1	1
868	1	1
872	1	1
875	1	1
879	1	1
882	1	1
883	1	1
885	1	1
			MISSING_ELSE
890	1	1
891	1	1
892	1	1
896	1	1
900	1	1
904	1	1
905	1	1
909	1	1
910	1	1
914	1	1
915	1	1
917	1	1
918	1	1
919	1	1
			==> MISSING_ELSE
924	0	1
928	0	1
929	0	1
933	0	1
934	0	1
938	0	1
939	0	1
941	0	1
947	0	1
948	0	1
952	0	1
953	0	1
			==> MISSING_ELSE
959	1	1
960	1	1
962	1	1
963	1	1
964	1	1
968	1	1
969	1	1
973	1	1
974	1	1
975	1	1
979	1	1
980	1	1
983	1	1
984	1	1
985	1	1
1009	1	1
1011	1	1
1012	1	1
1014	1	1
			MISSING_ELSE
1018	1	1
1019	1	1
1023	1	1
1032	1	1
1037	1	1
1041	1	1
1042	1	1
1043	1	1
1044	1	1
1045	1	1
1046	1	1
1047	1	1
1048	1	1
1049	1	1
1050	1	1
1051	1	1
1052	1	1
1053	1	1
1054	1	1
1055	1	1
1056	1	1
1057	1	1
1058	1	1
1060	1	1
1063	2	2
1064	1	1
1065	2	2
			MISSING_ELSE
			MISSING_ELSE
1067	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
			MISSING_ELSE
1085	1	1
1086	1	1
1087	1	1
1088	1	1
			MISSING_ELSE
1093	1	1
1094	1	1
1095	1	1
1096	1	1
			MISSING_ELSE
1101	1	1
1102	1	1
1103	1	1
1104	1	1
1105	1	1
1106	1	1
1108	1	1
1109	1	1
			MISSING_ELSE
1115	1	1
1116	1	1
1118	1	1
1119	1	1
1120	1	1
1121	1	1
1122	1	1
1123	1	1
			MISSING_ELSE
1128	1	1
1129	1	1
1130	1	1
1131	1	1
1132	1	1
1133	1	1
1134	1	1
1135	1	1
1137	1	1
1138	1	1
			MISSING_ELSE
1145	1	1
1146	1	1
1147	1	1
1148	1	1
			MISSING_ELSE
1153	1	1
1155	1	1
1156	1	1
1158	1	1
1163	1	1
1164	1	1
1165	1	1
1167	0	1
1168	0	1
1169	0	1
1170	0	1
			MISSING_ELSE
1172	1	1
1173	1	1
1174	1	1
1175	1	1
			MISSING_ELSE
1181	1	1
1182	1	1
1183	1	1
1184	1	1
1185	1	1
1187	1	1
1188	1	1
1189	1	1
			MISSING_ELSE
1195	1	1
1196	1	1
1197	1	1
1198	1	1
			MISSING_ELSE
1203	1	1
1205	1	1
1206	1	1
1207	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
			MISSING_ELSE
1216	1	1
1217	1	1
1218	1	1
1219	1	1
1220	1	1
1221	1	1
1222	1	1
1224	1	1
1225	1	1
			MISSING_ELSE
1232	1	1
1233	1	1
1234	1	1
1235	1	1
1236	1	1
			MISSING_ELSE
1241	1	1
1242	1	1
1244	1	1
1245	1	1
1246	1	1
1247	1	1
1248	1	1
1249	1	1
			MISSING_ELSE
1254	1	1
1255	1	1
1256	1	1
1257	1	1
1258	1	1
1259	1	1
1260	1	1
1261	1	1
1263	1	1
1264	1	1
1265	1	1
1268	1	1
1269	1	1
1270	1	1
1271	1	1
			MISSING_ELSE
1277	1	1
1278	1	1
1279	1	1
1280	1	1
			MISSING_ELSE
1285	1	1
1286	1	1
1287	1	1
1288	1	1
1289	1	1
			MISSING_ELSE
1294	1	1
1295	1	1
1296	1	1
1297	1	1
1298	1	1
1299	1	1
1300	1	1
1302	1	1
1303	1	1
1304	1	1
			MISSING_ELSE
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1334	1	1
1335	1	1
1337	1	1
1338	1	1
1339	1	1
1350	1	1
1352	1	1
1353	1	1
			MISSING_ELSE
1355	1	1
1359	1	1
1360	1	1
1361	1	1
1366	0	1
1367	0	1
1369	0	1
1370	0	1
1373	1	1
1375	1	1
1376	1	1
1379	1	1
			MISSING_ELSE
1385	1	1
1386	1	1
			==> MISSING_ELSE
1391	2	2
			MISSING_ELSE
1395	1	1
1396	1	1
1397	1	1
1398	1	1
			MISSING_ELSE
1403	1	1
1409	1	1
1410	1	1
1411	1	1
1412	1	1
1413	1	1
1414	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
1420	1	1
1421	1	1
1423	1	1
1424	1	1
1425	1	1
1430	2	2
			MISSING_ELSE
1434	1	1
1435	1	1
1436	1	1
1437	1	1
			MISSING_ELSE
1442	1	1
1443	1	1
1444	1	1
1446	1	1
1447	1	1
1448	1	1
			==> MISSING_ELSE
1454	1	1
1455	1	1
			MISSING_ELSE
1461	1	1
1463	1	1
1464	1	1
1467	1	1
			MISSING_ELSE
1475	1	1
1479	1	1
1486	1	1
1487	0	1
1489	1	1
1491	1	1
1492	1	1
			MISSING_ELSE
1497	1	1
1498	1	1
			==> MISSING_ELSE
1503	2	2
			MISSING_ELSE
1507	1	1
1508	1	1
1509	1	1
1510	1	1
			MISSING_ELSE
1515	1	1
1518	1	1
			==> MISSING_ELSE
1523	0	1
1524	0	1
			==> MISSING_ELSE
1529	0	1
1530	0	1
			==> MISSING_ELSE
1535	0	1
1536	0	1
1537	0	1
1538	0	1
			==> MISSING_ELSE
1543	0	1
1545	0	1
			==> MISSING_ELSE
1555	1	1
1561	1	1
			MISSING_ELSE
1567	1	1
1568	1	1
1575	1	1
1576	1	1
1577	1	1
1580	1	1
			MISSING_ELSE
1585	1	1
1586	1	1
			MISSING_ELSE
1595	1	1
1596	1	1
			MISSING_ELSE
1621	1	1
1630	0	1
1631	1	1
1632	1	1
1633	1	1
1634	1	1
			MISSING_ELSE
1641	1	1
1645	1	1
1646	1	1
1648	1	1
1654	1	1
1655	1	1
1656	1	1
1658	1	1
1659	1	1
1663	1	1
1664	1	1
1667	1	1
1670	1	1
1674	1	1

---

Cond Coverage for Module : i2c_fsm

	Total	Covered	Percent
Conditions	310	265	85.48
Logical	310	265	85.48
Non-Logical	0	0
Event	0	0

 LINE       198
 EXPRESSION (host_enable_i || target_enable_i || (((!host_idle_o)) && ((!host_enable_i))))
             ------1------    -------2-------    --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T9,T17,T18
0	1	0	Covered	T1,T2,T5
1	0	0	Covered	T4,T6,T8

 LINE       198
 SUB-EXPRESSION (((!host_idle_o)) && ((!host_enable_i)))
                 --------1-------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T10
1	1	Covered	T9,T17,T18

 LINE       227
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T19,T20,T21

 LINE       230
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       269
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       285
 EXPRESSION (unhandled_unexp_nak_i && host_enable_i && host_nack_handler_timeout_en_i)
             ----------1----------    ------2------    ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T23,T24
1	0	1	Not Covered
1	1	0	Covered	T14,T25,T26
1	1	1	Covered	T22,T23,T24

 LINE       337
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T15,T27,T28

 LINE       372
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T10
1	1	Covered	T9,T17,T18

 LINE       384
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T14
1	1	Not Covered

 LINE       408
 EXPRESSION (start_det_trigger || stop_det_trigger)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       410
 EXPRESSION (start_det_pending || stop_det_pending)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       420
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || start_det || stop_det_trigger)
             ----------1---------    -----2----    ----3----    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T5
0	0	0	1	Covered	T1,T2,T5
0	0	1	0	Covered	T1,T2,T5
0	1	0	0	Covered	T1,T2,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || stop_det || start_det_trigger)
             ----------1---------    -----2----    ----3---    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T5
0	0	0	1	Covered	T1,T2,T5
0	0	1	0	Covered	T1,T2,T5
0	1	0	0	Covered	T1,T2,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       436
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       436
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       436
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       437
 EXPRESSION (target_enable_i && start_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2--------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       440
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       440
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       440
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       440
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       441
 EXPRESSION (target_enable_i && stop_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2-------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       444
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       452
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       455
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5

 LINE       463
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       473
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       482
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       568
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T9,T10

 LINE       573
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T10
1	1	Covered	T4,T9,T10

 LINE       584
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T12,T13

 LINE       584
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T9,T10
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T4,T6,T8
1	1	1	Covered	T11,T12,T13

 LINE       584
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T4,T9,T10
1	1	0	Covered	T4,T9,T10
1	1	1	Covered	T4,T9,T10

 LINE       584
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T10

 LINE       591
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       610
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T31,T32
1	0	1	1	Covered	T1,T2,T5
1	1	0	1	Covered	T1,T2,T5
1	1	1	0	Covered	T1,T2,T5
1	1	1	1	Covered	T5,T33,T34

 LINE       639
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T8
1	1	Not Covered

 LINE       686
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Not Covered

 LINE       687
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T9,T35,T29

 LINE       706
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T22,T23,T24
1	0	1	1	Covered	T4,T9,T35
1	1	0	1	Covered	T4,T9,T35
1	1	1	0	Covered	T22,T23,T24
1	1	1	1	Covered	T22,T23,T24

 LINE       708
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Not Covered

 LINE       709
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       728
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Not Covered

 LINE       729
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       735
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Covered	T4,T9,T10

 LINE       735
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       735
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       748
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       755
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       759
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Not Covered

 LINE       760
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T9,T35,T14

 LINE       766
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       797
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T29,T30,T14
1	1	Covered	T4,T9,T10

 LINE       840
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       917
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       941
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       962
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T39,T40
0	1	Not Covered
1	0	Covered	T39,T40

 LINE       1009
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       1012
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       1023
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1032
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       1063
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T8
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       1076
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1085
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1093
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T4,T9,T10

 LINE       1102
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1116
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Covered	T27,T44,T45

 LINE       1120
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1129
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1133
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1145
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1153
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Covered	T4,T9,T10

 LINE       1172
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1181
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1195
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1203
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Covered	T27,T44,T45

 LINE       1207
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1216
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1219
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1233
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1242
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10
1	1	Covered	T27,T46,T47

 LINE       1246
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1255
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1257
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1277
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1285
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1295
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1315
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T29,T30,T14
1	1	Covered	T4,T9,T10

 LINE       1332
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T4,T9,T10

 LINE       1350
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1385
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       1385
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       1403
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       1409
 EXPRESSION (stretch_addr && ((!nack_next_byte_q)))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Not Covered
1	1	Covered	T39,T40

 LINE       1442
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       1486
 EXPRESSION (acq_fifo_full_or_last_space || nack_next_byte_q)
             -------------1-------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Not Covered
1	0	Not Covered

 LINE       1497
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       1497
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       1515
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       1518
 EXPRESSION (stretch_rx ? StretchAcqFull : AcquireByte)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T39,T40

 LINE       1523
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1523
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1543
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1555
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T39,T40
0	1	Not Covered
1	0	Covered	T39,T40

 LINE       1561
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T39,T40
1	Not Covered

 LINE       1585
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       1595
 EXPRESSION (((~stretch_rx)) || nack_timeout)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T39,T40
0	1	Not Covered
1	0	Covered	T39,T40

 LINE       1621
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Not Covered

 LINE       1641
 EXPRESSION (target_enable_i && ((!target_idle)) && (stop_det | start_det))
             -------1-------    --------2-------    -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       1641
 SUB-EXPRESSION (stop_det | start_det)
                 ----1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       1667
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T5
1	1	Covered	T19,T20,T21

 LINE       1670
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T6
1	0	1	Covered	T4,T9,T10
1	1	0	Covered	T4,T9,T35
1	1	1	Covered	T4,T9,T10

---

FSM Coverage for Module : i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	47	43	91.49	(Not included in score)
Transitions	156	73	46.79
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1508	Covered	T1,T2,T5
AcquireAckPulse	1503	Covered	T1,T2,T5
AcquireAckSetup	1498	Covered	T1,T2,T5
AcquireAckWait	1489	Covered	T1,T2,T5
AcquireByte	1414	Covered	T1,T2,T5
AcquireStart	1632	Covered	T1,T2,T5
Active	1065	Covered	T4,T9,T10
AddrAckHold	1396	Covered	T1,T2,T5
AddrAckPulse	1391	Covered	T1,T2,T5
AddrAckSetup	1386	Covered	T1,T2,T5
AddrAckWait	1369	Covered	T1,T2,T5
AddrRead	1352	Covered	T1,T2,T5
ClockLow	1094	Covered	T4,T9,T10
ClockLowAck	1134	Covered	T4,T9,T10
ClockPulse	1108	Covered	T4,T9,T10
ClockPulseAck	1146	Covered	T4,T9,T10
ClockStart	1086	Covered	T4,T9,T10
ClockStop	1167	Covered	T4,T9,T10
HoldBit	1121	Covered	T4,T9,T10
HoldDevAck	1173	Covered	T4,T9,T10
HoldStart	1077	Covered	T4,T9,T10
HoldStop	1286	Covered	T4,T9,T10
HostClockLowAck	1220	Covered	T4,T9,T10
HostClockPulseAck	1234	Covered	T4,T9,T10
HostHoldBitAck	1247	Covered	T4,T9,T10
Idle	1063	Covered	T1,T2,T3
NackHold	1536	Not Covered
NackPulse	1530	Not Covered
NackSetup	1524	Not Covered
NackWait	1367	Not Covered
PopFmtFifo	1187	Covered	T4,T9,T10
ReadClockLow	1224	Covered	T4,T9,T10
ReadClockPulse	1196	Covered	T4,T9,T10
ReadHoldBit	1208	Covered	T4,T9,T10
SetupStart	1105	Covered	T4,T9,T10
SetupStop	1278	Covered	T4,T9,T10
StretchAcqFull	1518	Covered	T39,T40
StretchAddr	1410	Covered	T39,T40
StretchTx	1421	Covered	T1,T2,T5
StretchTxSetup	1575	Covered	T1,T2,T5
TransmitAck	1444	Covered	T1,T2,T5
TransmitAckPulse	1455	Covered	T1,T2,T5
TransmitHold	1435	Covered	T1,T2,T5
TransmitPulse	1430	Covered	T1,T2,T5
TransmitSetup	1423	Covered	T1,T2,T5
TransmitWait	1412	Covered	T1,T2,T5
WaitForStop	1467	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1518	Covered	T1,T2,T5
AcquireAckHold->AcquireStart	1632	Not Covered
AcquireAckHold->Idle	1630	Not Covered
AcquireAckHold->StretchAcqFull	1518	Covered	T39,T40
AcquireAckPulse->AcquireAckHold	1508	Covered	T1,T2,T5
AcquireAckPulse->AcquireStart	1632	Not Covered
AcquireAckPulse->Idle	1630	Not Covered
AcquireAckSetup->AcquireAckPulse	1503	Covered	T1,T2,T5
AcquireAckSetup->AcquireStart	1632	Not Covered
AcquireAckSetup->Idle	1630	Not Covered
AcquireAckWait->AcquireAckSetup	1498	Covered	T1,T2,T5
AcquireAckWait->AcquireStart	1632	Not Covered
AcquireAckWait->Idle	1630	Not Covered
AcquireByte->AcquireAckWait	1489	Covered	T1,T2,T5
AcquireByte->AcquireStart	1632	Covered	T1,T2,T5
AcquireByte->Idle	1630	Covered	T1,T2,T5
AcquireByte->NackWait	1487	Not Covered
AcquireStart->AddrRead	1352	Covered	T1,T2,T5
AcquireStart->Idle	1630	Not Covered
Active->AcquireStart	1632	Not Covered
Active->ClockLow	1320	Covered	T36,T29,T17
Active->Idle	1630	Not Covered
Active->ReadClockLow	1312	Covered	T4,T9,T10
Active->SetupStart	1316	Covered	T4,T9,T10
AddrAckHold->AcquireByte	1414	Covered	T1,T2,T5
AddrAckHold->AcquireStart	1632	Not Covered
AddrAckHold->Idle	1630	Not Covered
AddrAckHold->StretchAddr	1410	Covered	T39,T40
AddrAckHold->TransmitWait	1412	Covered	T1,T2,T5
AddrAckPulse->AcquireStart	1632	Not Covered
AddrAckPulse->AddrAckHold	1396	Covered	T1,T2,T5
AddrAckPulse->Idle	1630	Not Covered
AddrAckSetup->AcquireStart	1632	Not Covered
AddrAckSetup->AddrAckPulse	1391	Covered	T1,T2,T5
AddrAckSetup->Idle	1630	Not Covered
AddrAckWait->AcquireStart	1632	Not Covered
AddrAckWait->AddrAckSetup	1386	Covered	T1,T2,T5
AddrAckWait->Idle	1630	Not Covered
AddrRead->AcquireStart	1632	Covered	T6,T48,T49
AddrRead->AddrAckWait	1369	Covered	T1,T2,T5
AddrRead->Idle	1379	Covered	T1,T31,T32
AddrRead->NackWait	1367	Not Covered
ClockLow->AcquireStart	1632	Not Covered
ClockLow->ClockPulse	1108	Covered	T4,T9,T10
ClockLow->Idle	1630	Covered	T50,T29,T15
ClockLow->SetupStart	1105	Covered	T29,T30,T14
ClockLowAck->AcquireStart	1632	Not Covered
ClockLowAck->ClockPulseAck	1146	Covered	T4,T9,T10
ClockLowAck->Idle	1630	Not Covered
ClockPulse->AcquireStart	1632	Not Covered
ClockPulse->HoldBit	1121	Covered	T4,T9,T10
ClockPulse->Idle	1630	Covered	T29,T51,T15
ClockPulseAck->AcquireStart	1632	Not Covered
ClockPulseAck->ClockStop	1167	Not Covered
ClockPulseAck->HoldDevAck	1173	Covered	T4,T9,T10
ClockPulseAck->Idle	1630	Covered	T50,T29,T51
ClockStart->AcquireStart	1632	Not Covered
ClockStart->ClockLow	1094	Covered	T4,T9,T10
ClockStart->Idle	1630	Not Covered
ClockStop->AcquireStart	1632	Not Covered
ClockStop->Idle	1630	Not Covered
ClockStop->SetupStop	1278	Covered	T4,T9,T10
HoldBit->AcquireStart	1632	Not Covered
HoldBit->ClockLow	1137	Covered	T4,T9,T10
HoldBit->ClockLowAck	1134	Covered	T4,T9,T10
HoldBit->Idle	1630	Covered	T29,T51,T52
HoldDevAck->AcquireStart	1632	Not Covered
HoldDevAck->ClockStop	1183	Covered	T29,T14,T53
HoldDevAck->Idle	1630	Not Covered
HoldDevAck->PopFmtFifo	1187	Covered	T4,T9,T10
HoldStart->AcquireStart	1632	Not Covered
HoldStart->ClockStart	1086	Covered	T4,T9,T10
HoldStart->Idle	1630	Not Covered
HoldStop->AcquireStart	1632	Not Covered
HoldStop->Idle	1298	Covered	T9,T17,T18
HoldStop->PopFmtFifo	1302	Covered	T4,T9,T10
HostClockLowAck->AcquireStart	1632	Not Covered
HostClockLowAck->HostClockPulseAck	1234	Covered	T4,T9,T10
HostClockLowAck->Idle	1630	Not Covered
HostClockPulseAck->AcquireStart	1632	Not Covered
HostClockPulseAck->HostHoldBitAck	1247	Covered	T4,T9,T10
HostClockPulseAck->Idle	1630	Not Covered
HostHoldBitAck->AcquireStart	1632	Not Covered
HostHoldBitAck->ClockStop	1259	Covered	T4,T9,T10
HostHoldBitAck->Idle	1630	Not Covered
HostHoldBitAck->PopFmtFifo	1263	Covered	T9,T35,T29
HostHoldBitAck->ReadClockLow	1268	Covered	T4,T9,T10
Idle->AcquireStart	1632	Covered	T1,T2,T5
Idle->Active	1065	Covered	T4,T9,T10
NackHold->AcquireStart	1632	Not Covered
NackHold->Idle	1545	Not Covered
NackPulse->AcquireStart	1632	Not Covered
NackPulse->Idle	1630	Not Covered
NackPulse->NackHold	1536	Not Covered
NackSetup->AcquireStart	1632	Not Covered
NackSetup->Idle	1630	Not Covered
NackSetup->NackPulse	1530	Not Covered
NackWait->AcquireStart	1632	Not Covered
NackWait->Idle	1630	Not Covered
NackWait->NackSetup	1524	Not Covered
PopFmtFifo->AcquireStart	1632	Not Covered
PopFmtFifo->Active	1337	Covered	T4,T9,T10
PopFmtFifo->ClockStop	1329	Covered	T9,T17,T18
PopFmtFifo->Idle	1333	Covered	T4,T9,T10
ReadClockLow->AcquireStart	1632	Not Covered
ReadClockLow->Idle	1630	Not Covered
ReadClockLow->ReadClockPulse	1196	Covered	T4,T9,T10
ReadClockPulse->AcquireStart	1632	Not Covered
ReadClockPulse->Idle	1630	Not Covered
ReadClockPulse->ReadHoldBit	1208	Covered	T4,T9,T10
ReadHoldBit->AcquireStart	1632	Not Covered
ReadHoldBit->HostClockLowAck	1220	Covered	T4,T9,T10
ReadHoldBit->Idle	1630	Not Covered
ReadHoldBit->ReadClockLow	1224	Covered	T4,T9,T10
SetupStart->AcquireStart	1632	Not Covered
SetupStart->HoldStart	1077	Covered	T4,T9,T10
SetupStart->Idle	1630	Not Covered
SetupStop->AcquireStart	1632	Not Covered
SetupStop->HoldStop	1286	Covered	T4,T9,T10
SetupStop->Idle	1630	Not Covered
StretchAcqFull->AcquireByte	1596	Covered	T39,T40
StretchAcqFull->AcquireStart	1632	Not Covered
StretchAcqFull->Idle	1630	Not Covered
StretchAddr->AcquireByte	1561	Covered	T39,T40
StretchAddr->AcquireStart	1632	Not Covered
StretchAddr->Idle	1630	Not Covered
StretchAddr->StretchTx	1561	Not Covered
StretchTx->AcquireStart	1632	Not Covered
StretchTx->Idle	1630	Not Covered
StretchTx->StretchTxSetup	1575	Covered	T1,T2,T5
StretchTxSetup->AcquireStart	1632	Not Covered
StretchTxSetup->Idle	1630	Not Covered
StretchTxSetup->TransmitSetup	1586	Covered	T1,T2,T5
TransmitAck->AcquireStart	1632	Not Covered
TransmitAck->Idle	1630	Not Covered
TransmitAck->TransmitAckPulse	1455	Covered	T1,T2,T5
TransmitAckPulse->AcquireStart	1632	Covered	T54
TransmitAckPulse->Idle	1630	Not Covered
TransmitAckPulse->TransmitWait	1464	Covered	T1,T2,T5
TransmitAckPulse->WaitForStop	1467	Covered	T1,T2,T5
TransmitHold->AcquireStart	1632	Not Covered
TransmitHold->Idle	1630	Not Covered
TransmitHold->TransmitAck	1444	Covered	T1,T2,T5
TransmitHold->TransmitSetup	1448	Covered	T1,T2,T5
TransmitPulse->AcquireStart	1632	Covered	T5,T33,T34
TransmitPulse->Idle	1630	Covered	T5,T33,T34
TransmitPulse->TransmitHold	1435	Covered	T1,T2,T5
TransmitSetup->AcquireStart	1632	Not Covered
TransmitSetup->Idle	1630	Not Covered
TransmitSetup->TransmitPulse	1430	Covered	T1,T2,T5
TransmitWait->AcquireStart	1632	Not Covered
TransmitWait->Idle	1630	Not Covered
TransmitWait->StretchTx	1421	Covered	T1,T2,T5
TransmitWait->TransmitSetup	1423	Covered	T1,T2,T5
WaitForStop->AcquireStart	1632	Covered	T1,T2,T5
WaitForStop->Idle	1630	Covered	T1,T2,T5

---

Branch Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
Branches		309	270	87.38
IF	182	15	14	93.33
IF	209	2	2	100.00
IF	222	5	5	100.00
IF	240	3	3	100.00
IF	266	4	4	100.00
IF	282	4	3	75.00
IF	301	4	3	75.00
IF	312	4	4	100.00
IF	325	4	4	100.00
IF	336	3	3	100.00
IF	343	4	4	100.00
IF	356	2	2	100.00
IF	370	5	5	100.00
IF	382	5	4	80.00
IF	406	4	4	100.00
IF	416	4	4	100.00
IF	426	4	4	100.00
IF	448	5	5	100.00
IF	469	5	5	100.00
IF	480	4	4	100.00
IF	566	4	4	100.00
IF	589	3	3	100.00
CASE	633	79	65	82.28
IF	1009	3	3	100.00
CASE	1060	122	102	83.61
IF	1621	4	3	75.00
IF	1645	2	2	100.00
IF	1654	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	182	if (load_tcount)
-2-:	183	case (tcount_sel)
-3-:	198	if (((host_enable_i || target_enable_i) || ((!host_idle_o) && (!host_enable_i))))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T4,T9,T10
1	tHoldStart	-	Covered	T4,T9,T10
1	tSetupData	-	Covered	T1,T2,T5
1	tClockStart	-	Covered	T1,T2,T4
1	tClockLow	-	Covered	T4,T9,T10
1	tClockPulse	-	Covered	T4,T9,T10
1	tClockHigh	-	Covered	T4,T9,T10
1	tHoldBit	-	Covered	T4,T9,T10
1	tClockStop	-	Covered	T4,T9,T10
1	tSetupStop	-	Covered	T4,T9,T10
1	tHoldStop	-	Covered	T4,T9,T10
1	tNoDelay	-	Covered	T4,T9,T10
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T4
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_ni))
-2-:	224	if (stretch_en)
-3-:	227	if (((!target_idle_o) && event_host_timeout_o))
-4-:	230	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T4,T9,T10
0	0	1	-	Covered	T19,T20,T21
0	0	0	1	Covered	T1,T2,T5
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	if ((!rst_ni))
-2-:	242	if (actively_stretching)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T40
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	269	if ((stretch_idle_cnt == stretch_cnt_threshold))
-3-:	271	if ((!stretch_en))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	282	if ((!rst_ni))
-2-:	285	if (((unhandled_unexp_nak_i && host_enable_i) && host_nack_handler_timeout_en_i))
-3-:	288	if ((unhandled_nak_cnt > host_nack_handler_timeout_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Not Covered
0	1	0	Covered	T22,T23,T24
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if ((!rst_ni))
-2-:	303	if (set_nack_next_byte)
-3-:	305	if (clear_nack_next_byte)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	312	if ((!rst_ni))
-2-:	314	if (bit_clr)
-3-:	316	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T9,T10
0	0	1	Covered	T4,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	325	if ((!rst_ni))
-2-:	327	if (read_byte_clr)
-3-:	329	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T9,T10
0	0	1	Covered	T4,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if ((!fmt_flag_read_bytes_i))
-2-:	337	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	343	if ((!rst_ni))
-2-:	345	if (byte_clr)
-3-:	347	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T9,T10
0	0	1	Covered	T4,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	356	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	370	if ((!rst_ni))
-2-:	372	if ((trans_started && (!host_enable_i)))
-3-:	374	if (log_start)
-4-:	376	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T9,T17,T18
0	0	1	-	Covered	T4,T9,T10
0	0	0	1	Covered	T4,T9,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	382	if ((!rst_ni))
-2-:	384	if ((pend_restart && (!host_enable_i)))
-3-:	386	if (req_restart)
-4-:	388	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T29,T30,T14
0	0	0	1	Covered	T4,T9,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	406	if ((!rst_ni))
-2-:	408	if ((start_det_trigger || stop_det_trigger))
-3-:	410	if ((start_det_pending || stop_det_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	416	if ((!rst_ni))
-2-:	418	if (start_det_trigger)
-3-:	420	if (((((!target_enable_i) || (!scl_i)) || start_det) || stop_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	426	if ((!rst_ni))
-2-:	428	if (stop_det_trigger)
-3-:	430	if (((((!target_enable_i) || (!scl_i)) || stop_det) || start_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	448	if ((!rst_ni))
-2-:	450	if (start_det)
-3-:	452	if ((scl_i_q && (!scl_i)))
-4-:	455	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T5
0	0	1	1	Covered	T1,T2,T4
0	0	1	0	Covered	T1,T2,T4
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	469	if ((!rst_ni))
-2-:	471	if (input_byte_clr)
-3-:	473	if (((!scl_i_q) && scl_i))
-4-:	474	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T5
0	0	1	1	Covered	T1,T2,T4
0	0	1	0	Covered	T1,T2,T4
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	480	if ((!rst_ni))
-2-:	482	if (((!scl_i_q) && scl_i))
-3-:	483	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T4
0	1	0	Covered	T1,T2,T4
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	566	if ((!rst_ni))
-2-:	568	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	573	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T9,T10
0	0	1	Covered	T4,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	589	if ((!rst_ni))
-2-:	591	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	case (state_q)
-2-:	639	if ((host_enable_i && trans_started))
-3-:	657	if (log_start)
-4-:	673	if (pend_restart)
-5-:	686	if ((scl_i_q && (!scl_i)))
-6-:	687	if ((sda_i_q != sda_i))
-7-:	706	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	708	if ((scl_i_q && (!scl_i)))
-9-:	709	if ((sda_i_q != sda_i))
-10-:	728	if ((scl_i_q && (!scl_i)))
-11-:	729	if ((sda_i_q != sda_i))
-12-:	735	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	747	if (fmt_flag_read_continue_i)
-14-:	748	if ((byte_index == 9'b1))
-15-:	754	if (fmt_flag_read_continue_i)
-16-:	755	if ((byte_index == 9'b1))
-17-:	759	if ((scl_i_q && (!scl_i)))
-18-:	760	if ((sda_i_q != sda_i))
-19-:	765	if (fmt_flag_read_continue_i)
-20-:	766	if ((byte_index == 9'b1))
-21-:	802	if (fmt_flag_stop_after_i)
-22-:	840	if ((tcount_q == 20'b1))
-23-:	841	if (nack_next_byte_q)
-24-:	883	if ((!scl_i))
-25-:	917	if ((tcount_q == 20'b1))
-26-:	941	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T14
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T35,T29
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T35,T29
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T35,T29
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T9,T35,T14
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T9,T35,T29
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T4,T9,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T4,T9,T10
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T9,T10
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T9,T10
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T5
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
NackWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	1009	if ((start_det || stop_det))
-2-:	1012	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1060	case (state_q)
-2-:	1063	if (((!host_enable_i) && (!target_enable_i)))
-3-:	1064	if (host_enable_i)
-4-:	1065	if (fmt_fifo_rvalid_i)
-5-:	1076	if ((tcount_q == 20'b1))
-6-:	1085	if ((tcount_q == 20'b1))
-7-:	1093	if ((tcount_q == 20'b1))
-8-:	1102	if ((tcount_q == 20'b1))
-9-:	1104	if (pend_restart)
-10-:	1116	if (((!scl_i) && stretch_predict_cnt_expired))
-11-:	1120	if ((tcount_q == 20'b1))
-12-:	1129	if ((tcount_q == 20'b1))
-13-:	1133	if ((bit_index == '0))
-14-:	1145	if ((tcount_q == 20'b1))
-15-:	1153	if (((!scl_i) && stretch_predict_cnt_expired))
-16-:	1158	if (unhandled_unexp_nak_i)
-17-:	1165	if (unhandled_nak_cnt_expired)
-18-:	1172	if ((tcount_q == 20'b1))
-19-:	1181	if ((tcount_q == 20'b1))
-20-:	1182	if (fmt_flag_stop_after_i)
-21-:	1195	if ((tcount_q == 20'b1))
-22-:	1203	if (((!scl_i) && stretch_predict_cnt_expired))
-23-:	1207	if ((tcount_q == 20'b1))
-24-:	1216	if ((tcount_q == 20'b1))
-25-:	1219	if ((bit_index == '0))
-26-:	1233	if ((tcount_q == 20'b1))
-27-:	1242	if (((!scl_i) && stretch_predict_cnt_expired))
-28-:	1246	if ((tcount_q == 20'b1))
-29-:	1255	if ((tcount_q == 20'b1))
-30-:	1257	if ((byte_index == 9'b1))
-31-:	1258	if (fmt_flag_stop_after_i)
-32-:	1277	if ((tcount_q == 20'b1))
-33-:	1285	if ((tcount_q == 20'b1))
-34-:	1295	if ((tcount_q == 20'b1))
-35-:	1297	if ((!host_enable_i))
-36-:	1310	if (fmt_flag_read_bytes_i)
-37-:	1315	if ((fmt_flag_start_before_i && (!trans_started)))
-38-:	1328	if ((!host_enable_i))
-39-:	1332	if ((fmt_fifo_depth_i == 7'b1))
-40-:	1350	if ((scl_i_q && (!scl_i)))
-41-:	1359	if (bit_ack)
-42-:	1360	if (address_match)
-43-:	1361	if (acq_fifo_full_or_last_space)
-44-:	1366	if (rw_bit_q)
-45-:	1385	if (((tcount_q == 20'b1) && (!scl_i)))
-46-:	1391	if (scl_i)
-47-:	1395	if ((!scl_i))
-48-:	1403	if ((tcount_q == 20'b1))
-49-:	1409	if ((stretch_addr && (!nack_next_byte_q)))
-50-:	1411	if (rw_bit_q)
-51-:	1413	if ((!rw_bit_q))
-52-:	1420	if (stretch_tx)
-53-:	1430	if (scl_i)
-54-:	1434	if ((!scl_i))
-55-:	1442	if ((tcount_q == 20'b1))
-56-:	1443	if (bit_ack)
-57-:	1454	if (scl_i)
-58-:	1461	if ((!scl_i))
-59-:	1463	if (host_ack)
-60-:	1479	if (bit_ack)
-61-:	1486	if ((acq_fifo_full_or_last_space || nack_next_byte_q))
-62-:	1497	if (((tcount_q == 20'b1) && (!scl_i)))
-63-:	1503	if (scl_i)
-64-:	1507	if ((!scl_i))
-65-:	1515	if ((tcount_q == 20'b1))
-66-:	1518	(stretch_rx) ? 
-67-:	1523	if (((tcount_q == 20'b1) && (!scl_i)))
-68-:	1529	if (scl_i)
-69-:	1535	if ((!scl_i))
-70-:	1543	if ((tcount_q == 20'b1))
-71-:	1555	if (((!stretch_addr) || nack_timeout))
-72-:	1561	(rw_bit_q) ? 
-73-:	1568	if ((!stretch_tx))
-74-:	1585	if ((tcount_q == 20'b1))
-75-:	1595	if (((~stretch_rx) || nack_timeout))

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T1,T2,T3
(1.Idle )->(!2)->(3)->(4)	Covered	T4,T9,T10
(1.Idle )->(!2)->(3)->(!4)	Covered	T4,T6,T8
(1.Idle )->(!2)->(!3)	Covered	T1,T2,T5
(1.SetupStart )->(5)	Covered	T4,T9,T10
(1.SetupStart )->(!5)	Covered	T4,T9,T10
(1.HoldStart )->(6)	Covered	T4,T9,T10
(1.HoldStart )->(!6)	Covered	T4,T9,T10
(1.ClockStart )->(7)	Covered	T4,T9,T10
(1.ClockStart )->(!7)	Covered	T41,T42,T43
(1.ClockLow )->(8)->(9)	Covered	T29,T30,T14
(1.ClockLow )->(8)->(!9)	Covered	T4,T9,T10
(1.ClockLow )->(!8)	Covered	T4,T9,T10
(1.ClockPulse )->(10)	Covered	T27,T44,T45
(1.ClockPulse )->(!10)->(11)	Covered	T4,T9,T10
(1.ClockPulse )->(!10)->(!11)	Covered	T4,T9,T10
(1.HoldBit )->(12)->(13)	Covered	T4,T9,T10
(1.HoldBit )->(12)->(!13)	Covered	T4,T9,T10
(1.HoldBit )->(!12)	Covered	T4,T9,T10
(1.ClockLowAck )->(14)	Covered	T4,T9,T10
(1.ClockLowAck )->(!14)	Covered	T4,T9,T10
(1.ClockPulseAck )->(15)	Covered	T4,T9,T10
(1.ClockPulseAck )->(!15)->(16)->(17)	Not Covered
(1.ClockPulseAck )->(!15)->(16)->(!17)	Covered	T22,T23,T24
(1.ClockPulseAck )->(!15)->(!16)->(18)	Covered	T4,T9,T10
(1.ClockPulseAck )->(!15)->(!16)->(!18)	Covered	T4,T9,T10
(1.HoldDevAck )->(19)->(20)	Covered	T29,T14,T53
(1.HoldDevAck )->(19)->(!20)	Covered	T4,T9,T10
(1.HoldDevAck )->(!19)	Covered	T4,T9,T10
(1.ReadClockLow )->(21)	Covered	T4,T9,T10
(1.ReadClockLow )->(!21)	Covered	T4,T9,T10
(1.ReadClockPulse )->(22)	Covered	T27,T44,T45
(1.ReadClockPulse )->(!22)->(23)	Covered	T4,T9,T10
(1.ReadClockPulse )->(!22)->(!23)	Covered	T4,T9,T10
(1.ReadHoldBit )->(24)->(25)	Covered	T4,T9,T10
(1.ReadHoldBit )->(24)->(!25)	Covered	T4,T9,T10
(1.ReadHoldBit )->(!24)	Covered	T4,T9,T10
(1.HostClockLowAck )->(26)	Covered	T4,T9,T10
(1.HostClockLowAck )->(!26)	Covered	T4,T9,T10
(1.HostClockPulseAck )->(27)	Covered	T27,T46,T47
(1.HostClockPulseAck )->(!27)->(28)	Covered	T4,T9,T10
(1.HostClockPulseAck )->(!27)->(!28)	Covered	T4,T9,T10
(1.HostHoldBitAck )->(29)->(30)->(31)	Covered	T4,T9,T10
(1.HostHoldBitAck )->(29)->(30)->(!31)	Covered	T9,T35,T29
(1.HostHoldBitAck )->(29)->(!30)	Covered	T4,T9,T10
(1.HostHoldBitAck )->(!29)	Covered	T4,T9,T10
(1.ClockStop )->(32)	Covered	T4,T9,T10
(1.ClockStop )->(!32)	Covered	T4,T9,T10
(1.SetupStop )->(33)	Covered	T4,T9,T10
(1.SetupStop )->(!33)	Covered	T4,T9,T10
(1.HoldStop )->(34)->(35)	Covered	T9,T17,T18
(1.HoldStop )->(34)->(!35)	Covered	T4,T9,T10
(1.HoldStop )->(!34)	Covered	T4,T9,T10
(1.Active )->(36)	Covered	T4,T9,T10
(1.Active )->(!36)->(37)	Covered	T4,T9,T10
(1.Active )->(!36)->(!37)	Covered	T36,T29,T17
(1.PopFmtFifo )->(38)	Covered	T9,T17,T18
(1.PopFmtFifo )->(!38)->(39)	Covered	T4,T9,T10
(1.PopFmtFifo )->(!38)->(!39)	Covered	T4,T9,T10
(1.AcquireStart )->(40)	Covered	T1,T2,T5
(1.AcquireStart )->(!40)	Covered	T1,T2,T5
(1.AddrRead )->(41)->(42)->(43)->(44)	Not Covered
(1.AddrRead )->(41)->(42)->(43)->(!44)	Not Covered
(1.AddrRead )->(41)->(42)->(!43)	Covered	T1,T2,T5
(1.AddrRead )->(41)->(!42)	Covered	T1,T31,T32
(1.AddrRead )->(!41)	Covered	T1,T2,T5
(1.AddrAckWait )->(45)	Covered	T1,T2,T5
(1.AddrAckWait )->(!45)	Not Covered
(1.AddrAckSetup )->(46)	Covered	T1,T2,T5
(1.AddrAckSetup )->(!46)	Covered	T1,T2,T5
(1.AddrAckPulse )->(47)	Covered	T1,T2,T5
(1.AddrAckPulse )->(!47)	Covered	T1,T2,T5
(1.AddrAckHold )->(48)->(49)	Covered	T39,T40
(1.AddrAckHold )->(48)->(!49)->(50)	Covered	T1,T2,T5
(1.AddrAckHold )->(48)->(!49)->(!50)->(51)	Covered	T1,T2,T5
(1.AddrAckHold )->(48)->(!49)->(!50)->(!51)	Not Covered
(1.AddrAckHold )->(!48)	Not Covered
(1.TransmitWait )->(52)	Covered	T1,T2,T5
(1.TransmitWait )->(!52)	Covered	T1,T2,T5
(1.TransmitSetup )->(53)	Covered	T1,T2,T5
(1.TransmitSetup )->(!53)	Covered	T1,T2,T5
(1.TransmitPulse )->(54)	Covered	T1,T2,T5
(1.TransmitPulse )->(!54)	Covered	T1,T2,T5
(1.TransmitHold )->(55)->(56)	Covered	T1,T2,T5
(1.TransmitHold )->(55)->(!56)	Covered	T1,T2,T5
(1.TransmitHold )->(!55)	Not Covered
(1.TransmitAck )->(57)	Covered	T1,T2,T5
(1.TransmitAck )->(!57)	Covered	T1,T2,T5
(1.TransmitAckPulse )->(58)->(59)	Covered	T1,T2,T5
(1.TransmitAckPulse )->(58)->(!59)	Covered	T1,T2,T5
(1.TransmitAckPulse )->(!58)	Covered	T1,T2,T5
(1.WaitForStop )	Covered	T1,T2,T5
(1.AcquireByte )->(60)->(61)	Not Covered
(1.AcquireByte )->(60)->(!61)	Covered	T1,T2,T5
(1.AcquireByte )->(!60)	Covered	T1,T2,T5
(1.AcquireAckWait )->(62)	Covered	T1,T2,T5
(1.AcquireAckWait )->(!62)	Not Covered
(1.AcquireAckSetup )->(63)	Covered	T1,T2,T5
(1.AcquireAckSetup )->(!63)	Covered	T1,T2,T5
(1.AcquireAckPulse )->(64)	Covered	T1,T2,T5
(1.AcquireAckPulse )->(!64)	Covered	T1,T2,T5
(1.AcquireAckHold )->(65)->(66)	Covered	T39,T40
(1.AcquireAckHold )->(65)->(!66)	Covered	T1,T2,T5
(1.AcquireAckHold )->(!65)	Not Covered
(1.NackWait )->(67)	Not Covered
(1.NackWait )->(!67)	Not Covered
(1.NackSetup )->(68)	Not Covered
(1.NackSetup )->(!68)	Not Covered
(1.NackPulse )->(69)	Not Covered
(1.NackPulse )->(!69)	Not Covered
(1.NackHold )->(70)	Not Covered
(1.NackHold )->(!70)	Not Covered
(1.StretchAddr )->(71)->(72)	Not Covered
(1.StretchAddr )->(71)->(!72)	Covered	T39,T40
(1.StretchAddr )->(!71)	Covered	T39,T40
(1.StretchTx )->(73)	Covered	T1,T2,T5
(1.StretchTx )->(!73)	Covered	T1,T2,T5
(1.StretchTxSetup )->(74)	Covered	T1,T2,T5
(1.StretchTxSetup )->(!74)	Covered	T1,T2,T5
(1.StretchAcqFull )->(75)	Covered	T39,T40
(1.StretchAcqFull )->(!75)	Covered	T39,T40
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1621	if (((!target_idle) && (!target_enable_i)))
-2-:	1631	if (start_det)
-3-:	1633	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1645	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1654	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	244853889	2655540	0	0
AcqFifoDeepEnough_A	244853889	244707687	0	0
SclInputGlitch_A	231994986	7431047	0	0
SclOutputGlitch_A	244853889	3832235	0	0
SclSdaChangeNotSimultaneous_A	244853889	244707687	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244853889	2655540	0	0
T1	56385	286	0	0
T2	990349	21173	0	0
T3	1196	0	0	0
T4	140940	0	0	0
T5	81945	3673	0	0
T6	39533	99	0	0
T7	525199	20872	0	0
T8	35459	97	0	0
T9	85940	0	0	0
T10	10090	0	0	0
T16	0	347	0	0
T19	0	463	0	0
T55	0	22597	0	0
T56	0	500	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244853889	244707687	0	0
T1	56385	56295	0	0
T2	990349	990263	0	0
T3	1196	1101	0	0
T4	140940	140854	0	0
T5	81945	81892	0	0
T6	39533	39463	0	0
T7	525199	525148	0	0
T8	35459	35403	0	0
T9	85940	85809	0	0
T10	10090	10037	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231994986	7431047	0	0
T1	56385	2683	0	0
T2	990349	41396	0	0
T3	1196	0	0	0
T4	140940	7735	0	0
T5	81945	3620	0	0
T6	39533	1857	0	0
T7	525199	19504	0	0
T8	35459	1872	0	0
T9	85940	4985	0	0
T10	10090	586	0	0
T35	0	11954	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244853889	3832235	0	0
T1	56385	9	0	0
T2	990349	238	0	0
T3	1196	0	0	0
T4	140940	7735	0	0
T5	81945	25	0	0
T6	39533	11	0	0
T7	525199	175	0	0
T8	35459	11	0	0
T9	85940	4985	0	0
T10	10090	586	0	0
T35	0	11954	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244853889	244707687	0	0
T1	56385	56295	0	0
T2	990349	990263	0	0
T3	1196	1101	0	0
T4	140940	140854	0	0
T5	81945	81892	0	0
T6	39533	39463	0	0
T7	525199	525148	0	0
T8	35459	35403	0	0
T9	85940	85809	0	0
T10	10090	10037	0	0