Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	245529975	8283	0	0
host_fifo_config_rd_A	245529975	4664	0	0
host_nack_handler_timeout_rd_A	245529975	1539	0	0
host_timeout_ctrl_rd_A	245529975	1249	0	0
intr_enable_rd_A	245529975	3757	0	0
ovrd_rd_A	245529975	2209	0	0
target_fifo_config_rd_A	245529975	1662	0	0
target_id_rd_A	245529975	1662	0	0
target_timeout_ctrl_rd_A	245529975	1411	0	0
timeout_ctrl_rd_A	245529975	1458	0	0
timing0_rd_A	245529975	1375	0	0
timing1_rd_A	245529975	1523	0	0
timing2_rd_A	245529975	1512	0	0
timing3_rd_A	245529975	1425	0	0
timing4_rd_A	245529975	1441	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	8283	0	0
T71	12385	2	0	0
T89	7112	274	0	0
T90	7075	1	0	0
T105	5392	219	0	0
T106	2537	113	0	0
T107	7065	3	0	0
T109	1891	173	0	0
T111	5524	64	0	0
T115	2455	149	0	0
T117	7020	2	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	4664	0	0
T15	137837	166	0	0
T18	114510	0	0	0
T21	147082	0	0	0
T78	234351	0	0	0
T86	92409	0	0	0
T146	0	115	0	0
T147	0	96	0	0
T148	0	70	0	0
T149	0	133	0	0
T150	0	128	0	0
T151	0	97	0	0
T152	0	156	0	0
T153	0	192	0	0
T154	0	228	0	0
T155	868	0	0	0
T156	73281	0	0	0
T157	222432	0	0	0
T158	374198	0	0	0
T159	138727	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1539	0	0
T71	12385	52	0	0
T72	47193	324	0	0
T89	7112	8	0	0
T90	7075	36	0	0
T108	7498	60	0	0
T117	7020	46	0	0
T124	2020	17	0	0
T125	1583	11	0	0
T126	2707	13	0	0
T142	3709	17	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1249	0	0
T71	12385	47	0	0
T72	47193	223	0	0
T89	7112	11	0	0
T90	7075	18	0	0
T108	7498	36	0	0
T117	7020	35	0	0
T124	2020	7	0	0
T125	1583	1	0	0
T126	2707	12	0	0
T142	3709	28	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	3757	0	0
T11	2645	0	0	0
T14	793345	46	0	0
T16	68793	0	0	0
T17	117595	0	0	0
T19	118224	0	0	0
T29	250476	19	0	0
T30	213216	0	0	0
T55	100898	0	0	0
T56	97494	0	0	0
T71	0	269	0	0
T72	0	277	0	0
T84	1689	0	0	0
T90	0	114	0	0
T108	0	230	0	0
T160	0	20	0	0
T161	0	21	0	0
T162	0	14	0	0
T163	0	22	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	2209	0	0
T33	65945	0	0	0
T58	140060	0	0	0
T103	1304	65	0	0
T104	80648	0	0	0
T164	0	52	0	0
T165	0	28	0	0
T166	0	23	0	0
T167	0	17	0	0
T168	0	65	0	0
T169	0	52	0	0
T170	0	42	0	0
T171	0	29	0	0
T172	0	41	0	0
T173	607925	0	0	0
T174	152941	0	0	0
T175	29880	0	0	0
T176	69278	0	0	0
T177	88877	0	0	0
T178	36180	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1662	0	0
T71	12385	94	0	0
T72	47193	263	0	0
T89	7112	2	0	0
T90	7075	66	0	0
T108	7498	102	0	0
T117	7020	82	0	0
T124	2020	14	0	0
T125	1583	4	0	0
T126	2707	11	0	0
T142	3709	10	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1662	0	0
T71	12385	105	0	0
T72	47193	279	0	0
T89	7112	5	0	0
T90	7075	63	0	0
T108	7498	80	0	0
T117	7020	59	0	0
T124	2020	20	0	0
T125	1583	22	0	0
T126	2707	16	0	0
T142	3709	17	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1411	0	0
T71	12385	46	0	0
T72	47193	299	0	0
T89	7112	7	0	0
T90	7075	38	0	0
T108	7498	82	0	0
T117	7020	55	0	0
T124	2020	8	0	0
T125	1583	6	0	0
T126	2707	11	0	0
T142	3709	26	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1458	0	0
T71	12385	45	0	0
T72	47193	275	0	0
T89	7112	14	0	0
T90	7075	23	0	0
T108	7498	48	0	0
T117	7020	35	0	0
T124	2020	5	0	0
T125	1583	12	0	0
T126	2707	19	0	0
T142	3709	46	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1375	0	0
T71	12385	52	0	0
T72	47193	260	0	0
T89	7112	4	0	0
T90	7075	35	0	0
T108	7498	71	0	0
T117	7020	55	0	0
T124	2020	5	0	0
T125	1583	4	0	0
T126	2707	7	0	0
T142	3709	40	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1523	0	0
T71	12385	66	0	0
T72	47193	213	0	0
T89	7112	2	0	0
T90	7075	52	0	0
T108	7498	61	0	0
T117	7020	36	0	0
T124	2020	12	0	0
T125	1583	7	0	0
T126	2707	8	0	0
T142	3709	15	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1512	0	0
T71	12385	73	0	0
T72	47193	330	0	0
T89	7112	10	0	0
T90	7075	33	0	0
T108	7498	50	0	0
T117	7020	76	0	0
T124	2020	11	0	0
T125	1583	4	0	0
T126	2707	2	0	0
T142	3709	43	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1425	0	0
T71	12385	67	0	0
T72	47193	255	0	0
T89	7112	6	0	0
T90	7075	36	0	0
T108	7498	45	0	0
T117	7020	59	0	0
T124	2020	12	0	0
T125	1583	4	0	0
T126	2707	7	0	0
T142	3709	14	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245529975	1441	0	0
T71	12385	71	0	0
T72	47193	262	0	0
T90	7075	40	0	0
T108	7498	39	0	0
T110	10579	10	0	0
T117	7020	75	0	0
T124	2020	5	0	0
T125	1583	2	0	0
T126	2707	11	0	0
T142	3709	29	0	0