Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

158711

1

T4

281

T5

19

T6

832

ack

13819

1

T4

34

T5

5

T6

26

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	648	1			T4	3		T6	4		T71	1
high	35268	1			T4	64		T5	1		T6	189
med	64150	1			T4	109		T5	10		T6	336
sml	71799	1			T4	139		T5	13		T6	327
all_zero	665	1			T6	2		T71	4		T72	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86012

1

T4

166

T5

14

T6

434

auto[1]

86518

1

T4

149

T5

10

T6

424

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118519

1

T4

215

T5

16

T6

583

auto[1]

54011

1

T4

100

T5

8

T6

275

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165044

1

T4

299

T5

15

T6

846

auto[1]

7486

1

T4

16

T5

9

T6

12

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163215

1

T4

282

T5

18

T6

833

auto[1]

9315

1

T4

33

T5

6

T6

25

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164088

1

T4

283

T5

20

T6

834

auto[1]

8442

1

T4

32

T5

4

T6

24

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86012

1

T4

166

T5

14

T6

434

auto[1]

86518

1

T4

149

T5

10

T6

424

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118519

1

T4

215

T5

16

T6

583

auto[1]

54011

1

T4

100

T5

8

T6

275

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165044

1

T4

299

T5

15

T6

846

auto[1]

7486

1

T4

16

T5

9

T6

12

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163215

1

T4

282

T5

18

T6

833

auto[1]

9315

1

T4

33

T5

6

T6

25

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164088

1

T4

283

T5

20

T6

834

auto[1]

8442

1

T4

32

T5

4

T6

24

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T253

1

T254

1

T255

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T4

1

T256

1

T257

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T258

1

T259

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

248

1

T4

3

T6

2

T94

4

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

141

1

T94

2

T113

2

T177

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

131

1

T6

1

T43

1

T44

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

464

1

T4

4

T6

2

T41

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

255

1

T4

3

T43

2

T94

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

242

1

T5

1

T6

2

T94

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

492

1

T4

2

T6

4

T43

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

269

1

T4

2

T6

3

T43

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

240

1

T4

3

T6

1

T44

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T95

1

T232

1

T178

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T174

1

T260

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T55

1

T253

1

T261

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50554	1			T4	80		T5	5		T6	260
write_address_byte	9315	1			T4	33		T5	6		T6	25
read_with_ack	2323	1			T5	5		T43	9		T44	3
read_with_nack	5163	1			T4	16		T5	4		T6	12
stop_byte	8442	1			T4	32		T5	4		T6	24
write_address_byte_nak	4629	1			T4	29		T5	6		T6	22
data_byte_nack	158711	1			T4	281		T5	19		T6	832
stop_byte_nack	4976	1			T4	28		T5	3		T6	21
nakok_byte_nack	79628	1			T4	134		T5	9		T6	408
nakok_addr_byte_nack	2265	1			T4	8		T5	4		T6	11