Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 85.71 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_rd_wr_cg 85.71 1 100 1 64 64



Group Instance : i2c_rd_wr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64



Summary for Group Instance i2c_rd_wr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 2 16 88.89
Crosses 24 4 20 83.33


Variables for Group Instance i2c_rd_wr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
address_match 2 0 2 100.00 100 1 1 2
cp_address_match 4 0 4 100.00 100 1 1 0
cp_read_byte 5 1 4 80.00 100 1 1 0
cp_write_byte 5 1 4 80.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0


Crosses for Group Instance i2c_rd_wr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_address_match_x_ip_mode 4 0 4 100.00 100 1 1 0
cross_write_byte_x_ip_mode 10 2 8 80.00 100 1 1 0
cross_read_byte_x_ip_mode 10 2 8 80.00 100 1 1 0


Summary for Variable address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for address_match

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11929398 1 T2 22620 T3 18321 T8 11322
auto[1] 15531645 1 T1 104 T2 476 T3 821


Summary for Variable cp_address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_address_match

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_addr_no_match 5838735 1 T3 18305 T8 4305 T10 2377
read_addr_match 11024969 1 T1 5 T3 816 T4 5233
write_addr_no_match 5904156 1 T2 22602 T8 3779 T10 2046
write_addr_match 4427082 1 T1 11 T2 474 T4 7425


Summary for Variable cp_read_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_read_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 3417225 1 T3 3836 T4 1118 T5 432
med 6558038 1 T3 7716 T4 2059 T5 1602
low 6720116 1 T3 7372 T4 1967 T5 846
all_zero 168325 1 T1 5 T3 197 T4 89


Summary for Variable cp_write_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_write_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 2095812 1 T2 4840 T4 1275 T5 56
med 4016267 1 T2 9420 T4 3143 T5 111
low 4114167 1 T2 8665 T4 2958 T5 241
all_zero 104992 1 T1 11 T2 151 T4 49


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 12901442 1 T2 23096 T3 19142 T8 11628
host 14559601 1 T1 104 T4 12678 T5 4754


Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins
address_matchip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] device 11929278 1 T2 22620 T3 18321 T8 11322
auto[0] host 120 1 T62 2 T167 2 T131 4
auto[1] device 972164 1 T2 476 T3 821 T8 306
auto[1] host 14559481 1 T1 104 T4 12678 T5 4754


Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1285771 1 T2 4840 T8 740 T10 470
high host 810041 1 T4 1275 T5 56 T6 4218
med device 2455945 1 T2 9420 T8 1527 T10 1026
med host 1560322 1 T4 3143 T5 111 T6 8084
low device 2529710 1 T2 8665 T8 1560 T10 610
low host 1584457 1 T4 2958 T5 241 T6 8307
all_zero device 58468 1 T2 151 T8 63 T10 16
all_zero host 46524 1 T1 11 T4 49 T5 21


Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1285771 1 T2 4840 T8 740 T10 470
high host 810041 1 T4 1275 T5 56 T6 4218
med device 2455945 1 T2 9420 T8 1527 T10 1026
med host 1560322 1 T4 3143 T5 111 T6 8084
low device 2529710 1 T2 8665 T8 1560 T10 610
low host 1584457 1 T4 2958 T5 241 T6 8307
all_zero device 58468 1 T2 151 T8 63 T10 16
all_zero host 46524 1 T1 11 T4 49 T5 21

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