Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41002028	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9196282

1

T1

130

T2

427

T3

253

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49288748	1			T1	368		T2	1651		T3	21654
values[0x0]	455024	1			T1	52		T2	11		T3	402
values[0x1]	454538	1			T1	68		T2	15		T3	327

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29337044	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20861266

1

T1

240

T2

724

T3

8486

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	185576	1			T2	9		T3	88		T4	35
valid_sources[0x01]	185060	1			T2	6		T3	91		T4	49
valid_sources[0x02]	187899	1			T2	8		T3	99		T4	35
valid_sources[0x03]	178665	1			T2	3		T3	79		T4	53
valid_sources[0x04]	182375	1			T1	1		T2	9		T3	79
valid_sources[0x05]	677827	1			T1	1		T2	7		T3	78
valid_sources[0x06]	181291	1			T2	7		T3	53		T4	29
valid_sources[0x07]	212869	1			T1	5		T2	6		T3	101
valid_sources[0x08]	177819	1			T2	3		T3	82		T4	41
valid_sources[0x09]	186873	1			T2	9		T3	98		T4	48
valid_sources[0x0a]	178525	1			T3	86		T4	42		T6	485
valid_sources[0x0b]	184387	1			T2	4		T3	74		T4	45
valid_sources[0x0c]	176771	1			T2	5		T3	76		T4	35
valid_sources[0x0d]	190777	1			T2	1		T3	94		T4	27
valid_sources[0x0e]	176235	1			T1	4		T2	9		T3	86
valid_sources[0x0f]	183427	1			T1	9		T2	5		T3	81
valid_sources[0x10]	179708	1			T1	4		T2	7		T3	76
valid_sources[0x11]	205818	1			T1	1		T2	10		T3	96
valid_sources[0x12]	173341	1			T2	9		T3	97		T4	34
valid_sources[0x13]	172517	1			T2	5		T3	115		T4	43
valid_sources[0x14]	169327	1			T3	81		T4	29		T6	591
valid_sources[0x15]	187799	1			T2	7		T3	94		T4	33
valid_sources[0x16]	184084	1			T2	13		T3	97		T4	43
valid_sources[0x17]	178482	1			T2	4		T3	91		T4	44
valid_sources[0x18]	181369	1			T2	3		T3	93		T4	42
valid_sources[0x19]	176142	1			T2	6		T3	92		T4	44
valid_sources[0x1a]	176080	1			T2	8		T3	75		T4	47
valid_sources[0x1b]	181397	1			T2	3		T3	56		T4	27
valid_sources[0x1c]	191192	1			T2	3		T3	84		T4	49
valid_sources[0x1d]	186054	1			T1	1		T2	11		T3	90
valid_sources[0x1e]	186284	1			T1	3		T2	12		T3	87
valid_sources[0x1f]	180921	1			T1	8		T2	8		T3	77
valid_sources[0x20]	242553	1			T1	1		T2	10		T3	100
valid_sources[0x21]	191935	1			T1	2		T2	7		T3	93
valid_sources[0x22]	173367	1			T1	2		T2	4		T3	78
valid_sources[0x23]	179277	1			T1	5		T2	7		T3	104
valid_sources[0x24]	172114	1			T2	5		T3	74		T4	31
valid_sources[0x25]	521764	1			T2	8		T3	103		T4	51
valid_sources[0x26]	177165	1			T1	1		T2	8		T3	92
valid_sources[0x27]	170942	1			T2	7		T3	105		T4	30
valid_sources[0x28]	185274	1			T1	6		T2	10		T3	77
valid_sources[0x29]	177072	1			T2	3		T3	85		T4	42
valid_sources[0x2a]	171809	1			T2	4		T3	83		T4	41
valid_sources[0x2b]	181854	1			T2	7		T3	59		T4	34
valid_sources[0x2c]	172156	1			T2	8		T3	102		T4	34
valid_sources[0x2d]	181073	1			T2	7		T3	101		T4	38
valid_sources[0x2e]	264082	1			T2	5		T3	100		T4	38
valid_sources[0x2f]	174055	1			T2	12		T3	91		T4	56
valid_sources[0x30]	191274	1			T2	6		T3	65		T4	40
valid_sources[0x31]	183379	1			T2	1		T3	72		T4	32
valid_sources[0x32]	175875	1			T2	7		T3	104		T4	49
valid_sources[0x33]	181279	1			T1	1		T2	5		T3	81
valid_sources[0x34]	167129	1			T1	2		T2	3		T3	92
valid_sources[0x35]	176316	1			T1	8		T2	9		T3	105
valid_sources[0x36]	182134	1			T2	12		T3	87		T4	32
valid_sources[0x37]	198299	1			T1	3		T2	14		T3	110
valid_sources[0x38]	173700	1			T2	3		T3	97		T4	31
valid_sources[0x39]	179049	1			T2	4		T3	74		T4	43
valid_sources[0x3a]	181469	1			T1	18		T2	12		T3	86
valid_sources[0x3b]	178567	1			T2	6		T3	90		T4	46
valid_sources[0x3c]	170981	1			T2	6		T3	84		T4	57
valid_sources[0x3d]	176440	1			T2	4		T3	121		T4	47
valid_sources[0x3e]	172584	1			T2	4		T3	73		T4	33
valid_sources[0x3f]	187884	1			T2	7		T3	101		T4	27
valid_sources[0x40]	176193	1			T1	8		T2	7		T3	75
valid_sources[0x41]	176935	1			T2	6		T3	85		T4	43
valid_sources[0x42]	181718	1			T2	5		T3	78		T4	53
valid_sources[0x43]	424068	1			T2	7		T3	87		T4	47
valid_sources[0x44]	178109	1			T2	7		T3	95		T4	39
valid_sources[0x45]	178686	1			T1	4		T2	2		T3	85
valid_sources[0x46]	175649	1			T2	4		T3	83		T4	39
valid_sources[0x47]	185704	1			T1	5		T2	10		T3	79
valid_sources[0x48]	178265	1			T1	4		T2	4		T3	78
valid_sources[0x49]	170563	1			T1	11		T2	13		T3	81
valid_sources[0x4a]	184997	1			T2	3		T3	99		T4	34
valid_sources[0x4b]	194051	1			T2	7		T3	92		T4	41
valid_sources[0x4c]	181028	1			T2	8		T3	73		T4	48
valid_sources[0x4d]	177431	1			T1	1		T2	1		T3	87
valid_sources[0x4e]	179802	1			T2	3		T3	98		T4	36
valid_sources[0x4f]	191725	1			T2	2		T3	82		T4	37
valid_sources[0x50]	179088	1			T1	1		T2	4		T3	94
valid_sources[0x51]	167294	1			T2	11		T3	97		T4	43
valid_sources[0x52]	193400	1			T1	5		T2	6		T3	122
valid_sources[0x53]	845334	1			T2	4		T3	91		T4	49
valid_sources[0x54]	174643	1			T1	6		T2	3		T3	74
valid_sources[0x55]	178336	1			T2	3		T3	81		T4	45
valid_sources[0x56]	178974	1			T1	7		T2	13		T3	79
valid_sources[0x57]	191933	1			T1	8		T2	10		T3	92
valid_sources[0x58]	230397	1			T2	16		T3	78		T4	47
valid_sources[0x59]	176515	1			T2	5		T3	102		T4	44
valid_sources[0x5a]	171115	1			T1	7		T2	13		T3	78
valid_sources[0x5b]	172061	1			T1	6		T2	6		T3	86
valid_sources[0x5c]	170140	1			T2	3		T3	74		T4	43
valid_sources[0x5d]	182786	1			T1	4		T2	6		T3	87
valid_sources[0x5e]	201380	1			T2	4		T3	74		T4	34
valid_sources[0x5f]	172251	1			T2	12		T3	78		T4	48
valid_sources[0x60]	191906	1			T2	5		T3	76		T4	39
valid_sources[0x61]	178991	1			T2	4		T3	83		T4	33
valid_sources[0x62]	169163	1			T2	6		T3	87		T4	36
valid_sources[0x63]	188895	1			T1	1		T2	13		T3	82
valid_sources[0x64]	185727	1			T2	9		T3	92		T4	38
valid_sources[0x65]	173450	1			T2	8		T3	66		T4	42
valid_sources[0x66]	182641	1			T2	1		T3	94		T4	42
valid_sources[0x67]	170761	1			T1	13		T2	7		T3	79
valid_sources[0x68]	179110	1			T2	6		T3	88		T4	44
valid_sources[0x69]	175067	1			T1	15		T2	8		T3	110
valid_sources[0x6a]	174135	1			T2	7		T3	103		T4	42
valid_sources[0x6b]	180514	1			T2	9		T3	94		T4	48
valid_sources[0x6c]	193572	1			T2	9		T3	95		T4	35
valid_sources[0x6d]	647632	1			T1	1		T2	11		T3	69
valid_sources[0x6e]	254262	1			T2	14		T3	78		T4	41
valid_sources[0x6f]	192304	1			T2	8		T3	69		T4	34
valid_sources[0x70]	179898	1			T1	3		T2	8		T3	108
valid_sources[0x71]	166609	1			T2	2		T3	92		T4	47
valid_sources[0x72]	180481	1			T1	7		T2	7		T3	82
valid_sources[0x73]	180529	1			T1	1		T2	11		T3	87
valid_sources[0x74]	184726	1			T1	1		T2	15		T3	97
valid_sources[0x75]	183344	1			T1	3		T2	4		T3	104
valid_sources[0x76]	180263	1			T2	5		T3	80		T4	40
valid_sources[0x77]	175295	1			T2	4		T3	71		T4	32
valid_sources[0x78]	178882	1			T2	10		T3	85		T4	50
valid_sources[0x79]	170568	1			T1	10		T2	4		T3	70
valid_sources[0x7a]	186644	1			T2	6		T3	78		T4	36
valid_sources[0x7b]	696894	1			T1	33		T2	3		T3	90
valid_sources[0x7c]	204119	1			T2	3		T3	92		T4	44
valid_sources[0x7d]	172315	1			T1	9		T2	9		T3	99
valid_sources[0x7e]	178348	1			T2	3		T3	84		T4	34
valid_sources[0x7f]	180093	1			T1	1		T2	8		T3	84
valid_sources[0x80]	185556	1			T1	2		T2	8		T3	75

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8808342

1

T1

44

T2

407

T3

38

values[0x0]

all_enables

biggest_size

231356

1

T1

37

T2

8

T3

149

values[0x1]

all_enables

biggest_size

156584

1

T1

49

T2

12

T3

66