Unified Coverage Report :: Module :: i2c_controller_fsm

Module : i2c_controller_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.97	96.55	92.77		96.97	93.57	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_controller_fsm	95.97	96.55	92.77		96.97	93.57	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_controller_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.97	96.55	92.77		96.97	93.57	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.97	96.55	92.77		96.97	93.57	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.44	97.17	72.94			91.67	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
TOTAL		406	392	96.55
ALWAYS	120	17	16	94.12
ALWAYS	147	3	3	100.00
ALWAYS	160	5	5	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	6	6	100.00
ALWAYS	203	9	8	88.89
CONT_ASSIGN	218	1	1	100.00
ALWAYS	222	7	7	100.00
ALWAYS	235	6	6	100.00
ALWAYS	246	5	5	100.00
ALWAYS	253	7	7	100.00
ALWAYS	266	5	5	100.00
ALWAYS	280	8	8	100.00
ALWAYS	292	8	7	87.50
ALWAYS	304	3	3	100.00
CONT_ASSIGN	346	1	1	100.00
ALWAYS	351	6	6	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
ALWAYS	379	119	116	97.48
ALWAYS	582	181	173	95.58
ALWAYS	913	3	3	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	924	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
122	1	1
123	1	1
124	1	1
125	0	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
137	1	1
142	1	1
			MISSING_ELSE
147	1	1
148	1	1
150	1	1
160	1	1
161	1	1
162	1	1
164	1	1
166	1	1
183	1	1
187	1	1
188	1	1
190	1	1
191	1	1
192	1	1
193	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	0	1
			MISSING_ELSE
213	1	1
214	1	1
218	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
229	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
			MISSING_ELSE
246	2	2
247	2	2
248	1	1
253	1	1
254	1	1
255	1	1
256	1	1
257	1	1
258	1	1
260	1	1
266	1	1
267	1	1
268	1	1
270	1	1
271	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
			MISSING_ELSE
292	1	1
293	1	1
294	1	1
295	0	1
296	1	1
297	1	1
298	1	1
299	1	1
			MISSING_ELSE
304	1	1
305	1	1
307	1	1
346	1	1
351	1	1
352	1	1
353	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
369	1	1
374	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
395	1	1
396	1	1
397	1	1
398	1	1
400	1	1
401	1	1
411	1	1
412	1	1
413	1	1
414	2	2
			MISSING_ELSE
418	1	1
419	1	1
420	1	1
424	1	1
425	1	1
426	1	1
429	1	1
430	1	1
431	1	1
433	1	1
435	1	1
439	1	1
440	1	1
441	1	1
442	1	1
443	1	2
			MISSING_ELSE
444	2	2
			MISSING_ELSE
448	1	1
449	1	1
450	1	1
454	1	1
455	1	1
456	1	1
460	1	1
461	1	1
462	1	1
463	2	2
			MISSING_ELSE
464	1	1
465	1	2
			MISSING_ELSE
466	2	2
			MISSING_ELSE
470	1	1
471	1	1
472	1	1
476	1	1
477	1	1
478	1	1
482	1	1
483	1	1
484	1	1
485	2	2
			MISSING_ELSE
486	2	2
			MISSING_ELSE
490	1	1
491	1	1
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
499	1	1
500	1	1
504	2	2
505	2	2
506	1	1
510	1	1
511	2	2
512	2	2
513	1	1
514	1	1
515	1	1
516	1	2
			MISSING_ELSE
517	2	2
			MISSING_ELSE
521	1	1
522	2	2
523	2	2
524	1	1
525	1	1
529	1	1
530	1	1
531	1	1
535	1	1
536	1	1
537	1	1
541	1	1
542	1	1
543	1	1
544	1	1
548	1	1
554	1	1
558	1	1
559	2	2
560	1	1
561	1	1
582	1	1
583	1	1
584	1	1
585	1	1
586	1	1
587	1	1
588	1	1
589	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
597	1	1
601	1	1
602	1	1
613	1	1
615	0	1
616	0	1
617	0	1
618	0	1
			MISSING_ELSE
620	1	1
621	1	1
			MISSING_ELSE
623	1	1
624	0	1
625	0	1
626	0	1
627	0	1
			MISSING_ELSE
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
			MISSING_ELSE
646	1	1
647	1	1
648	1	1
649	1	1
			MISSING_ELSE
654	1	1
655	1	1
656	1	1
657	1	1
			MISSING_ELSE
662	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
669	1	1
670	1	1
			MISSING_ELSE
676	1	1
677	1	1
679	1	1
680	1	1
681	1	1
682	1	1
683	1	1
684	1	1
			MISSING_ELSE
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
698	1	1
699	1	1
			MISSING_ELSE
706	1	1
707	1	1
708	1	1
709	1	1
			MISSING_ELSE
714	1	1
716	1	1
717	1	1
719	1	1
720	1	1
721	1	1
722	1	1
			MISSING_ELSE
728	1	1
729	1	1
730	1	1
731	1	1
732	1	1
734	1	1
735	1	1
736	1	1
			MISSING_ELSE
742	1	1
743	1	1
744	1	1
745	1	1
			MISSING_ELSE
750	1	1
752	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
758	1	1
			MISSING_ELSE
763	1	1
764	1	1
765	1	1
766	1	1
767	1	1
768	1	1
769	1	1
771	1	1
772	1	1
			MISSING_ELSE
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
788	1	1
789	1	1
791	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
			MISSING_ELSE
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
807	1	1
808	1	1
810	1	1
811	1	1
812	1	1
815	1	1
816	1	1
817	1	1
818	1	1
			MISSING_ELSE
824	1	1
825	1	1
826	1	1
827	1	1
			MISSING_ELSE
832	1	1
833	1	1
834	1	1
835	1	1
836	1	1
			MISSING_ELSE
841	1	1
842	1	1
843	1	1
844	1	1
845	1	1
847	1	1
848	1	1
849	1	1
851	1	1
852	1	1
853	1	1
			MISSING_ELSE
859	1	1
860	1	1
861	1	1
862	1	1
863	1	1
864	1	1
865	1	1
866	1	1
867	1	1
869	1	1
870	1	1
871	1	1
872	1	1
877	1	1
878	1	1
879	1	1
880	1	1
881	1	1
882	1	1
883	1	1
884	1	1
885	1	1
887	1	1
888	1	1
889	1	1
913	1	1
914	1	1
916	1	1
920	1	1
921	1	1
924	1	1

---

Cond Coverage for Module : i2c_controller_fsm

	Total	Covered	Percent
Conditions	166	154	92.77
Logical	166	154	92.77
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION (host_enable_i || (((!host_idle_o)) && ((!host_enable_i))))
             ------1------    --------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T38,T75,T76
1	0	Covered	T1,T4,T5

 LINE       137
 SUB-EXPRESSION (((!host_idle_o)) && ((!host_enable_i)))
                 --------1-------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T38,T75,T76

 LINE       162
 EXPRESSION (stretch_en && ((!scl_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       190
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       247
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T71,T80

 LINE       282
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T76,T81,T82

 LINE       294
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T71,T43
1	1	Not Covered

 LINE       353
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       358
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       369
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T7,T9,T71

 LINE       369
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T7,T9,T71

 LINE       369
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       369
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       374
 EXPRESSION (unhandled_unexp_nak_i && host_enable_i && (state_q == Idle) && host_nack_handler_timeout_en_i && ((!unhandled_nak_timeout_i)))
             ----------1----------    ------2------    --------3--------    ---------------4--------------    --------------5-------------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T5,T68,T69
1	0	1	1	1	Not Covered
1	1	0	1	1	Covered	T5,T68,T69
1	1	1	0	1	Covered	T83
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T5,T68,T69

 LINE       374
 SUB-EXPRESSION (state_q == Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       443
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       444
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T6

 LINE       463
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T68,T69
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T5,T68,T69
1	1	1	1	Covered	T5,T68,T69

 LINE       465
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       466
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       485
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T67,T84

 LINE       486
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       492
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       492
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       492
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       505
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       512
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       516
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       517
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T44,T41

 LINE       523
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       554
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T35,T85,T86
1	0	Covered	T5,T71,T43
1	1	Covered	T1,T4,T5

 LINE       602
 EXPRESSION (unhandled_unexp_nak_i || unhandled_nak_timeout_i)
             ----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Not Covered
1	0	Covered	T5,T68,T69

 LINE       613
 EXPRESSION (trans_started && unhandled_nak_cnt_expired)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T68,T69
1	1	Not Covered

 LINE       623
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       637
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       646
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       654
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T80,T87
1	Covered	T1,T4,T5

 LINE       663
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       677
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T88,T89,T90

 LINE       681
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       690
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       694
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       706
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       714
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       719
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T6

 LINE       728
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       742
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       750
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T88,T89,T90

 LINE       754
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       763
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       766
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       780
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       789
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T88,T82,T91

 LINE       793
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       802
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       804
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       824
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       832
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       842
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       864
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T35,T85,T86
1	0	Covered	T5,T71,T43
1	1	Covered	T1,T4,T5

 LINE       877
 EXPRESSION (((!host_enable_i)) && trans_started)
             ---------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T38,T75,T76
1	1	Covered	T92

 LINE       882
 EXPRESSION (((!host_enable_i)) || (fmt_fifo_depth_i == 7'b1) || unhandled_unexp_nak_i)
             ---------1--------    -------------2------------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T5,T68,T69
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T38,T75,T76

 LINE       882
 SUB-EXPRESSION (fmt_fifo_depth_i == 7'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       924
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T1,T4,T5

---

FSM Coverage for Module : i2c_controller_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	33	32	96.97
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Active	621	Covered	T1,T4,T5
ClockLow	655	Covered	T1,T4,T5
ClockLowAck	695	Covered	T1,T4,T5
ClockPulse	669	Covered	T1,T4,T5
ClockPulseAck	707	Covered	T1,T4,T5
ClockStart	647	Covered	T1,T4,T5
ClockStop	616	Covered	T4,T5,T6
HoldBit	682	Covered	T1,T4,T5
HoldDevAck	720	Covered	T4,T5,T6
HoldStart	638	Covered	T1,T4,T5
HoldStop	833	Covered	T4,T5,T6
HostClockLowAck	767	Covered	T4,T5,T6
HostClockPulseAck	781	Covered	T4,T5,T6
HostHoldBitAck	794	Covered	T4,T5,T6
Idle	847	Covered	T1,T2,T3
PopFmtFifo	734	Covered	T4,T5,T6
ReadClockLow	771	Covered	T4,T5,T6
ReadClockPulse	743	Covered	T4,T5,T6
ReadHoldBit	755	Covered	T4,T5,T6
SetupStart	666	Covered	T1,T4,T5
SetupStop	825	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
Active->ClockLow	869	Covered	T4,T5,T6
Active->ReadClockLow	861	Covered	T4,T5,T6
Active->SetupStart	865	Covered	T1,T4,T5
ClockLow->ClockPulse	669	Covered	T1,T4,T5
ClockLow->SetupStart	666	Covered	T5,T71,T43
ClockLowAck->ClockPulseAck	707	Covered	T1,T4,T5
ClockPulse->HoldBit	682	Covered	T1,T4,T5
ClockPulseAck->HoldDevAck	720	Covered	T4,T5,T6
ClockStart->ClockLow	655	Covered	T1,T4,T5
ClockStop->SetupStop	825	Covered	T4,T5,T6
HoldBit->ClockLow	698	Covered	T1,T4,T5
HoldBit->ClockLowAck	695	Covered	T1,T4,T5
HoldDevAck->ClockStop	730	Covered	T4,T5,T6
HoldDevAck->PopFmtFifo	734	Covered	T4,T5,T6
HoldStart->ClockStart	647	Covered	T1,T4,T5
HoldStop->Idle	847	Covered	T92
HoldStop->PopFmtFifo	851	Covered	T4,T5,T6
HostClockLowAck->HostClockPulseAck	781	Covered	T4,T5,T6
HostClockPulseAck->HostHoldBitAck	794	Covered	T4,T5,T6
HostHoldBitAck->ClockStop	806	Covered	T4,T5,T6
HostHoldBitAck->PopFmtFifo	810	Covered	T5,T9,T71
HostHoldBitAck->ReadClockLow	815	Covered	T4,T5,T6
Idle->Active	621	Covered	T1,T4,T5
Idle->ClockStop	616	Not Covered
PopFmtFifo->Active	887	Covered	T4,T5,T6
PopFmtFifo->ClockStop	879	Covered	T92
PopFmtFifo->Idle	883	Covered	T4,T5,T6
ReadClockLow->ReadClockPulse	743	Covered	T4,T5,T6
ReadClockPulse->ReadHoldBit	755	Covered	T4,T5,T6
ReadHoldBit->HostClockLowAck	767	Covered	T4,T5,T6
ReadHoldBit->ReadClockLow	771	Covered	T4,T5,T6
SetupStart->HoldStart	638	Covered	T1,T4,T5
SetupStop->HoldStop	833	Covered	T4,T5,T6

---

Branch Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
Branches		171	160	93.57
IF	121	15	13	86.67
IF	147	2	2	100.00
IF	160	3	3	100.00
IF	187	4	4	100.00
IF	203	4	3	75.00
IF	222	4	4	100.00
IF	235	4	4	100.00
IF	246	3	3	100.00
IF	253	4	4	100.00
IF	266	2	2	100.00
IF	280	5	5	100.00
IF	292	5	4	80.00
IF	304	2	2	100.00
IF	351	4	4	100.00
CASE	390	48	44	91.67
CASE	597	60	57	95.00
IF	913	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	121	if (load_tcount)
-2-:	122	case (tcount_sel)
-3-:	137	if ((host_enable_i || ((!host_idle_o) && (!host_enable_i))))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T1,T4,T5
1	tHoldStart	-	Covered	T1,T4,T5
1	tSetupData	-	Not Covered
1	tClockStart	-	Covered	T1,T4,T5
1	tClockLow	-	Covered	T1,T4,T5
1	tClockPulse	-	Covered	T1,T4,T5
1	tClockHigh	-	Covered	T1,T4,T5
1	tHoldBit	-	Covered	T1,T4,T5
1	tClockStop	-	Covered	T4,T5,T6
1	tSetupStop	-	Covered	T4,T5,T6
1	tHoldStop	-	Covered	T4,T5,T6
1	tNoDelay	-	Covered	T4,T5,T6
1	default	-	Not Covered
0	-	1	Covered	T1,T4,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	147	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	if ((!rst_ni))
-2-:	162	if ((stretch_en && (!scl_i)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	187	if ((!rst_ni))
-2-:	190	if ((stretch_idle_cnt == stretch_cnt_threshold))
-3-:	192	if ((!stretch_en))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	206	if (incr_nak_cnt)
-3-:	209	if ((unhandled_nak_cnt > host_nack_handler_timeout_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Not Covered
0	1	0	Covered	T5,T68,T69
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_ni))
-2-:	224	if (bit_clr)
-3-:	226	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))
-2-:	237	if (read_byte_clr)
-3-:	239	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	246	if ((!fmt_flag_read_bytes_i))
-2-:	247	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T71,T80
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	253	if ((!rst_ni))
-2-:	255	if (byte_clr)
-3-:	257	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	280	if ((!rst_ni))
-2-:	282	if ((trans_started && (!host_enable_i)))
-3-:	284	if (log_start)
-4-:	286	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T76,T81,T82
0	0	1	-	Covered	T1,T4,T5
0	0	0	1	Covered	T4,T5,T6
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	292	if ((!rst_ni))
-2-:	294	if ((pend_restart && (!host_enable_i)))
-3-:	296	if (req_restart)
-4-:	298	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T5,T71,T43
0	0	0	1	Covered	T1,T4,T5
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	351	if ((!rst_ni))
-2-:	353	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	358	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	390	case (state_q)
-2-:	396	if (trans_started)
-3-:	414	if (log_start)
-4-:	430	if (pend_restart)
-5-:	443	if ((scl_i_q && (!scl_i)))
-6-:	444	if ((sda_i_q != sda_i))
-7-:	463	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	465	if ((scl_i_q && (!scl_i)))
-9-:	466	if ((sda_i_q != sda_i))
-10-:	485	if ((scl_i_q && (!scl_i)))
-11-:	486	if ((sda_i_q != sda_i))
-12-:	492	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	504	if (fmt_flag_read_continue_i)
-14-:	505	if ((byte_index == 9'b1))
-15-:	511	if (fmt_flag_read_continue_i)
-16-:	512	if ((byte_index == 9'b1))
-17-:	516	if ((scl_i_q && (!scl_i)))
-18-:	517	if ((sda_i_q != sda_i))
-19-:	522	if (fmt_flag_read_continue_i)
-20-:	523	if ((byte_index == 9'b1))
-21-:	559	if (fmt_flag_stop_after_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T68,T69
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T71,T43
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T68,T69
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T67,T84
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T9,T71
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T9,T71
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T4,T44,T41
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T4,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T9,T71
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	597	case (state_q)
-2-:	601	if (host_enable_i)
-3-:	602	if ((unhandled_unexp_nak_i || unhandled_nak_timeout_i))
-4-:	613	if ((trans_started && unhandled_nak_cnt_expired))
-5-:	620	if (fmt_fifo_rvalid_i)
-6-:	623	if ((trans_started && (!host_enable_i)))
-7-:	637	if ((tcount_q == 20'b1))
-8-:	646	if ((tcount_q == 20'b1))
-9-:	654	if ((tcount_q == 20'b1))
-10-:	663	if ((tcount_q == 20'b1))
-11-:	665	if (pend_restart)
-12-:	677	if (((!scl_i) && stretch_predict_cnt_expired))
-13-:	681	if ((tcount_q == 20'b1))
-14-:	690	if ((tcount_q == 20'b1))
-15-:	694	if ((bit_index == '0))
-16-:	706	if ((tcount_q == 20'b1))
-17-:	714	if (((!scl_i) && stretch_predict_cnt_expired))
-18-:	719	if ((tcount_q == 20'b1))
-19-:	728	if ((tcount_q == 20'b1))
-20-:	729	if (fmt_flag_stop_after_i)
-21-:	742	if ((tcount_q == 20'b1))
-22-:	750	if (((!scl_i) && stretch_predict_cnt_expired))
-23-:	754	if ((tcount_q == 20'b1))
-24-:	763	if ((tcount_q == 20'b1))
-25-:	766	if ((bit_index == '0))
-26-:	780	if ((tcount_q == 20'b1))
-27-:	789	if (((!scl_i) && stretch_predict_cnt_expired))
-28-:	793	if ((tcount_q == 20'b1))
-29-:	802	if ((tcount_q == 20'b1))
-30-:	804	if ((byte_index == 9'b1))
-31-:	805	if (fmt_flag_stop_after_i)
-32-:	824	if ((tcount_q == 20'b1))
-33-:	832	if ((tcount_q == 20'b1))
-34-:	842	if ((tcount_q == 20'b1))
-35-:	845	if (auto_stop_q)
-36-:	859	if (fmt_flag_read_bytes_i)
-37-:	864	if ((fmt_flag_start_before_i && (!trans_started)))
-38-:	877	if (((!host_enable_i) && trans_started))
-39-:	882	if ((((!host_enable_i) || (fmt_fifo_depth_i == 7'b1)) || unhandled_unexp_nak_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	Status	Tests
Idle	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T68,T69
Idle	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
Idle	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
Idle	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
SetupStart	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldStart	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldStart	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockStart	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockStart	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T80,T87
ClockLow	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T71,T43
ClockLow	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockLow	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulse	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T88,T89,T90
ClockPulse	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulse	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T88,T89,T90
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T88,T82,T91
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Covered	T5,T9,T71
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T5,T6
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T5,T6
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	Covered	T92
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T4,T5,T6
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T5,T6
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T4,T5,T6
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T4,T5
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T4,T5,T6
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T92
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T5,T6
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	913	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_controller_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SclOutputGlitch_A	413189226	4896971	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413189226	4896971	0	0
T1	6377	34	0	0
T2	155936	0	0	0
T3	174779	0	0	0
T4	90151	4408	0	0
T5	35665	1576	0	0
T6	279074	15236	0	0
T7	1726	0	0	0
T8	97115	0	0	0
T9	315453	2702	0	0
T10	34318	0	0	0
T39	0	6545	0	0
T40	0	10710	0	0
T70	0	730	0	0
T71	0	4944	0	0
T72	0	1114	0	0