Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1099871	1			T1	3		T2	293		T3	187
all_values[1]	1099871	1			T1	3		T2	293		T3	187
all_values[2]	1099871	1			T1	3		T2	293		T3	187
all_values[3]	1099871	1			T1	3		T2	293		T3	187
all_values[4]	1099871	1			T1	3		T2	293		T3	187
all_values[5]	1099871	1			T1	3		T2	293		T3	187
all_values[6]	1099871	1			T1	3		T2	293		T3	187
all_values[7]	1099871	1			T1	3		T2	293		T3	187
all_values[8]	1099871	1			T1	3		T2	293		T3	187
all_values[9]	1099871	1			T1	3		T2	293		T3	187
all_values[10]	1099871	1			T1	3		T2	293		T3	187
all_values[11]	1099871	1			T1	3		T2	293		T3	187
all_values[12]	1099871	1			T1	3		T2	293		T3	187
all_values[13]	1099871	1			T1	3		T2	293		T3	187
all_values[14]	1099871	1			T1	3		T2	293		T3	187

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11624836

1

T1

37

T2

3675

T3

2374

auto[1]

4873229

1

T1

8

T2

720

T3

431

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14177376

1

T1

45

T2

4395

T3

2805

auto[1]

2320689

1

T69

120987

T81

47240

T49

272329

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98874	1			T1	1		T2	9		T3	18
all_values[0]	auto[0]	auto[1]	9413	1			T69	1150		T81	49		T49	1415
all_values[0]	auto[1]	auto[0]	859874	1			T1	2		T2	284		T3	169
all_values[0]	auto[1]	auto[1]	131710	1			T69	6946		T81	3099		T49	16741
all_values[1]	auto[0]	auto[0]	942529	1			T1	3		T2	293		T3	187
all_values[1]	auto[0]	auto[1]	156462	1			T69	8093		T81	3147		T49	18139
all_values[1]	auto[1]	auto[0]	579	1			T66	2		T72	2		T46	2
all_values[1]	auto[1]	auto[1]	301	1			T69	4		T81	1		T49	13
all_values[2]	auto[0]	auto[0]	943337	1			T1	3		T2	293		T3	187
all_values[2]	auto[0]	auto[1]	156365	1			T69	7866		T81	3148		T49	18151
all_values[2]	auto[1]	auto[1]	169	1			T69	1		T81	2		T49	2
all_values[3]	auto[0]	auto[0]	960660	1			T1	3		T2	293		T3	187
all_values[3]	auto[0]	auto[1]	138988	1			T69	7863		T81	3146		T49	18152
all_values[3]	auto[1]	auto[1]	223	1			T69	4		T81	4		T49	3
all_values[4]	auto[0]	auto[0]	941014	1			T1	3		T2	293		T3	187
all_values[4]	auto[0]	auto[1]	158626	1			T69	8092		T81	3149		T49	18150
all_values[4]	auto[1]	auto[0]	30	1			T73	2		T216	1		T217	1
all_values[4]	auto[1]	auto[1]	201	1			T69	3		T81	1		T49	6
all_values[5]	auto[0]	auto[0]	941047	1			T1	3		T2	293		T3	187
all_values[5]	auto[0]	auto[1]	158598	1			T69	8094		T81	3148		T49	18151
all_values[5]	auto[1]	auto[1]	226	1			T69	2		T81	2		T49	5
all_values[6]	auto[0]	auto[0]	181849	1			T1	2		T2	279		T3	185
all_values[6]	auto[0]	auto[1]	17908	1			T69	4631		T81	209		T49	3203
all_values[6]	auto[1]	auto[0]	759218	1			T1	1		T2	14		T3	2
all_values[6]	auto[1]	auto[1]	140896	1			T69	3466		T81	2941		T49	14952
all_values[7]	auto[0]	auto[0]	913540	1			T1	2		T2	222		T3	144
all_values[7]	auto[0]	auto[1]	154483	1			T69	7655		T81	3050		T49	17926
all_values[7]	auto[1]	auto[0]	27514	1			T1	1		T2	71		T3	43
all_values[7]	auto[1]	auto[1]	4334	1			T69	442		T81	98		T49	230
all_values[8]	auto[0]	auto[0]	148211	1			T1	2		T2	256		T3	167
all_values[8]	auto[0]	auto[1]	12265	1			T69	4710		T81	24		T49	291
all_values[8]	auto[1]	auto[0]	794879	1			T1	1		T2	37		T3	20
all_values[8]	auto[1]	auto[1]	144516	1			T69	3387		T81	3126		T49	17865
all_values[9]	auto[0]	auto[0]	172081	1			T1	2		T2	269		T3	173
all_values[9]	auto[0]	auto[1]	16503	1			T69	4776		T81	81		T49	671
all_values[9]	auto[1]	auto[0]	768949	1			T1	1		T2	24		T3	14
all_values[9]	auto[1]	auto[1]	142338	1			T69	3321		T81	3067		T49	17485
all_values[10]	auto[0]	auto[0]	941051	1			T1	3		T2	293		T3	187
all_values[10]	auto[0]	auto[1]	158624	1			T69	8092		T81	3147		T49	18151
all_values[10]	auto[1]	auto[1]	196	1			T69	3		T81	2		T49	5
all_values[11]	auto[0]	auto[0]	2919	1			T1	1		T2	3		T3	4
all_values[11]	auto[0]	auto[1]	523	1			T69	45		T49	14		T162	23
all_values[11]	auto[1]	auto[0]	938112	1			T1	2		T2	290		T3	183
all_values[11]	auto[1]	auto[1]	158317	1			T69	8052		T81	3150		T49	18142
all_values[12]	auto[0]	auto[0]	941030	1			T1	3		T2	293		T3	187
all_values[12]	auto[0]	auto[1]	158637	1			T69	8095		T81	3149		T49	18153
all_values[12]	auto[1]	auto[1]	204	1			T69	2		T81	1		T49	2
all_values[13]	auto[0]	auto[0]	941333	1			T1	3		T2	293		T3	187
all_values[13]	auto[0]	auto[1]	158310	1			T69	8094		T81	3146		T49	18154
all_values[13]	auto[1]	auto[0]	1	1			T30	1		-	-		-	-
all_values[13]	auto[1]	auto[1]	227	1			T69	1		T81	3		T49	2
all_values[14]	auto[0]	auto[0]	958745	1			T1	3		T2	293		T3	187
all_values[14]	auto[0]	auto[1]	140911	1			T69	8096		T81	3148		T49	18153
all_values[14]	auto[1]	auto[1]	215	1			T69	1		T81	2		T49	2