Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 60 0 60 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 15 0 15 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 60 0 60 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 1099871 1 T1 3 T2 293 T3 187
all_pins[1] 1099871 1 T1 3 T2 293 T3 187
all_pins[2] 1099871 1 T1 3 T2 293 T3 187
all_pins[3] 1099871 1 T1 3 T2 293 T3 187
all_pins[4] 1099871 1 T1 3 T2 293 T3 187
all_pins[5] 1099871 1 T1 3 T2 293 T3 187
all_pins[6] 1099871 1 T1 3 T2 293 T3 187
all_pins[7] 1099871 1 T1 3 T2 293 T3 187
all_pins[8] 1099871 1 T1 3 T2 293 T3 187
all_pins[9] 1099871 1 T1 3 T2 293 T3 187
all_pins[10] 1099871 1 T1 3 T2 293 T3 187
all_pins[11] 1099871 1 T1 3 T2 293 T3 187
all_pins[12] 1099871 1 T1 3 T2 293 T3 187
all_pins[13] 1099871 1 T1 3 T2 293 T3 187
all_pins[14] 1099871 1 T1 3 T2 293 T3 187


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 11629675 1 T1 37 T2 3666 T3 2371
values[0x1] 4868390 1 T1 8 T2 729 T3 434
transitions[0x0=>0x1] 3912278 1 T1 5 T2 698 T3 416
transitions[0x1=>0x0] 3911246 1 T1 4 T2 697 T3 415


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 0 60 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 111647 1 T1 1 T2 9 T3 18
all_pins[0] values[0x1] 988224 1 T1 2 T2 284 T3 169
all_pins[0] transitions[0x0=>0x1] 987386 1 T1 2 T2 284 T3 169
all_pins[0] transitions[0x1=>0x0] 88 1 T72 2 T69 3 T73 2
all_pins[1] values[0x0] 1098945 1 T1 3 T2 293 T3 187
all_pins[1] values[0x1] 926 1 T66 2 T72 2 T46 2
all_pins[1] transitions[0x0=>0x1] 917 1 T66 2 T72 2 T46 2
all_pins[1] transitions[0x1=>0x0] 74 1 T69 1 T81 1 T162 1
all_pins[2] values[0x0] 1099788 1 T1 3 T2 293 T3 187
all_pins[2] values[0x1] 83 1 T69 1 T81 1 T162 1
all_pins[2] transitions[0x0=>0x1] 63 1 T162 1 T163 1 T74 2
all_pins[2] transitions[0x1=>0x0] 90 1 T69 1 T81 1 T49 1
all_pins[3] values[0x0] 1099761 1 T1 3 T2 293 T3 187
all_pins[3] values[0x1] 110 1 T69 2 T81 2 T49 1
all_pins[3] transitions[0x0=>0x1] 91 1 T69 2 T81 2 T49 1
all_pins[3] transitions[0x1=>0x0] 114 1 T73 2 T216 1 T217 1
all_pins[4] values[0x0] 1099738 1 T1 3 T2 293 T3 187
all_pins[4] values[0x1] 133 1 T73 2 T216 1 T217 1
all_pins[4] transitions[0x0=>0x1] 117 1 T73 2 T216 1 T217 1
all_pins[4] transitions[0x1=>0x0] 91 1 T81 2 T49 2 T162 3
all_pins[5] values[0x0] 1099764 1 T1 3 T2 293 T3 187
all_pins[5] values[0x1] 107 1 T81 2 T49 2 T162 3
all_pins[5] transitions[0x0=>0x1] 83 1 T81 2 T49 2 T162 3
all_pins[5] transitions[0x1=>0x0] 899755 1 T1 1 T2 14 T3 2
all_pins[6] values[0x0] 200092 1 T1 2 T2 279 T3 185
all_pins[6] values[0x1] 899779 1 T1 1 T2 14 T3 2
all_pins[6] transitions[0x0=>0x1] 877980 1 T2 10 T3 1 T4 1
all_pins[6] transitions[0x1=>0x0] 13703 1 T2 72 T3 44 T39 51
all_pins[7] values[0x0] 1064369 1 T1 2 T2 217 T3 142
all_pins[7] values[0x1] 35502 1 T1 1 T2 76 T3 45
all_pins[7] transitions[0x0=>0x1] 11265 1 T2 57 T3 35 T39 45
all_pins[7] transitions[0x1=>0x0] 914837 1 T2 21 T3 11 T4 1
all_pins[8] values[0x0] 160797 1 T1 2 T2 253 T3 166
all_pins[8] values[0x1] 939074 1 T1 1 T2 40 T3 21
all_pins[8] transitions[0x0=>0x1] 30121 1 T2 32 T3 14 T39 23
all_pins[8] transitions[0x1=>0x0] 2246 1 T2 17 T3 7 T39 12
all_pins[9] values[0x0] 188672 1 T1 2 T2 268 T3 173
all_pins[9] values[0x1] 911199 1 T1 1 T2 25 T3 14
all_pins[9] transitions[0x0=>0x1] 911169 1 T1 1 T2 25 T3 14
all_pins[9] transitions[0x1=>0x0] 56 1 T69 1 T49 1 T162 3
all_pins[10] values[0x0] 1099785 1 T1 3 T2 293 T3 187
all_pins[10] values[0x1] 86 1 T69 1 T49 1 T162 3
all_pins[10] transitions[0x0=>0x1] 60 1 T69 1 T162 2 T163 3
all_pins[10] transitions[0x1=>0x0] 1092801 1 T1 2 T2 290 T3 183
all_pins[11] values[0x0] 7044 1 T1 1 T2 3 T3 4
all_pins[11] values[0x1] 1092827 1 T1 2 T2 290 T3 183
all_pins[11] transitions[0x0=>0x1] 1092790 1 T1 2 T2 290 T3 183
all_pins[11] transitions[0x1=>0x0] 62 1 T49 2 T163 1 T74 1
all_pins[12] values[0x0] 1099772 1 T1 3 T2 293 T3 187
all_pins[12] values[0x1] 99 1 T81 1 T49 2 T162 1
all_pins[12] transitions[0x0=>0x1] 75 1 T81 1 T49 2 T162 1
all_pins[12] transitions[0x1=>0x0] 108 1 T49 2 T162 3 T163 3
all_pins[13] values[0x0] 1099739 1 T1 3 T2 293 T3 187
all_pins[13] values[0x1] 132 1 T49 2 T162 3 T163 3
all_pins[13] transitions[0x0=>0x1] 95 1 T49 2 T162 3 T163 2
all_pins[13] transitions[0x1=>0x0] 72 1 T69 1 T49 2 T162 2
all_pins[14] values[0x0] 1099762 1 T1 3 T2 293 T3 187
all_pins[14] values[0x1] 109 1 T69 1 T49 2 T162 2
all_pins[14] transitions[0x0=>0x1] 66 1 T162 1 T163 1 T74 3
all_pins[14] transitions[0x1=>0x0] 987149 1 T1 1 T2 283 T3 168

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