Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	478	1			T69	8		T81	4		T49	7
all_values[1]	478	1			T69	8		T81	4		T49	7
all_values[2]	478	1			T69	8		T81	4		T49	7
all_values[3]	478	1			T69	8		T81	4		T49	7
all_values[4]	478	1			T69	8		T81	4		T49	7
all_values[5]	478	1			T69	8		T81	4		T49	7
all_values[6]	478	1			T69	8		T81	4		T49	7
all_values[7]	478	1			T69	8		T81	4		T49	7
all_values[8]	478	1			T69	8		T81	4		T49	7
all_values[9]	478	1			T69	8		T81	4		T49	7
all_values[10]	478	1			T69	8		T81	4		T49	7
all_values[11]	478	1			T69	8		T81	4		T49	7
all_values[12]	478	1			T69	8		T81	4		T49	7
all_values[13]	478	1			T69	8		T81	4		T49	7
all_values[14]	478	1			T69	8		T81	4		T49	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3827

1

T69

63

T81

39

T49

51

auto[1]

3343

1

T69

57

T81

21

T49

54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T69

16

T81

10

T49

11

auto[1]

6119

1

T69

104

T81

50

T49

94

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4191

1

T69

80

T81

35

T49

51

auto[1]

2979

1

T69

40

T81

25

T49

54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	48	1			T81	2		T249	2		T179	2
all_values[0]	auto[0]	auto[0]	auto[1]	106	1			T69	1		T81	1		T162	3
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T69	1		T250	1		T251	1
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T69	1		T49	2		T162	1
all_values[0]	auto[1]	auto[0]	auto[1]	102	1			T69	5		T81	1		T49	2
all_values[0]	auto[1]	auto[1]	auto[1]	99	1			T49	3		T162	2		T163	4
all_values[1]	auto[0]	auto[0]	auto[0]	50	1			T81	1		T49	2		T206	1
all_values[1]	auto[0]	auto[0]	auto[1]	113	1			T69	3		T81	1		T162	1
all_values[1]	auto[0]	auto[1]	auto[0]	32	1			T81	1		T49	2		T162	1
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T69	1		T49	2		T162	3
all_values[1]	auto[1]	auto[0]	auto[1]	104	1			T162	1		T74	2		T206	2
all_values[1]	auto[1]	auto[1]	auto[1]	92	1			T69	4		T81	1		T49	1
all_values[2]	auto[0]	auto[0]	auto[0]	47	1			T69	1		T162	2		T163	1
all_values[2]	auto[0]	auto[0]	auto[1]	105	1			T69	1		T81	1		T49	1
all_values[2]	auto[0]	auto[1]	auto[0]	36	1			T69	3		T49	3		T163	1
all_values[2]	auto[0]	auto[1]	auto[1]	121	1			T69	2		T81	1		T49	1
all_values[2]	auto[1]	auto[0]	auto[1]	91	1			T69	1		T81	2		T49	1
all_values[2]	auto[1]	auto[1]	auto[1]	78	1			T49	1		T163	2		T74	3
all_values[3]	auto[0]	auto[0]	auto[0]	29	1			T69	1		T49	1		T162	1
all_values[3]	auto[0]	auto[0]	auto[1]	113	1			T69	1		T81	1		T49	2
all_values[3]	auto[0]	auto[1]	auto[0]	39	1			T69	3		T163	3		T252	1
all_values[3]	auto[0]	auto[1]	auto[1]	118	1			T69	2		T81	1		T162	1
all_values[3]	auto[1]	auto[0]	auto[1]	107	1			T69	1		T81	2		T49	3
all_values[3]	auto[1]	auto[1]	auto[1]	72	1			T49	1		T163	1		T74	4
all_values[4]	auto[0]	auto[0]	auto[0]	43	1			T69	1		T162	1		T74	2
all_values[4]	auto[0]	auto[0]	auto[1]	102	1			T69	3		T49	1		T162	1
all_values[4]	auto[0]	auto[1]	auto[0]	25	1			T69	1		T162	2		T163	1
all_values[4]	auto[0]	auto[1]	auto[1]	109	1			T81	3		T163	4		T74	4
all_values[4]	auto[1]	auto[0]	auto[1]	99	1			T69	3		T81	1		T49	4
all_values[4]	auto[1]	auto[1]	auto[1]	100	1			T49	2		T163	3		T74	3
all_values[5]	auto[0]	auto[0]	auto[0]	38	1			T162	2		T74	1		T179	1
all_values[5]	auto[0]	auto[0]	auto[1]	104	1			T69	2		T49	2		T163	1
all_values[5]	auto[0]	auto[1]	auto[0]	29	1			T69	1		T162	2		T163	1
all_values[5]	auto[0]	auto[1]	auto[1]	113	1			T69	3		T81	2		T49	1
all_values[5]	auto[1]	auto[0]	auto[1]	98	1			T81	1		T49	2		T163	4
all_values[5]	auto[1]	auto[1]	auto[1]	96	1			T69	2		T81	1		T49	2
all_values[6]	auto[0]	auto[0]	auto[0]	51	1			T49	1		T163	4		T206	2
all_values[6]	auto[0]	auto[0]	auto[1]	100	1			T69	2		T81	2		T49	2
all_values[6]	auto[0]	auto[1]	auto[0]	27	1			T163	3		T206	1		T252	2
all_values[6]	auto[0]	auto[1]	auto[1]	106	1			T69	3		T49	2		T162	3
all_values[6]	auto[1]	auto[0]	auto[1]	104	1			T69	1		T81	2		T49	1
all_values[6]	auto[1]	auto[1]	auto[1]	90	1			T69	2		T49	1		T162	1
all_values[7]	auto[0]	auto[0]	auto[0]	40	1			T74	1		T179	1		T253	1
all_values[7]	auto[0]	auto[0]	auto[1]	115	1			T69	4		T81	1		T49	2
all_values[7]	auto[0]	auto[1]	auto[0]	32	1			T81	2		T74	1		T252	1
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T69	2		T49	1		T162	2
all_values[7]	auto[1]	auto[0]	auto[1]	111	1			T69	1		T162	2		T163	3
all_values[7]	auto[1]	auto[1]	auto[1]	90	1			T69	1		T81	1		T49	4
all_values[8]	auto[0]	auto[0]	auto[0]	41	1			T206	2		T252	2		T250	1
all_values[8]	auto[0]	auto[0]	auto[1]	99	1			T69	1		T81	1		T49	1
all_values[8]	auto[0]	auto[1]	auto[0]	24	1			T206	1		T250	1		T254	1
all_values[8]	auto[0]	auto[1]	auto[1]	99	1			T69	2		T49	3		T162	1
all_values[8]	auto[1]	auto[0]	auto[1]	139	1			T69	2		T81	1		T49	2
all_values[8]	auto[1]	auto[1]	auto[1]	76	1			T69	3		T81	2		T49	1
all_values[9]	auto[0]	auto[0]	auto[0]	43	1			T81	2		T162	2		T74	1
all_values[9]	auto[0]	auto[0]	auto[1]	93	1			T69	5		T81	1		T49	2
all_values[9]	auto[0]	auto[1]	auto[0]	15	1			T163	2		T255	1		T251	2
all_values[9]	auto[0]	auto[1]	auto[1]	110	1			T69	1		T162	1		T163	4
all_values[9]	auto[1]	auto[0]	auto[1]	113	1			T69	1		T81	1		T49	3
all_values[9]	auto[1]	auto[1]	auto[1]	104	1			T69	1		T49	2		T162	1
all_values[10]	auto[0]	auto[0]	auto[0]	51	1			T69	1		T81	1		T162	2
all_values[10]	auto[0]	auto[0]	auto[1]	105	1			T69	3		T81	1		T49	1
all_values[10]	auto[0]	auto[1]	auto[0]	27	1			T69	1		T163	1		T250	2
all_values[10]	auto[0]	auto[1]	auto[1]	99	1			T49	1		T163	4		T74	2
all_values[10]	auto[1]	auto[0]	auto[1]	123	1			T69	3		T81	2		T49	5
all_values[10]	auto[1]	auto[1]	auto[1]	73	1			T162	3		T163	3		T74	2
all_values[11]	auto[0]	auto[0]	auto[0]	26	1			T252	2		T253	1		T256	1
all_values[11]	auto[0]	auto[0]	auto[1]	102	1			T69	4		T81	1		T49	1
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T162	1		T163	1		T256	2
all_values[11]	auto[0]	auto[1]	auto[1]	116	1			T69	2		T81	1		T49	2
all_values[11]	auto[1]	auto[0]	auto[1]	117	1			T49	2		T162	2		T163	1
all_values[11]	auto[1]	auto[1]	auto[1]	92	1			T69	2		T81	2		T49	2
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T49	1		T162	1		T206	1
all_values[12]	auto[0]	auto[0]	auto[1]	117	1			T69	3		T81	2		T49	1
all_values[12]	auto[0]	auto[1]	auto[0]	15	1			T252	1		T253	2		T257	2
all_values[12]	auto[0]	auto[1]	auto[1]	106	1			T69	3		T81	1		T49	3
all_values[12]	auto[1]	auto[0]	auto[1]	110	1			T69	1		T162	2		T163	4
all_values[12]	auto[1]	auto[1]	auto[1]	94	1			T69	1		T81	1		T49	2
all_values[13]	auto[0]	auto[0]	auto[0]	45	1			T69	1		T81	1		T162	2
all_values[13]	auto[0]	auto[0]	auto[1]	104	1			T69	2		T81	1		T49	1
all_values[13]	auto[0]	auto[1]	auto[0]	38	1			T69	1		T162	1		T163	1
all_values[13]	auto[0]	auto[1]	auto[1]	100	1			T69	2		T49	2		T162	2
all_values[13]	auto[1]	auto[0]	auto[1]	92	1			T69	1		T81	2		T74	2
all_values[13]	auto[1]	auto[1]	auto[1]	99	1			T69	1		T49	4		T162	2
all_values[14]	auto[0]	auto[0]	auto[0]	52	1			T49	1		T252	3		T250	2
all_values[14]	auto[0]	auto[0]	auto[1]	93	1			T69	2		T81	2		T49	2
all_values[14]	auto[0]	auto[1]	auto[0]	21	1			T163	1		T249	1		T250	2
all_values[14]	auto[0]	auto[1]	auto[1]	98	1			T69	3		T49	1		T162	1
all_values[14]	auto[1]	auto[0]	auto[1]	106	1			T69	1		T81	1		T49	1
all_values[14]	auto[1]	auto[1]	auto[1]	108	1			T69	2		T81	1		T49	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal