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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.65 97.85 92.15 97.66 89.57 95.18 98.67 91.49


Total test records in report: 1469
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T1307 /workspace/coverage/default/18.i2c_host_smoke.730953274 Apr 16 02:33:28 PM PDT 24 Apr 16 02:33:59 PM PDT 24 1963744993 ps
T1308 /workspace/coverage/default/12.i2c_host_perf.1272368752 Apr 16 02:32:48 PM PDT 24 Apr 16 02:33:30 PM PDT 24 994764593 ps
T1309 /workspace/coverage/default/48.i2c_target_hrst.3854237076 Apr 16 02:36:50 PM PDT 24 Apr 16 02:36:53 PM PDT 24 502063589 ps
T1310 /workspace/coverage/default/40.i2c_target_intr_smoke.1912471902 Apr 16 02:35:55 PM PDT 24 Apr 16 02:36:02 PM PDT 24 4979169297 ps
T1311 /workspace/coverage/default/11.i2c_host_may_nack.103817708 Apr 16 02:32:50 PM PDT 24 Apr 16 02:33:13 PM PDT 24 2118389689 ps
T1312 /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3494888966 Apr 16 02:33:33 PM PDT 24 Apr 16 02:33:48 PM PDT 24 623786166 ps
T1313 /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1760472398 Apr 16 02:31:57 PM PDT 24 Apr 16 02:32:26 PM PDT 24 10143320421 ps
T1314 /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.284605939 Apr 16 02:35:31 PM PDT 24 Apr 16 02:35:33 PM PDT 24 616237660 ps
T1315 /workspace/coverage/default/22.i2c_host_stretch_timeout.1816006178 Apr 16 02:33:58 PM PDT 24 Apr 16 02:34:10 PM PDT 24 1341446736 ps
T1316 /workspace/coverage/default/4.i2c_host_stretch_timeout.1088218314 Apr 16 02:32:10 PM PDT 24 Apr 16 02:32:41 PM PDT 24 2823493897 ps
T1317 /workspace/coverage/default/25.i2c_target_stress_rd.2638663822 Apr 16 02:34:22 PM PDT 24 Apr 16 02:34:38 PM PDT 24 3947311261 ps
T1318 /workspace/coverage/default/32.i2c_target_hrst.3087110280 Apr 16 02:35:05 PM PDT 24 Apr 16 02:35:09 PM PDT 24 880480715 ps
T1319 /workspace/coverage/default/44.i2c_host_stretch_timeout.3790769239 Apr 16 02:36:15 PM PDT 24 Apr 16 02:36:36 PM PDT 24 2071484763 ps
T1320 /workspace/coverage/default/11.i2c_host_stretch_timeout.3830829224 Apr 16 02:32:44 PM PDT 24 Apr 16 02:32:57 PM PDT 24 648114453 ps
T1321 /workspace/coverage/default/25.i2c_host_mode_toggle.1105915870 Apr 16 02:34:20 PM PDT 24 Apr 16 02:34:57 PM PDT 24 1768556843 ps
T1322 /workspace/coverage/default/5.i2c_host_fifo_overflow.1899978534 Apr 16 02:32:11 PM PDT 24 Apr 16 02:32:47 PM PDT 24 2503689627 ps
T1323 /workspace/coverage/default/25.i2c_target_timeout.200056561 Apr 16 02:34:18 PM PDT 24 Apr 16 02:34:25 PM PDT 24 2789840344 ps
T1324 /workspace/coverage/default/42.i2c_target_bad_addr.729074429 Apr 16 02:36:09 PM PDT 24 Apr 16 02:36:12 PM PDT 24 357054714 ps
T1325 /workspace/coverage/default/23.i2c_target_stress_wr.3309455202 Apr 16 02:34:03 PM PDT 24 Apr 16 02:37:11 PM PDT 24 29082546806 ps
T1326 /workspace/coverage/default/15.i2c_target_stretch.2642995623 Apr 16 02:33:14 PM PDT 24 Apr 16 02:47:18 PM PDT 24 17004077992 ps
T1327 /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1838068380 Apr 16 02:33:05 PM PDT 24 Apr 16 02:33:20 PM PDT 24 554979761 ps
T1328 /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4241572686 Apr 16 02:33:32 PM PDT 24 Apr 16 02:33:43 PM PDT 24 636902605 ps
T1329 /workspace/coverage/default/7.i2c_target_unexp_stop.1882992631 Apr 16 02:32:22 PM PDT 24 Apr 16 02:32:26 PM PDT 24 572627934 ps
T1330 /workspace/coverage/default/43.i2c_host_error_intr.927102911 Apr 16 02:36:08 PM PDT 24 Apr 16 02:36:11 PM PDT 24 182588589 ps
T115 /workspace/coverage/default/3.i2c_sec_cm.2675560377 Apr 16 02:32:05 PM PDT 24 Apr 16 02:32:07 PM PDT 24 40796358 ps
T1331 /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2380339951 Apr 16 02:31:21 PM PDT 24 Apr 16 02:31:26 PM PDT 24 274594893 ps
T1332 /workspace/coverage/default/15.i2c_host_mode_toggle.3227401023 Apr 16 02:33:13 PM PDT 24 Apr 16 02:34:31 PM PDT 24 2172610757 ps
T1333 /workspace/coverage/default/8.i2c_host_fifo_reset_rx.4103253458 Apr 16 02:32:26 PM PDT 24 Apr 16 02:32:34 PM PDT 24 149259521 ps
T1334 /workspace/coverage/default/23.i2c_host_stress_all.422158326 Apr 16 02:34:00 PM PDT 24 Apr 16 02:42:48 PM PDT 24 6123623764 ps
T1335 /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1954677668 Apr 16 02:33:53 PM PDT 24 Apr 16 02:34:07 PM PDT 24 370915278 ps
T1336 /workspace/coverage/default/18.i2c_target_hrst.1382887367 Apr 16 02:33:34 PM PDT 24 Apr 16 02:33:36 PM PDT 24 2018973123 ps
T237 /workspace/coverage/default/27.i2c_host_stretch_timeout.3105672286 Apr 16 02:34:26 PM PDT 24 Apr 16 02:34:42 PM PDT 24 1870985296 ps
T1337 /workspace/coverage/default/41.i2c_host_mode_toggle.2470428307 Apr 16 02:36:03 PM PDT 24 Apr 16 02:36:24 PM PDT 24 1348029808 ps
T1338 /workspace/coverage/default/30.i2c_host_override.2887882018 Apr 16 02:34:45 PM PDT 24 Apr 16 02:34:48 PM PDT 24 99099355 ps
T1339 /workspace/coverage/default/27.i2c_host_override.3865109002 Apr 16 02:34:27 PM PDT 24 Apr 16 02:34:29 PM PDT 24 30672718 ps
T1340 /workspace/coverage/default/41.i2c_host_override.2864758928 Apr 16 02:35:55 PM PDT 24 Apr 16 02:35:56 PM PDT 24 106269598 ps
T1341 /workspace/coverage/default/42.i2c_target_stretch.1840342008 Apr 16 02:36:14 PM PDT 24 Apr 16 02:43:20 PM PDT 24 20592335817 ps
T1342 /workspace/coverage/default/31.i2c_alert_test.1147773838 Apr 16 02:34:58 PM PDT 24 Apr 16 02:35:00 PM PDT 24 47967081 ps
T1343 /workspace/coverage/default/5.i2c_target_stress_wr.736238379 Apr 16 02:32:12 PM PDT 24 Apr 16 03:17:44 PM PDT 24 71976053196 ps
T1344 /workspace/coverage/default/49.i2c_host_override.3964010595 Apr 16 02:36:53 PM PDT 24 Apr 16 02:36:55 PM PDT 24 64217804 ps
T1345 /workspace/coverage/default/4.i2c_host_fifo_reset_rx.752702511 Apr 16 02:32:04 PM PDT 24 Apr 16 02:32:15 PM PDT 24 1526149874 ps
T1346 /workspace/coverage/default/27.i2c_host_fifo_full.3576015767 Apr 16 02:34:30 PM PDT 24 Apr 16 02:35:34 PM PDT 24 8283648434 ps
T1347 /workspace/coverage/default/40.i2c_host_mode_toggle.3880906871 Apr 16 02:35:51 PM PDT 24 Apr 16 02:36:16 PM PDT 24 2373014785 ps
T1348 /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2738182397 Apr 16 02:33:37 PM PDT 24 Apr 16 02:33:44 PM PDT 24 10176942266 ps
T1349 /workspace/coverage/default/21.i2c_target_intr_stress_wr.1599986521 Apr 16 02:33:51 PM PDT 24 Apr 16 02:33:57 PM PDT 24 9240770762 ps
T1350 /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3771425202 Apr 16 02:35:43 PM PDT 24 Apr 16 02:35:45 PM PDT 24 193303932 ps
T1351 /workspace/coverage/default/17.i2c_host_fifo_watermark.2415499588 Apr 16 02:33:23 PM PDT 24 Apr 16 02:36:04 PM PDT 24 10387483162 ps
T1352 /workspace/coverage/default/0.i2c_target_intr_stress_wr.1316530332 Apr 16 02:31:21 PM PDT 24 Apr 16 02:31:36 PM PDT 24 6816685427 ps
T1353 /workspace/coverage/default/33.i2c_target_intr_stress_wr.1298731081 Apr 16 02:35:07 PM PDT 24 Apr 16 02:35:17 PM PDT 24 14057454938 ps
T1354 /workspace/coverage/default/47.i2c_host_stretch_timeout.311972509 Apr 16 02:36:41 PM PDT 24 Apr 16 02:36:58 PM PDT 24 723660457 ps
T1355 /workspace/coverage/default/7.i2c_host_smoke.3220129206 Apr 16 02:32:18 PM PDT 24 Apr 16 02:33:42 PM PDT 24 26527345056 ps
T1356 /workspace/coverage/default/35.i2c_target_bad_addr.2503406159 Apr 16 02:35:36 PM PDT 24 Apr 16 02:35:41 PM PDT 24 4015708397 ps
T1357 /workspace/coverage/default/20.i2c_host_error_intr.3728479176 Apr 16 02:33:43 PM PDT 24 Apr 16 02:33:45 PM PDT 24 77873739 ps
T1358 /workspace/coverage/default/36.i2c_host_fifo_overflow.492827555 Apr 16 02:35:30 PM PDT 24 Apr 16 02:36:17 PM PDT 24 5650411693 ps
T1359 /workspace/coverage/default/9.i2c_host_fifo_full.3022090202 Apr 16 02:32:41 PM PDT 24 Apr 16 02:34:49 PM PDT 24 7517406863 ps
T1360 /workspace/coverage/default/31.i2c_host_error_intr.3878714390 Apr 16 02:34:53 PM PDT 24 Apr 16 02:34:55 PM PDT 24 137962576 ps
T181 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2900535153 Apr 16 02:07:30 PM PDT 24 Apr 16 02:07:33 PM PDT 24 20615064 ps
T78 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3870708486 Apr 16 02:07:19 PM PDT 24 Apr 16 02:07:20 PM PDT 24 45257306 ps
T182 /workspace/coverage/cover_reg_top/28.i2c_intr_test.1356131149 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 190755498 ps
T109 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.61478561 Apr 16 02:06:55 PM PDT 24 Apr 16 02:06:57 PM PDT 24 110016288 ps
T79 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.49594945 Apr 16 02:07:26 PM PDT 24 Apr 16 02:07:27 PM PDT 24 43045181 ps
T110 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3494445154 Apr 16 02:07:24 PM PDT 24 Apr 16 02:07:27 PM PDT 24 278231130 ps
T80 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.143760872 Apr 16 02:07:12 PM PDT 24 Apr 16 02:07:14 PM PDT 24 79808708 ps
T141 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3162612084 Apr 16 02:07:30 PM PDT 24 Apr 16 02:07:32 PM PDT 24 18224032 ps
T1361 /workspace/coverage/cover_reg_top/45.i2c_intr_test.340957241 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 17733114 ps
T124 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1013253641 Apr 16 02:07:27 PM PDT 24 Apr 16 02:07:30 PM PDT 24 598898869 ps
T183 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1228858222 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:33 PM PDT 24 58841933 ps
T125 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2656459370 Apr 16 02:06:53 PM PDT 24 Apr 16 02:06:55 PM PDT 24 48602979 ps
T126 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2066267852 Apr 16 02:07:11 PM PDT 24 Apr 16 02:07:13 PM PDT 24 49214441 ps
T184 /workspace/coverage/cover_reg_top/3.i2c_intr_test.902900070 Apr 16 02:07:00 PM PDT 24 Apr 16 02:07:01 PM PDT 24 36302667 ps
T127 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1039826709 Apr 16 02:07:26 PM PDT 24 Apr 16 02:07:29 PM PDT 24 70532380 ps
T128 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1074103658 Apr 16 02:07:13 PM PDT 24 Apr 16 02:07:16 PM PDT 24 127731788 ps
T134 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1240029451 Apr 16 02:07:20 PM PDT 24 Apr 16 02:07:23 PM PDT 24 484892218 ps
T129 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3730305151 Apr 16 02:07:20 PM PDT 24 Apr 16 02:07:23 PM PDT 24 111137091 ps
T156 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1595228466 Apr 16 02:07:23 PM PDT 24 Apr 16 02:07:24 PM PDT 24 39576766 ps
T157 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.407286331 Apr 16 02:07:19 PM PDT 24 Apr 16 02:07:21 PM PDT 24 26949688 ps
T1362 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1054442673 Apr 16 02:07:26 PM PDT 24 Apr 16 02:07:27 PM PDT 24 18656007 ps
T135 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3359208837 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:35 PM PDT 24 282184564 ps
T1363 /workspace/coverage/cover_reg_top/15.i2c_intr_test.251417125 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:32 PM PDT 24 56438738 ps
T158 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4225529882 Apr 16 02:07:29 PM PDT 24 Apr 16 02:07:31 PM PDT 24 33958147 ps
T1364 /workspace/coverage/cover_reg_top/26.i2c_intr_test.3535090310 Apr 16 02:07:33 PM PDT 24 Apr 16 02:07:35 PM PDT 24 52445774 ps
T159 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2507131940 Apr 16 02:06:56 PM PDT 24 Apr 16 02:06:58 PM PDT 24 35561034 ps
T130 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2707411849 Apr 16 02:07:09 PM PDT 24 Apr 16 02:07:11 PM PDT 24 88532647 ps
T137 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3832267431 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:35 PM PDT 24 41463005 ps
T164 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.4072400109 Apr 16 02:06:59 PM PDT 24 Apr 16 02:07:01 PM PDT 24 298262221 ps
T1365 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2952922920 Apr 16 02:07:02 PM PDT 24 Apr 16 02:07:03 PM PDT 24 21781435 ps
T160 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1737072448 Apr 16 02:06:53 PM PDT 24 Apr 16 02:06:55 PM PDT 24 200977789 ps
T142 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3616608612 Apr 16 02:07:02 PM PDT 24 Apr 16 02:07:03 PM PDT 24 53713731 ps
T1366 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1455533090 Apr 16 02:06:53 PM PDT 24 Apr 16 02:06:55 PM PDT 24 23261276 ps
T165 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2940203442 Apr 16 02:07:18 PM PDT 24 Apr 16 02:07:19 PM PDT 24 124938946 ps
T1367 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4268454477 Apr 16 02:07:30 PM PDT 24 Apr 16 02:07:32 PM PDT 24 18955744 ps
T161 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4279175906 Apr 16 02:07:23 PM PDT 24 Apr 16 02:07:24 PM PDT 24 38887061 ps
T1368 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3642858299 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:08 PM PDT 24 17328207 ps
T1369 /workspace/coverage/cover_reg_top/35.i2c_intr_test.4149879276 Apr 16 02:07:38 PM PDT 24 Apr 16 02:07:40 PM PDT 24 74285110 ps
T1370 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3606492558 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:07 PM PDT 24 189377599 ps
T1371 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3507514089 Apr 16 02:07:14 PM PDT 24 Apr 16 02:07:16 PM PDT 24 16823823 ps
T143 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.183980768 Apr 16 02:07:17 PM PDT 24 Apr 16 02:07:18 PM PDT 24 68614467 ps
T218 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.900303783 Apr 16 02:07:05 PM PDT 24 Apr 16 02:07:07 PM PDT 24 251218131 ps
T166 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2741830273 Apr 16 02:07:09 PM PDT 24 Apr 16 02:07:12 PM PDT 24 263583407 ps
T1372 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1883155395 Apr 16 02:07:20 PM PDT 24 Apr 16 02:07:22 PM PDT 24 131978089 ps
T1373 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1041217280 Apr 16 02:07:25 PM PDT 24 Apr 16 02:07:26 PM PDT 24 29634633 ps
T144 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2322468762 Apr 16 02:07:12 PM PDT 24 Apr 16 02:07:13 PM PDT 24 76544236 ps
T1374 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3966879468 Apr 16 02:07:12 PM PDT 24 Apr 16 02:07:13 PM PDT 24 166231293 ps
T139 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2271864221 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:09 PM PDT 24 53659042 ps
T1375 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.646223363 Apr 16 02:07:14 PM PDT 24 Apr 16 02:07:16 PM PDT 24 451792984 ps
T1376 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1550083039 Apr 16 02:07:29 PM PDT 24 Apr 16 02:07:31 PM PDT 24 96077039 ps
T1377 /workspace/coverage/cover_reg_top/5.i2c_intr_test.439715121 Apr 16 02:07:04 PM PDT 24 Apr 16 02:07:06 PM PDT 24 23675629 ps
T145 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.416728602 Apr 16 02:06:54 PM PDT 24 Apr 16 02:06:57 PM PDT 24 129777455 ps
T219 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4122916962 Apr 16 02:07:27 PM PDT 24 Apr 16 02:07:29 PM PDT 24 171429272 ps
T1378 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.423222161 Apr 16 02:06:55 PM PDT 24 Apr 16 02:06:58 PM PDT 24 299690700 ps
T1379 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3600240205 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 53577611 ps
T1380 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1493022619 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:34 PM PDT 24 18029347 ps
T1381 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1997963990 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:08 PM PDT 24 74171349 ps
T136 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.956031 Apr 16 02:07:26 PM PDT 24 Apr 16 02:07:29 PM PDT 24 85839742 ps
T1382 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.83411235 Apr 16 02:07:15 PM PDT 24 Apr 16 02:07:17 PM PDT 24 35608262 ps
T1383 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2720650424 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 30734922 ps
T1384 /workspace/coverage/cover_reg_top/37.i2c_intr_test.622069936 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:34 PM PDT 24 145662044 ps
T1385 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2107206035 Apr 16 02:06:59 PM PDT 24 Apr 16 02:07:01 PM PDT 24 32697215 ps
T1386 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1154155335 Apr 16 02:07:38 PM PDT 24 Apr 16 02:07:39 PM PDT 24 45799219 ps
T1387 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1876109741 Apr 16 02:07:07 PM PDT 24 Apr 16 02:07:09 PM PDT 24 160663234 ps
T1388 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.985884018 Apr 16 02:07:18 PM PDT 24 Apr 16 02:07:20 PM PDT 24 20502598 ps
T146 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1419399013 Apr 16 02:06:58 PM PDT 24 Apr 16 02:06:59 PM PDT 24 20179414 ps
T1389 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2496206446 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:33 PM PDT 24 20238659 ps
T1390 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1944340355 Apr 16 02:07:14 PM PDT 24 Apr 16 02:07:16 PM PDT 24 59504250 ps
T1391 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3926112151 Apr 16 02:07:36 PM PDT 24 Apr 16 02:07:37 PM PDT 24 16769888 ps
T1392 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1532373051 Apr 16 02:07:05 PM PDT 24 Apr 16 02:07:06 PM PDT 24 23471576 ps
T1393 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2040308307 Apr 16 02:07:26 PM PDT 24 Apr 16 02:07:28 PM PDT 24 187896546 ps
T1394 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1427108938 Apr 16 02:07:19 PM PDT 24 Apr 16 02:07:21 PM PDT 24 27372459 ps
T147 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.67217845 Apr 16 02:07:17 PM PDT 24 Apr 16 02:07:19 PM PDT 24 58331094 ps
T1395 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3089410868 Apr 16 02:07:14 PM PDT 24 Apr 16 02:07:16 PM PDT 24 227799169 ps
T1396 /workspace/coverage/cover_reg_top/20.i2c_intr_test.703318626 Apr 16 02:07:24 PM PDT 24 Apr 16 02:07:25 PM PDT 24 18681569 ps
T1397 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3222957971 Apr 16 02:07:19 PM PDT 24 Apr 16 02:07:20 PM PDT 24 103269204 ps
T220 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2371951528 Apr 16 02:07:22 PM PDT 24 Apr 16 02:07:24 PM PDT 24 226904943 ps
T1398 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2146736220 Apr 16 02:07:19 PM PDT 24 Apr 16 02:07:21 PM PDT 24 16682798 ps
T148 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3165291911 Apr 16 02:07:23 PM PDT 24 Apr 16 02:07:25 PM PDT 24 27921234 ps
T140 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.960914148 Apr 16 02:06:54 PM PDT 24 Apr 16 02:06:57 PM PDT 24 91863937 ps
T1399 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4047690603 Apr 16 02:07:18 PM PDT 24 Apr 16 02:07:21 PM PDT 24 236856937 ps
T1400 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1878306072 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 52159923 ps
T1401 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.516536513 Apr 16 02:06:52 PM PDT 24 Apr 16 02:06:54 PM PDT 24 18997176 ps
T1402 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1931271498 Apr 16 02:07:24 PM PDT 24 Apr 16 02:07:25 PM PDT 24 36871092 ps
T1403 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3086809928 Apr 16 02:07:28 PM PDT 24 Apr 16 02:07:30 PM PDT 24 88563409 ps
T1404 /workspace/coverage/cover_reg_top/23.i2c_intr_test.4006211854 Apr 16 02:07:30 PM PDT 24 Apr 16 02:07:32 PM PDT 24 50823612 ps
T1405 /workspace/coverage/cover_reg_top/0.i2c_intr_test.251052995 Apr 16 02:06:55 PM PDT 24 Apr 16 02:06:56 PM PDT 24 17775963 ps
T149 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2179997755 Apr 16 02:06:52 PM PDT 24 Apr 16 02:06:54 PM PDT 24 29377144 ps
T1406 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3771652478 Apr 16 02:06:55 PM PDT 24 Apr 16 02:06:56 PM PDT 24 66921776 ps
T1407 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1634897981 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 18082697 ps
T1408 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3355339578 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 63731058 ps
T1409 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3706577275 Apr 16 02:07:30 PM PDT 24 Apr 16 02:07:32 PM PDT 24 45587674 ps
T1410 /workspace/coverage/cover_reg_top/2.i2c_intr_test.2376353108 Apr 16 02:06:56 PM PDT 24 Apr 16 02:06:57 PM PDT 24 189748272 ps
T1411 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3585982385 Apr 16 02:07:18 PM PDT 24 Apr 16 02:07:19 PM PDT 24 21097332 ps
T1412 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3532464807 Apr 16 02:06:59 PM PDT 24 Apr 16 02:07:03 PM PDT 24 996082288 ps
T1413 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2498960166 Apr 16 02:07:17 PM PDT 24 Apr 16 02:07:19 PM PDT 24 95529306 ps
T1414 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2269184105 Apr 16 02:07:30 PM PDT 24 Apr 16 02:07:32 PM PDT 24 36361655 ps
T1415 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2123024538 Apr 16 02:07:26 PM PDT 24 Apr 16 02:07:27 PM PDT 24 22001192 ps
T138 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2946035544 Apr 16 02:07:04 PM PDT 24 Apr 16 02:07:06 PM PDT 24 283105613 ps
T1416 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.989359970 Apr 16 02:07:18 PM PDT 24 Apr 16 02:07:21 PM PDT 24 159829336 ps
T1417 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2428409035 Apr 16 02:06:59 PM PDT 24 Apr 16 02:07:05 PM PDT 24 2366962194 ps
T1418 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3688874932 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:34 PM PDT 24 16545087 ps
T1419 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.359561872 Apr 16 02:06:59 PM PDT 24 Apr 16 02:07:00 PM PDT 24 28385900 ps
T132 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1840832850 Apr 16 02:06:54 PM PDT 24 Apr 16 02:06:56 PM PDT 24 89769355 ps
T1420 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1571459355 Apr 16 02:07:19 PM PDT 24 Apr 16 02:07:20 PM PDT 24 18885755 ps
T1421 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4011330198 Apr 16 02:06:58 PM PDT 24 Apr 16 02:07:01 PM PDT 24 260312189 ps
T1422 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1279830520 Apr 16 02:07:28 PM PDT 24 Apr 16 02:07:29 PM PDT 24 166636106 ps
T1423 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2712949312 Apr 16 02:07:27 PM PDT 24 Apr 16 02:07:29 PM PDT 24 65257552 ps
T1424 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.506932725 Apr 16 02:07:20 PM PDT 24 Apr 16 02:07:22 PM PDT 24 47477155 ps
T1425 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1425138105 Apr 16 02:07:38 PM PDT 24 Apr 16 02:07:40 PM PDT 24 17241237 ps
T1426 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2934455565 Apr 16 02:07:00 PM PDT 24 Apr 16 02:07:03 PM PDT 24 110368266 ps
T1427 /workspace/coverage/cover_reg_top/38.i2c_intr_test.1497698654 Apr 16 02:07:37 PM PDT 24 Apr 16 02:07:39 PM PDT 24 69842778 ps
T1428 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3070827249 Apr 16 02:06:53 PM PDT 24 Apr 16 02:06:55 PM PDT 24 20522213 ps
T1429 /workspace/coverage/cover_reg_top/16.i2c_intr_test.340894612 Apr 16 02:07:25 PM PDT 24 Apr 16 02:07:26 PM PDT 24 28015412 ps
T1430 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1271132734 Apr 16 02:07:33 PM PDT 24 Apr 16 02:07:35 PM PDT 24 20174226 ps
T1431 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2038809443 Apr 16 02:06:55 PM PDT 24 Apr 16 02:06:56 PM PDT 24 83325924 ps
T133 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1912347940 Apr 16 02:07:19 PM PDT 24 Apr 16 02:07:22 PM PDT 24 95849579 ps
T1432 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1120408814 Apr 16 02:07:00 PM PDT 24 Apr 16 02:07:01 PM PDT 24 16982750 ps
T150 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1446261891 Apr 16 02:06:53 PM PDT 24 Apr 16 02:06:55 PM PDT 24 26918020 ps
T266 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.859821715 Apr 16 02:06:58 PM PDT 24 Apr 16 02:07:00 PM PDT 24 40453796 ps
T1433 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.426629174 Apr 16 02:07:24 PM PDT 24 Apr 16 02:07:26 PM PDT 24 101526610 ps
T1434 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.17307580 Apr 16 02:07:14 PM PDT 24 Apr 16 02:07:15 PM PDT 24 121026546 ps
T1435 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1217173775 Apr 16 02:07:13 PM PDT 24 Apr 16 02:07:15 PM PDT 24 385526532 ps
T1436 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2321973502 Apr 16 02:06:54 PM PDT 24 Apr 16 02:06:56 PM PDT 24 23603281 ps
T1437 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4000521204 Apr 16 02:07:29 PM PDT 24 Apr 16 02:07:31 PM PDT 24 40291306 ps
T1438 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.202422016 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:08 PM PDT 24 50594560 ps
T131 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2327883133 Apr 16 02:07:20 PM PDT 24 Apr 16 02:07:23 PM PDT 24 149573524 ps
T1439 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.267775477 Apr 16 02:07:24 PM PDT 24 Apr 16 02:07:25 PM PDT 24 27959810 ps
T1440 /workspace/coverage/cover_reg_top/42.i2c_intr_test.567166343 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:34 PM PDT 24 48696218 ps
T1441 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.48085531 Apr 16 02:07:14 PM PDT 24 Apr 16 02:07:15 PM PDT 24 46345669 ps
T1442 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.643132010 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:08 PM PDT 24 236077709 ps
T1443 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2746333927 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 45736893 ps
T1444 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.861256783 Apr 16 02:07:27 PM PDT 24 Apr 16 02:07:30 PM PDT 24 90212682 ps
T1445 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2974713165 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:08 PM PDT 24 65730655 ps
T1446 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1828339688 Apr 16 02:07:12 PM PDT 24 Apr 16 02:07:13 PM PDT 24 34225951 ps
T1447 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1404076242 Apr 16 02:06:58 PM PDT 24 Apr 16 02:07:00 PM PDT 24 29689157 ps
T1448 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2949180575 Apr 16 02:06:58 PM PDT 24 Apr 16 02:07:00 PM PDT 24 191630694 ps
T1449 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1374492781 Apr 16 02:07:24 PM PDT 24 Apr 16 02:07:25 PM PDT 24 158956214 ps
T1450 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.47866028 Apr 16 02:07:03 PM PDT 24 Apr 16 02:07:05 PM PDT 24 59040795 ps
T1451 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2651876028 Apr 16 02:06:53 PM PDT 24 Apr 16 02:06:56 PM PDT 24 124741140 ps
T151 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3460967521 Apr 16 02:07:00 PM PDT 24 Apr 16 02:07:02 PM PDT 24 46266213 ps
T1452 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2016774523 Apr 16 02:06:59 PM PDT 24 Apr 16 02:07:00 PM PDT 24 40740967 ps
T152 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3439942366 Apr 16 02:07:01 PM PDT 24 Apr 16 02:07:03 PM PDT 24 45038298 ps
T1453 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1061319272 Apr 16 02:07:14 PM PDT 24 Apr 16 02:07:16 PM PDT 24 101776753 ps
T1454 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3842086671 Apr 16 02:07:31 PM PDT 24 Apr 16 02:07:33 PM PDT 24 100381367 ps
T1455 /workspace/coverage/cover_reg_top/44.i2c_intr_test.365983177 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 49305992 ps
T153 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1706757811 Apr 16 02:06:53 PM PDT 24 Apr 16 02:06:55 PM PDT 24 72757438 ps
T154 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3237068090 Apr 16 02:07:26 PM PDT 24 Apr 16 02:07:28 PM PDT 24 36952165 ps
T1456 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3139420649 Apr 16 02:07:32 PM PDT 24 Apr 16 02:07:35 PM PDT 24 120053049 ps
T1457 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2309505023 Apr 16 02:07:27 PM PDT 24 Apr 16 02:07:29 PM PDT 24 240754139 ps
T1458 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3336855440 Apr 16 02:07:23 PM PDT 24 Apr 16 02:07:25 PM PDT 24 39283073 ps
T1459 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2593201399 Apr 16 02:07:13 PM PDT 24 Apr 16 02:07:14 PM PDT 24 16252042 ps
T1460 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1213277854 Apr 16 02:07:20 PM PDT 24 Apr 16 02:07:22 PM PDT 24 26277805 ps
T1461 /workspace/coverage/cover_reg_top/7.i2c_intr_test.4238619348 Apr 16 02:07:06 PM PDT 24 Apr 16 02:07:07 PM PDT 24 43970358 ps
T1462 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.964677050 Apr 16 02:07:21 PM PDT 24 Apr 16 02:07:23 PM PDT 24 42306490 ps
T1463 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3459526721 Apr 16 02:07:13 PM PDT 24 Apr 16 02:07:15 PM PDT 24 72501063 ps
T1464 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3937193941 Apr 16 02:07:09 PM PDT 24 Apr 16 02:07:11 PM PDT 24 89473012 ps
T1465 /workspace/coverage/cover_reg_top/24.i2c_intr_test.4251034220 Apr 16 02:07:30 PM PDT 24 Apr 16 02:07:32 PM PDT 24 39890301 ps
T1466 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3677975101 Apr 16 02:07:11 PM PDT 24 Apr 16 02:07:13 PM PDT 24 51025044 ps
T1467 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1230788276 Apr 16 02:06:52 PM PDT 24 Apr 16 02:06:55 PM PDT 24 233737545 ps
T1468 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.586300747 Apr 16 02:07:28 PM PDT 24 Apr 16 02:07:30 PM PDT 24 33595546 ps
T1469 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4210738676 Apr 16 02:07:09 PM PDT 24 Apr 16 02:07:10 PM PDT 24 25385904 ps
T155 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1995526951 Apr 16 02:07:00 PM PDT 24 Apr 16 02:07:03 PM PDT 24 112872376 ps

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3042274094
Short name T1
Test name
Test status
Simulation time 12097247462 ps
CPU time 115.29 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 596988 kb
Host smart-7a85a085-0ec6-4484-8cdc-ccbc122b6145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042274094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3042274094
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.257783961
Short name T34
Test name
Test status
Simulation time 10046271829 ps
CPU time 83.52 seconds
Started Apr 16 02:35:00 PM PDT 24
Finished Apr 16 02:36:25 PM PDT 24
Peak memory 559752 kb
Host smart-6df3dedc-3665-4686-9502-e6829b822d93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257783961 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_tx.257783961
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.2883551847
Short name T13
Test name
Test status
Simulation time 4477437526 ps
CPU time 9.95 seconds
Started Apr 16 02:31:30 PM PDT 24
Finished Apr 16 02:31:41 PM PDT 24
Peak memory 204240 kb
Host smart-28234417-a482-479a-bfaa-31f9e3d83775
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883551847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.2883551847
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3162912405
Short name T69
Test name
Test status
Simulation time 31596423297 ps
CPU time 1472.38 seconds
Started Apr 16 02:33:01 PM PDT 24
Finished Apr 16 02:57:34 PM PDT 24
Peak memory 2559460 kb
Host smart-44449fd6-c3a9-409c-8aa0-cab4fad3abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162912405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3162912405
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1385187316
Short name T7
Test name
Test status
Simulation time 3696351722 ps
CPU time 127.95 seconds
Started Apr 16 02:33:18 PM PDT 24
Finished Apr 16 02:35:26 PM PDT 24
Peak memory 652952 kb
Host smart-3fe64ad6-025f-4d70-a148-4934eb3e3ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385187316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1385187316
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1013253641
Short name T124
Test name
Test status
Simulation time 598898869 ps
CPU time 2.46 seconds
Started Apr 16 02:07:27 PM PDT 24
Finished Apr 16 02:07:30 PM PDT 24
Peak memory 203700 kb
Host smart-4ef75528-c27d-4918-b5cb-58d188466864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013253641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1013253641
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.564042152
Short name T20
Test name
Test status
Simulation time 26270494579 ps
CPU time 111.47 seconds
Started Apr 16 02:34:16 PM PDT 24
Finished Apr 16 02:36:08 PM PDT 24
Peak memory 1604628 kb
Host smart-15fdb639-1448-4dfc-b4da-bffcb47275c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564042152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.564042152
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3718334483
Short name T206
Test name
Test status
Simulation time 61337815711 ps
CPU time 914.75 seconds
Started Apr 16 02:34:22 PM PDT 24
Finished Apr 16 02:49:38 PM PDT 24
Peak memory 2150916 kb
Host smart-36d3f15d-1206-42a2-8f79-e09e65b46ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718334483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3718334483
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_override.478189006
Short name T185
Test name
Test status
Simulation time 51575982 ps
CPU time 0.64 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 02:36:47 PM PDT 24
Peak memory 203692 kb
Host smart-62a43710-329e-42b5-8878-624284bcd671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478189006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.478189006
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1610900614
Short name T322
Test name
Test status
Simulation time 271478191 ps
CPU time 3.6 seconds
Started Apr 16 02:31:24 PM PDT 24
Finished Apr 16 02:31:29 PM PDT 24
Peak memory 203956 kb
Host smart-3c79c95c-1007-4af5-8d63-942f7213bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610900614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1610900614
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2986730654
Short name T111
Test name
Test status
Simulation time 444795655 ps
CPU time 1.03 seconds
Started Apr 16 02:31:40 PM PDT 24
Finished Apr 16 02:31:42 PM PDT 24
Peak memory 222168 kb
Host smart-b8e771b7-5722-424e-92d6-8e866edccf45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986730654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2986730654
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3162612084
Short name T141
Test name
Test status
Simulation time 18224032 ps
CPU time 0.75 seconds
Started Apr 16 02:07:30 PM PDT 24
Finished Apr 16 02:07:32 PM PDT 24
Peak memory 203472 kb
Host smart-62fb5782-157b-4230-9f9c-1afda7b25925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162612084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3162612084
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3833873444
Short name T249
Test name
Test status
Simulation time 37955821551 ps
CPU time 998.03 seconds
Started Apr 16 02:32:46 PM PDT 24
Finished Apr 16 02:49:25 PM PDT 24
Peak memory 1654120 kb
Host smart-942ab13c-e383-4d0d-8abd-9249522d5fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833873444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3833873444
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.804156619
Short name T10
Test name
Test status
Simulation time 583197958 ps
CPU time 2.75 seconds
Started Apr 16 02:32:10 PM PDT 24
Finished Apr 16 02:32:13 PM PDT 24
Peak memory 203952 kb
Host smart-b3b171d2-c1a1-4d8f-ab92-f29815375638
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804156619 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.804156619
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2066267852
Short name T126
Test name
Test status
Simulation time 49214441 ps
CPU time 1.39 seconds
Started Apr 16 02:07:11 PM PDT 24
Finished Apr 16 02:07:13 PM PDT 24
Peak memory 203820 kb
Host smart-62270509-5048-4ba8-81d2-2ba31d9955dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066267852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2066267852
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1581539608
Short name T65
Test name
Test status
Simulation time 450467814 ps
CPU time 0.9 seconds
Started Apr 16 02:35:28 PM PDT 24
Finished Apr 16 02:35:30 PM PDT 24
Peak memory 203704 kb
Host smart-67ecfb83-c729-4393-abf7-2ec1d80ea9f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581539608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1581539608
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.274585495
Short name T66
Test name
Test status
Simulation time 1960815065 ps
CPU time 38.84 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:34:37 PM PDT 24
Peak memory 358808 kb
Host smart-a85f251b-7a3a-4dfe-8388-211f8f06d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274585495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.274585495
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2900535153
Short name T181
Test name
Test status
Simulation time 20615064 ps
CPU time 0.7 seconds
Started Apr 16 02:07:30 PM PDT 24
Finished Apr 16 02:07:33 PM PDT 24
Peak memory 203404 kb
Host smart-241cb8d3-e0cb-43c7-a339-0d89d06ddb87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900535153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2900535153
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2337463755
Short name T41
Test name
Test status
Simulation time 148173380 ps
CPU time 7.02 seconds
Started Apr 16 02:35:19 PM PDT 24
Finished Apr 16 02:35:27 PM PDT 24
Peak memory 203976 kb
Host smart-aa861eec-c131-4c49-80a8-07465c0ff1cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337463755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2337463755
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.1441869534
Short name T222
Test name
Test status
Simulation time 45422521865 ps
CPU time 73.48 seconds
Started Apr 16 02:35:36 PM PDT 24
Finished Apr 16 02:36:51 PM PDT 24
Peak memory 522892 kb
Host smart-80eaf420-9fe1-443f-960e-fee00a98a798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441869534 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.1441869534
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2295616549
Short name T107
Test name
Test status
Simulation time 48765977 ps
CPU time 0.63 seconds
Started Apr 16 02:32:50 PM PDT 24
Finished Apr 16 02:32:52 PM PDT 24
Peak memory 203580 kb
Host smart-1930dbeb-0a76-4ddd-8e15-b63cae979473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295616549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2295616549
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1706757811
Short name T153
Test name
Test status
Simulation time 72757438 ps
CPU time 1.79 seconds
Started Apr 16 02:06:53 PM PDT 24
Finished Apr 16 02:06:55 PM PDT 24
Peak memory 203764 kb
Host smart-7f9e6600-8144-42b6-a3eb-a4630a776faa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706757811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1706757811
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.376884227
Short name T247
Test name
Test status
Simulation time 9066458553 ps
CPU time 5.66 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:36:16 PM PDT 24
Peak memory 219580 kb
Host smart-17b76c77-89b6-46b8-94eb-e542122d2386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376884227 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.376884227
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1840832850
Short name T132
Test name
Test status
Simulation time 89769355 ps
CPU time 1.35 seconds
Started Apr 16 02:06:54 PM PDT 24
Finished Apr 16 02:06:56 PM PDT 24
Peak memory 203696 kb
Host smart-87f8b6c4-8711-48e0-9af7-55ffe5db6a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840832850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1840832850
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1074103658
Short name T128
Test name
Test status
Simulation time 127731788 ps
CPU time 2.67 seconds
Started Apr 16 02:07:13 PM PDT 24
Finished Apr 16 02:07:16 PM PDT 24
Peak memory 203624 kb
Host smart-1e68b9f1-48c8-434a-a1bc-202e9448f1df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074103658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1074103658
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1006653857
Short name T74
Test name
Test status
Simulation time 199006344731 ps
CPU time 2179.86 seconds
Started Apr 16 02:36:39 PM PDT 24
Finished Apr 16 03:13:01 PM PDT 24
Peak memory 2644640 kb
Host smart-bc37a05e-bc36-4517-9879-9fb29fa1785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006653857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1006653857
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.2593991789
Short name T234
Test name
Test status
Simulation time 65218828650 ps
CPU time 863.46 seconds
Started Apr 16 02:34:55 PM PDT 24
Finished Apr 16 02:49:20 PM PDT 24
Peak memory 1865768 kb
Host smart-3fbf09be-3f78-4357-878b-77c1b308d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593991789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.2593991789
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2405691498
Short name T485
Test name
Test status
Simulation time 10047515155 ps
CPU time 78.56 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:36:30 PM PDT 24
Peak memory 540860 kb
Host smart-9bdd854c-078a-41ed-a281-5c91a3be8b73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405691498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2405691498
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.932046697
Short name T214
Test name
Test status
Simulation time 125807169 ps
CPU time 0.9 seconds
Started Apr 16 02:31:22 PM PDT 24
Finished Apr 16 02:31:24 PM PDT 24
Peak memory 203700 kb
Host smart-002dff3f-eb8b-4ae9-9e5d-ec945d9209dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932046697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.932046697
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1011348118
Short name T211
Test name
Test status
Simulation time 87211766 ps
CPU time 0.87 seconds
Started Apr 16 02:31:30 PM PDT 24
Finished Apr 16 02:31:31 PM PDT 24
Peak memory 203708 kb
Host smart-e1b83ded-b6fc-4a79-b204-1cb2e9c0ecb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011348118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1011348118
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3158318981
Short name T47
Test name
Test status
Simulation time 2777654749 ps
CPU time 173.9 seconds
Started Apr 16 02:33:48 PM PDT 24
Finished Apr 16 02:36:43 PM PDT 24
Peak memory 816384 kb
Host smart-b2c95127-b611-4043-8eb7-6818d087baed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158318981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3158318981
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_override.4144621269
Short name T224
Test name
Test status
Simulation time 26950305 ps
CPU time 0.67 seconds
Started Apr 16 02:34:04 PM PDT 24
Finished Apr 16 02:34:06 PM PDT 24
Peak memory 203652 kb
Host smart-ac496061-b6d2-4077-ba82-fe77b9a4970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144621269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.4144621269
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2348373731
Short name T208
Test name
Test status
Simulation time 10121027807 ps
CPU time 12.76 seconds
Started Apr 16 02:35:21 PM PDT 24
Finished Apr 16 02:35:35 PM PDT 24
Peak memory 272612 kb
Host smart-e370e91f-7e38-4560-b810-e1577aa1838b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348373731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2348373731
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1204926343
Short name T99
Test name
Test status
Simulation time 10155914634 ps
CPU time 14.13 seconds
Started Apr 16 02:34:16 PM PDT 24
Finished Apr 16 02:34:31 PM PDT 24
Peak memory 288504 kb
Host smart-9a5c2139-667a-4ec4-b2a5-cf4b4aadf27e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204926343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1204926343
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3347085430
Short name T390
Test name
Test status
Simulation time 15512789982 ps
CPU time 161.52 seconds
Started Apr 16 02:32:54 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 2206004 kb
Host smart-41fa427a-ffc2-45dc-a71e-881dcf0ed6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347085430 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3347085430
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2179997755
Short name T149
Test name
Test status
Simulation time 29377144 ps
CPU time 0.79 seconds
Started Apr 16 02:06:52 PM PDT 24
Finished Apr 16 02:06:54 PM PDT 24
Peak memory 203536 kb
Host smart-5a861334-8a11-41a9-88a3-64b3fe933ea5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179997755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2179997755
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1228858222
Short name T183
Test name
Test status
Simulation time 58841933 ps
CPU time 0.7 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:33 PM PDT 24
Peak memory 203448 kb
Host smart-f6132bdb-4d1e-481e-ba72-191047159d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228858222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1228858222
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.456956456
Short name T474
Test name
Test status
Simulation time 738057979 ps
CPU time 2.27 seconds
Started Apr 16 02:31:26 PM PDT 24
Finished Apr 16 02:31:29 PM PDT 24
Peak memory 204012 kb
Host smart-3b1d8c0a-6c71-4b84-9e25-4939faab809f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456956456 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.456956456
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.375236317
Short name T229
Test name
Test status
Simulation time 578720179 ps
CPU time 10.07 seconds
Started Apr 16 02:32:46 PM PDT 24
Finished Apr 16 02:32:57 PM PDT 24
Peak memory 206352 kb
Host smart-a22b86b3-3de5-43da-aa6f-6a700f9a7182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375236317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.375236317
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3164146766
Short name T227
Test name
Test status
Simulation time 5068870165 ps
CPU time 7.33 seconds
Started Apr 16 02:32:43 PM PDT 24
Finished Apr 16 02:32:51 PM PDT 24
Peak memory 213716 kb
Host smart-0ebc214d-670c-4f5e-9abf-07010f7ce629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164146766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3164146766
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.455797717
Short name T238
Test name
Test status
Simulation time 15764117170 ps
CPU time 100.61 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:34:25 PM PDT 24
Peak memory 1147020 kb
Host smart-7127ddf4-1b47-4b6f-a633-f147b56ff4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455797717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.455797717
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3037682880
Short name T221
Test name
Test status
Simulation time 775561466 ps
CPU time 2.37 seconds
Started Apr 16 02:32:51 PM PDT 24
Finished Apr 16 02:32:54 PM PDT 24
Peak memory 204016 kb
Host smart-4f7eea8d-5bf3-4de8-804f-09785b50dc0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037682880 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3037682880
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.45954193
Short name T243
Test name
Test status
Simulation time 65212884272 ps
CPU time 306.92 seconds
Started Apr 16 02:32:54 PM PDT 24
Finished Apr 16 02:38:02 PM PDT 24
Peak memory 1154652 kb
Host smart-68e9135d-79b7-40f8-b382-bbe6081f9923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45954193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.45954193
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3105672286
Short name T237
Test name
Test status
Simulation time 1870985296 ps
CPU time 14.85 seconds
Started Apr 16 02:34:26 PM PDT 24
Finished Apr 16 02:34:42 PM PDT 24
Peak memory 228520 kb
Host smart-d72f3475-b52e-483c-8c8f-844039d17e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105672286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3105672286
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3086088541
Short name T807
Test name
Test status
Simulation time 10157655897 ps
CPU time 29.19 seconds
Started Apr 16 02:34:31 PM PDT 24
Finished Apr 16 02:35:01 PM PDT 24
Peak memory 352980 kb
Host smart-70e7fdf6-444a-4590-9695-50c2655917da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086088541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3086088541
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.2470236995
Short name T30
Test name
Test status
Simulation time 1622370695 ps
CPU time 6.45 seconds
Started Apr 16 02:31:58 PM PDT 24
Finished Apr 16 02:32:05 PM PDT 24
Peak memory 212184 kb
Host smart-0dcf893a-4faa-4609-b47e-228e7dd53d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470236995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.2470236995
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.303319412
Short name T54
Test name
Test status
Simulation time 10100120858 ps
CPU time 65.83 seconds
Started Apr 16 02:32:58 PM PDT 24
Finished Apr 16 02:34:05 PM PDT 24
Peak memory 470640 kb
Host smart-9ed5c303-ce76-4cb8-9d8b-cfcd478fa55f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303319412 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.303319412
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2327883133
Short name T131
Test name
Test status
Simulation time 149573524 ps
CPU time 1.49 seconds
Started Apr 16 02:07:20 PM PDT 24
Finished Apr 16 02:07:23 PM PDT 24
Peak memory 203852 kb
Host smart-a00eebb4-1003-408b-8061-2b4e77714b56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327883133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2327883133
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.4142034905
Short name T83
Test name
Test status
Simulation time 10284899203 ps
CPU time 12.8 seconds
Started Apr 16 02:32:54 PM PDT 24
Finished Apr 16 02:33:08 PM PDT 24
Peak memory 273720 kb
Host smart-fd4e47f0-9353-4049-9243-8998451902b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142034905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.4142034905
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.416728602
Short name T145
Test name
Test status
Simulation time 129777455 ps
CPU time 2.75 seconds
Started Apr 16 02:06:54 PM PDT 24
Finished Apr 16 02:06:57 PM PDT 24
Peak memory 203740 kb
Host smart-1acb6591-79b8-4793-8e99-df33dd07f628
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416728602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.416728602
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3771652478
Short name T1406
Test name
Test status
Simulation time 66921776 ps
CPU time 0.75 seconds
Started Apr 16 02:06:55 PM PDT 24
Finished Apr 16 02:06:56 PM PDT 24
Peak memory 203488 kb
Host smart-738ac94b-cef0-4599-8651-3d6360f6f1cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771652478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3771652478
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2321973502
Short name T1436
Test name
Test status
Simulation time 23603281 ps
CPU time 0.82 seconds
Started Apr 16 02:06:54 PM PDT 24
Finished Apr 16 02:06:56 PM PDT 24
Peak memory 203680 kb
Host smart-d26a4c6c-82a6-490e-8339-3f057dd1dfcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321973502 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2321973502
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.516536513
Short name T1401
Test name
Test status
Simulation time 18997176 ps
CPU time 0.74 seconds
Started Apr 16 02:06:52 PM PDT 24
Finished Apr 16 02:06:54 PM PDT 24
Peak memory 203492 kb
Host smart-a30d3bb1-57fa-4efb-a4b6-2d38e0727090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516536513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.516536513
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.251052995
Short name T1405
Test name
Test status
Simulation time 17775963 ps
CPU time 0.72 seconds
Started Apr 16 02:06:55 PM PDT 24
Finished Apr 16 02:06:56 PM PDT 24
Peak memory 203436 kb
Host smart-54134fda-b5a0-4792-9225-db6f7773a36a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251052995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.251052995
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1737072448
Short name T160
Test name
Test status
Simulation time 200977789 ps
CPU time 1.11 seconds
Started Apr 16 02:06:53 PM PDT 24
Finished Apr 16 02:06:55 PM PDT 24
Peak memory 203800 kb
Host smart-d97cd90a-58ac-4234-8fbf-37405ac41119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737072448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1737072448
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1230788276
Short name T1467
Test name
Test status
Simulation time 233737545 ps
CPU time 1.5 seconds
Started Apr 16 02:06:52 PM PDT 24
Finished Apr 16 02:06:55 PM PDT 24
Peak memory 203704 kb
Host smart-fe59dae0-819d-4f83-aab7-2635c74f77ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230788276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1230788276
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.960914148
Short name T140
Test name
Test status
Simulation time 91863937 ps
CPU time 2.11 seconds
Started Apr 16 02:06:54 PM PDT 24
Finished Apr 16 02:06:57 PM PDT 24
Peak memory 203780 kb
Host smart-74892bea-ffb4-467b-90e5-9a0c294be7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960914148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.960914148
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2651876028
Short name T1451
Test name
Test status
Simulation time 124741140 ps
CPU time 1.69 seconds
Started Apr 16 02:06:53 PM PDT 24
Finished Apr 16 02:06:56 PM PDT 24
Peak memory 203812 kb
Host smart-4664ae83-74c7-4d4e-9f79-2b02b234a80a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651876028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2651876028
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1446261891
Short name T150
Test name
Test status
Simulation time 26918020 ps
CPU time 0.7 seconds
Started Apr 16 02:06:53 PM PDT 24
Finished Apr 16 02:06:55 PM PDT 24
Peak memory 203476 kb
Host smart-f557122e-fe27-41f2-84fe-6dba355ace4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446261891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1446261891
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1455533090
Short name T1366
Test name
Test status
Simulation time 23261276 ps
CPU time 0.8 seconds
Started Apr 16 02:06:53 PM PDT 24
Finished Apr 16 02:06:55 PM PDT 24
Peak memory 203596 kb
Host smart-1d4f26d1-9be6-4b31-a15a-8a6ef2f7b4b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455533090 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1455533090
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2038809443
Short name T1431
Test name
Test status
Simulation time 83325924 ps
CPU time 0.69 seconds
Started Apr 16 02:06:55 PM PDT 24
Finished Apr 16 02:06:56 PM PDT 24
Peak memory 203488 kb
Host smart-ad4f91a1-37f1-4eba-a2df-6ffa1effce1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038809443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2038809443
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3070827249
Short name T1428
Test name
Test status
Simulation time 20522213 ps
CPU time 0.69 seconds
Started Apr 16 02:06:53 PM PDT 24
Finished Apr 16 02:06:55 PM PDT 24
Peak memory 203404 kb
Host smart-aac69d82-9961-4931-ace0-fff5dc789e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070827249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3070827249
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2507131940
Short name T159
Test name
Test status
Simulation time 35561034 ps
CPU time 0.88 seconds
Started Apr 16 02:06:56 PM PDT 24
Finished Apr 16 02:06:58 PM PDT 24
Peak memory 203552 kb
Host smart-5561a5cf-5fd4-4797-9b17-c4d94e00993d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507131940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2507131940
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.423222161
Short name T1378
Test name
Test status
Simulation time 299690700 ps
CPU time 1.54 seconds
Started Apr 16 02:06:55 PM PDT 24
Finished Apr 16 02:06:58 PM PDT 24
Peak memory 203684 kb
Host smart-8e2f2c2a-03f1-42af-af6a-d0e6fcd53a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423222161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.423222161
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2656459370
Short name T125
Test name
Test status
Simulation time 48602979 ps
CPU time 1.38 seconds
Started Apr 16 02:06:53 PM PDT 24
Finished Apr 16 02:06:55 PM PDT 24
Peak memory 203808 kb
Host smart-35871513-58cf-4deb-b8b4-59eba44bbb2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656459370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2656459370
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.506932725
Short name T1424
Test name
Test status
Simulation time 47477155 ps
CPU time 0.8 seconds
Started Apr 16 02:07:20 PM PDT 24
Finished Apr 16 02:07:22 PM PDT 24
Peak memory 203512 kb
Host smart-c0851857-1fed-434f-8720-40b60b955eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506932725 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.506932725
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.267775477
Short name T1439
Test name
Test status
Simulation time 27959810 ps
CPU time 0.75 seconds
Started Apr 16 02:07:24 PM PDT 24
Finished Apr 16 02:07:25 PM PDT 24
Peak memory 203516 kb
Host smart-377d310f-5f79-4c91-b599-b0bf7a5dae7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267775477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.267775477
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3966879468
Short name T1374
Test name
Test status
Simulation time 166231293 ps
CPU time 0.69 seconds
Started Apr 16 02:07:12 PM PDT 24
Finished Apr 16 02:07:13 PM PDT 24
Peak memory 203440 kb
Host smart-b7f3cffd-08c8-491c-ae24-f0c832f2069a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966879468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3966879468
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.985884018
Short name T1388
Test name
Test status
Simulation time 20502598 ps
CPU time 0.83 seconds
Started Apr 16 02:07:18 PM PDT 24
Finished Apr 16 02:07:20 PM PDT 24
Peak memory 203492 kb
Host smart-694e09a6-a9e2-4117-8662-c2692c599a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985884018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.985884018
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.964677050
Short name T1462
Test name
Test status
Simulation time 42306490 ps
CPU time 1.16 seconds
Started Apr 16 02:07:21 PM PDT 24
Finished Apr 16 02:07:23 PM PDT 24
Peak memory 203808 kb
Host smart-ee94157c-edad-49c4-a9b6-fc176558d54a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964677050 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.964677050
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.67217845
Short name T147
Test name
Test status
Simulation time 58331094 ps
CPU time 0.75 seconds
Started Apr 16 02:07:17 PM PDT 24
Finished Apr 16 02:07:19 PM PDT 24
Peak memory 203484 kb
Host smart-da93b43a-1db7-42bf-adc8-c03473929823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67217845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.67217845
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1571459355
Short name T1420
Test name
Test status
Simulation time 18885755 ps
CPU time 0.66 seconds
Started Apr 16 02:07:19 PM PDT 24
Finished Apr 16 02:07:20 PM PDT 24
Peak memory 203440 kb
Host smart-e309d91c-23e4-4040-8868-f4623e9bf217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571459355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1571459355
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1213277854
Short name T1460
Test name
Test status
Simulation time 26277805 ps
CPU time 1.05 seconds
Started Apr 16 02:07:20 PM PDT 24
Finished Apr 16 02:07:22 PM PDT 24
Peak memory 203804 kb
Host smart-19768f02-ca07-4f3b-a341-8a1b4c0d138f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213277854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1213277854
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3730305151
Short name T129
Test name
Test status
Simulation time 111137091 ps
CPU time 2.07 seconds
Started Apr 16 02:07:20 PM PDT 24
Finished Apr 16 02:07:23 PM PDT 24
Peak memory 203668 kb
Host smart-523d0e6f-9be5-4b9c-a730-da8d5a36286c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730305151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3730305151
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4047690603
Short name T1399
Test name
Test status
Simulation time 236856937 ps
CPU time 2.24 seconds
Started Apr 16 02:07:18 PM PDT 24
Finished Apr 16 02:07:21 PM PDT 24
Peak memory 203864 kb
Host smart-b9b98e02-f5b1-4e2d-92a7-812cbd1bba90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047690603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4047690603
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3870708486
Short name T78
Test name
Test status
Simulation time 45257306 ps
CPU time 0.81 seconds
Started Apr 16 02:07:19 PM PDT 24
Finished Apr 16 02:07:20 PM PDT 24
Peak memory 203560 kb
Host smart-b7405ffa-5bf7-411d-891f-8d3e94129e7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870708486 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3870708486
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1427108938
Short name T1394
Test name
Test status
Simulation time 27372459 ps
CPU time 0.79 seconds
Started Apr 16 02:07:19 PM PDT 24
Finished Apr 16 02:07:21 PM PDT 24
Peak memory 203560 kb
Host smart-8a9afaa0-fc78-4efe-99e6-009756648f56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427108938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1427108938
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3585982385
Short name T1411
Test name
Test status
Simulation time 21097332 ps
CPU time 0.7 seconds
Started Apr 16 02:07:18 PM PDT 24
Finished Apr 16 02:07:19 PM PDT 24
Peak memory 203424 kb
Host smart-92a7d101-0566-4a36-9718-3ea4a1b2f4b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585982385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3585982385
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.407286331
Short name T157
Test name
Test status
Simulation time 26949688 ps
CPU time 1.13 seconds
Started Apr 16 02:07:19 PM PDT 24
Finished Apr 16 02:07:21 PM PDT 24
Peak memory 203716 kb
Host smart-6aa19e41-2e56-4e08-98a1-e6880bfa3313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407286331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.407286331
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.989359970
Short name T1416
Test name
Test status
Simulation time 159829336 ps
CPU time 2.11 seconds
Started Apr 16 02:07:18 PM PDT 24
Finished Apr 16 02:07:21 PM PDT 24
Peak memory 203664 kb
Host smart-e3cba2b0-d4e0-44db-bbb3-bb9b01551149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989359970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.989359970
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2371951528
Short name T220
Test name
Test status
Simulation time 226904943 ps
CPU time 2.26 seconds
Started Apr 16 02:07:22 PM PDT 24
Finished Apr 16 02:07:24 PM PDT 24
Peak memory 203804 kb
Host smart-0fa4bee2-de4a-4ec0-afea-c02d30b7f56e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371951528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2371951528
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2940203442
Short name T165
Test name
Test status
Simulation time 124938946 ps
CPU time 0.9 seconds
Started Apr 16 02:07:18 PM PDT 24
Finished Apr 16 02:07:19 PM PDT 24
Peak memory 203492 kb
Host smart-9db1cb6e-caeb-480a-98c5-9417223c2b1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940203442 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2940203442
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.183980768
Short name T143
Test name
Test status
Simulation time 68614467 ps
CPU time 0.76 seconds
Started Apr 16 02:07:17 PM PDT 24
Finished Apr 16 02:07:18 PM PDT 24
Peak memory 203492 kb
Host smart-129690a0-dc07-4f83-8dd1-531cb8a1bd00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183980768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.183980768
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2146736220
Short name T1398
Test name
Test status
Simulation time 16682798 ps
CPU time 0.7 seconds
Started Apr 16 02:07:19 PM PDT 24
Finished Apr 16 02:07:21 PM PDT 24
Peak memory 203420 kb
Host smart-461bc712-7d72-486d-ab91-7fd23537a487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146736220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2146736220
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3222957971
Short name T1397
Test name
Test status
Simulation time 103269204 ps
CPU time 0.92 seconds
Started Apr 16 02:07:19 PM PDT 24
Finished Apr 16 02:07:20 PM PDT 24
Peak memory 203584 kb
Host smart-942caaf0-7817-453b-8841-2e28a91eefeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222957971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3222957971
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2498960166
Short name T1413
Test name
Test status
Simulation time 95529306 ps
CPU time 2 seconds
Started Apr 16 02:07:17 PM PDT 24
Finished Apr 16 02:07:19 PM PDT 24
Peak memory 203692 kb
Host smart-ad272714-4ed1-4e61-984b-6ae9f414258b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498960166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2498960166
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2712949312
Short name T1423
Test name
Test status
Simulation time 65257552 ps
CPU time 1.05 seconds
Started Apr 16 02:07:27 PM PDT 24
Finished Apr 16 02:07:29 PM PDT 24
Peak memory 203564 kb
Host smart-8f9f58f6-5001-4e8a-991b-1cfb441beb48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712949312 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2712949312
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3237068090
Short name T154
Test name
Test status
Simulation time 36952165 ps
CPU time 0.67 seconds
Started Apr 16 02:07:26 PM PDT 24
Finished Apr 16 02:07:28 PM PDT 24
Peak memory 203428 kb
Host smart-f2e17025-7d0c-4b2b-ae9e-123cac8a787f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237068090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3237068090
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1883155395
Short name T1372
Test name
Test status
Simulation time 131978089 ps
CPU time 0.68 seconds
Started Apr 16 02:07:20 PM PDT 24
Finished Apr 16 02:07:22 PM PDT 24
Peak memory 203400 kb
Host smart-e5ee537f-d3e3-4c56-9d19-3f548c53de66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883155395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1883155395
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4279175906
Short name T161
Test name
Test status
Simulation time 38887061 ps
CPU time 1.03 seconds
Started Apr 16 02:07:23 PM PDT 24
Finished Apr 16 02:07:24 PM PDT 24
Peak memory 203792 kb
Host smart-a79c5da7-0bf6-4f39-9c8e-02ff7215fcc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279175906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.4279175906
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1240029451
Short name T134
Test name
Test status
Simulation time 484892218 ps
CPU time 2.49 seconds
Started Apr 16 02:07:20 PM PDT 24
Finished Apr 16 02:07:23 PM PDT 24
Peak memory 203672 kb
Host smart-369947e0-f80d-4b06-a829-078b724abaef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240029451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1240029451
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1912347940
Short name T133
Test name
Test status
Simulation time 95849579 ps
CPU time 2.01 seconds
Started Apr 16 02:07:19 PM PDT 24
Finished Apr 16 02:07:22 PM PDT 24
Peak memory 203728 kb
Host smart-50400a18-5efe-400e-84ff-3d76ccbfa171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912347940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1912347940
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.426629174
Short name T1433
Test name
Test status
Simulation time 101526610 ps
CPU time 1.37 seconds
Started Apr 16 02:07:24 PM PDT 24
Finished Apr 16 02:07:26 PM PDT 24
Peak memory 203852 kb
Host smart-4dc240c6-a8ad-4607-871f-587c93d75d94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426629174 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.426629174
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1931271498
Short name T1402
Test name
Test status
Simulation time 36871092 ps
CPU time 0.68 seconds
Started Apr 16 02:07:24 PM PDT 24
Finished Apr 16 02:07:25 PM PDT 24
Peak memory 203476 kb
Host smart-ce701d60-2ef8-4a56-ba5a-f8c1a2ebbc95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931271498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1931271498
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.251417125
Short name T1363
Test name
Test status
Simulation time 56438738 ps
CPU time 0.67 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:32 PM PDT 24
Peak memory 203432 kb
Host smart-ac03eb7e-a91f-4d02-8811-cf516455ce19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251417125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.251417125
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3086809928
Short name T1403
Test name
Test status
Simulation time 88563409 ps
CPU time 1.04 seconds
Started Apr 16 02:07:28 PM PDT 24
Finished Apr 16 02:07:30 PM PDT 24
Peak memory 203724 kb
Host smart-437e1dcd-3171-4f68-a776-68f042a7910d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086809928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3086809928
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.861256783
Short name T1444
Test name
Test status
Simulation time 90212682 ps
CPU time 2.05 seconds
Started Apr 16 02:07:27 PM PDT 24
Finished Apr 16 02:07:30 PM PDT 24
Peak memory 203664 kb
Host smart-54c75b4a-a0b8-4bb2-957e-5ea470e4fbd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861256783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.861256783
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3359208837
Short name T135
Test name
Test status
Simulation time 282184564 ps
CPU time 1.49 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203832 kb
Host smart-32623300-908a-499c-b899-883426b033e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359208837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3359208837
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1041217280
Short name T1373
Test name
Test status
Simulation time 29634633 ps
CPU time 0.9 seconds
Started Apr 16 02:07:25 PM PDT 24
Finished Apr 16 02:07:26 PM PDT 24
Peak memory 203572 kb
Host smart-6403d48a-e2f6-4b69-b195-b469e59e01ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041217280 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1041217280
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.49594945
Short name T79
Test name
Test status
Simulation time 43045181 ps
CPU time 0.69 seconds
Started Apr 16 02:07:26 PM PDT 24
Finished Apr 16 02:07:27 PM PDT 24
Peak memory 203496 kb
Host smart-2c438da2-9e8a-4808-8c4e-137619fc7bdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49594945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.49594945
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.340894612
Short name T1429
Test name
Test status
Simulation time 28015412 ps
CPU time 0.66 seconds
Started Apr 16 02:07:25 PM PDT 24
Finished Apr 16 02:07:26 PM PDT 24
Peak memory 203668 kb
Host smart-0e3436a7-0477-428c-ab42-84b72e274097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340894612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.340894612
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1595228466
Short name T156
Test name
Test status
Simulation time 39576766 ps
CPU time 0.84 seconds
Started Apr 16 02:07:23 PM PDT 24
Finished Apr 16 02:07:24 PM PDT 24
Peak memory 203548 kb
Host smart-50137e9a-2775-4583-9db8-f2af86ba2ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595228466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1595228466
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2309505023
Short name T1457
Test name
Test status
Simulation time 240754139 ps
CPU time 1.32 seconds
Started Apr 16 02:07:27 PM PDT 24
Finished Apr 16 02:07:29 PM PDT 24
Peak memory 203812 kb
Host smart-691d7b33-684f-443e-826a-24532f3091a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309505023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2309505023
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4000521204
Short name T1437
Test name
Test status
Simulation time 40291306 ps
CPU time 0.87 seconds
Started Apr 16 02:07:29 PM PDT 24
Finished Apr 16 02:07:31 PM PDT 24
Peak memory 203548 kb
Host smart-5235cc2b-c726-457c-9200-148af4f56320
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000521204 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.4000521204
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1374492781
Short name T1449
Test name
Test status
Simulation time 158956214 ps
CPU time 0.68 seconds
Started Apr 16 02:07:24 PM PDT 24
Finished Apr 16 02:07:25 PM PDT 24
Peak memory 203440 kb
Host smart-7a93bf57-9235-4762-b3ed-98137032d5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374492781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1374492781
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3355339578
Short name T1408
Test name
Test status
Simulation time 63731058 ps
CPU time 0.93 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203564 kb
Host smart-2405e610-0e77-492d-b042-2140e31393b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355339578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3355339578
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3832267431
Short name T137
Test name
Test status
Simulation time 41463005 ps
CPU time 2.06 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203680 kb
Host smart-0a7ea2c2-9d48-4321-b250-cfa7c2d2341e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832267431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3832267431
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1039826709
Short name T127
Test name
Test status
Simulation time 70532380 ps
CPU time 1.47 seconds
Started Apr 16 02:07:26 PM PDT 24
Finished Apr 16 02:07:29 PM PDT 24
Peak memory 203804 kb
Host smart-62e8af02-a9f9-4095-939b-b6a9e0c2440f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039826709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1039826709
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1279830520
Short name T1422
Test name
Test status
Simulation time 166636106 ps
CPU time 0.97 seconds
Started Apr 16 02:07:28 PM PDT 24
Finished Apr 16 02:07:29 PM PDT 24
Peak memory 203600 kb
Host smart-accf7184-1bb3-4cea-8e7a-8a4629e4ca7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279830520 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1279830520
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2123024538
Short name T1415
Test name
Test status
Simulation time 22001192 ps
CPU time 0.7 seconds
Started Apr 16 02:07:26 PM PDT 24
Finished Apr 16 02:07:27 PM PDT 24
Peak memory 203508 kb
Host smart-1bdc0377-a1ca-4941-9cfb-371fa8b60363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123024538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2123024538
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1054442673
Short name T1362
Test name
Test status
Simulation time 18656007 ps
CPU time 0.71 seconds
Started Apr 16 02:07:26 PM PDT 24
Finished Apr 16 02:07:27 PM PDT 24
Peak memory 203456 kb
Host smart-a01fcd29-401d-49a2-85a5-aa6021a52dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054442673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1054442673
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4225529882
Short name T158
Test name
Test status
Simulation time 33958147 ps
CPU time 0.9 seconds
Started Apr 16 02:07:29 PM PDT 24
Finished Apr 16 02:07:31 PM PDT 24
Peak memory 203548 kb
Host smart-7de48728-e3f4-478e-a644-6b31ec616911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225529882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.4225529882
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2040308307
Short name T1393
Test name
Test status
Simulation time 187896546 ps
CPU time 1.64 seconds
Started Apr 16 02:07:26 PM PDT 24
Finished Apr 16 02:07:28 PM PDT 24
Peak memory 203756 kb
Host smart-6a0dc79a-6f1c-45b5-8276-3357cdfbcd30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040308307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2040308307
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.956031
Short name T136
Test name
Test status
Simulation time 85839742 ps
CPU time 2.21 seconds
Started Apr 16 02:07:26 PM PDT 24
Finished Apr 16 02:07:29 PM PDT 24
Peak memory 203812 kb
Host smart-a2628c18-182e-4a3d-92ae-424258e90a36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.956031
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.586300747
Short name T1468
Test name
Test status
Simulation time 33595546 ps
CPU time 0.93 seconds
Started Apr 16 02:07:28 PM PDT 24
Finished Apr 16 02:07:30 PM PDT 24
Peak memory 203508 kb
Host smart-4f1f272e-5374-4732-bcb2-da95019d7728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586300747 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.586300747
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3165291911
Short name T148
Test name
Test status
Simulation time 27921234 ps
CPU time 0.7 seconds
Started Apr 16 02:07:23 PM PDT 24
Finished Apr 16 02:07:25 PM PDT 24
Peak memory 203524 kb
Host smart-09b32462-1b42-45f4-b9d3-011c37332652
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165291911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3165291911
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3688874932
Short name T1418
Test name
Test status
Simulation time 16545087 ps
CPU time 0.67 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:34 PM PDT 24
Peak memory 203432 kb
Host smart-c6dd5563-3b12-402c-bd69-8af2fcd7e255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688874932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3688874932
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3336855440
Short name T1458
Test name
Test status
Simulation time 39283073 ps
CPU time 0.84 seconds
Started Apr 16 02:07:23 PM PDT 24
Finished Apr 16 02:07:25 PM PDT 24
Peak memory 203584 kb
Host smart-db04f95a-673a-4a2d-82b7-f2b55fb54e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336855440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3336855440
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3494445154
Short name T110
Test name
Test status
Simulation time 278231130 ps
CPU time 1.7 seconds
Started Apr 16 02:07:24 PM PDT 24
Finished Apr 16 02:07:27 PM PDT 24
Peak memory 203740 kb
Host smart-c419304a-71ce-447e-884f-1ac620fceede
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494445154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3494445154
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4122916962
Short name T219
Test name
Test status
Simulation time 171429272 ps
CPU time 1.41 seconds
Started Apr 16 02:07:27 PM PDT 24
Finished Apr 16 02:07:29 PM PDT 24
Peak memory 203816 kb
Host smart-40167c83-0494-4580-8075-709d073d3a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122916962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4122916962
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3439942366
Short name T152
Test name
Test status
Simulation time 45038298 ps
CPU time 1.23 seconds
Started Apr 16 02:07:01 PM PDT 24
Finished Apr 16 02:07:03 PM PDT 24
Peak memory 203792 kb
Host smart-e74cc48d-61f5-4fcc-8286-e449dedddb46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439942366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3439942366
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3532464807
Short name T1412
Test name
Test status
Simulation time 996082288 ps
CPU time 3.12 seconds
Started Apr 16 02:06:59 PM PDT 24
Finished Apr 16 02:07:03 PM PDT 24
Peak memory 203748 kb
Host smart-b07be099-e098-4e9d-a699-5aebcf10d553
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532464807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3532464807
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2016774523
Short name T1452
Test name
Test status
Simulation time 40740967 ps
CPU time 0.9 seconds
Started Apr 16 02:06:59 PM PDT 24
Finished Apr 16 02:07:00 PM PDT 24
Peak memory 203648 kb
Host smart-7e5d541d-e430-4366-a2f6-1a976b0cbca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016774523 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2016774523
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2952922920
Short name T1365
Test name
Test status
Simulation time 21781435 ps
CPU time 0.71 seconds
Started Apr 16 02:07:02 PM PDT 24
Finished Apr 16 02:07:03 PM PDT 24
Peak memory 203296 kb
Host smart-854fbf66-ced9-43a2-92c0-39629213ee89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952922920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2952922920
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2376353108
Short name T1410
Test name
Test status
Simulation time 189748272 ps
CPU time 0.72 seconds
Started Apr 16 02:06:56 PM PDT 24
Finished Apr 16 02:06:57 PM PDT 24
Peak memory 203436 kb
Host smart-015b6da2-3276-4262-85d9-7d87dd33746b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376353108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2376353108
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1404076242
Short name T1447
Test name
Test status
Simulation time 29689157 ps
CPU time 1 seconds
Started Apr 16 02:06:58 PM PDT 24
Finished Apr 16 02:07:00 PM PDT 24
Peak memory 203784 kb
Host smart-48172c04-762e-4f32-af35-fe29e3f3ded9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404076242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1404076242
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.61478561
Short name T109
Test name
Test status
Simulation time 110016288 ps
CPU time 1.86 seconds
Started Apr 16 02:06:55 PM PDT 24
Finished Apr 16 02:06:57 PM PDT 24
Peak memory 203712 kb
Host smart-5b6006d8-181c-4a86-b250-8e6a698075e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61478561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.61478561
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.703318626
Short name T1396
Test name
Test status
Simulation time 18681569 ps
CPU time 0.69 seconds
Started Apr 16 02:07:24 PM PDT 24
Finished Apr 16 02:07:25 PM PDT 24
Peak memory 203440 kb
Host smart-f0a9624d-3461-4076-9daf-dd19a7c48713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703318626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.703318626
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2746333927
Short name T1443
Test name
Test status
Simulation time 45736893 ps
CPU time 0.68 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203396 kb
Host smart-30d403b4-0b87-4f27-b53e-53638fd76a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746333927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2746333927
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1634897981
Short name T1407
Test name
Test status
Simulation time 18082697 ps
CPU time 0.68 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203432 kb
Host smart-10c3bd48-9967-40e7-baeb-b82fa4a155a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634897981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1634897981
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.4006211854
Short name T1404
Test name
Test status
Simulation time 50823612 ps
CPU time 0.73 seconds
Started Apr 16 02:07:30 PM PDT 24
Finished Apr 16 02:07:32 PM PDT 24
Peak memory 203348 kb
Host smart-3e5138e9-1000-44e2-9131-7ac89f3d3258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006211854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4006211854
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.4251034220
Short name T1465
Test name
Test status
Simulation time 39890301 ps
CPU time 0.62 seconds
Started Apr 16 02:07:30 PM PDT 24
Finished Apr 16 02:07:32 PM PDT 24
Peak memory 203396 kb
Host smart-88fdbf70-e668-4b6d-a565-7ee2f5efba58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251034220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.4251034220
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3926112151
Short name T1391
Test name
Test status
Simulation time 16769888 ps
CPU time 0.67 seconds
Started Apr 16 02:07:36 PM PDT 24
Finished Apr 16 02:07:37 PM PDT 24
Peak memory 203444 kb
Host smart-069ad0eb-c30f-40a8-85b1-39856bd61eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926112151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3926112151
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3535090310
Short name T1364
Test name
Test status
Simulation time 52445774 ps
CPU time 0.68 seconds
Started Apr 16 02:07:33 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203380 kb
Host smart-0c407433-7a0e-41d0-aee6-00c78bb9c742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535090310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3535090310
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1356131149
Short name T182
Test name
Test status
Simulation time 190755498 ps
CPU time 0.68 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203444 kb
Host smart-7644eef7-56ae-439e-a40b-13cdfec7f367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356131149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1356131149
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3600240205
Short name T1379
Test name
Test status
Simulation time 53577611 ps
CPU time 0.67 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203396 kb
Host smart-7b504b2c-bbb7-4668-984a-ae43675a8123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600240205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3600240205
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3460967521
Short name T151
Test name
Test status
Simulation time 46266213 ps
CPU time 1.26 seconds
Started Apr 16 02:07:00 PM PDT 24
Finished Apr 16 02:07:02 PM PDT 24
Peak memory 203652 kb
Host smart-f640088f-fa4f-4d13-ac7a-0ac12f003b23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460967521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3460967521
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2428409035
Short name T1417
Test name
Test status
Simulation time 2366962194 ps
CPU time 5.83 seconds
Started Apr 16 02:06:59 PM PDT 24
Finished Apr 16 02:07:05 PM PDT 24
Peak memory 203796 kb
Host smart-1510f32c-533c-44dd-bdac-672b964168b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428409035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2428409035
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1419399013
Short name T146
Test name
Test status
Simulation time 20179414 ps
CPU time 0.69 seconds
Started Apr 16 02:06:58 PM PDT 24
Finished Apr 16 02:06:59 PM PDT 24
Peak memory 203284 kb
Host smart-2bb45312-8b21-449b-b3cf-97aa0a22bb20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419399013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1419399013
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.359561872
Short name T1419
Test name
Test status
Simulation time 28385900 ps
CPU time 0.83 seconds
Started Apr 16 02:06:59 PM PDT 24
Finished Apr 16 02:07:00 PM PDT 24
Peak memory 203620 kb
Host smart-66e06779-c262-4466-bb42-fc85e3df430f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359561872 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.359561872
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3616608612
Short name T142
Test name
Test status
Simulation time 53713731 ps
CPU time 0.78 seconds
Started Apr 16 02:07:02 PM PDT 24
Finished Apr 16 02:07:03 PM PDT 24
Peak memory 203452 kb
Host smart-078be072-7716-436f-815a-3f97a0243124
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616608612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3616608612
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.902900070
Short name T184
Test name
Test status
Simulation time 36302667 ps
CPU time 0.64 seconds
Started Apr 16 02:07:00 PM PDT 24
Finished Apr 16 02:07:01 PM PDT 24
Peak memory 203412 kb
Host smart-9619b2ad-015c-4619-82dc-12160bc1196b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902900070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.902900070
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2949180575
Short name T1448
Test name
Test status
Simulation time 191630694 ps
CPU time 1.18 seconds
Started Apr 16 02:06:58 PM PDT 24
Finished Apr 16 02:07:00 PM PDT 24
Peak memory 203788 kb
Host smart-96429058-d8a6-49ab-a4fb-4b74cbf3f57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949180575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2949180575
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.4072400109
Short name T164
Test name
Test status
Simulation time 298262221 ps
CPU time 1.33 seconds
Started Apr 16 02:06:59 PM PDT 24
Finished Apr 16 02:07:01 PM PDT 24
Peak memory 203716 kb
Host smart-629b71b3-adbc-4d22-9c2a-be8b89c63f88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072400109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.4072400109
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2946035544
Short name T138
Test name
Test status
Simulation time 283105613 ps
CPU time 1.53 seconds
Started Apr 16 02:07:04 PM PDT 24
Finished Apr 16 02:07:06 PM PDT 24
Peak memory 203744 kb
Host smart-fba19592-4058-49d2-b914-669e802b1e83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946035544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2946035544
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1493022619
Short name T1380
Test name
Test status
Simulation time 18029347 ps
CPU time 0.71 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:34 PM PDT 24
Peak memory 203444 kb
Host smart-943b6ab2-024b-4bac-a4e3-c23bc620e43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493022619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1493022619
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2269184105
Short name T1414
Test name
Test status
Simulation time 36361655 ps
CPU time 0.66 seconds
Started Apr 16 02:07:30 PM PDT 24
Finished Apr 16 02:07:32 PM PDT 24
Peak memory 203404 kb
Host smart-0e46165f-69ff-40c8-bfe1-1597d5e4bd73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269184105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2269184105
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3842086671
Short name T1454
Test name
Test status
Simulation time 100381367 ps
CPU time 0.66 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:33 PM PDT 24
Peak memory 203444 kb
Host smart-4ec207cc-71bc-46b2-80c4-2317e3d94a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842086671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3842086671
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1154155335
Short name T1386
Test name
Test status
Simulation time 45799219 ps
CPU time 0.66 seconds
Started Apr 16 02:07:38 PM PDT 24
Finished Apr 16 02:07:39 PM PDT 24
Peak memory 203432 kb
Host smart-93d32c80-7837-4f44-ae1e-8c0ade2707a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154155335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1154155335
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2496206446
Short name T1389
Test name
Test status
Simulation time 20238659 ps
CPU time 0.73 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:33 PM PDT 24
Peak memory 203392 kb
Host smart-993971cb-6571-4da2-9796-b040f549899e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496206446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2496206446
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.4149879276
Short name T1369
Test name
Test status
Simulation time 74285110 ps
CPU time 0.7 seconds
Started Apr 16 02:07:38 PM PDT 24
Finished Apr 16 02:07:40 PM PDT 24
Peak memory 202532 kb
Host smart-84f05492-25fc-4a48-90fc-56f415d97268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149879276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.4149879276
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.622069936
Short name T1384
Test name
Test status
Simulation time 145662044 ps
CPU time 0.64 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:34 PM PDT 24
Peak memory 203464 kb
Host smart-8ef6cf9e-575e-42cd-abfc-8b7d9c854c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622069936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.622069936
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1497698654
Short name T1427
Test name
Test status
Simulation time 69842778 ps
CPU time 0.66 seconds
Started Apr 16 02:07:37 PM PDT 24
Finished Apr 16 02:07:39 PM PDT 24
Peak memory 203352 kb
Host smart-13fe7845-c931-4210-b766-381b7f0302b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497698654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1497698654
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3139420649
Short name T1456
Test name
Test status
Simulation time 120053049 ps
CPU time 0.7 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203440 kb
Host smart-f8be3c0f-e895-41dd-a166-84192265593e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139420649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3139420649
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1995526951
Short name T155
Test name
Test status
Simulation time 112872376 ps
CPU time 1.97 seconds
Started Apr 16 02:07:00 PM PDT 24
Finished Apr 16 02:07:03 PM PDT 24
Peak memory 203800 kb
Host smart-5a037b6f-4942-4452-87fb-9997c10d7775
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995526951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1995526951
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.859821715
Short name T266
Test name
Test status
Simulation time 40453796 ps
CPU time 0.77 seconds
Started Apr 16 02:06:58 PM PDT 24
Finished Apr 16 02:07:00 PM PDT 24
Peak memory 203536 kb
Host smart-5380dc48-cc72-4d88-8667-90de8b15c6c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859821715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.859821715
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2974713165
Short name T1445
Test name
Test status
Simulation time 65730655 ps
CPU time 0.98 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:08 PM PDT 24
Peak memory 203596 kb
Host smart-3abff619-8e74-4131-a5dc-8bd08bf48ab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974713165 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2974713165
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2107206035
Short name T1385
Test name
Test status
Simulation time 32697215 ps
CPU time 0.69 seconds
Started Apr 16 02:06:59 PM PDT 24
Finished Apr 16 02:07:01 PM PDT 24
Peak memory 203524 kb
Host smart-35e4b0f0-6a96-4472-8133-9c24cdf93364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107206035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2107206035
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1120408814
Short name T1432
Test name
Test status
Simulation time 16982750 ps
CPU time 0.67 seconds
Started Apr 16 02:07:00 PM PDT 24
Finished Apr 16 02:07:01 PM PDT 24
Peak memory 203404 kb
Host smart-bbba8c0b-3fb8-46b7-9d13-8355cb12e3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120408814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1120408814
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.47866028
Short name T1450
Test name
Test status
Simulation time 59040795 ps
CPU time 1.17 seconds
Started Apr 16 02:07:03 PM PDT 24
Finished Apr 16 02:07:05 PM PDT 24
Peak memory 203776 kb
Host smart-87b50aee-43a2-4508-9239-df0fd0259d82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47866028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outs
tanding.47866028
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2934455565
Short name T1426
Test name
Test status
Simulation time 110368266 ps
CPU time 2.57 seconds
Started Apr 16 02:07:00 PM PDT 24
Finished Apr 16 02:07:03 PM PDT 24
Peak memory 203776 kb
Host smart-85c8914c-0757-49b1-82e7-7f22fc95f0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934455565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2934455565
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4011330198
Short name T1421
Test name
Test status
Simulation time 260312189 ps
CPU time 2.05 seconds
Started Apr 16 02:06:58 PM PDT 24
Finished Apr 16 02:07:01 PM PDT 24
Peak memory 203760 kb
Host smart-42a437a6-5d45-4e1f-8e0b-1a5d9a185d88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011330198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.4011330198
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4268454477
Short name T1367
Test name
Test status
Simulation time 18955744 ps
CPU time 0.65 seconds
Started Apr 16 02:07:30 PM PDT 24
Finished Apr 16 02:07:32 PM PDT 24
Peak memory 203412 kb
Host smart-3567b502-7edf-4259-a969-e34edb859511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268454477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4268454477
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1271132734
Short name T1430
Test name
Test status
Simulation time 20174226 ps
CPU time 0.67 seconds
Started Apr 16 02:07:33 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203404 kb
Host smart-354cf437-8ffe-4668-b8f2-d1547c1e9cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271132734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1271132734
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.567166343
Short name T1440
Test name
Test status
Simulation time 48696218 ps
CPU time 0.65 seconds
Started Apr 16 02:07:31 PM PDT 24
Finished Apr 16 02:07:34 PM PDT 24
Peak memory 203400 kb
Host smart-44728aa0-351a-49d2-8e92-d354f91bd0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567166343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.567166343
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1878306072
Short name T1400
Test name
Test status
Simulation time 52159923 ps
CPU time 0.67 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203428 kb
Host smart-5db2857b-f6f4-4174-aa78-46dfd8830420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878306072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1878306072
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.365983177
Short name T1455
Test name
Test status
Simulation time 49305992 ps
CPU time 0.7 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203380 kb
Host smart-5e6f8256-a57a-400c-baa0-362d24072c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365983177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.365983177
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.340957241
Short name T1361
Test name
Test status
Simulation time 17733114 ps
CPU time 0.68 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203388 kb
Host smart-d48937b5-95a5-4483-89c6-1d0588851efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340957241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.340957241
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1550083039
Short name T1376
Test name
Test status
Simulation time 96077039 ps
CPU time 0.69 seconds
Started Apr 16 02:07:29 PM PDT 24
Finished Apr 16 02:07:31 PM PDT 24
Peak memory 203396 kb
Host smart-62bae92b-793d-47b6-8f22-2861554e46eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550083039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1550083039
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1425138105
Short name T1425
Test name
Test status
Simulation time 17241237 ps
CPU time 0.67 seconds
Started Apr 16 02:07:38 PM PDT 24
Finished Apr 16 02:07:40 PM PDT 24
Peak memory 202440 kb
Host smart-54c9b3f0-ce8b-49cb-9541-d4bc2f05fec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425138105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1425138105
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3706577275
Short name T1409
Test name
Test status
Simulation time 45587674 ps
CPU time 0.68 seconds
Started Apr 16 02:07:30 PM PDT 24
Finished Apr 16 02:07:32 PM PDT 24
Peak memory 203412 kb
Host smart-97966cb8-d142-490f-a801-1b461f713531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706577275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3706577275
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2720650424
Short name T1383
Test name
Test status
Simulation time 30734922 ps
CPU time 0.72 seconds
Started Apr 16 02:07:32 PM PDT 24
Finished Apr 16 02:07:35 PM PDT 24
Peak memory 203444 kb
Host smart-9fc6a9f0-6423-45aa-b8e1-87f43da6a38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720650424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2720650424
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1997963990
Short name T1381
Test name
Test status
Simulation time 74171349 ps
CPU time 1.09 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:08 PM PDT 24
Peak memory 203632 kb
Host smart-659d4d4b-e3d0-4cff-b7d8-a4c54075ded6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997963990 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1997963990
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1532373051
Short name T1392
Test name
Test status
Simulation time 23471576 ps
CPU time 0.69 seconds
Started Apr 16 02:07:05 PM PDT 24
Finished Apr 16 02:07:06 PM PDT 24
Peak memory 203532 kb
Host smart-b2daab91-7b84-48f1-93bd-d030b06a50fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532373051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1532373051
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.439715121
Short name T1377
Test name
Test status
Simulation time 23675629 ps
CPU time 0.64 seconds
Started Apr 16 02:07:04 PM PDT 24
Finished Apr 16 02:07:06 PM PDT 24
Peak memory 203440 kb
Host smart-f165432f-3f29-450d-9809-22d9df346832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439715121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.439715121
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.643132010
Short name T1442
Test name
Test status
Simulation time 236077709 ps
CPU time 1.11 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:08 PM PDT 24
Peak memory 203800 kb
Host smart-09fc1694-3aa8-4d9e-b536-be753420f06c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643132010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out
standing.643132010
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2741830273
Short name T166
Test name
Test status
Simulation time 263583407 ps
CPU time 2.52 seconds
Started Apr 16 02:07:09 PM PDT 24
Finished Apr 16 02:07:12 PM PDT 24
Peak memory 203736 kb
Host smart-32fb4fb0-c0df-4256-99d3-15a909b28d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741830273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2741830273
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2271864221
Short name T139
Test name
Test status
Simulation time 53659042 ps
CPU time 1.48 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:09 PM PDT 24
Peak memory 203828 kb
Host smart-b473ee8f-3788-483d-8998-831189a71cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271864221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2271864221
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3606492558
Short name T1370
Test name
Test status
Simulation time 189377599 ps
CPU time 0.8 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:07 PM PDT 24
Peak memory 203544 kb
Host smart-096acd1f-745c-43c0-9cfb-a52ca1c70976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606492558 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3606492558
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4210738676
Short name T1469
Test name
Test status
Simulation time 25385904 ps
CPU time 0.7 seconds
Started Apr 16 02:07:09 PM PDT 24
Finished Apr 16 02:07:10 PM PDT 24
Peak memory 203496 kb
Host smart-7eb959d3-c5a6-4244-96ab-51ca3a9b4c2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210738676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.4210738676
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3642858299
Short name T1368
Test name
Test status
Simulation time 17328207 ps
CPU time 0.65 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:08 PM PDT 24
Peak memory 203404 kb
Host smart-b2af72bb-b919-43af-9e8e-08ea1585e0c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642858299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3642858299
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3937193941
Short name T1464
Test name
Test status
Simulation time 89473012 ps
CPU time 1.11 seconds
Started Apr 16 02:07:09 PM PDT 24
Finished Apr 16 02:07:11 PM PDT 24
Peak memory 203840 kb
Host smart-b5654ff9-da71-47f9-823e-ca3984c533b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937193941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3937193941
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2707411849
Short name T130
Test name
Test status
Simulation time 88532647 ps
CPU time 1.45 seconds
Started Apr 16 02:07:09 PM PDT 24
Finished Apr 16 02:07:11 PM PDT 24
Peak memory 203716 kb
Host smart-8a0711fc-d977-43ee-a9ff-f160c3551940
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707411849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2707411849
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.900303783
Short name T218
Test name
Test status
Simulation time 251218131 ps
CPU time 1.42 seconds
Started Apr 16 02:07:05 PM PDT 24
Finished Apr 16 02:07:07 PM PDT 24
Peak memory 203808 kb
Host smart-27225693-fd1e-4ea0-8b7d-00c480ff1f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900303783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.900303783
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1828339688
Short name T1446
Test name
Test status
Simulation time 34225951 ps
CPU time 0.84 seconds
Started Apr 16 02:07:12 PM PDT 24
Finished Apr 16 02:07:13 PM PDT 24
Peak memory 203592 kb
Host smart-87ded7ca-50b0-42ac-ae6f-dd08d516a811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828339688 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1828339688
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2322468762
Short name T144
Test name
Test status
Simulation time 76544236 ps
CPU time 0.76 seconds
Started Apr 16 02:07:12 PM PDT 24
Finished Apr 16 02:07:13 PM PDT 24
Peak memory 203540 kb
Host smart-679435b9-d62c-443b-8094-4db093089c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322468762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2322468762
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.4238619348
Short name T1461
Test name
Test status
Simulation time 43970358 ps
CPU time 0.63 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:07 PM PDT 24
Peak memory 203468 kb
Host smart-9860bab2-7471-4758-a572-5f20e85da9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238619348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.4238619348
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1217173775
Short name T1435
Test name
Test status
Simulation time 385526532 ps
CPU time 1.12 seconds
Started Apr 16 02:07:13 PM PDT 24
Finished Apr 16 02:07:15 PM PDT 24
Peak memory 203808 kb
Host smart-76391edf-2fbc-4a29-9328-baf4d6246ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217173775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1217173775
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1876109741
Short name T1387
Test name
Test status
Simulation time 160663234 ps
CPU time 1.96 seconds
Started Apr 16 02:07:07 PM PDT 24
Finished Apr 16 02:07:09 PM PDT 24
Peak memory 203700 kb
Host smart-10c772f2-f170-4d2d-8f9e-18c92f5ea1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876109741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1876109741
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.202422016
Short name T1438
Test name
Test status
Simulation time 50594560 ps
CPU time 1.41 seconds
Started Apr 16 02:07:06 PM PDT 24
Finished Apr 16 02:07:08 PM PDT 24
Peak memory 203744 kb
Host smart-2872c710-db39-44ad-a4bd-af78fb95bd46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202422016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.202422016
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3089410868
Short name T1395
Test name
Test status
Simulation time 227799169 ps
CPU time 1.28 seconds
Started Apr 16 02:07:14 PM PDT 24
Finished Apr 16 02:07:16 PM PDT 24
Peak memory 203832 kb
Host smart-2bda5ee0-4496-40dd-9aed-96b62e5e017e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089410868 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3089410868
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2593201399
Short name T1459
Test name
Test status
Simulation time 16252042 ps
CPU time 0.69 seconds
Started Apr 16 02:07:13 PM PDT 24
Finished Apr 16 02:07:14 PM PDT 24
Peak memory 203576 kb
Host smart-203b6422-a2bb-4d01-9b84-62bf8ef88abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593201399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2593201399
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3507514089
Short name T1371
Test name
Test status
Simulation time 16823823 ps
CPU time 0.69 seconds
Started Apr 16 02:07:14 PM PDT 24
Finished Apr 16 02:07:16 PM PDT 24
Peak memory 203352 kb
Host smart-ce37fa8d-1f4c-4525-90fd-e3795cc2341a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507514089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3507514089
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.17307580
Short name T1434
Test name
Test status
Simulation time 121026546 ps
CPU time 0.83 seconds
Started Apr 16 02:07:14 PM PDT 24
Finished Apr 16 02:07:15 PM PDT 24
Peak memory 203448 kb
Host smart-a88f24d6-ec32-4526-b5b4-6078a5700358
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17307580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outs
tanding.17307580
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3459526721
Short name T1463
Test name
Test status
Simulation time 72501063 ps
CPU time 1.12 seconds
Started Apr 16 02:07:13 PM PDT 24
Finished Apr 16 02:07:15 PM PDT 24
Peak memory 203744 kb
Host smart-9d7a06eb-a955-4bed-8a59-a36e0c92cc2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459526721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3459526721
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.646223363
Short name T1375
Test name
Test status
Simulation time 451792984 ps
CPU time 1.34 seconds
Started Apr 16 02:07:14 PM PDT 24
Finished Apr 16 02:07:16 PM PDT 24
Peak memory 203784 kb
Host smart-47c673af-75bb-4e09-9c8d-38ca3a20c701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646223363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.646223363
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.143760872
Short name T80
Test name
Test status
Simulation time 79808708 ps
CPU time 0.89 seconds
Started Apr 16 02:07:12 PM PDT 24
Finished Apr 16 02:07:14 PM PDT 24
Peak memory 203584 kb
Host smart-ac1f1e4e-7b92-4377-8f90-7971f73bed95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143760872 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.143760872
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.48085531
Short name T1441
Test name
Test status
Simulation time 46345669 ps
CPU time 0.67 seconds
Started Apr 16 02:07:14 PM PDT 24
Finished Apr 16 02:07:15 PM PDT 24
Peak memory 203368 kb
Host smart-d493f30f-b5f6-4f4f-a2c6-f4460ca2311b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48085531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.48085531
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1944340355
Short name T1390
Test name
Test status
Simulation time 59504250 ps
CPU time 0.71 seconds
Started Apr 16 02:07:14 PM PDT 24
Finished Apr 16 02:07:16 PM PDT 24
Peak memory 203440 kb
Host smart-ec38c06d-b1c9-4966-89bd-29ee6a416e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944340355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1944340355
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1061319272
Short name T1453
Test name
Test status
Simulation time 101776753 ps
CPU time 1.23 seconds
Started Apr 16 02:07:14 PM PDT 24
Finished Apr 16 02:07:16 PM PDT 24
Peak memory 203700 kb
Host smart-e86088ad-d020-4d6f-86c7-d0df21985828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061319272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.1061319272
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.83411235
Short name T1382
Test name
Test status
Simulation time 35608262 ps
CPU time 1.5 seconds
Started Apr 16 02:07:15 PM PDT 24
Finished Apr 16 02:07:17 PM PDT 24
Peak memory 203648 kb
Host smart-aa2e372b-8a5b-4698-ae4b-a369f3efc428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83411235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.83411235
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3677975101
Short name T1466
Test name
Test status
Simulation time 51025044 ps
CPU time 1.42 seconds
Started Apr 16 02:07:11 PM PDT 24
Finished Apr 16 02:07:13 PM PDT 24
Peak memory 203796 kb
Host smart-ea4b4eba-efd6-4afe-a330-e7ff8ee74e53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677975101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3677975101
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3834796605
Short name T591
Test name
Test status
Simulation time 40940213 ps
CPU time 0.63 seconds
Started Apr 16 02:31:28 PM PDT 24
Finished Apr 16 02:31:29 PM PDT 24
Peak memory 203592 kb
Host smart-c376b293-8373-4cf9-9209-ed25d352e5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834796605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3834796605
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2828186451
Short name T628
Test name
Test status
Simulation time 229928198 ps
CPU time 1.42 seconds
Started Apr 16 02:31:24 PM PDT 24
Finished Apr 16 02:31:26 PM PDT 24
Peak memory 212292 kb
Host smart-34e8cba8-b25e-4a91-ad3e-ff5b2bbe7497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828186451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2828186451
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2380339951
Short name T1331
Test name
Test status
Simulation time 274594893 ps
CPU time 4.47 seconds
Started Apr 16 02:31:21 PM PDT 24
Finished Apr 16 02:31:26 PM PDT 24
Peak memory 248056 kb
Host smart-6d20c1f0-05d2-4c0c-9dd5-d2f88295e4fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380339951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2380339951
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.4026988447
Short name T968
Test name
Test status
Simulation time 2352589801 ps
CPU time 84.56 seconds
Started Apr 16 02:31:19 PM PDT 24
Finished Apr 16 02:32:45 PM PDT 24
Peak memory 769872 kb
Host smart-b067c836-55ec-4513-bd51-1445aff606a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026988447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.4026988447
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.402821312
Short name T856
Test name
Test status
Simulation time 5752940390 ps
CPU time 47.05 seconds
Started Apr 16 02:31:18 PM PDT 24
Finished Apr 16 02:32:06 PM PDT 24
Peak memory 561052 kb
Host smart-684193dc-ac53-4153-9e49-4d96776e6eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402821312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.402821312
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.488079277
Short name T966
Test name
Test status
Simulation time 215693353 ps
CPU time 2.26 seconds
Started Apr 16 02:31:19 PM PDT 24
Finished Apr 16 02:31:22 PM PDT 24
Peak memory 203912 kb
Host smart-175de2bb-a703-41e6-bdbf-a289a9e9e4c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488079277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.488079277
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2717388078
Short name T760
Test name
Test status
Simulation time 10691187575 ps
CPU time 65.26 seconds
Started Apr 16 02:31:20 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 759616 kb
Host smart-40446469-a966-4604-9ff6-13a1db18c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717388078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2717388078
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3554240639
Short name T312
Test name
Test status
Simulation time 23462157370 ps
CPU time 76.6 seconds
Started Apr 16 02:31:25 PM PDT 24
Finished Apr 16 02:32:42 PM PDT 24
Peak memory 347772 kb
Host smart-c136cdf0-0412-497c-9181-b91f4c84a063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554240639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3554240639
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.944722898
Short name T705
Test name
Test status
Simulation time 24919943 ps
CPU time 0.68 seconds
Started Apr 16 02:31:19 PM PDT 24
Finished Apr 16 02:31:21 PM PDT 24
Peak memory 203668 kb
Host smart-cc635c5c-c0af-47a2-8246-9ec5143e1b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944722898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.944722898
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1908573733
Short name T870
Test name
Test status
Simulation time 75485073962 ps
CPU time 1397.34 seconds
Started Apr 16 02:31:21 PM PDT 24
Finished Apr 16 02:54:39 PM PDT 24
Peak memory 203932 kb
Host smart-e4bba4d2-6d7b-4388-abb5-5d72a24f3b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908573733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1908573733
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1330624679
Short name T545
Test name
Test status
Simulation time 5067708492 ps
CPU time 59.53 seconds
Started Apr 16 02:31:23 PM PDT 24
Finished Apr 16 02:32:23 PM PDT 24
Peak memory 308436 kb
Host smart-2e8c2397-3a70-4a5d-960e-6963ca16a32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330624679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1330624679
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.1201722749
Short name T204
Test name
Test status
Simulation time 84266128138 ps
CPU time 2740.57 seconds
Started Apr 16 02:31:19 PM PDT 24
Finished Apr 16 03:17:01 PM PDT 24
Peak memory 2002720 kb
Host smart-48beb0cd-fa97-4939-a433-a78e92e2a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201722749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1201722749
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.3140523200
Short name T1022
Test name
Test status
Simulation time 6029689646 ps
CPU time 16.75 seconds
Started Apr 16 02:31:23 PM PDT 24
Finished Apr 16 02:31:40 PM PDT 24
Peak memory 212264 kb
Host smart-1f84fd9b-6e51-4851-bff0-9366bbb349be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140523200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3140523200
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1913926215
Short name T112
Test name
Test status
Simulation time 62925168 ps
CPU time 0.93 seconds
Started Apr 16 02:31:27 PM PDT 24
Finished Apr 16 02:31:29 PM PDT 24
Peak memory 222164 kb
Host smart-5a3c52b5-ea11-4aff-85f7-361f1b125213
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913926215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1913926215
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1460259759
Short name T584
Test name
Test status
Simulation time 832607229 ps
CPU time 3.95 seconds
Started Apr 16 02:31:24 PM PDT 24
Finished Apr 16 02:31:28 PM PDT 24
Peak memory 212232 kb
Host smart-633b7e29-5d54-4862-b1bb-e8d01ee0ba19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460259759 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1460259759
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3776286336
Short name T421
Test name
Test status
Simulation time 10134350018 ps
CPU time 66.01 seconds
Started Apr 16 02:31:19 PM PDT 24
Finished Apr 16 02:32:25 PM PDT 24
Peak memory 530896 kb
Host smart-b5677745-e389-4d55-bb98-7f077640ffaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776286336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3776286336
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1789838987
Short name T1253
Test name
Test status
Simulation time 10044342654 ps
CPU time 75.98 seconds
Started Apr 16 02:31:19 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 582084 kb
Host smart-2ef3deda-e3ca-4cca-87ef-2b1329427853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789838987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1789838987
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1653939709
Short name T23
Test name
Test status
Simulation time 1806967660 ps
CPU time 8.66 seconds
Started Apr 16 02:31:20 PM PDT 24
Finished Apr 16 02:31:29 PM PDT 24
Peak memory 204112 kb
Host smart-5ca5ea78-0757-4226-829f-8f72473db49f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653939709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1653939709
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2362022523
Short name T292
Test name
Test status
Simulation time 978067427 ps
CPU time 4.74 seconds
Started Apr 16 02:31:24 PM PDT 24
Finished Apr 16 02:31:29 PM PDT 24
Peak memory 203988 kb
Host smart-e56a492d-dc30-434f-a4b7-b91412a1a1df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362022523 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2362022523
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1316530332
Short name T1352
Test name
Test status
Simulation time 6816685427 ps
CPU time 14.63 seconds
Started Apr 16 02:31:21 PM PDT 24
Finished Apr 16 02:31:36 PM PDT 24
Peak memory 204052 kb
Host smart-512bbe79-fd4f-4f70-ae30-6f2ff0672233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316530332 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1316530332
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.320128618
Short name T935
Test name
Test status
Simulation time 1671688863 ps
CPU time 31.51 seconds
Started Apr 16 02:31:20 PM PDT 24
Finished Apr 16 02:31:53 PM PDT 24
Peak memory 203956 kb
Host smart-d8e0a88e-85ea-484f-a48a-c45f592df78a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320128618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.320128618
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3570595919
Short name T914
Test name
Test status
Simulation time 2013682605 ps
CPU time 28.98 seconds
Started Apr 16 02:31:26 PM PDT 24
Finished Apr 16 02:31:56 PM PDT 24
Peak memory 234728 kb
Host smart-5f437101-2e7c-4265-a6af-5f9df8f46b56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570595919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3570595919
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2306548671
Short name T1112
Test name
Test status
Simulation time 9922034859 ps
CPU time 18.81 seconds
Started Apr 16 02:31:25 PM PDT 24
Finished Apr 16 02:31:44 PM PDT 24
Peak memory 204016 kb
Host smart-12abf5e7-6564-4633-995a-0ddee1a27707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306548671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2306548671
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.145100810
Short name T262
Test name
Test status
Simulation time 19513735199 ps
CPU time 922.9 seconds
Started Apr 16 02:31:25 PM PDT 24
Finished Apr 16 02:46:49 PM PDT 24
Peak memory 2308736 kb
Host smart-d65c4d86-8e62-421b-a802-294c1fa052db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145100810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.145100810
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.621894782
Short name T470
Test name
Test status
Simulation time 2058977095 ps
CPU time 7.24 seconds
Started Apr 16 02:31:20 PM PDT 24
Finished Apr 16 02:31:28 PM PDT 24
Peak memory 217616 kb
Host smart-e15a0252-53d6-413e-b655-fb990ffaa9ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621894782 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.621894782
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.28757225
Short name T727
Test name
Test status
Simulation time 64748632 ps
CPU time 0.62 seconds
Started Apr 16 02:31:40 PM PDT 24
Finished Apr 16 02:31:42 PM PDT 24
Peak memory 203520 kb
Host smart-764f0898-024d-4e5e-b09d-184e7631a624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28757225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.28757225
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2924658101
Short name T890
Test name
Test status
Simulation time 278716889 ps
CPU time 1.13 seconds
Started Apr 16 02:31:29 PM PDT 24
Finished Apr 16 02:31:31 PM PDT 24
Peak memory 204064 kb
Host smart-dd27bf0d-8b16-4450-b1f1-ce0c7852008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924658101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2924658101
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.459255825
Short name T1118
Test name
Test status
Simulation time 636717843 ps
CPU time 7.95 seconds
Started Apr 16 02:31:29 PM PDT 24
Finished Apr 16 02:31:37 PM PDT 24
Peak memory 220640 kb
Host smart-4cd8c0b2-133e-4bed-9819-d61ca1ffba94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459255825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.459255825
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3005249712
Short name T82
Test name
Test status
Simulation time 3220194893 ps
CPU time 41.84 seconds
Started Apr 16 02:31:34 PM PDT 24
Finished Apr 16 02:32:16 PM PDT 24
Peak memory 435628 kb
Host smart-f20b6738-a660-47b0-a256-0d46ee79d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005249712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3005249712
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.23055048
Short name T202
Test name
Test status
Simulation time 1706847650 ps
CPU time 119.23 seconds
Started Apr 16 02:31:23 PM PDT 24
Finished Apr 16 02:33:23 PM PDT 24
Peak memory 606404 kb
Host smart-1bce52a5-98ae-4882-9041-4fed21aca90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23055048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.23055048
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.971895122
Short name T888
Test name
Test status
Simulation time 724221696 ps
CPU time 6.38 seconds
Started Apr 16 02:31:35 PM PDT 24
Finished Apr 16 02:31:42 PM PDT 24
Peak memory 220688 kb
Host smart-19c6143d-a988-4147-a622-616975fbd3e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971895122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.971895122
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2299834101
Short name T171
Test name
Test status
Simulation time 4292505493 ps
CPU time 111.86 seconds
Started Apr 16 02:31:23 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 1250536 kb
Host smart-9dac8688-8cc5-4625-bd0a-5149f745814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299834101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2299834101
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1041054728
Short name T554
Test name
Test status
Simulation time 1238465692 ps
CPU time 4.44 seconds
Started Apr 16 02:31:40 PM PDT 24
Finished Apr 16 02:31:45 PM PDT 24
Peak memory 203896 kb
Host smart-7c2dba4a-8198-4337-98c2-d5448ae8b7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041054728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1041054728
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1427935549
Short name T419
Test name
Test status
Simulation time 6335486166 ps
CPU time 72.68 seconds
Started Apr 16 02:31:41 PM PDT 24
Finished Apr 16 02:32:54 PM PDT 24
Peak memory 319528 kb
Host smart-9830e476-0511-4e7f-8d68-b2a6446cc9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427935549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1427935549
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.505278675
Short name T97
Test name
Test status
Simulation time 28862573 ps
CPU time 0.63 seconds
Started Apr 16 02:31:23 PM PDT 24
Finished Apr 16 02:31:24 PM PDT 24
Peak memory 203652 kb
Host smart-939ca2c5-25dc-4de9-ad9d-da810bb714f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505278675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.505278675
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1208852768
Short name T1202
Test name
Test status
Simulation time 7495896153 ps
CPU time 76.4 seconds
Started Apr 16 02:31:33 PM PDT 24
Finished Apr 16 02:32:50 PM PDT 24
Peak memory 228572 kb
Host smart-fb6f1b3d-ea41-48ca-9284-015883980e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208852768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1208852768
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2307614418
Short name T328
Test name
Test status
Simulation time 1660003202 ps
CPU time 29.21 seconds
Started Apr 16 02:31:26 PM PDT 24
Finished Apr 16 02:31:56 PM PDT 24
Peak memory 400308 kb
Host smart-87696439-d10b-4ebe-82e6-67a0ca32cc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307614418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2307614418
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1231026990
Short name T693
Test name
Test status
Simulation time 20303178517 ps
CPU time 124.46 seconds
Started Apr 16 02:31:32 PM PDT 24
Finished Apr 16 02:33:37 PM PDT 24
Peak memory 865980 kb
Host smart-5ef71b19-064c-44c3-88ba-dd21e7fe5c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231026990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1231026990
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1737112034
Short name T420
Test name
Test status
Simulation time 1651506784 ps
CPU time 15.45 seconds
Started Apr 16 02:31:28 PM PDT 24
Finished Apr 16 02:31:44 PM PDT 24
Peak memory 220420 kb
Host smart-d1b05aba-ebd6-44d7-9f3a-75d67eb57c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737112034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1737112034
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2870500617
Short name T784
Test name
Test status
Simulation time 4559545720 ps
CPU time 4.73 seconds
Started Apr 16 02:31:37 PM PDT 24
Finished Apr 16 02:31:43 PM PDT 24
Peak memory 212276 kb
Host smart-0f56d8bf-dc5b-4766-bfd8-532269efd93a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870500617 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2870500617
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1985548585
Short name T362
Test name
Test status
Simulation time 10228427637 ps
CPU time 8.85 seconds
Started Apr 16 02:31:34 PM PDT 24
Finished Apr 16 02:31:43 PM PDT 24
Peak memory 244740 kb
Host smart-85d23d80-d088-4106-8b78-289cdaaf667e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985548585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1985548585
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.342907486
Short name T122
Test name
Test status
Simulation time 10048823164 ps
CPU time 77.92 seconds
Started Apr 16 02:31:35 PM PDT 24
Finished Apr 16 02:32:54 PM PDT 24
Peak memory 567312 kb
Host smart-8d1436cb-c1ab-4ae3-b3e0-6f2307b6dae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342907486 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.342907486
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2628358758
Short name T946
Test name
Test status
Simulation time 593792714 ps
CPU time 3.2 seconds
Started Apr 16 02:31:37 PM PDT 24
Finished Apr 16 02:31:41 PM PDT 24
Peak memory 204004 kb
Host smart-644c8dee-e1d5-42df-9d4c-c7cd3058a4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628358758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2628358758
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3667424283
Short name T33
Test name
Test status
Simulation time 2034682330 ps
CPU time 5.06 seconds
Started Apr 16 02:31:38 PM PDT 24
Finished Apr 16 02:31:43 PM PDT 24
Peak memory 220024 kb
Host smart-6294b065-e6dd-408e-994b-83e68ddfa977
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667424283 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3667424283
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.225959563
Short name T314
Test name
Test status
Simulation time 2731703974 ps
CPU time 2.13 seconds
Started Apr 16 02:31:33 PM PDT 24
Finished Apr 16 02:31:36 PM PDT 24
Peak memory 204048 kb
Host smart-c1898b15-7eb2-4c2a-b8cd-b479f3b6af2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225959563 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.225959563
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1089412249
Short name T1236
Test name
Test status
Simulation time 1024866260 ps
CPU time 26.29 seconds
Started Apr 16 02:31:31 PM PDT 24
Finished Apr 16 02:31:58 PM PDT 24
Peak memory 204004 kb
Host smart-059ee083-3322-4a29-b411-8833ab4edf76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089412249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1089412249
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2789155925
Short name T1007
Test name
Test status
Simulation time 318642212 ps
CPU time 12.43 seconds
Started Apr 16 02:31:33 PM PDT 24
Finished Apr 16 02:31:46 PM PDT 24
Peak memory 204004 kb
Host smart-e7dd1966-93d8-440a-8521-abf365d73908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789155925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2789155925
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3592760058
Short name T769
Test name
Test status
Simulation time 15643806667 ps
CPU time 31.7 seconds
Started Apr 16 02:31:32 PM PDT 24
Finished Apr 16 02:32:04 PM PDT 24
Peak memory 204036 kb
Host smart-f4c67192-3841-473c-b8cd-58823580fe9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592760058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3592760058
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.4130726341
Short name T1077
Test name
Test status
Simulation time 33580519085 ps
CPU time 286.48 seconds
Started Apr 16 02:31:30 PM PDT 24
Finished Apr 16 02:36:17 PM PDT 24
Peak memory 2027504 kb
Host smart-f8d1dd63-13c9-4da0-ad8d-760a1e7cf8bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130726341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.4130726341
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1348277954
Short name T11
Test name
Test status
Simulation time 10064201162 ps
CPU time 7.15 seconds
Started Apr 16 02:31:34 PM PDT 24
Finished Apr 16 02:31:42 PM PDT 24
Peak memory 210660 kb
Host smart-1c932fe0-bd91-4954-a9a3-d9bfd2d74b0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348277954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1348277954
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2609925935
Short name T623
Test name
Test status
Simulation time 16179848 ps
CPU time 0.66 seconds
Started Apr 16 02:32:42 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 203572 kb
Host smart-dc08bdb7-61b3-4eaf-aaaf-0fccbdf40fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609925935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2609925935
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2563761209
Short name T579
Test name
Test status
Simulation time 429308576 ps
CPU time 1.62 seconds
Started Apr 16 02:32:39 PM PDT 24
Finished Apr 16 02:32:41 PM PDT 24
Peak memory 220440 kb
Host smart-bdbf9b74-5e74-4ed7-922d-42880ac8fbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563761209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2563761209
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1748460640
Short name T274
Test name
Test status
Simulation time 1101127897 ps
CPU time 5.7 seconds
Started Apr 16 02:32:40 PM PDT 24
Finished Apr 16 02:32:47 PM PDT 24
Peak memory 263708 kb
Host smart-74ada9be-5915-4869-9e4f-d075a60240a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748460640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1748460640
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3528975817
Short name T848
Test name
Test status
Simulation time 1220663933 ps
CPU time 36.41 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:33:18 PM PDT 24
Peak memory 428892 kb
Host smart-607adfdb-f5b9-449b-80fe-bff7b2654fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528975817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3528975817
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.580202673
Short name T949
Test name
Test status
Simulation time 7033999701 ps
CPU time 119.81 seconds
Started Apr 16 02:32:39 PM PDT 24
Finished Apr 16 02:34:40 PM PDT 24
Peak memory 566928 kb
Host smart-d3140ef0-c77c-4d96-ab44-64973e1dbe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580202673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.580202673
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1287608884
Short name T1095
Test name
Test status
Simulation time 147688746 ps
CPU time 1.08 seconds
Started Apr 16 02:32:40 PM PDT 24
Finished Apr 16 02:32:42 PM PDT 24
Peak memory 203924 kb
Host smart-c4a75161-b665-42b9-b2ba-bca1c29ec101
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287608884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1287608884
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1548063802
Short name T857
Test name
Test status
Simulation time 843441520 ps
CPU time 6.65 seconds
Started Apr 16 02:32:40 PM PDT 24
Finished Apr 16 02:32:47 PM PDT 24
Peak memory 222252 kb
Host smart-0ccbe927-9081-4a7c-a1de-194220745022
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548063802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1548063802
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3041502131
Short name T1247
Test name
Test status
Simulation time 3806808934 ps
CPU time 283.54 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:37:25 PM PDT 24
Peak memory 1076000 kb
Host smart-a113cbb2-a201-4ade-8178-2605b0698db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041502131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3041502131
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2142665115
Short name T413
Test name
Test status
Simulation time 287675764 ps
CPU time 4.36 seconds
Started Apr 16 02:32:45 PM PDT 24
Finished Apr 16 02:32:50 PM PDT 24
Peak memory 203968 kb
Host smart-d0cd2ca8-dead-4db0-96a4-374f299a01b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142665115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2142665115
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3985162412
Short name T381
Test name
Test status
Simulation time 2077279487 ps
CPU time 38.25 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:33:23 PM PDT 24
Peak memory 444544 kb
Host smart-d5db9093-e7c4-4dc5-bdd1-63cc68519919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985162412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3985162412
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1244554401
Short name T315
Test name
Test status
Simulation time 24781148 ps
CPU time 0.65 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:32:43 PM PDT 24
Peak memory 203684 kb
Host smart-4f4facb8-d96e-46a0-9af5-8526233817ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244554401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1244554401
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3158931729
Short name T1064
Test name
Test status
Simulation time 3103786128 ps
CPU time 9.47 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:32:51 PM PDT 24
Peak memory 220368 kb
Host smart-bd4c4f04-0743-497f-9502-342c19e44921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158931729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3158931729
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3335028697
Short name T350
Test name
Test status
Simulation time 1593606331 ps
CPU time 75.03 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:33:57 PM PDT 24
Peak memory 332512 kb
Host smart-e5f9f430-eb3c-495e-8e63-542ad7f3e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335028697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3335028697
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1991254834
Short name T571
Test name
Test status
Simulation time 30029445415 ps
CPU time 1002.12 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:49:24 PM PDT 24
Peak memory 3147120 kb
Host smart-07b72ee3-b7cf-49b5-9c05-5de644457a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991254834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1991254834
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.639594865
Short name T782
Test name
Test status
Simulation time 406906312 ps
CPU time 19.43 seconds
Started Apr 16 02:32:40 PM PDT 24
Finished Apr 16 02:33:00 PM PDT 24
Peak memory 212148 kb
Host smart-70d9aeb1-39d4-4303-9bec-e610b52da947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639594865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.639594865
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.271063956
Short name T650
Test name
Test status
Simulation time 1070449069 ps
CPU time 4.47 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:32:54 PM PDT 24
Peak memory 204004 kb
Host smart-25ee912a-9d04-45b8-b4e8-a479e594d0fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271063956 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.271063956
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2435456644
Short name T649
Test name
Test status
Simulation time 10111274157 ps
CPU time 37.27 seconds
Started Apr 16 02:32:42 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 374960 kb
Host smart-391b02a9-f651-4d5c-83e6-a51d3c0dba27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435456644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2435456644
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3678629051
Short name T515
Test name
Test status
Simulation time 10030390955 ps
CPU time 47.54 seconds
Started Apr 16 02:32:45 PM PDT 24
Finished Apr 16 02:33:33 PM PDT 24
Peak memory 490512 kb
Host smart-33764f64-a52a-4204-bc7e-df7f5cb2e9e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678629051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3678629051
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3700668968
Short name T27
Test name
Test status
Simulation time 844917603 ps
CPU time 2.24 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:32:48 PM PDT 24
Peak memory 203944 kb
Host smart-16422ffd-a7cd-4319-9f02-c31b0e995958
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700668968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3700668968
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2992295191
Short name T305
Test name
Test status
Simulation time 1560012728 ps
CPU time 7.01 seconds
Started Apr 16 02:32:47 PM PDT 24
Finished Apr 16 02:32:54 PM PDT 24
Peak memory 211608 kb
Host smart-9fa00aed-cc86-41b9-ba25-f80ffcadff03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992295191 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2992295191
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.227057067
Short name T653
Test name
Test status
Simulation time 13092606589 ps
CPU time 86.07 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:34:11 PM PDT 24
Peak memory 1477260 kb
Host smart-459947dd-0e62-4844-b936-91d624f721c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227057067 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.227057067
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1509176020
Short name T879
Test name
Test status
Simulation time 9155729491 ps
CPU time 13.96 seconds
Started Apr 16 02:32:38 PM PDT 24
Finished Apr 16 02:32:53 PM PDT 24
Peak memory 203980 kb
Host smart-cbad92c9-02f3-42ac-a255-257a45c33a7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509176020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1509176020
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3623439046
Short name T563
Test name
Test status
Simulation time 16314202931 ps
CPU time 31.38 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 204068 kb
Host smart-3b32915d-6d7a-4cc9-890b-790aad1529c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623439046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3623439046
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1628622777
Short name T401
Test name
Test status
Simulation time 1119333588 ps
CPU time 6.33 seconds
Started Apr 16 02:32:50 PM PDT 24
Finished Apr 16 02:32:57 PM PDT 24
Peak memory 208412 kb
Host smart-86675806-e2c2-4d06-9176-19ec177c6425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628622777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1628622777
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.287650274
Short name T525
Test name
Test status
Simulation time 71815714 ps
CPU time 1.31 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:32:46 PM PDT 24
Peak memory 212276 kb
Host smart-4eb837fe-5ba7-4583-8b0f-3dad054d3d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287650274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.287650274
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1129261996
Short name T176
Test name
Test status
Simulation time 1855907261 ps
CPU time 9.2 seconds
Started Apr 16 02:32:50 PM PDT 24
Finished Apr 16 02:33:00 PM PDT 24
Peak memory 289792 kb
Host smart-797073d8-0f99-4a45-b083-2a8a40482ca4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129261996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1129261996
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.4243399021
Short name T871
Test name
Test status
Simulation time 1781921413 ps
CPU time 111.97 seconds
Started Apr 16 02:32:42 PM PDT 24
Finished Apr 16 02:34:35 PM PDT 24
Peak memory 534436 kb
Host smart-1ed92ccf-9843-48e1-bc2b-79015a25d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243399021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.4243399021
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.907855467
Short name T1000
Test name
Test status
Simulation time 9495565349 ps
CPU time 62.14 seconds
Started Apr 16 02:32:46 PM PDT 24
Finished Apr 16 02:33:49 PM PDT 24
Peak memory 629868 kb
Host smart-703d4162-2e00-4c4c-a31c-dbc8ba18f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907855467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.907855467
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3530214721
Short name T923
Test name
Test status
Simulation time 518798022 ps
CPU time 1.06 seconds
Started Apr 16 02:32:49 PM PDT 24
Finished Apr 16 02:32:51 PM PDT 24
Peak memory 203912 kb
Host smart-c7a55e3b-49ef-42e2-83e0-2eb310b06a92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530214721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3530214721
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.866108102
Short name T687
Test name
Test status
Simulation time 527523698 ps
CPU time 7.64 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:32:57 PM PDT 24
Peak memory 226676 kb
Host smart-12c12904-9e02-44a0-a7d0-2d71513ca317
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866108102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
866108102
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.103817708
Short name T1311
Test name
Test status
Simulation time 2118389689 ps
CPU time 22.17 seconds
Started Apr 16 02:32:50 PM PDT 24
Finished Apr 16 02:33:13 PM PDT 24
Peak memory 203924 kb
Host smart-ba59a90e-ae44-47be-b34d-800300e0262e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103817708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.103817708
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.419705547
Short name T1217
Test name
Test status
Simulation time 7683894043 ps
CPU time 16.32 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 299028 kb
Host smart-df9e09a0-04ee-4c06-b2c5-b47b9fb08693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419705547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.419705547
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.1051864745
Short name T740
Test name
Test status
Simulation time 27624560 ps
CPU time 0.69 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:32:46 PM PDT 24
Peak memory 203624 kb
Host smart-85c64080-c17f-4b0b-96de-f1775e2a230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051864745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1051864745
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1791615930
Short name T697
Test name
Test status
Simulation time 3542012444 ps
CPU time 38.08 seconds
Started Apr 16 02:32:45 PM PDT 24
Finished Apr 16 02:33:24 PM PDT 24
Peak memory 204036 kb
Host smart-ef9dccb0-07a3-4a2e-a4a5-52cbfcf54f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791615930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1791615930
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.4286463387
Short name T2
Test name
Test status
Simulation time 1678889463 ps
CPU time 27.85 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:33:17 PM PDT 24
Peak memory 365848 kb
Host smart-a0db33a9-0787-4768-ab34-44df50f4ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286463387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.4286463387
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3830829224
Short name T1320
Test name
Test status
Simulation time 648114453 ps
CPU time 12.79 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:32:57 PM PDT 24
Peak memory 220400 kb
Host smart-4ef25a75-d7c6-4e2d-9e1c-e0b3b2402b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830829224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3830829224
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3879987355
Short name T483
Test name
Test status
Simulation time 1106264710 ps
CPU time 4.68 seconds
Started Apr 16 02:32:49 PM PDT 24
Finished Apr 16 02:32:54 PM PDT 24
Peak memory 204040 kb
Host smart-745c3b27-6b37-41ae-9796-e2ab39322bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879987355 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3879987355
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.4160465117
Short name T490
Test name
Test status
Simulation time 10055099356 ps
CPU time 73.23 seconds
Started Apr 16 02:32:46 PM PDT 24
Finished Apr 16 02:34:00 PM PDT 24
Peak memory 541172 kb
Host smart-a271e04d-a882-4690-b009-43b08f29fc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160465117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.4160465117
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3826372844
Short name T100
Test name
Test status
Simulation time 10182778717 ps
CPU time 15.82 seconds
Started Apr 16 02:32:45 PM PDT 24
Finished Apr 16 02:33:01 PM PDT 24
Peak memory 296828 kb
Host smart-65ff144e-d7c4-47ee-8881-cd97d044c906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826372844 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3826372844
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2755699820
Short name T811
Test name
Test status
Simulation time 638083456 ps
CPU time 3.63 seconds
Started Apr 16 02:32:46 PM PDT 24
Finished Apr 16 02:32:50 PM PDT 24
Peak memory 205164 kb
Host smart-d021d4eb-f0bc-43d6-9e4d-93fb5c078d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755699820 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2755699820
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1801278057
Short name T626
Test name
Test status
Simulation time 6385064129 ps
CPU time 13.67 seconds
Started Apr 16 02:32:50 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 203996 kb
Host smart-0b88ef00-236f-4288-bc43-69ba058930db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801278057 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1801278057
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3737404427
Short name T788
Test name
Test status
Simulation time 1128753893 ps
CPU time 18.02 seconds
Started Apr 16 02:32:47 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 203972 kb
Host smart-4cfb74f7-f801-4b36-be2b-02f787c514ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737404427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3737404427
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2025314162
Short name T1255
Test name
Test status
Simulation time 3073037866 ps
CPU time 31.56 seconds
Started Apr 16 02:32:44 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 204088 kb
Host smart-321c273f-f986-430a-994f-8c0b14988acd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025314162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2025314162
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1287909322
Short name T820
Test name
Test status
Simulation time 37606597751 ps
CPU time 71.42 seconds
Started Apr 16 02:32:47 PM PDT 24
Finished Apr 16 02:33:59 PM PDT 24
Peak memory 1179020 kb
Host smart-53300f68-910e-4c8c-bf8a-6a2b0cf552d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287909322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1287909322
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2285565443
Short name T558
Test name
Test status
Simulation time 16908788221 ps
CPU time 6.63 seconds
Started Apr 16 02:32:50 PM PDT 24
Finished Apr 16 02:32:57 PM PDT 24
Peak memory 220244 kb
Host smart-fc1178b9-c549-4151-88a0-c680939e89f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285565443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2285565443
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3397971553
Short name T1088
Test name
Test status
Simulation time 18965491 ps
CPU time 0.64 seconds
Started Apr 16 02:32:54 PM PDT 24
Finished Apr 16 02:32:55 PM PDT 24
Peak memory 203580 kb
Host smart-b39e48fd-07e4-4a7c-9a13-52eab6f007d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397971553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3397971553
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3170522121
Short name T510
Test name
Test status
Simulation time 213080632 ps
CPU time 1.29 seconds
Started Apr 16 02:32:49 PM PDT 24
Finished Apr 16 02:32:51 PM PDT 24
Peak memory 212300 kb
Host smart-3ac4eaf3-0e2b-4d1c-9d5b-c17efa73ef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170522121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3170522121
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2072230898
Short name T695
Test name
Test status
Simulation time 192189734 ps
CPU time 8.78 seconds
Started Apr 16 02:32:51 PM PDT 24
Finished Apr 16 02:33:01 PM PDT 24
Peak memory 237264 kb
Host smart-d482d00c-96e1-4853-a73d-3f02298f452f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072230898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2072230898
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.537651580
Short name T460
Test name
Test status
Simulation time 1226274991 ps
CPU time 29.79 seconds
Started Apr 16 02:32:52 PM PDT 24
Finished Apr 16 02:33:22 PM PDT 24
Peak memory 426900 kb
Host smart-24e63ee8-132f-431e-8099-997c00b41c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537651580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.537651580
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.4173898890
Short name T535
Test name
Test status
Simulation time 4137988634 ps
CPU time 36.59 seconds
Started Apr 16 02:32:51 PM PDT 24
Finished Apr 16 02:33:29 PM PDT 24
Peak memory 491348 kb
Host smart-c0b00867-d025-4b09-be30-802dab4569a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173898890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4173898890
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3267608511
Short name T1100
Test name
Test status
Simulation time 541495646 ps
CPU time 0.92 seconds
Started Apr 16 02:32:49 PM PDT 24
Finished Apr 16 02:32:51 PM PDT 24
Peak memory 203724 kb
Host smart-7bc6a80f-c9a3-4e9f-b375-6b233f279081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267608511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3267608511
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.421179131
Short name T639
Test name
Test status
Simulation time 211354215 ps
CPU time 6.34 seconds
Started Apr 16 02:32:51 PM PDT 24
Finished Apr 16 02:32:58 PM PDT 24
Peak memory 221200 kb
Host smart-a4db2722-3aaa-4b13-9b0d-6ff4b0b809ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421179131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.
421179131
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.86726357
Short name T1012
Test name
Test status
Simulation time 3502846134 ps
CPU time 225.5 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:36:35 PM PDT 24
Peak memory 995796 kb
Host smart-16525344-fc61-4926-9359-1db8b7dcb35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86726357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.86726357
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1764743378
Short name T73
Test name
Test status
Simulation time 11105794584 ps
CPU time 7.06 seconds
Started Apr 16 02:32:53 PM PDT 24
Finished Apr 16 02:33:01 PM PDT 24
Peak memory 204024 kb
Host smart-aa84d113-62eb-4551-aec3-58a405b973c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764743378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1764743378
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1742602183
Short name T410
Test name
Test status
Simulation time 2458456042 ps
CPU time 23.84 seconds
Started Apr 16 02:32:55 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 327356 kb
Host smart-9c66b9eb-5bc3-4e3e-b7d2-6daf65875ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742602183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1742602183
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.4062950952
Short name T876
Test name
Test status
Simulation time 46901484 ps
CPU time 0.65 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:32:50 PM PDT 24
Peak memory 203676 kb
Host smart-a60c4a75-5e2d-4d54-b944-b84ff1764376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062950952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4062950952
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.1272368752
Short name T1308
Test name
Test status
Simulation time 994764593 ps
CPU time 41.35 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:33:30 PM PDT 24
Peak memory 309000 kb
Host smart-71b7bd79-f905-4ecc-817e-11031fd9bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272368752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1272368752
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3385595332
Short name T380
Test name
Test status
Simulation time 1057806616 ps
CPU time 53.08 seconds
Started Apr 16 02:32:51 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 313092 kb
Host smart-01ff0f75-f4bd-4f62-a86d-be40791222a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385595332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3385595332
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.4024597104
Short name T643
Test name
Test status
Simulation time 55453944259 ps
CPU time 1014.25 seconds
Started Apr 16 02:32:50 PM PDT 24
Finished Apr 16 02:49:46 PM PDT 24
Peak memory 2269876 kb
Host smart-cda1e126-01c2-4857-b5f7-2d126ce44d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024597104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.4024597104
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1228770597
Short name T855
Test name
Test status
Simulation time 1520040236 ps
CPU time 14.18 seconds
Started Apr 16 02:32:49 PM PDT 24
Finished Apr 16 02:33:04 PM PDT 24
Peak memory 217508 kb
Host smart-d6a6f4ee-2881-4e0b-a860-5a1299b6e16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228770597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1228770597
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1323678609
Short name T1071
Test name
Test status
Simulation time 562372079 ps
CPU time 2.9 seconds
Started Apr 16 02:32:55 PM PDT 24
Finished Apr 16 02:32:59 PM PDT 24
Peak memory 203976 kb
Host smart-7e78e608-b015-4004-98c0-a1947f4ac67f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323678609 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1323678609
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2567996559
Short name T53
Test name
Test status
Simulation time 10054076854 ps
CPU time 30.43 seconds
Started Apr 16 02:32:55 PM PDT 24
Finished Apr 16 02:33:26 PM PDT 24
Peak memory 352396 kb
Host smart-363ed50e-19b4-47de-8f09-81cba82168d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567996559 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2567996559
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3761321169
Short name T26
Test name
Test status
Simulation time 1300616421 ps
CPU time 2.15 seconds
Started Apr 16 02:32:56 PM PDT 24
Finished Apr 16 02:32:58 PM PDT 24
Peak memory 204024 kb
Host smart-8fbcad7a-3abe-476b-b721-c2fb238acec2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761321169 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3761321169
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3466784866
Short name T731
Test name
Test status
Simulation time 1231554273 ps
CPU time 3.19 seconds
Started Apr 16 02:32:52 PM PDT 24
Finished Apr 16 02:32:56 PM PDT 24
Peak memory 204044 kb
Host smart-16761641-8aac-45c3-83ec-ad85f2be5d59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466784866 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3466784866
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2378357959
Short name T351
Test name
Test status
Simulation time 1224810890 ps
CPU time 18.22 seconds
Started Apr 16 02:32:48 PM PDT 24
Finished Apr 16 02:33:07 PM PDT 24
Peak memory 204028 kb
Host smart-1800ed5e-73b5-42fa-ba56-b0c03b0bb884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378357959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2378357959
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1333638998
Short name T374
Test name
Test status
Simulation time 6857490875 ps
CPU time 54.8 seconds
Started Apr 16 02:32:51 PM PDT 24
Finished Apr 16 02:33:46 PM PDT 24
Peak memory 206080 kb
Host smart-b87625ad-777d-4d3d-af58-a601cdddba73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333638998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1333638998
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3872616794
Short name T737
Test name
Test status
Simulation time 40345370557 ps
CPU time 73.36 seconds
Started Apr 16 02:32:51 PM PDT 24
Finished Apr 16 02:34:05 PM PDT 24
Peak memory 1235800 kb
Host smart-17566dde-0af3-432e-b4bc-fd9f8428dfb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872616794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3872616794
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.574634127
Short name T581
Test name
Test status
Simulation time 4129835572 ps
CPU time 108.77 seconds
Started Apr 16 02:32:54 PM PDT 24
Finished Apr 16 02:34:44 PM PDT 24
Peak memory 634312 kb
Host smart-4e34d70e-39b6-4cb8-a972-2d1b3a919dbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574634127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.574634127
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2917928593
Short name T652
Test name
Test status
Simulation time 1412160079 ps
CPU time 6.65 seconds
Started Apr 16 02:32:53 PM PDT 24
Finished Apr 16 02:33:01 PM PDT 24
Peak memory 220212 kb
Host smart-55d63f1e-81ea-4edb-8ad8-4f5ba3bbbaa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917928593 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2917928593
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2739487876
Short name T468
Test name
Test status
Simulation time 39925145 ps
CPU time 0.64 seconds
Started Apr 16 02:32:59 PM PDT 24
Finished Apr 16 02:33:00 PM PDT 24
Peak memory 203592 kb
Host smart-2bedbd64-f643-477a-a9b5-524ff2fea2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739487876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2739487876
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.299413717
Short name T458
Test name
Test status
Simulation time 359093552 ps
CPU time 1.51 seconds
Started Apr 16 02:33:00 PM PDT 24
Finished Apr 16 02:33:02 PM PDT 24
Peak memory 204076 kb
Host smart-abfad3f5-638d-4d12-a353-a13ba6ac35b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299413717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.299413717
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1407278445
Short name T321
Test name
Test status
Simulation time 420107351 ps
CPU time 21.53 seconds
Started Apr 16 02:32:59 PM PDT 24
Finished Apr 16 02:33:21 PM PDT 24
Peak memory 287528 kb
Host smart-c037361e-c2df-4ef7-9995-9ce51e5c79bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407278445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1407278445
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.4285665669
Short name T521
Test name
Test status
Simulation time 1478569878 ps
CPU time 39.47 seconds
Started Apr 16 02:33:01 PM PDT 24
Finished Apr 16 02:33:41 PM PDT 24
Peak memory 512400 kb
Host smart-99218a4c-8463-4931-9fb7-8c0176fbfc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285665669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.4285665669
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2403379961
Short name T712
Test name
Test status
Simulation time 2479210404 ps
CPU time 41.85 seconds
Started Apr 16 02:32:55 PM PDT 24
Finished Apr 16 02:33:38 PM PDT 24
Peak memory 553148 kb
Host smart-7e98cc87-c9f0-4abe-9820-9551d287931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403379961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2403379961
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2785143177
Short name T215
Test name
Test status
Simulation time 605153357 ps
CPU time 1.03 seconds
Started Apr 16 02:32:53 PM PDT 24
Finished Apr 16 02:32:55 PM PDT 24
Peak memory 203740 kb
Host smart-fdb9a946-51ca-460f-a787-93093e71c5ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785143177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2785143177
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1379121028
Short name T619
Test name
Test status
Simulation time 634520169 ps
CPU time 8.87 seconds
Started Apr 16 02:33:01 PM PDT 24
Finished Apr 16 02:33:11 PM PDT 24
Peak memory 232436 kb
Host smart-a3198c6b-6224-4368-bcd0-7a2676c2ba19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379121028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1379121028
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.3176382814
Short name T123
Test name
Test status
Simulation time 296176496 ps
CPU time 10.51 seconds
Started Apr 16 02:33:05 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 203940 kb
Host smart-3c3e30b1-aa52-4cd5-980b-80f298b2ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176382814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3176382814
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2440200819
Short name T725
Test name
Test status
Simulation time 1762343803 ps
CPU time 77.1 seconds
Started Apr 16 02:33:05 PM PDT 24
Finished Apr 16 02:34:23 PM PDT 24
Peak memory 297072 kb
Host smart-3c23b21e-943c-467f-9fc4-c7a9a5b2f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440200819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2440200819
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3456227340
Short name T186
Test name
Test status
Simulation time 32577553 ps
CPU time 0.73 seconds
Started Apr 16 02:32:56 PM PDT 24
Finished Apr 16 02:32:57 PM PDT 24
Peak memory 203664 kb
Host smart-7648fc25-f4b6-4c4e-9449-54a61e6c62f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456227340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3456227340
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.4092422905
Short name T559
Test name
Test status
Simulation time 25016636937 ps
CPU time 790.97 seconds
Started Apr 16 02:32:57 PM PDT 24
Finished Apr 16 02:46:09 PM PDT 24
Peak memory 2566372 kb
Host smart-8a57a11f-e094-45f6-a4a4-022052c5cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092422905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.4092422905
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1242573302
Short name T298
Test name
Test status
Simulation time 3193855711 ps
CPU time 25.19 seconds
Started Apr 16 02:32:55 PM PDT 24
Finished Apr 16 02:33:21 PM PDT 24
Peak memory 326872 kb
Host smart-36cd24b2-fee8-4a47-a609-0fd2c7ffead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242573302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1242573302
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1047042662
Short name T233
Test name
Test status
Simulation time 1756671200 ps
CPU time 8.96 seconds
Started Apr 16 02:32:58 PM PDT 24
Finished Apr 16 02:33:07 PM PDT 24
Peak memory 219972 kb
Host smart-891ed138-0d83-460d-9b50-79634e5cfc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047042662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1047042662
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1478522152
Short name T900
Test name
Test status
Simulation time 975403181 ps
CPU time 4.25 seconds
Started Apr 16 02:33:00 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 212180 kb
Host smart-40da9560-1ca7-49fb-8a4a-009d58b8abe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478522152 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1478522152
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2997987404
Short name T358
Test name
Test status
Simulation time 10819087080 ps
CPU time 3.7 seconds
Started Apr 16 02:32:57 PM PDT 24
Finished Apr 16 02:33:02 PM PDT 24
Peak memory 225612 kb
Host smart-9fc6242b-c82d-427d-b130-7b8f7a8f4f61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997987404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2997987404
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3254452091
Short name T729
Test name
Test status
Simulation time 1264129577 ps
CPU time 1.6 seconds
Started Apr 16 02:32:59 PM PDT 24
Finished Apr 16 02:33:01 PM PDT 24
Peak memory 203932 kb
Host smart-021080a4-6883-4c23-a09e-e4d6d74e3d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254452091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3254452091
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.894857614
Short name T1140
Test name
Test status
Simulation time 2589466343 ps
CPU time 6.24 seconds
Started Apr 16 02:33:04 PM PDT 24
Finished Apr 16 02:33:11 PM PDT 24
Peak memory 210456 kb
Host smart-227c9343-173c-419c-b0a3-b0e681a347f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894857614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.894857614
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2645232071
Short name T765
Test name
Test status
Simulation time 11776989133 ps
CPU time 4.67 seconds
Started Apr 16 02:32:59 PM PDT 24
Finished Apr 16 02:33:04 PM PDT 24
Peak memory 204012 kb
Host smart-8f7682fc-f5e5-4327-9393-b2882a0666da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645232071 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2645232071
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1208576107
Short name T637
Test name
Test status
Simulation time 1978839662 ps
CPU time 12.28 seconds
Started Apr 16 02:33:01 PM PDT 24
Finished Apr 16 02:33:14 PM PDT 24
Peak memory 203956 kb
Host smart-3283245e-56e2-4496-afc6-4428812a9733
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208576107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1208576107
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.853622747
Short name T961
Test name
Test status
Simulation time 1448097129 ps
CPU time 32.26 seconds
Started Apr 16 02:32:59 PM PDT 24
Finished Apr 16 02:33:32 PM PDT 24
Peak memory 204040 kb
Host smart-4cfbcba2-8a0f-4266-b913-4a8bbf587928
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853622747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.853622747
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3379427112
Short name T1106
Test name
Test status
Simulation time 30145726876 ps
CPU time 218.59 seconds
Started Apr 16 02:33:00 PM PDT 24
Finished Apr 16 02:36:40 PM PDT 24
Peak memory 2699060 kb
Host smart-14827ca9-47d3-4c14-9bf5-fd34ddc78d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379427112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3379427112
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3420509567
Short name T892
Test name
Test status
Simulation time 5435090048 ps
CPU time 20.08 seconds
Started Apr 16 02:33:01 PM PDT 24
Finished Apr 16 02:33:22 PM PDT 24
Peak memory 426672 kb
Host smart-aca46e2f-743c-4fc2-a9cd-c49ba8c5066f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420509567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3420509567
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2717393877
Short name T992
Test name
Test status
Simulation time 1328694097 ps
CPU time 6.45 seconds
Started Apr 16 02:33:00 PM PDT 24
Finished Apr 16 02:33:07 PM PDT 24
Peak memory 220240 kb
Host smart-ae69256d-3cc6-47ed-8598-ed3e991abf71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717393877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2717393877
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3512393207
Short name T621
Test name
Test status
Simulation time 18029237 ps
CPU time 0.63 seconds
Started Apr 16 02:33:13 PM PDT 24
Finished Apr 16 02:33:14 PM PDT 24
Peak memory 203620 kb
Host smart-ebc479d6-0e68-479a-b9a4-8166ad6aa469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512393207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3512393207
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1226137939
Short name T537
Test name
Test status
Simulation time 314668542 ps
CPU time 1.19 seconds
Started Apr 16 02:33:02 PM PDT 24
Finished Apr 16 02:33:04 PM PDT 24
Peak memory 204004 kb
Host smart-7380af8c-d467-4f4b-aa8c-f2fc6fae1e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226137939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1226137939
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1838068380
Short name T1327
Test name
Test status
Simulation time 554979761 ps
CPU time 14.78 seconds
Started Apr 16 02:33:05 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 253464 kb
Host smart-14da65c3-73b7-4c2b-88e5-77a26880656f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838068380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1838068380
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2050597643
Short name T865
Test name
Test status
Simulation time 4577647508 ps
CPU time 82.2 seconds
Started Apr 16 02:33:03 PM PDT 24
Finished Apr 16 02:34:26 PM PDT 24
Peak memory 764444 kb
Host smart-313337ce-0dd9-4ee1-9597-552de9c65a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050597643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2050597643
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1310924250
Short name T775
Test name
Test status
Simulation time 1682640345 ps
CPU time 44.58 seconds
Started Apr 16 02:33:04 PM PDT 24
Finished Apr 16 02:33:49 PM PDT 24
Peak memory 527700 kb
Host smart-b8fdcd00-a480-4e54-af7b-aa7e5ef8c212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310924250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1310924250
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.808572953
Short name T841
Test name
Test status
Simulation time 157484658 ps
CPU time 1.14 seconds
Started Apr 16 02:33:04 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 203892 kb
Host smart-66c39bfc-b4d0-4b79-bbc2-cb265397df13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808572953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fm
t.808572953
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1362427489
Short name T428
Test name
Test status
Simulation time 954200775 ps
CPU time 2.28 seconds
Started Apr 16 02:33:03 PM PDT 24
Finished Apr 16 02:33:06 PM PDT 24
Peak memory 203972 kb
Host smart-1f21d85a-74fe-4979-affe-1af81cf41a56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362427489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1362427489
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2268018684
Short name T977
Test name
Test status
Simulation time 8307503935 ps
CPU time 346.85 seconds
Started Apr 16 02:33:04 PM PDT 24
Finished Apr 16 02:38:51 PM PDT 24
Peak memory 1215012 kb
Host smart-d3160047-35bb-44e4-b31b-e308532a507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268018684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2268018684
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3283205078
Short name T391
Test name
Test status
Simulation time 282262129 ps
CPU time 11.54 seconds
Started Apr 16 02:33:10 PM PDT 24
Finished Apr 16 02:33:22 PM PDT 24
Peak memory 203940 kb
Host smart-49283e13-96e2-4c1f-8a29-528e52c181ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283205078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3283205078
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2680507120
Short name T761
Test name
Test status
Simulation time 4346248430 ps
CPU time 38.55 seconds
Started Apr 16 02:33:07 PM PDT 24
Finished Apr 16 02:33:47 PM PDT 24
Peak memory 310628 kb
Host smart-2725a773-3f58-4094-b39b-2d1802c3b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680507120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2680507120
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3260201171
Short name T42
Test name
Test status
Simulation time 45770311 ps
CPU time 0.64 seconds
Started Apr 16 02:33:04 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 203604 kb
Host smart-5462c588-74d7-4aa7-b272-f8eeb464ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260201171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3260201171
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3980081070
Short name T680
Test name
Test status
Simulation time 10033200356 ps
CPU time 189.9 seconds
Started Apr 16 02:33:03 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 212200 kb
Host smart-9897f359-84ca-4031-a357-1249e9c653d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980081070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3980081070
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2895363101
Short name T1176
Test name
Test status
Simulation time 3438580934 ps
CPU time 40.04 seconds
Started Apr 16 02:33:05 PM PDT 24
Finished Apr 16 02:33:46 PM PDT 24
Peak memory 265028 kb
Host smart-38e92ad1-ae53-48e3-99d5-7d29b35e0cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895363101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2895363101
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3891255078
Short name T829
Test name
Test status
Simulation time 9699539059 ps
CPU time 840.8 seconds
Started Apr 16 02:33:03 PM PDT 24
Finished Apr 16 02:47:04 PM PDT 24
Peak memory 1888828 kb
Host smart-0b0e0ab7-1054-4cc1-b413-c11c10af3eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891255078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3891255078
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3774384184
Short name T1304
Test name
Test status
Simulation time 1699688485 ps
CPU time 37.17 seconds
Started Apr 16 02:33:04 PM PDT 24
Finished Apr 16 02:33:42 PM PDT 24
Peak memory 212188 kb
Host smart-e29390ee-b9f8-4b16-bdbb-693f6b870706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774384184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3774384184
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1259199574
Short name T548
Test name
Test status
Simulation time 906176205 ps
CPU time 3.79 seconds
Started Apr 16 02:33:07 PM PDT 24
Finished Apr 16 02:33:12 PM PDT 24
Peak memory 212196 kb
Host smart-dc0351fb-32ec-4d93-b1e3-e674b353257c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259199574 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1259199574
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2544901423
Short name T732
Test name
Test status
Simulation time 10243317169 ps
CPU time 11.38 seconds
Started Apr 16 02:33:14 PM PDT 24
Finished Apr 16 02:33:26 PM PDT 24
Peak memory 278808 kb
Host smart-32e2f69a-6acf-4086-a6b3-8b563faa232d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544901423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2544901423
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1415885210
Short name T1072
Test name
Test status
Simulation time 10064880345 ps
CPU time 54.68 seconds
Started Apr 16 02:33:11 PM PDT 24
Finished Apr 16 02:34:06 PM PDT 24
Peak memory 474156 kb
Host smart-16cb5a16-6618-404d-8ad7-f0187ff0274a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415885210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1415885210
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1130368322
Short name T659
Test name
Test status
Simulation time 1165326029 ps
CPU time 2.6 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:11 PM PDT 24
Peak memory 203956 kb
Host smart-e7017e8d-a872-4a93-acbe-8223412f44d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130368322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1130368322
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3767969853
Short name T570
Test name
Test status
Simulation time 5532313891 ps
CPU time 7.09 seconds
Started Apr 16 02:33:02 PM PDT 24
Finished Apr 16 02:33:10 PM PDT 24
Peak memory 209804 kb
Host smart-5a20e232-b854-4ed0-ad36-225611730719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767969853 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3767969853
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2066650001
Short name T710
Test name
Test status
Simulation time 7830038917 ps
CPU time 20.26 seconds
Started Apr 16 02:33:06 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 417172 kb
Host smart-8b4771cd-b7da-4437-a272-a5d8ede14db1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066650001 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2066650001
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1438704774
Short name T489
Test name
Test status
Simulation time 1755390183 ps
CPU time 18.98 seconds
Started Apr 16 02:33:07 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 204016 kb
Host smart-b9d61b87-9dfe-466f-af11-2e24bfaa1ae4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438704774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1438704774
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.1240486128
Short name T585
Test name
Test status
Simulation time 42097013151 ps
CPU time 55.67 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:34:04 PM PDT 24
Peak memory 537952 kb
Host smart-639ca301-bc03-426d-b82d-c1e716774f8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240486128 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.1240486128
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1189772546
Short name T1068
Test name
Test status
Simulation time 780013234 ps
CPU time 6.87 seconds
Started Apr 16 02:33:05 PM PDT 24
Finished Apr 16 02:33:12 PM PDT 24
Peak memory 203960 kb
Host smart-8fb710c9-70ea-40e9-bf03-65b3a5809c66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189772546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1189772546
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3880338925
Short name T281
Test name
Test status
Simulation time 21576155554 ps
CPU time 19.71 seconds
Started Apr 16 02:33:03 PM PDT 24
Finished Apr 16 02:33:24 PM PDT 24
Peak memory 236892 kb
Host smart-3a3e5e61-ff23-4055-b600-64b6c5004be8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880338925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3880338925
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2001877808
Short name T833
Test name
Test status
Simulation time 3593748600 ps
CPU time 85.82 seconds
Started Apr 16 02:33:05 PM PDT 24
Finished Apr 16 02:34:32 PM PDT 24
Peak memory 1000516 kb
Host smart-91346e26-4abc-4b07-8947-986afc81cf6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001877808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2001877808
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2747494413
Short name T402
Test name
Test status
Simulation time 2483737010 ps
CPU time 5.64 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:14 PM PDT 24
Peak memory 218960 kb
Host smart-3cacaedb-e6a2-4523-b99c-456d3795f5aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747494413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2747494413
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2940840821
Short name T1179
Test name
Test status
Simulation time 48731169 ps
CPU time 0.62 seconds
Started Apr 16 02:33:12 PM PDT 24
Finished Apr 16 02:33:13 PM PDT 24
Peak memory 203572 kb
Host smart-aff5c007-dab5-4e9b-bc29-d9dab2b82255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940840821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2940840821
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.361713600
Short name T1038
Test name
Test status
Simulation time 96803064 ps
CPU time 1.71 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:10 PM PDT 24
Peak memory 212316 kb
Host smart-e5979bef-32fc-4288-a377-9f79836a0db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361713600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.361713600
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3591283773
Short name T459
Test name
Test status
Simulation time 207547225 ps
CPU time 4.55 seconds
Started Apr 16 02:33:14 PM PDT 24
Finished Apr 16 02:33:19 PM PDT 24
Peak memory 239124 kb
Host smart-e8b5589c-4377-455e-a62d-9e434833eca5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591283773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3591283773
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.190217207
Short name T1170
Test name
Test status
Simulation time 1786380646 ps
CPU time 51.38 seconds
Started Apr 16 02:33:09 PM PDT 24
Finished Apr 16 02:34:01 PM PDT 24
Peak memory 593060 kb
Host smart-8702a0b3-d425-4cca-b910-8751ddcd447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190217207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.190217207
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.244156582
Short name T1069
Test name
Test status
Simulation time 2511805439 ps
CPU time 77.43 seconds
Started Apr 16 02:33:07 PM PDT 24
Finished Apr 16 02:34:25 PM PDT 24
Peak memory 501696 kb
Host smart-46fda7a0-57cd-4f1b-a9bb-3cf8abc5cc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244156582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.244156582
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2649462303
Short name T393
Test name
Test status
Simulation time 355571478 ps
CPU time 0.91 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:10 PM PDT 24
Peak memory 203664 kb
Host smart-7e81548c-50c8-431a-a21f-f7f514afb8f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649462303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2649462303
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1394958515
Short name T1285
Test name
Test status
Simulation time 159204525 ps
CPU time 7.71 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 203912 kb
Host smart-8f236d22-0b3b-4de4-b8d3-53f6772dc28a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394958515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1394958515
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2108143488
Short name T1225
Test name
Test status
Simulation time 22005815697 ps
CPU time 96.09 seconds
Started Apr 16 02:33:09 PM PDT 24
Finished Apr 16 02:34:46 PM PDT 24
Peak memory 1163416 kb
Host smart-503937dd-d892-4cda-832a-bd51aa43777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108143488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2108143488
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2930030443
Short name T1103
Test name
Test status
Simulation time 466455648 ps
CPU time 18.1 seconds
Started Apr 16 02:33:20 PM PDT 24
Finished Apr 16 02:33:39 PM PDT 24
Peak memory 203916 kb
Host smart-fe283670-4bb4-4bb2-9336-38b52b0714f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930030443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2930030443
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3227401023
Short name T1332
Test name
Test status
Simulation time 2172610757 ps
CPU time 76.56 seconds
Started Apr 16 02:33:13 PM PDT 24
Finished Apr 16 02:34:31 PM PDT 24
Peak memory 349180 kb
Host smart-84b94f9d-b188-40c8-a2df-33f92dc860b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227401023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3227401023
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1857430073
Short name T44
Test name
Test status
Simulation time 26564804 ps
CPU time 0.66 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:10 PM PDT 24
Peak memory 203656 kb
Host smart-49a29e2e-9718-49e5-af4b-b8514eb9ada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857430073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1857430073
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2756660073
Short name T721
Test name
Test status
Simulation time 3050989642 ps
CPU time 7.98 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 203952 kb
Host smart-e235a66e-3b44-44ad-8825-a537d4263396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756660073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2756660073
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.180482924
Short name T1156
Test name
Test status
Simulation time 1469928528 ps
CPU time 21.24 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:30 PM PDT 24
Peak memory 321684 kb
Host smart-c94d2957-548e-4426-94d4-605edb246b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180482924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.180482924
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.3528417297
Short name T1129
Test name
Test status
Simulation time 16313723889 ps
CPU time 741.46 seconds
Started Apr 16 02:33:14 PM PDT 24
Finished Apr 16 02:45:36 PM PDT 24
Peak memory 2571732 kb
Host smart-fb711a51-aeb4-41c9-95c5-47ee3bb958e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528417297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.3528417297
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.492491580
Short name T1297
Test name
Test status
Simulation time 465407511 ps
CPU time 20.49 seconds
Started Apr 16 02:33:08 PM PDT 24
Finished Apr 16 02:33:29 PM PDT 24
Peak memory 212264 kb
Host smart-f7141440-6c5f-4413-8ed3-36569a91063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492491580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.492491580
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1488103609
Short name T29
Test name
Test status
Simulation time 2938446811 ps
CPU time 3.6 seconds
Started Apr 16 02:33:16 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 212256 kb
Host smart-ad7bd00c-3f50-4243-992a-9770f2b64780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488103609 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1488103609
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3095845350
Short name T84
Test name
Test status
Simulation time 10232115513 ps
CPU time 13.1 seconds
Started Apr 16 02:33:14 PM PDT 24
Finished Apr 16 02:33:28 PM PDT 24
Peak memory 265668 kb
Host smart-cba4438f-691d-4846-8ff6-1f62b7b420e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095845350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3095845350
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.1326579624
Short name T873
Test name
Test status
Simulation time 10293528927 ps
CPU time 14.07 seconds
Started Apr 16 02:33:12 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 295892 kb
Host smart-1de179c6-2729-4c67-8803-31f65382bc52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326579624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.1326579624
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.956004621
Short name T1193
Test name
Test status
Simulation time 766113865 ps
CPU time 2.37 seconds
Started Apr 16 02:33:21 PM PDT 24
Finished Apr 16 02:33:24 PM PDT 24
Peak memory 203948 kb
Host smart-dc4d02b1-1711-4ff0-b395-486ac777487f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956004621 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_hrst.956004621
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1218415190
Short name T644
Test name
Test status
Simulation time 1334640053 ps
CPU time 3.6 seconds
Started Apr 16 02:33:16 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 204008 kb
Host smart-7047ce63-8d6c-43ea-9d1c-528d3ff205db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218415190 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1218415190
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1851774294
Short name T631
Test name
Test status
Simulation time 3526249274 ps
CPU time 1.92 seconds
Started Apr 16 02:33:13 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 204040 kb
Host smart-e3061dd2-3857-4ec1-9ea9-4cce375cc662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851774294 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1851774294
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1303775307
Short name T102
Test name
Test status
Simulation time 1935872528 ps
CPU time 12.51 seconds
Started Apr 16 02:33:15 PM PDT 24
Finished Apr 16 02:33:28 PM PDT 24
Peak memory 203992 kb
Host smart-af2ef9a6-7209-431e-a547-757f8cddfbe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303775307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1303775307
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3530972067
Short name T1245
Test name
Test status
Simulation time 363923474 ps
CPU time 5.73 seconds
Started Apr 16 02:33:13 PM PDT 24
Finished Apr 16 02:33:19 PM PDT 24
Peak memory 204928 kb
Host smart-27352e55-34f5-4454-bd70-fbdab6c8eeee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530972067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3530972067
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2956398928
Short name T728
Test name
Test status
Simulation time 50150583502 ps
CPU time 1211.03 seconds
Started Apr 16 02:33:15 PM PDT 24
Finished Apr 16 02:53:26 PM PDT 24
Peak memory 7758992 kb
Host smart-70c0c001-bcb8-413f-a4cc-7f2ab4386d3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956398928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2956398928
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2642995623
Short name T1326
Test name
Test status
Simulation time 17004077992 ps
CPU time 843.91 seconds
Started Apr 16 02:33:14 PM PDT 24
Finished Apr 16 02:47:18 PM PDT 24
Peak memory 4137020 kb
Host smart-0c450a4e-1fac-4a1c-9d2b-19a828d58d22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642995623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2642995623
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2546907078
Short name T918
Test name
Test status
Simulation time 1069507164 ps
CPU time 5.86 seconds
Started Apr 16 02:33:21 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 209728 kb
Host smart-93b9b2c4-fcf7-4998-99da-71e0c8240ede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546907078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2546907078
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2584682732
Short name T519
Test name
Test status
Simulation time 28523508 ps
CPU time 0.64 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:33:25 PM PDT 24
Peak memory 203536 kb
Host smart-f828daca-671d-44b4-abe0-4ff7be7584d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584682732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2584682732
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2300503217
Short name T582
Test name
Test status
Simulation time 127060052 ps
CPU time 1.21 seconds
Started Apr 16 02:33:19 PM PDT 24
Finished Apr 16 02:33:21 PM PDT 24
Peak memory 220508 kb
Host smart-7097c838-1e28-4d1f-97d1-c2710d58c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300503217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2300503217
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.4029813502
Short name T677
Test name
Test status
Simulation time 1065702396 ps
CPU time 12.7 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:33:37 PM PDT 24
Peak memory 248848 kb
Host smart-1974063a-61c3-4f83-a58d-bd3f50d4cd06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029813502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.4029813502
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2797404320
Short name T45
Test name
Test status
Simulation time 12212715727 ps
CPU time 92.16 seconds
Started Apr 16 02:33:21 PM PDT 24
Finished Apr 16 02:34:54 PM PDT 24
Peak memory 539636 kb
Host smart-238097c8-b92e-4dc3-8479-c909b09daa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797404320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2797404320
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1252604660
Short name T1262
Test name
Test status
Simulation time 433334443 ps
CPU time 1.02 seconds
Started Apr 16 02:33:19 PM PDT 24
Finished Apr 16 02:33:21 PM PDT 24
Peak memory 203712 kb
Host smart-17525a5d-eb60-4dd1-8f95-fc90db687036
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252604660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1252604660
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2631143885
Short name T657
Test name
Test status
Simulation time 752313250 ps
CPU time 2.86 seconds
Started Apr 16 02:33:18 PM PDT 24
Finished Apr 16 02:33:21 PM PDT 24
Peak memory 203972 kb
Host smart-c89968a7-8932-49de-9120-43f5d467827e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631143885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2631143885
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2139777553
Short name T948
Test name
Test status
Simulation time 13568915108 ps
CPU time 95.1 seconds
Started Apr 16 02:33:21 PM PDT 24
Finished Apr 16 02:34:56 PM PDT 24
Peak memory 1018796 kb
Host smart-10b57b87-e83f-4045-aec0-e20729b7d4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139777553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2139777553
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1522789016
Short name T72
Test name
Test status
Simulation time 383515573 ps
CPU time 2.71 seconds
Started Apr 16 02:33:22 PM PDT 24
Finished Apr 16 02:33:26 PM PDT 24
Peak memory 203988 kb
Host smart-9a0553e7-9f85-4871-ac40-8dbdc90af6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522789016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1522789016
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2547069131
Short name T1190
Test name
Test status
Simulation time 5743160221 ps
CPU time 62.52 seconds
Started Apr 16 02:33:23 PM PDT 24
Finished Apr 16 02:34:26 PM PDT 24
Peak memory 314276 kb
Host smart-5b3e9de4-2fce-4267-922c-4b49d29b28cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547069131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2547069131
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.2725299486
Short name T188
Test name
Test status
Simulation time 54835386 ps
CPU time 0.64 seconds
Started Apr 16 02:33:13 PM PDT 24
Finished Apr 16 02:33:15 PM PDT 24
Peak memory 203672 kb
Host smart-5a9ade1e-6e52-4986-8840-aa3945521241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725299486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2725299486
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.826707088
Short name T98
Test name
Test status
Simulation time 51723814057 ps
CPU time 1884.02 seconds
Started Apr 16 02:33:19 PM PDT 24
Finished Apr 16 03:04:44 PM PDT 24
Peak memory 203952 kb
Host smart-f48fed4d-e69b-47a8-833e-aaa247a356af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826707088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.826707088
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2732192715
Short name T1268
Test name
Test status
Simulation time 16645118239 ps
CPU time 25.19 seconds
Started Apr 16 02:33:12 PM PDT 24
Finished Apr 16 02:33:37 PM PDT 24
Peak memory 317800 kb
Host smart-bc13b742-90df-48fe-a621-075f729c75fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732192715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2732192715
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.2338799562
Short name T1293
Test name
Test status
Simulation time 648140659 ps
CPU time 28.46 seconds
Started Apr 16 02:33:22 PM PDT 24
Finished Apr 16 02:33:52 PM PDT 24
Peak memory 212236 kb
Host smart-6a3b8004-cf71-4245-95ec-20160bcf2ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338799562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2338799562
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.801806353
Short name T1082
Test name
Test status
Simulation time 1016231041 ps
CPU time 4.63 seconds
Started Apr 16 02:33:17 PM PDT 24
Finished Apr 16 02:33:22 PM PDT 24
Peak memory 204236 kb
Host smart-f337eb72-2b71-448c-b044-87975f6491b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801806353 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.801806353
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.565285587
Short name T480
Test name
Test status
Simulation time 10130864359 ps
CPU time 54.05 seconds
Started Apr 16 02:33:23 PM PDT 24
Finished Apr 16 02:34:18 PM PDT 24
Peak memory 474928 kb
Host smart-d3ffa1ce-9383-4d34-97af-dcb9c2747176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565285587 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.565285587
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1141800295
Short name T722
Test name
Test status
Simulation time 10144526250 ps
CPU time 8.53 seconds
Started Apr 16 02:33:20 PM PDT 24
Finished Apr 16 02:33:29 PM PDT 24
Peak memory 256240 kb
Host smart-f7e82093-d628-44a0-96d1-b6bf7d0a353b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141800295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1141800295
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.656268629
Short name T385
Test name
Test status
Simulation time 2804966565 ps
CPU time 1.64 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 204084 kb
Host smart-0f476117-281e-4b6a-8d93-78492bf9a732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656268629 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.656268629
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3742424163
Short name T838
Test name
Test status
Simulation time 3879163375 ps
CPU time 6.29 seconds
Started Apr 16 02:33:23 PM PDT 24
Finished Apr 16 02:33:30 PM PDT 24
Peak memory 220264 kb
Host smart-10a5e742-edfa-4a29-8242-b70cd7514a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742424163 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3742424163
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3911884612
Short name T1213
Test name
Test status
Simulation time 4338946261 ps
CPU time 7.59 seconds
Started Apr 16 02:33:19 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 204008 kb
Host smart-45a32ec8-912d-40e4-a632-c293dcc5fd54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911884612 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3911884612
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.4234717730
Short name T929
Test name
Test status
Simulation time 636907546 ps
CPU time 10.3 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:33:35 PM PDT 24
Peak memory 204012 kb
Host smart-4971ab39-3370-4982-ada0-12a500eb28e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234717730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.4234717730
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2678429772
Short name T277
Test name
Test status
Simulation time 4021461232 ps
CPU time 12.88 seconds
Started Apr 16 02:33:19 PM PDT 24
Finished Apr 16 02:33:33 PM PDT 24
Peak memory 204076 kb
Host smart-f64c0e22-74b4-448b-9db5-2a814b2d1af3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678429772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2678429772
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2230985459
Short name T22
Test name
Test status
Simulation time 67417832268 ps
CPU time 280.06 seconds
Started Apr 16 02:33:18 PM PDT 24
Finished Apr 16 02:37:59 PM PDT 24
Peak memory 2701156 kb
Host smart-57b069de-6995-43d9-aae0-24c6058dd880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230985459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2230985459
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.2188929358
Short name T400
Test name
Test status
Simulation time 34687019795 ps
CPU time 181.15 seconds
Started Apr 16 02:33:19 PM PDT 24
Finished Apr 16 02:36:21 PM PDT 24
Peak memory 1708108 kb
Host smart-8f71eba3-1737-42b6-9eb7-034d12fb1fc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188929358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.2188929358
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2202159023
Short name T733
Test name
Test status
Simulation time 2963284681 ps
CPU time 6.87 seconds
Started Apr 16 02:33:17 PM PDT 24
Finished Apr 16 02:33:25 PM PDT 24
Peak memory 218192 kb
Host smart-636caa66-37da-404b-85f3-b62bf3b0ecff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202159023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2202159023
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.666416701
Short name T601
Test name
Test status
Simulation time 17242523 ps
CPU time 0.62 seconds
Started Apr 16 02:33:27 PM PDT 24
Finished Apr 16 02:33:28 PM PDT 24
Peak memory 203508 kb
Host smart-2df8ab48-7313-4eec-99b0-41aaeeb29b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666416701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.666416701
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2330431270
Short name T843
Test name
Test status
Simulation time 303099211 ps
CPU time 1.39 seconds
Started Apr 16 02:33:23 PM PDT 24
Finished Apr 16 02:33:25 PM PDT 24
Peak memory 212264 kb
Host smart-2b7a0dac-8a7d-408d-8f02-a5f22bca6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330431270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2330431270
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1342903757
Short name T445
Test name
Test status
Simulation time 3124845734 ps
CPU time 21.82 seconds
Started Apr 16 02:33:23 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 294728 kb
Host smart-238f35f4-b370-4bac-a22e-2e4b181bf7c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342903757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1342903757
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2264497996
Short name T534
Test name
Test status
Simulation time 5726431877 ps
CPU time 36.55 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:34:02 PM PDT 24
Peak memory 472932 kb
Host smart-0e40f24b-2a09-47ac-bc3d-03d25a00235c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264497996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2264497996
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3059254079
Short name T996
Test name
Test status
Simulation time 4424384356 ps
CPU time 37.16 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:34:02 PM PDT 24
Peak memory 521952 kb
Host smart-635f829b-f2af-4c5c-8fb0-8b173c2b26df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059254079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3059254079
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1646776745
Short name T201
Test name
Test status
Simulation time 97426815 ps
CPU time 0.89 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:33:25 PM PDT 24
Peak memory 203712 kb
Host smart-d1e038a6-d438-4bed-947a-8e8409c9cc89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646776745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1646776745
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1309750227
Short name T774
Test name
Test status
Simulation time 504192929 ps
CPU time 4.67 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:33:30 PM PDT 24
Peak memory 239736 kb
Host smart-421b2f8d-08ec-4deb-97e4-426b13ed8c9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309750227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1309750227
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2415499588
Short name T1351
Test name
Test status
Simulation time 10387483162 ps
CPU time 160.05 seconds
Started Apr 16 02:33:23 PM PDT 24
Finished Apr 16 02:36:04 PM PDT 24
Peak memory 800972 kb
Host smart-a4ff0331-4c8d-4a83-a66e-abe551d498b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415499588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2415499588
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.3979048490
Short name T283
Test name
Test status
Simulation time 473168090 ps
CPU time 9.48 seconds
Started Apr 16 02:33:28 PM PDT 24
Finished Apr 16 02:33:38 PM PDT 24
Peak memory 203904 kb
Host smart-31a99995-023e-48f1-b4ec-a9cc7e7ce88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979048490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3979048490
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3927792736
Short name T405
Test name
Test status
Simulation time 23878779115 ps
CPU time 30.19 seconds
Started Apr 16 02:33:28 PM PDT 24
Finished Apr 16 02:34:00 PM PDT 24
Peak memory 341908 kb
Host smart-cc5e976f-e5a2-44fd-bc82-4b941d9f2ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927792736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3927792736
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2844662453
Short name T1306
Test name
Test status
Simulation time 31688022 ps
CPU time 0.75 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:33:25 PM PDT 24
Peak memory 203684 kb
Host smart-a32b1b30-62aa-4f6e-a3f8-b701bf25f029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844662453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2844662453
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3820549435
Short name T1279
Test name
Test status
Simulation time 5142445530 ps
CPU time 164.33 seconds
Started Apr 16 02:33:22 PM PDT 24
Finished Apr 16 02:36:07 PM PDT 24
Peak memory 1284556 kb
Host smart-05ebc7a2-cf2e-4a4d-a90e-2a342e60b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820549435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3820549435
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.4035303512
Short name T717
Test name
Test status
Simulation time 9153174879 ps
CPU time 22.11 seconds
Started Apr 16 02:33:23 PM PDT 24
Finished Apr 16 02:33:46 PM PDT 24
Peak memory 293348 kb
Host smart-152ede66-c02d-4114-9820-733b49aedac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035303512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.4035303512
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1505154377
Short name T253
Test name
Test status
Simulation time 29507390821 ps
CPU time 971.49 seconds
Started Apr 16 02:33:25 PM PDT 24
Finished Apr 16 02:49:37 PM PDT 24
Peak memory 997480 kb
Host smart-af01351b-673b-494e-991f-db848da0666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505154377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1505154377
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.394062834
Short name T258
Test name
Test status
Simulation time 2466168749 ps
CPU time 25.73 seconds
Started Apr 16 02:33:22 PM PDT 24
Finished Apr 16 02:33:49 PM PDT 24
Peak memory 212296 kb
Host smart-d7733dcb-4cf6-4536-b96d-a997f83e6274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394062834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.394062834
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3144354007
Short name T672
Test name
Test status
Simulation time 6777797214 ps
CPU time 3.78 seconds
Started Apr 16 02:33:26 PM PDT 24
Finished Apr 16 02:33:31 PM PDT 24
Peak memory 212252 kb
Host smart-219d8ca8-eaca-40a1-9a5d-29fb943dd3b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144354007 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3144354007
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1353958331
Short name T981
Test name
Test status
Simulation time 10337975380 ps
CPU time 9.78 seconds
Started Apr 16 02:33:29 PM PDT 24
Finished Apr 16 02:33:40 PM PDT 24
Peak memory 260784 kb
Host smart-0b79fcc1-9827-4867-b441-2e0cfa43e689
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353958331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1353958331
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3185367635
Short name T882
Test name
Test status
Simulation time 10045238956 ps
CPU time 76.29 seconds
Started Apr 16 02:33:26 PM PDT 24
Finished Apr 16 02:34:44 PM PDT 24
Peak memory 572608 kb
Host smart-5d392bfe-29b3-437c-ad0d-f35be469d351
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185367635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3185367635
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.3312412165
Short name T1023
Test name
Test status
Simulation time 1615255309 ps
CPU time 2.06 seconds
Started Apr 16 02:33:26 PM PDT 24
Finished Apr 16 02:33:29 PM PDT 24
Peak memory 203976 kb
Host smart-8184db4d-e1bf-4bcf-9911-48435594f79a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312412165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.3312412165
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3116412869
Short name T748
Test name
Test status
Simulation time 3518452264 ps
CPU time 4.45 seconds
Started Apr 16 02:33:26 PM PDT 24
Finished Apr 16 02:33:32 PM PDT 24
Peak memory 208304 kb
Host smart-a59cdd58-2cf7-4cba-8189-0aae1ee3c6e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116412869 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3116412869
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.663670914
Short name T432
Test name
Test status
Simulation time 7696008804 ps
CPU time 18.64 seconds
Started Apr 16 02:33:27 PM PDT 24
Finished Apr 16 02:33:46 PM PDT 24
Peak memory 336076 kb
Host smart-ac3e8919-db9a-4331-9a03-4892869295b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663670914 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.663670914
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2723523947
Short name T347
Test name
Test status
Simulation time 2725151358 ps
CPU time 22.91 seconds
Started Apr 16 02:33:25 PM PDT 24
Finished Apr 16 02:33:49 PM PDT 24
Peak memory 204032 kb
Host smart-0453603a-1605-47ae-a8d1-d61b50c33d52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723523947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2723523947
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3702728447
Short name T1257
Test name
Test status
Simulation time 3055971975 ps
CPU time 29.96 seconds
Started Apr 16 02:33:22 PM PDT 24
Finished Apr 16 02:33:53 PM PDT 24
Peak memory 204104 kb
Host smart-dea0e003-8a3d-4207-bbc8-3f6b0aec3790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702728447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3702728447
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2466331146
Short name T404
Test name
Test status
Simulation time 29374718268 ps
CPU time 172.39 seconds
Started Apr 16 02:33:24 PM PDT 24
Finished Apr 16 02:36:18 PM PDT 24
Peak memory 2263644 kb
Host smart-bd2eb249-9e7d-4055-9bcc-74eb377881f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466331146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2466331146
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1549166630
Short name T36
Test name
Test status
Simulation time 9381146378 ps
CPU time 32.55 seconds
Started Apr 16 02:33:32 PM PDT 24
Finished Apr 16 02:34:05 PM PDT 24
Peak memory 527848 kb
Host smart-c7249ff8-10cd-4bee-88aa-f69dde9a7c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549166630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1549166630
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.196688116
Short name T995
Test name
Test status
Simulation time 3122113012 ps
CPU time 6.84 seconds
Started Apr 16 02:33:27 PM PDT 24
Finished Apr 16 02:33:35 PM PDT 24
Peak memory 204048 kb
Host smart-5851c507-b041-41cf-9317-8710af57d1c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196688116 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.196688116
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.337076406
Short name T302
Test name
Test status
Simulation time 22168874 ps
CPU time 0.6 seconds
Started Apr 16 02:33:30 PM PDT 24
Finished Apr 16 02:33:32 PM PDT 24
Peak memory 203604 kb
Host smart-77b281fe-ed1c-401a-bf6a-6b3fb8d210a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337076406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.337076406
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2712113560
Short name T813
Test name
Test status
Simulation time 56650292 ps
CPU time 1.28 seconds
Started Apr 16 02:33:28 PM PDT 24
Finished Apr 16 02:33:30 PM PDT 24
Peak memory 220460 kb
Host smart-e6308583-a62c-4f0a-9b12-974cd89d9f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712113560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2712113560
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2048432436
Short name T816
Test name
Test status
Simulation time 405692687 ps
CPU time 7.13 seconds
Started Apr 16 02:33:31 PM PDT 24
Finished Apr 16 02:33:39 PM PDT 24
Peak memory 289408 kb
Host smart-f4747741-1398-41a8-9600-6be306045720
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048432436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2048432436
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2169011724
Short name T361
Test name
Test status
Simulation time 5278811738 ps
CPU time 83.78 seconds
Started Apr 16 02:33:30 PM PDT 24
Finished Apr 16 02:34:55 PM PDT 24
Peak memory 768328 kb
Host smart-102a79c1-1780-488a-97ab-289313ed995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169011724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2169011724
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1892285619
Short name T1128
Test name
Test status
Simulation time 12860638356 ps
CPU time 64.59 seconds
Started Apr 16 02:33:28 PM PDT 24
Finished Apr 16 02:34:33 PM PDT 24
Peak memory 750852 kb
Host smart-0270494b-a69f-46ab-a85a-ee97792db260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892285619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1892285619
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2808979530
Short name T676
Test name
Test status
Simulation time 585517051 ps
CPU time 1.17 seconds
Started Apr 16 02:33:31 PM PDT 24
Finished Apr 16 02:33:33 PM PDT 24
Peak memory 203940 kb
Host smart-3cbecd91-2499-483d-8d0c-277ba7be67f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808979530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2808979530
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1022680397
Short name T798
Test name
Test status
Simulation time 673351852 ps
CPU time 3.81 seconds
Started Apr 16 02:33:30 PM PDT 24
Finished Apr 16 02:33:35 PM PDT 24
Peak memory 203864 kb
Host smart-587bbaeb-e458-46d3-8ed3-7ef48a1af3f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022680397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1022680397
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.327944920
Short name T754
Test name
Test status
Simulation time 8516561024 ps
CPU time 294.75 seconds
Started Apr 16 02:33:31 PM PDT 24
Finished Apr 16 02:38:26 PM PDT 24
Peak memory 1162292 kb
Host smart-9e57197c-7ede-4387-a141-671e52348267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327944920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.327944920
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.594887607
Short name T296
Test name
Test status
Simulation time 506549950 ps
CPU time 5.98 seconds
Started Apr 16 02:33:33 PM PDT 24
Finished Apr 16 02:33:40 PM PDT 24
Peak memory 203960 kb
Host smart-73bbbf5d-40f0-406c-9c4a-8303d9d61874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594887607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.594887607
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1453974946
Short name T632
Test name
Test status
Simulation time 2453491898 ps
CPU time 69.23 seconds
Started Apr 16 02:33:35 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 364248 kb
Host smart-a2a9a0f8-1219-4e8a-bcdc-4cc29862a974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453974946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1453974946
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.441286310
Short name T930
Test name
Test status
Simulation time 17040891 ps
CPU time 0.62 seconds
Started Apr 16 02:33:29 PM PDT 24
Finished Apr 16 02:33:30 PM PDT 24
Peak memory 203656 kb
Host smart-46eb10b0-fe1f-4684-b16f-5a76a75b4efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441286310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.441286310
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3012565394
Short name T498
Test name
Test status
Simulation time 5297448760 ps
CPU time 82.55 seconds
Started Apr 16 02:33:27 PM PDT 24
Finished Apr 16 02:34:51 PM PDT 24
Peak memory 520792 kb
Host smart-42ee4601-7d4c-405e-82b1-ac24ba732e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012565394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3012565394
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.730953274
Short name T1307
Test name
Test status
Simulation time 1963744993 ps
CPU time 30.74 seconds
Started Apr 16 02:33:28 PM PDT 24
Finished Apr 16 02:33:59 PM PDT 24
Peak memory 382144 kb
Host smart-294c4f39-cce0-46c8-8f14-d0404b45fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730953274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.730953274
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.177987911
Short name T179
Test name
Test status
Simulation time 15713652106 ps
CPU time 535.2 seconds
Started Apr 16 02:33:32 PM PDT 24
Finished Apr 16 02:42:28 PM PDT 24
Peak memory 1617844 kb
Host smart-8a6586e2-8407-40e8-9367-d2a8abe6f3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177987911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.177987911
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.409050020
Short name T860
Test name
Test status
Simulation time 612130057 ps
CPU time 10.01 seconds
Started Apr 16 02:33:26 PM PDT 24
Finished Apr 16 02:33:37 PM PDT 24
Peak memory 228524 kb
Host smart-89ce8a90-73b6-4663-b91d-7a94f4b36f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409050020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.409050020
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.4244275809
Short name T967
Test name
Test status
Simulation time 533760061 ps
CPU time 2.77 seconds
Started Apr 16 02:33:34 PM PDT 24
Finished Apr 16 02:33:37 PM PDT 24
Peak memory 204024 kb
Host smart-c3c00313-67f8-43d3-ab73-7a0965204776
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244275809 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.4244275809
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3891453895
Short name T1164
Test name
Test status
Simulation time 11027532484 ps
CPU time 8.69 seconds
Started Apr 16 02:33:32 PM PDT 24
Finished Apr 16 02:33:42 PM PDT 24
Peak memory 242368 kb
Host smart-7dbd18ba-d002-4b44-a633-528055047086
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891453895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3891453895
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3711421730
Short name T409
Test name
Test status
Simulation time 10316311019 ps
CPU time 14.68 seconds
Started Apr 16 02:33:44 PM PDT 24
Finished Apr 16 02:33:59 PM PDT 24
Peak memory 289860 kb
Host smart-5fef6d8e-770d-45b7-9f92-1150093e21b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711421730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3711421730
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1382887367
Short name T1336
Test name
Test status
Simulation time 2018973123 ps
CPU time 1.83 seconds
Started Apr 16 02:33:34 PM PDT 24
Finished Apr 16 02:33:36 PM PDT 24
Peak memory 204000 kb
Host smart-85a67ff8-dc38-4216-924d-14d9f4fdc11f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382887367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1382887367
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1282374634
Short name T1002
Test name
Test status
Simulation time 4680997335 ps
CPU time 5.61 seconds
Started Apr 16 02:33:31 PM PDT 24
Finished Apr 16 02:33:37 PM PDT 24
Peak memory 208116 kb
Host smart-49c6efa4-3f95-44b1-be39-979f13940c0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282374634 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1282374634
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2636607988
Short name T1105
Test name
Test status
Simulation time 17274861339 ps
CPU time 32.92 seconds
Started Apr 16 02:33:33 PM PDT 24
Finished Apr 16 02:34:07 PM PDT 24
Peak memory 679184 kb
Host smart-f7ade313-a370-4846-be5c-03dbbb147835
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636607988 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2636607988
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2592427235
Short name T910
Test name
Test status
Simulation time 1838511460 ps
CPU time 35.17 seconds
Started Apr 16 02:33:29 PM PDT 24
Finished Apr 16 02:34:05 PM PDT 24
Peak memory 204004 kb
Host smart-692e89a1-5adc-45d7-99c9-a16d9cb942d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592427235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2592427235
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.14423636
Short name T377
Test name
Test status
Simulation time 12940624397 ps
CPU time 28.54 seconds
Started Apr 16 02:33:28 PM PDT 24
Finished Apr 16 02:33:58 PM PDT 24
Peak memory 223684 kb
Host smart-71368aad-12f3-4118-93e3-89579b1d29a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14423636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_rd.14423636
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3820176332
Short name T1034
Test name
Test status
Simulation time 21537427150 ps
CPU time 24.06 seconds
Started Apr 16 02:33:32 PM PDT 24
Finished Apr 16 02:33:57 PM PDT 24
Peak memory 282336 kb
Host smart-7c507d05-a795-4431-b3d9-939196c33b02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820176332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3820176332
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1916612419
Short name T673
Test name
Test status
Simulation time 29592200536 ps
CPU time 1800.67 seconds
Started Apr 16 02:33:32 PM PDT 24
Finished Apr 16 03:03:34 PM PDT 24
Peak memory 7019200 kb
Host smart-5d3f7a75-68b4-4ab8-a40b-c4bc13bf3a2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916612419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1916612419
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.4112012175
Short name T399
Test name
Test status
Simulation time 3060530849 ps
CPU time 6.93 seconds
Started Apr 16 02:33:37 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 220236 kb
Host smart-078c1e7d-db6f-4bf7-ad5f-b2d9feeec178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112012175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.4112012175
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2955230405
Short name T1030
Test name
Test status
Simulation time 28405204 ps
CPU time 0.63 seconds
Started Apr 16 02:33:49 PM PDT 24
Finished Apr 16 02:33:51 PM PDT 24
Peak memory 203564 kb
Host smart-7c68fc75-bcba-4db5-a53b-8ff68c43205b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955230405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2955230405
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.591546322
Short name T286
Test name
Test status
Simulation time 299051197 ps
CPU time 1.51 seconds
Started Apr 16 02:33:42 PM PDT 24
Finished Apr 16 02:33:44 PM PDT 24
Peak memory 215308 kb
Host smart-438d8fdd-f2e9-43ed-9d7c-3fad73b06f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591546322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.591546322
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3494888966
Short name T1312
Test name
Test status
Simulation time 623786166 ps
CPU time 14.86 seconds
Started Apr 16 02:33:33 PM PDT 24
Finished Apr 16 02:33:48 PM PDT 24
Peak memory 224064 kb
Host smart-9a457a05-e051-4489-8473-30f2778b003e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494888966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3494888966
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.4110773349
Short name T346
Test name
Test status
Simulation time 7845469179 ps
CPU time 56.59 seconds
Started Apr 16 02:33:39 PM PDT 24
Finished Apr 16 02:34:37 PM PDT 24
Peak memory 637028 kb
Host smart-988dc484-5178-470f-8efc-206dd7d7e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110773349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.4110773349
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3859723029
Short name T858
Test name
Test status
Simulation time 2062228594 ps
CPU time 161.65 seconds
Started Apr 16 02:33:33 PM PDT 24
Finished Apr 16 02:36:15 PM PDT 24
Peak memory 716624 kb
Host smart-4240adfb-2d7b-4b6e-9d81-c7d9a0d7da92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859723029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3859723029
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2542660675
Short name T435
Test name
Test status
Simulation time 77557928 ps
CPU time 0.81 seconds
Started Apr 16 02:33:33 PM PDT 24
Finished Apr 16 02:33:34 PM PDT 24
Peak memory 203736 kb
Host smart-b3746eb0-f045-4081-85c4-52ae9f6fc960
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542660675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2542660675
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4241572686
Short name T1328
Test name
Test status
Simulation time 636902605 ps
CPU time 9.92 seconds
Started Apr 16 02:33:32 PM PDT 24
Finished Apr 16 02:33:43 PM PDT 24
Peak memory 237056 kb
Host smart-31b8d80d-02ed-4832-b9ff-6c92a3ca1b27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241572686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4241572686
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1665640766
Short name T899
Test name
Test status
Simulation time 3446869795 ps
CPU time 95.95 seconds
Started Apr 16 02:33:33 PM PDT 24
Finished Apr 16 02:35:10 PM PDT 24
Peak memory 1027116 kb
Host smart-50a85f06-df74-49a6-a617-6dddb7f25bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665640766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1665640766
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.1562406523
Short name T500
Test name
Test status
Simulation time 625602299 ps
CPU time 6.33 seconds
Started Apr 16 02:33:39 PM PDT 24
Finished Apr 16 02:33:46 PM PDT 24
Peak memory 203832 kb
Host smart-6d34b8c6-66ed-4cce-a226-5bf48a1b5800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562406523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.1562406523
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.182832603
Short name T1056
Test name
Test status
Simulation time 7389735573 ps
CPU time 36.4 seconds
Started Apr 16 02:33:38 PM PDT 24
Finished Apr 16 02:34:15 PM PDT 24
Peak memory 382032 kb
Host smart-6977a0c0-f4d6-4b43-882c-06f51b7c3e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182832603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.182832603
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2499739321
Short name T1165
Test name
Test status
Simulation time 47271869 ps
CPU time 0.71 seconds
Started Apr 16 02:33:33 PM PDT 24
Finished Apr 16 02:33:34 PM PDT 24
Peak memory 203656 kb
Host smart-d855491f-021d-4c04-88ca-6e9eb2032420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499739321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2499739321
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2783521799
Short name T392
Test name
Test status
Simulation time 1408796774 ps
CPU time 32.39 seconds
Started Apr 16 02:33:36 PM PDT 24
Finished Apr 16 02:34:09 PM PDT 24
Peak memory 232552 kb
Host smart-dedc921d-9674-4b7b-919a-711c7422d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783521799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2783521799
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1836188770
Short name T964
Test name
Test status
Simulation time 1960276890 ps
CPU time 13.2 seconds
Started Apr 16 02:33:35 PM PDT 24
Finished Apr 16 02:33:49 PM PDT 24
Peak memory 259416 kb
Host smart-7041e7aa-4095-4f7a-954b-18259ccb5301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836188770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1836188770
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.221207663
Short name T250
Test name
Test status
Simulation time 3301135801 ps
CPU time 80.94 seconds
Started Apr 16 02:33:39 PM PDT 24
Finished Apr 16 02:35:01 PM PDT 24
Peak memory 482624 kb
Host smart-8f8078c8-da55-43fa-b182-6d903a3033c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221207663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.221207663
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2110153239
Short name T1024
Test name
Test status
Simulation time 555138909 ps
CPU time 25.52 seconds
Started Apr 16 02:33:37 PM PDT 24
Finished Apr 16 02:34:03 PM PDT 24
Peak memory 212208 kb
Host smart-85952197-a762-4e7a-8940-d0176304c603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110153239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2110153239
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3611091208
Short name T1123
Test name
Test status
Simulation time 2511968571 ps
CPU time 3.11 seconds
Started Apr 16 02:33:38 PM PDT 24
Finished Apr 16 02:33:41 PM PDT 24
Peak memory 204032 kb
Host smart-7ff957a4-6eea-433b-9b13-bc791fc2224b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611091208 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3611091208
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2738182397
Short name T1348
Test name
Test status
Simulation time 10176942266 ps
CPU time 5.94 seconds
Started Apr 16 02:33:37 PM PDT 24
Finished Apr 16 02:33:44 PM PDT 24
Peak memory 229780 kb
Host smart-29d0ac4b-6a7c-4220-9d4a-213db07b9b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738182397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2738182397
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3055877514
Short name T622
Test name
Test status
Simulation time 10039020391 ps
CPU time 79.45 seconds
Started Apr 16 02:33:38 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 601496 kb
Host smart-8215a016-f04e-409d-95b4-77177f692379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055877514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3055877514
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3480235922
Short name T578
Test name
Test status
Simulation time 2079582482 ps
CPU time 2.69 seconds
Started Apr 16 02:33:39 PM PDT 24
Finished Apr 16 02:33:42 PM PDT 24
Peak memory 204004 kb
Host smart-b1bc1a45-3a66-487b-af67-ec7df96dd62e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480235922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3480235922
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.1734751501
Short name T1035
Test name
Test status
Simulation time 1714268643 ps
CPU time 5.05 seconds
Started Apr 16 02:33:36 PM PDT 24
Finished Apr 16 02:33:42 PM PDT 24
Peak memory 212188 kb
Host smart-27ed1a35-cc86-44b1-94b9-ce1b99749c58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734751501 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.1734751501
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.859816818
Short name T308
Test name
Test status
Simulation time 15482229086 ps
CPU time 5.76 seconds
Started Apr 16 02:33:40 PM PDT 24
Finished Apr 16 02:33:46 PM PDT 24
Peak memory 203944 kb
Host smart-535ec626-341b-47ce-9acf-427179ee494c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859816818 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.859816818
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1544914977
Short name T956
Test name
Test status
Simulation time 2473536472 ps
CPU time 9.87 seconds
Started Apr 16 02:33:37 PM PDT 24
Finished Apr 16 02:33:47 PM PDT 24
Peak memory 204048 kb
Host smart-be612dd8-0fb4-4f57-ba44-c899ab6bd3c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544914977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1544914977
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.2909522568
Short name T1181
Test name
Test status
Simulation time 53660109972 ps
CPU time 309.41 seconds
Started Apr 16 02:33:38 PM PDT 24
Finished Apr 16 02:38:49 PM PDT 24
Peak memory 2526036 kb
Host smart-5bd3c357-d4d7-4fb6-a09c-753270e2ae48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909522568 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.2909522568
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.341606268
Short name T828
Test name
Test status
Simulation time 1083549379 ps
CPU time 4.89 seconds
Started Apr 16 02:33:39 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 204020 kb
Host smart-a5cb02e1-8c3b-4db5-8f96-3116810c10e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341606268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.341606268
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2347375838
Short name T1234
Test name
Test status
Simulation time 60754113669 ps
CPU time 672.66 seconds
Started Apr 16 02:33:37 PM PDT 24
Finished Apr 16 02:44:51 PM PDT 24
Peak memory 5112224 kb
Host smart-26a0365a-61ec-4706-9b72-ae3f977816be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347375838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2347375838
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2027853547
Short name T635
Test name
Test status
Simulation time 7624107907 ps
CPU time 11.7 seconds
Started Apr 16 02:33:39 PM PDT 24
Finished Apr 16 02:33:51 PM PDT 24
Peak memory 318572 kb
Host smart-943a8e19-777f-4252-a793-9a3c908f4da3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027853547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2027853547
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1899750057
Short name T1018
Test name
Test status
Simulation time 1555730984 ps
CPU time 7.25 seconds
Started Apr 16 02:33:37 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 220132 kb
Host smart-6a93c5f4-6cbe-4b41-ba9f-95f4501f8daa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899750057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1899750057
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2144343507
Short name T1138
Test name
Test status
Simulation time 15373535 ps
CPU time 0.61 seconds
Started Apr 16 02:31:50 PM PDT 24
Finished Apr 16 02:31:51 PM PDT 24
Peak memory 203532 kb
Host smart-4ef97de9-70f6-4968-a99d-664a82bfc9d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144343507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2144343507
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.4192706192
Short name T739
Test name
Test status
Simulation time 87643349 ps
CPU time 1.21 seconds
Started Apr 16 02:31:38 PM PDT 24
Finished Apr 16 02:31:40 PM PDT 24
Peak memory 212232 kb
Host smart-10b3e934-9b14-44cf-9b5e-176fff8b9c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192706192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.4192706192
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.3448770673
Short name T284
Test name
Test status
Simulation time 235887598 ps
CPU time 4.33 seconds
Started Apr 16 02:31:39 PM PDT 24
Finished Apr 16 02:31:44 PM PDT 24
Peak memory 250620 kb
Host smart-a000aa44-a950-4003-8330-696ea53d864e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448770673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.3448770673
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.881218652
Short name T1089
Test name
Test status
Simulation time 1119528887 ps
CPU time 70.16 seconds
Started Apr 16 02:31:41 PM PDT 24
Finished Apr 16 02:32:52 PM PDT 24
Peak memory 475668 kb
Host smart-332948ab-0518-4414-96a0-08db27eeaec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881218652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.881218652
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3533872930
Short name T403
Test name
Test status
Simulation time 5905347804 ps
CPU time 51.18 seconds
Started Apr 16 02:31:42 PM PDT 24
Finished Apr 16 02:32:34 PM PDT 24
Peak memory 646248 kb
Host smart-71003357-92fd-4cb8-bbff-63e1023eacbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533872930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3533872930
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3735239960
Short name T495
Test name
Test status
Simulation time 224158085 ps
CPU time 1.01 seconds
Started Apr 16 02:31:41 PM PDT 24
Finished Apr 16 02:31:43 PM PDT 24
Peak memory 203892 kb
Host smart-ecef12fe-f4b2-4967-8ac7-66413548d3e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735239960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3735239960
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.1034031126
Short name T620
Test name
Test status
Simulation time 1722736497 ps
CPU time 3.17 seconds
Started Apr 16 02:31:42 PM PDT 24
Finished Apr 16 02:31:46 PM PDT 24
Peak memory 203928 kb
Host smart-d3565352-73b8-4b0e-9771-533a8384c769
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034031126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
1034031126
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3564365240
Short name T169
Test name
Test status
Simulation time 72565548262 ps
CPU time 113 seconds
Started Apr 16 02:31:42 PM PDT 24
Finished Apr 16 02:33:36 PM PDT 24
Peak memory 1232744 kb
Host smart-ed1d1617-707a-4826-a922-cc1356053d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564365240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3564365240
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1872542556
Short name T383
Test name
Test status
Simulation time 323342192 ps
CPU time 5.37 seconds
Started Apr 16 02:31:50 PM PDT 24
Finished Apr 16 02:31:56 PM PDT 24
Peak memory 203984 kb
Host smart-bcda5d22-4974-41c4-8695-2fa2bdef4b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872542556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1872542556
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3446739179
Short name T699
Test name
Test status
Simulation time 1247681758 ps
CPU time 19.92 seconds
Started Apr 16 02:31:44 PM PDT 24
Finished Apr 16 02:32:05 PM PDT 24
Peak memory 314812 kb
Host smart-3b97b853-aae1-43e8-b424-1833eb9ec5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446739179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3446739179
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1592263700
Short name T364
Test name
Test status
Simulation time 84946283 ps
CPU time 0.67 seconds
Started Apr 16 02:31:42 PM PDT 24
Finished Apr 16 02:31:43 PM PDT 24
Peak memory 203652 kb
Host smart-6dc225de-b933-44c3-9087-5d335867e3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592263700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1592263700
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.106873756
Short name T915
Test name
Test status
Simulation time 6857253993 ps
CPU time 51.76 seconds
Started Apr 16 02:31:41 PM PDT 24
Finished Apr 16 02:32:33 PM PDT 24
Peak memory 281140 kb
Host smart-f04f9b8f-e249-47d3-97db-072648b896a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106873756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.106873756
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2622981759
Short name T1185
Test name
Test status
Simulation time 4715352601 ps
CPU time 21.69 seconds
Started Apr 16 02:31:36 PM PDT 24
Finished Apr 16 02:31:59 PM PDT 24
Peak memory 287664 kb
Host smart-33232d8f-8ae4-47db-8beb-6ee4a5185407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622981759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2622981759
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.378469564
Short name T1153
Test name
Test status
Simulation time 15117573610 ps
CPU time 859.43 seconds
Started Apr 16 02:31:40 PM PDT 24
Finished Apr 16 02:46:00 PM PDT 24
Peak memory 1844520 kb
Host smart-969c5ad8-cea8-49b5-92a3-234cacec36d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378469564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.378469564
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1811141304
Short name T506
Test name
Test status
Simulation time 3196412871 ps
CPU time 28.05 seconds
Started Apr 16 02:31:42 PM PDT 24
Finished Apr 16 02:32:11 PM PDT 24
Peak memory 213324 kb
Host smart-51545c5d-f9cd-47e2-9df8-f94fd8b96a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811141304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1811141304
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2620207663
Short name T113
Test name
Test status
Simulation time 64964713 ps
CPU time 0.89 seconds
Started Apr 16 02:31:50 PM PDT 24
Finished Apr 16 02:31:52 PM PDT 24
Peak memory 222076 kb
Host smart-d13f7cd6-e724-4fa4-be2f-80f7bf612166
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620207663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2620207663
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1058391006
Short name T1048
Test name
Test status
Simulation time 626726837 ps
CPU time 3.63 seconds
Started Apr 16 02:31:44 PM PDT 24
Finished Apr 16 02:31:49 PM PDT 24
Peak memory 204008 kb
Host smart-c76e3a85-c692-4a3b-9e1d-576d0b57e829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058391006 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1058391006
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2364246008
Short name T465
Test name
Test status
Simulation time 10125135937 ps
CPU time 68.8 seconds
Started Apr 16 02:31:47 PM PDT 24
Finished Apr 16 02:32:56 PM PDT 24
Peak memory 495964 kb
Host smart-1ef62a8c-51b6-4bb6-840e-32b388720e43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364246008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2364246008
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2326409150
Short name T797
Test name
Test status
Simulation time 10041153895 ps
CPU time 68.21 seconds
Started Apr 16 02:31:43 PM PDT 24
Finished Apr 16 02:32:53 PM PDT 24
Peak memory 542436 kb
Host smart-4938907d-fe82-48e9-928f-0fad10506fcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326409150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2326409150
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3035477486
Short name T289
Test name
Test status
Simulation time 1078243680 ps
CPU time 3.1 seconds
Started Apr 16 02:31:48 PM PDT 24
Finished Apr 16 02:31:51 PM PDT 24
Peak memory 203996 kb
Host smart-3197cac9-995b-4d73-aa49-bffd0068593e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035477486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3035477486
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3065670242
Short name T866
Test name
Test status
Simulation time 972412946 ps
CPU time 4.84 seconds
Started Apr 16 02:31:44 PM PDT 24
Finished Apr 16 02:31:50 PM PDT 24
Peak memory 208620 kb
Host smart-bbf08ffb-8a92-4dc8-9e88-64f950499ccd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065670242 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3065670242
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3801071090
Short name T440
Test name
Test status
Simulation time 11323268265 ps
CPU time 8.94 seconds
Started Apr 16 02:31:44 PM PDT 24
Finished Apr 16 02:31:54 PM PDT 24
Peak memory 266236 kb
Host smart-795f84b5-2078-4b1b-8ce0-712be14b4ca1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801071090 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3801071090
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.4040770251
Short name T1039
Test name
Test status
Simulation time 7290163648 ps
CPU time 14.64 seconds
Started Apr 16 02:31:39 PM PDT 24
Finished Apr 16 02:31:54 PM PDT 24
Peak memory 204064 kb
Host smart-4af6f4c0-8fe4-4c61-a017-570e286d0cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040770251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.4040770251
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.1109855011
Short name T478
Test name
Test status
Simulation time 8972702197 ps
CPU time 51.08 seconds
Started Apr 16 02:31:43 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 290204 kb
Host smart-8783176b-764e-4fb9-a28d-097523645883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109855011 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.1109855011
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1657270274
Short name T228
Test name
Test status
Simulation time 1533035100 ps
CPU time 24.97 seconds
Started Apr 16 02:31:44 PM PDT 24
Finished Apr 16 02:32:10 PM PDT 24
Peak memory 204028 kb
Host smart-b95a16df-dba9-4ba1-90d8-58641ee57859
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657270274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1657270274
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.176868438
Short name T303
Test name
Test status
Simulation time 42371982830 ps
CPU time 19.03 seconds
Started Apr 16 02:31:40 PM PDT 24
Finished Apr 16 02:31:59 PM PDT 24
Peak memory 457144 kb
Host smart-7165a275-527c-45d7-beb5-746786508f21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176868438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.176868438
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.971805932
Short name T867
Test name
Test status
Simulation time 32592178077 ps
CPU time 2049.88 seconds
Started Apr 16 02:31:43 PM PDT 24
Finished Apr 16 03:05:54 PM PDT 24
Peak memory 3900080 kb
Host smart-40e2b68b-4177-4e43-bac7-559519c40aa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971805932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.971805932
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3775571908
Short name T846
Test name
Test status
Simulation time 2696599252 ps
CPU time 6.89 seconds
Started Apr 16 02:31:46 PM PDT 24
Finished Apr 16 02:31:54 PM PDT 24
Peak memory 212296 kb
Host smart-f330e269-f289-49f5-9b0b-bbe8c19b9b85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775571908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3775571908
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.3956611329
Short name T493
Test name
Test status
Simulation time 917944584 ps
CPU time 6.35 seconds
Started Apr 16 02:31:46 PM PDT 24
Finished Apr 16 02:31:53 PM PDT 24
Peak memory 203956 kb
Host smart-3fa03c82-5201-4a3b-ba29-f165e49c1b90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956611329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.3956611329
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.4040769473
Short name T1223
Test name
Test status
Simulation time 19162258 ps
CPU time 0.61 seconds
Started Apr 16 02:33:47 PM PDT 24
Finished Apr 16 02:33:48 PM PDT 24
Peak memory 203620 kb
Host smart-714c37aa-3321-4b53-87a6-6f756e8bfa04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040769473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.4040769473
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3728479176
Short name T1357
Test name
Test status
Simulation time 77873739 ps
CPU time 1.13 seconds
Started Apr 16 02:33:43 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 212296 kb
Host smart-d0974d88-8bdb-4d4d-a9b5-ab8fd3311e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728479176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3728479176
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1578582880
Short name T411
Test name
Test status
Simulation time 523500158 ps
CPU time 8.86 seconds
Started Apr 16 02:33:42 PM PDT 24
Finished Apr 16 02:33:52 PM PDT 24
Peak memory 304088 kb
Host smart-678513d1-2f55-408e-9487-50ea59fe4920
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578582880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1578582880
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3655396517
Short name T832
Test name
Test status
Simulation time 21720145960 ps
CPU time 87.81 seconds
Started Apr 16 02:33:42 PM PDT 24
Finished Apr 16 02:35:11 PM PDT 24
Peak memory 798736 kb
Host smart-f6f052bc-8ee2-4c41-8b71-19a5452522ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655396517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3655396517
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.151847991
Short name T1160
Test name
Test status
Simulation time 7026306727 ps
CPU time 147.47 seconds
Started Apr 16 02:33:42 PM PDT 24
Finished Apr 16 02:36:10 PM PDT 24
Peak memory 693028 kb
Host smart-fded1c2b-5e56-407c-bc0b-fa4f90c67d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151847991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.151847991
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1224091541
Short name T1134
Test name
Test status
Simulation time 486706203 ps
CPU time 0.84 seconds
Started Apr 16 02:33:41 PM PDT 24
Finished Apr 16 02:33:43 PM PDT 24
Peak memory 203744 kb
Host smart-b5daf6e1-e705-402a-a659-ac878119e566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224091541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1224091541
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3534505130
Short name T502
Test name
Test status
Simulation time 570585930 ps
CPU time 8.67 seconds
Started Apr 16 02:33:43 PM PDT 24
Finished Apr 16 02:33:53 PM PDT 24
Peak memory 231324 kb
Host smart-4875f1a8-1bb8-40d9-86e9-05c438e9258a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534505130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3534505130
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3039508427
Short name T173
Test name
Test status
Simulation time 2813424418 ps
CPU time 62.33 seconds
Started Apr 16 02:33:42 PM PDT 24
Finished Apr 16 02:34:46 PM PDT 24
Peak memory 852168 kb
Host smart-5ad5bf03-133c-480a-8df2-f4a116f65308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039508427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3039508427
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.105518153
Short name T787
Test name
Test status
Simulation time 2466077649 ps
CPU time 16.13 seconds
Started Apr 16 02:33:49 PM PDT 24
Finished Apr 16 02:34:06 PM PDT 24
Peak memory 204016 kb
Host smart-1f96e38b-bbbe-4945-a78a-7244b3464e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105518153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.105518153
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3471769544
Short name T1254
Test name
Test status
Simulation time 2749684932 ps
CPU time 58.93 seconds
Started Apr 16 02:33:45 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 277196 kb
Host smart-486987e9-6473-403f-b6a5-83b40b7fe2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471769544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3471769544
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3481764088
Short name T583
Test name
Test status
Simulation time 28165157 ps
CPU time 0.68 seconds
Started Apr 16 02:33:43 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 203652 kb
Host smart-ad1e179d-7010-4014-9032-289f98ff0d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481764088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3481764088
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2979581907
Short name T1286
Test name
Test status
Simulation time 24993828841 ps
CPU time 509.78 seconds
Started Apr 16 02:33:44 PM PDT 24
Finished Apr 16 02:42:14 PM PDT 24
Peak memory 212260 kb
Host smart-88f7e53e-d757-4168-8b1c-44017f64e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979581907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2979581907
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1793843994
Short name T916
Test name
Test status
Simulation time 1359510162 ps
CPU time 25.1 seconds
Started Apr 16 02:33:42 PM PDT 24
Finished Apr 16 02:34:08 PM PDT 24
Peak memory 299116 kb
Host smart-0ee6acf6-b75b-4487-8425-25249260d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793843994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1793843994
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3128600587
Short name T293
Test name
Test status
Simulation time 4340180692 ps
CPU time 323.55 seconds
Started Apr 16 02:33:42 PM PDT 24
Finished Apr 16 02:39:07 PM PDT 24
Peak memory 778564 kb
Host smart-0ea7002a-006c-4eba-8606-881607bacb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128600587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3128600587
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.431293144
Short name T847
Test name
Test status
Simulation time 2450948110 ps
CPU time 26.27 seconds
Started Apr 16 02:33:46 PM PDT 24
Finished Apr 16 02:34:13 PM PDT 24
Peak memory 212288 kb
Host smart-844d67c2-c952-45e3-8bcf-fab02e87056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431293144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.431293144
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.4025083860
Short name T195
Test name
Test status
Simulation time 1136478619 ps
CPU time 2.58 seconds
Started Apr 16 02:33:47 PM PDT 24
Finished Apr 16 02:33:51 PM PDT 24
Peak memory 203976 kb
Host smart-2238cc9f-aecc-4df3-a0fb-e8e47380beb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025083860 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.4025083860
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.905574342
Short name T52
Test name
Test status
Simulation time 10107897177 ps
CPU time 34.71 seconds
Started Apr 16 02:33:45 PM PDT 24
Finished Apr 16 02:34:21 PM PDT 24
Peak memory 403144 kb
Host smart-94a434ad-5c4f-4e8f-9251-5baaee78a7d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905574342 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.905574342
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1473513166
Short name T450
Test name
Test status
Simulation time 10059864466 ps
CPU time 66.82 seconds
Started Apr 16 02:33:48 PM PDT 24
Finished Apr 16 02:34:56 PM PDT 24
Peak memory 525132 kb
Host smart-afeb6c4b-4698-42bf-9906-4396105be3ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473513166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1473513166
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.4291727711
Short name T758
Test name
Test status
Simulation time 894634172 ps
CPU time 2.64 seconds
Started Apr 16 02:33:47 PM PDT 24
Finished Apr 16 02:33:50 PM PDT 24
Peak memory 204016 kb
Host smart-37c90d3b-0dbf-4ad3-8623-fd38e6642b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291727711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.4291727711
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.548201166
Short name T853
Test name
Test status
Simulation time 734202635 ps
CPU time 3.85 seconds
Started Apr 16 02:33:48 PM PDT 24
Finished Apr 16 02:33:53 PM PDT 24
Peak memory 204024 kb
Host smart-fe987f0e-bf03-492e-8550-9a91e6ec19eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548201166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.548201166
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.703025968
Short name T423
Test name
Test status
Simulation time 8621907971 ps
CPU time 12.74 seconds
Started Apr 16 02:33:46 PM PDT 24
Finished Apr 16 02:33:59 PM PDT 24
Peak memory 305180 kb
Host smart-8fd29a0c-d060-4ac1-bfb6-35d39e7c51b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703025968 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.703025968
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2829129522
Short name T1013
Test name
Test status
Simulation time 979597850 ps
CPU time 38.69 seconds
Started Apr 16 02:33:46 PM PDT 24
Finished Apr 16 02:34:25 PM PDT 24
Peak memory 203944 kb
Host smart-51bbb7d3-8423-4590-96f5-5faf3e6d7a07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829129522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2829129522
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3378143930
Short name T920
Test name
Test status
Simulation time 2975396588 ps
CPU time 11.73 seconds
Started Apr 16 02:33:48 PM PDT 24
Finished Apr 16 02:34:01 PM PDT 24
Peak memory 208544 kb
Host smart-1925d67f-78e0-438b-99f3-1462c2b8e9e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378143930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3378143930
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.1895845445
Short name T488
Test name
Test status
Simulation time 19647190659 ps
CPU time 3.23 seconds
Started Apr 16 02:33:46 PM PDT 24
Finished Apr 16 02:33:50 PM PDT 24
Peak memory 204084 kb
Host smart-96b57ab1-8c5a-45b4-aed5-3649321dfd09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895845445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.1895845445
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.649183185
Short name T368
Test name
Test status
Simulation time 9845018790 ps
CPU time 410.66 seconds
Started Apr 16 02:33:48 PM PDT 24
Finished Apr 16 02:40:39 PM PDT 24
Peak memory 2397844 kb
Host smart-ca98f687-8a5d-4fe7-9ef7-f156dc53321e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649183185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.649183185
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2105815191
Short name T1107
Test name
Test status
Simulation time 9239348262 ps
CPU time 6.68 seconds
Started Apr 16 02:33:45 PM PDT 24
Finished Apr 16 02:33:52 PM PDT 24
Peak memory 204048 kb
Host smart-3ab8f124-7965-4b87-b213-695d8017d27c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105815191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2105815191
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3044005664
Short name T922
Test name
Test status
Simulation time 20512345 ps
CPU time 0.61 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:33:59 PM PDT 24
Peak memory 203544 kb
Host smart-8ed57a19-5d22-49b4-8c84-7370f8cd033c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044005664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3044005664
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.150326045
Short name T481
Test name
Test status
Simulation time 392684356 ps
CPU time 1.3 seconds
Started Apr 16 02:33:53 PM PDT 24
Finished Apr 16 02:33:55 PM PDT 24
Peak memory 212312 kb
Host smart-4a063b7b-b55f-4e3a-ad2e-8ebd8120cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150326045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.150326045
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1954677668
Short name T1335
Test name
Test status
Simulation time 370915278 ps
CPU time 13.31 seconds
Started Apr 16 02:33:53 PM PDT 24
Finished Apr 16 02:34:07 PM PDT 24
Peak memory 255764 kb
Host smart-ab6b80d9-8951-4a7b-8f40-1191010d8418
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954677668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.1954677668
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.4045785906
Short name T1210
Test name
Test status
Simulation time 5694001071 ps
CPU time 33.46 seconds
Started Apr 16 02:33:52 PM PDT 24
Finished Apr 16 02:34:27 PM PDT 24
Peak memory 424024 kb
Host smart-1bd04552-6a32-4b4d-9276-b4dee5d28fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045785906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.4045785906
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.450282269
Short name T552
Test name
Test status
Simulation time 1667576759 ps
CPU time 120.55 seconds
Started Apr 16 02:33:47 PM PDT 24
Finished Apr 16 02:35:48 PM PDT 24
Peak memory 613356 kb
Host smart-8f795388-12d5-4b19-8fd5-47d5ca169c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450282269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.450282269
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1151823922
Short name T713
Test name
Test status
Simulation time 137683187 ps
CPU time 1.12 seconds
Started Apr 16 02:33:48 PM PDT 24
Finished Apr 16 02:33:50 PM PDT 24
Peak memory 203968 kb
Host smart-70b04676-4239-4984-85bd-81ba6db140ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151823922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1151823922
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.965025914
Short name T1017
Test name
Test status
Simulation time 960174541 ps
CPU time 2.8 seconds
Started Apr 16 02:33:50 PM PDT 24
Finished Apr 16 02:33:54 PM PDT 24
Peak memory 216368 kb
Host smart-71c7947f-a7d6-4ee9-a0cd-3318468fc622
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965025914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
965025914
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3697246208
Short name T379
Test name
Test status
Simulation time 2769203830 ps
CPU time 23.81 seconds
Started Apr 16 02:33:58 PM PDT 24
Finished Apr 16 02:34:22 PM PDT 24
Peak memory 204032 kb
Host smart-28a61831-8253-469f-9cb7-67afb23c1059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697246208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3697246208
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.346695807
Short name T187
Test name
Test status
Simulation time 327627247 ps
CPU time 0.72 seconds
Started Apr 16 02:33:51 PM PDT 24
Finished Apr 16 02:33:53 PM PDT 24
Peak memory 203672 kb
Host smart-8aa471e5-0de1-47bc-b9d9-ed96367949ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346695807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.346695807
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3333466347
Short name T889
Test name
Test status
Simulation time 11890604180 ps
CPU time 73.35 seconds
Started Apr 16 02:33:52 PM PDT 24
Finished Apr 16 02:35:06 PM PDT 24
Peak memory 213584 kb
Host smart-9b653cdf-898f-4e4a-8e59-ec1341d2751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333466347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3333466347
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1521235796
Short name T533
Test name
Test status
Simulation time 2790939706 ps
CPU time 65.49 seconds
Started Apr 16 02:33:47 PM PDT 24
Finished Apr 16 02:34:53 PM PDT 24
Peak memory 311316 kb
Host smart-e534a2a4-7026-47f3-8934-88f179210ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521235796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1521235796
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2432636884
Short name T446
Test name
Test status
Simulation time 2898356651 ps
CPU time 6.46 seconds
Started Apr 16 02:33:51 PM PDT 24
Finished Apr 16 02:33:58 PM PDT 24
Peak memory 217148 kb
Host smart-53f7c92c-0d75-45f7-a288-a4ac7e2574a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432636884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2432636884
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2457496542
Short name T116
Test name
Test status
Simulation time 3329931556 ps
CPU time 3.77 seconds
Started Apr 16 02:33:53 PM PDT 24
Finished Apr 16 02:33:58 PM PDT 24
Peak memory 212236 kb
Host smart-f1a6839b-456f-4bbf-845c-0e262e4fdb48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457496542 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2457496542
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2983221842
Short name T342
Test name
Test status
Simulation time 10131475560 ps
CPU time 16.72 seconds
Started Apr 16 02:33:52 PM PDT 24
Finished Apr 16 02:34:10 PM PDT 24
Peak memory 288200 kb
Host smart-02acf730-1a27-4563-9db8-9ea2e69b4340
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983221842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2983221842
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.872329683
Short name T905
Test name
Test status
Simulation time 10420046052 ps
CPU time 14.46 seconds
Started Apr 16 02:33:53 PM PDT 24
Finished Apr 16 02:34:08 PM PDT 24
Peak memory 307532 kb
Host smart-7c7f58e0-e82f-41a2-9d97-5d706f23a340
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872329683 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.872329683
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.593581421
Short name T911
Test name
Test status
Simulation time 332064836 ps
CPU time 2 seconds
Started Apr 16 02:33:58 PM PDT 24
Finished Apr 16 02:34:01 PM PDT 24
Peak memory 204020 kb
Host smart-d2403118-13e7-476f-a648-73ce6063300f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593581421 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.593581421
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1528298889
Short name T270
Test name
Test status
Simulation time 10408262429 ps
CPU time 6.27 seconds
Started Apr 16 02:33:53 PM PDT 24
Finished Apr 16 02:34:00 PM PDT 24
Peak memory 212296 kb
Host smart-40f0234b-6c3f-49fa-a3b0-798d119d0f33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528298889 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1528298889
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1599986521
Short name T1349
Test name
Test status
Simulation time 9240770762 ps
CPU time 5.54 seconds
Started Apr 16 02:33:51 PM PDT 24
Finished Apr 16 02:33:57 PM PDT 24
Peak memory 204084 kb
Host smart-4caf2bf5-924a-4b76-89b3-c3f74d3e1a80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599986521 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1599986521
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.459235527
Short name T246
Test name
Test status
Simulation time 2470909546 ps
CPU time 16.44 seconds
Started Apr 16 02:33:51 PM PDT 24
Finished Apr 16 02:34:08 PM PDT 24
Peak memory 204076 kb
Host smart-2caf7491-2a14-47e0-bfb3-7024424477ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459235527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.459235527
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2727721026
Short name T518
Test name
Test status
Simulation time 7411598495 ps
CPU time 77.56 seconds
Started Apr 16 02:33:51 PM PDT 24
Finished Apr 16 02:35:09 PM PDT 24
Peak memory 207672 kb
Host smart-b29f8b75-adda-4493-b07e-343f1dec763d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727721026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2727721026
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.36027294
Short name T985
Test name
Test status
Simulation time 23478614281 ps
CPU time 14.91 seconds
Started Apr 16 02:33:53 PM PDT 24
Finished Apr 16 02:34:09 PM PDT 24
Peak memory 282020 kb
Host smart-e9afc49d-6eeb-4990-9b83-0c53f0a9db36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36027294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stress_wr.36027294
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1011240043
Short name T735
Test name
Test status
Simulation time 14652876430 ps
CPU time 2315.76 seconds
Started Apr 16 02:33:50 PM PDT 24
Finished Apr 16 03:12:27 PM PDT 24
Peak memory 3677044 kb
Host smart-41085d28-a92a-4f0c-b4ea-10ba988b2005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011240043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1011240043
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2986459443
Short name T276
Test name
Test status
Simulation time 6436666421 ps
CPU time 7.39 seconds
Started Apr 16 02:33:51 PM PDT 24
Finished Apr 16 02:33:59 PM PDT 24
Peak memory 220284 kb
Host smart-f15d9b13-fa83-430d-855f-312089b97b0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986459443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2986459443
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1437928809
Short name T108
Test name
Test status
Simulation time 115988103 ps
CPU time 0.6 seconds
Started Apr 16 02:34:01 PM PDT 24
Finished Apr 16 02:34:03 PM PDT 24
Peak memory 203572 kb
Host smart-c735fb3e-94d7-4e3c-942c-c54fe4110589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437928809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1437928809
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3932990044
Short name T497
Test name
Test status
Simulation time 181700375 ps
CPU time 1.39 seconds
Started Apr 16 02:33:58 PM PDT 24
Finished Apr 16 02:34:00 PM PDT 24
Peak memory 212268 kb
Host smart-c83bb8e9-29b1-4c03-84f6-da7a6975d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932990044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3932990044
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.486609617
Short name T1148
Test name
Test status
Simulation time 408392002 ps
CPU time 20.56 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:34:18 PM PDT 24
Peak memory 292104 kb
Host smart-25f9b086-a050-43f6-b950-589e41aa935a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486609617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.486609617
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2863177377
Short name T704
Test name
Test status
Simulation time 28301474072 ps
CPU time 39.54 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:34:37 PM PDT 24
Peak memory 525700 kb
Host smart-682e1955-f7d6-4fab-b430-c733018fc7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863177377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2863177377
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.424557050
Short name T1015
Test name
Test status
Simulation time 1405385478 ps
CPU time 92.95 seconds
Started Apr 16 02:34:00 PM PDT 24
Finished Apr 16 02:35:33 PM PDT 24
Peak memory 536036 kb
Host smart-45873f57-546a-4b2f-855d-535a8d579dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424557050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.424557050
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2736559867
Short name T310
Test name
Test status
Simulation time 333905121 ps
CPU time 0.82 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:33:58 PM PDT 24
Peak memory 203704 kb
Host smart-3df22c75-a924-40e7-848d-1022c6e7ee7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736559867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2736559867
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.446466203
Short name T768
Test name
Test status
Simulation time 248698825 ps
CPU time 3.69 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:34:01 PM PDT 24
Peak memory 203912 kb
Host smart-20fe9f6d-b802-4c4d-a10d-d06456cddf89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446466203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
446466203
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3887062651
Short name T88
Test name
Test status
Simulation time 2254582414 ps
CPU time 132.7 seconds
Started Apr 16 02:33:59 PM PDT 24
Finished Apr 16 02:36:12 PM PDT 24
Peak memory 687952 kb
Host smart-6533f3eb-8150-4636-b428-74038936edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887062651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3887062651
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3782763479
Short name T1108
Test name
Test status
Simulation time 1642753650 ps
CPU time 16.72 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:34:24 PM PDT 24
Peak memory 204000 kb
Host smart-d78186b4-5bb1-44bc-a148-7cdf30399fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782763479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3782763479
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3091666771
Short name T505
Test name
Test status
Simulation time 3807936318 ps
CPU time 79.05 seconds
Started Apr 16 02:34:05 PM PDT 24
Finished Apr 16 02:35:25 PM PDT 24
Peak memory 354980 kb
Host smart-60813aa8-f2e7-4f02-8f10-5c1e7ce057ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091666771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3091666771
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2501313042
Short name T952
Test name
Test status
Simulation time 47025962 ps
CPU time 0.61 seconds
Started Apr 16 02:33:55 PM PDT 24
Finished Apr 16 02:33:56 PM PDT 24
Peak memory 203648 kb
Host smart-d1adbabe-3ccf-4a57-8e6a-31e5ffa6a225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501313042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2501313042
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1379205686
Short name T595
Test name
Test status
Simulation time 1124123016 ps
CPU time 21.86 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:34:20 PM PDT 24
Peak memory 301060 kb
Host smart-5bf91c37-3a93-46f0-a839-9a8d8ccfaaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379205686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1379205686
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1816006178
Short name T1315
Test name
Test status
Simulation time 1341446736 ps
CPU time 10.89 seconds
Started Apr 16 02:33:58 PM PDT 24
Finished Apr 16 02:34:10 PM PDT 24
Peak memory 220320 kb
Host smart-8f16214c-93cf-44b6-8bdf-9e7d1c001781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816006178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1816006178
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2140351858
Short name T851
Test name
Test status
Simulation time 13888761457 ps
CPU time 3.56 seconds
Started Apr 16 02:34:01 PM PDT 24
Finished Apr 16 02:34:06 PM PDT 24
Peak memory 204068 kb
Host smart-b9f8cb8f-96f8-42c7-9037-b8615c296135
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140351858 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2140351858
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3600029720
Short name T686
Test name
Test status
Simulation time 10222115052 ps
CPU time 25.16 seconds
Started Apr 16 02:34:03 PM PDT 24
Finished Apr 16 02:34:29 PM PDT 24
Peak memory 311504 kb
Host smart-ed9536cc-b456-4040-bccc-f83752268458
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600029720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3600029720
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3211388925
Short name T356
Test name
Test status
Simulation time 10117217514 ps
CPU time 11.04 seconds
Started Apr 16 02:34:02 PM PDT 24
Finished Apr 16 02:34:14 PM PDT 24
Peak memory 271460 kb
Host smart-daa5e704-7636-4fe1-bf87-af3cf4b4f959
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211388925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3211388925
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.485792159
Short name T14
Test name
Test status
Simulation time 386670058 ps
CPU time 2.2 seconds
Started Apr 16 02:34:01 PM PDT 24
Finished Apr 16 02:34:04 PM PDT 24
Peak memory 204036 kb
Host smart-949cf518-1cac-4c6e-bbd4-7dc83013249b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485792159 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.485792159
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3671243516
Short name T683
Test name
Test status
Simulation time 2447023445 ps
CPU time 3.48 seconds
Started Apr 16 02:33:58 PM PDT 24
Finished Apr 16 02:34:02 PM PDT 24
Peak memory 204084 kb
Host smart-2e2d3c45-5e52-45bb-9a12-fa7c15248e25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671243516 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3671243516
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.211216750
Short name T1115
Test name
Test status
Simulation time 2743850821 ps
CPU time 3.79 seconds
Started Apr 16 02:33:59 PM PDT 24
Finished Apr 16 02:34:04 PM PDT 24
Peak memory 204024 kb
Host smart-b7eb5e0c-8030-4736-be74-2d93a3326bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211216750 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.211216750
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.2532836948
Short name T641
Test name
Test status
Simulation time 1336363350 ps
CPU time 8.53 seconds
Started Apr 16 02:33:55 PM PDT 24
Finished Apr 16 02:34:05 PM PDT 24
Peak memory 204012 kb
Host smart-64bb3371-8274-48eb-a7bc-3bc3364b8318
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532836948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.2532836948
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.297864823
Short name T203
Test name
Test status
Simulation time 5837659507 ps
CPU time 28.04 seconds
Started Apr 16 02:33:59 PM PDT 24
Finished Apr 16 02:34:27 PM PDT 24
Peak memory 225308 kb
Host smart-59f420ea-5ad3-4d54-80dc-683bd1324317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297864823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.297864823
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1091524666
Short name T898
Test name
Test status
Simulation time 25525645488 ps
CPU time 100.8 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:35:39 PM PDT 24
Peak memory 1407360 kb
Host smart-afc5cbcf-4688-4e48-974f-8687874a5059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091524666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1091524666
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1527302473
Short name T117
Test name
Test status
Simulation time 3244533217 ps
CPU time 6.2 seconds
Started Apr 16 02:33:57 PM PDT 24
Finished Apr 16 02:34:04 PM PDT 24
Peak memory 220268 kb
Host smart-950fa00e-144e-4d6b-b678-29b63c03f0fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527302473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1527302473
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1442432586
Short name T1065
Test name
Test status
Simulation time 24427680 ps
CPU time 0.59 seconds
Started Apr 16 02:34:11 PM PDT 24
Finished Apr 16 02:34:12 PM PDT 24
Peak memory 203552 kb
Host smart-cd41a92c-3b34-4502-83bc-d8680f000d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442432586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1442432586
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2561749075
Short name T530
Test name
Test status
Simulation time 87974141 ps
CPU time 1.45 seconds
Started Apr 16 02:34:05 PM PDT 24
Finished Apr 16 02:34:07 PM PDT 24
Peak memory 212260 kb
Host smart-9c35ecc8-bb8a-4d77-a16b-6b195a880dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561749075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2561749075
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3587257042
Short name T989
Test name
Test status
Simulation time 441628059 ps
CPU time 11.31 seconds
Started Apr 16 02:34:04 PM PDT 24
Finished Apr 16 02:34:16 PM PDT 24
Peak memory 244040 kb
Host smart-c50a6282-5133-4996-9523-21e1b0e6efef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587257042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3587257042
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2311619093
Short name T476
Test name
Test status
Simulation time 3086697342 ps
CPU time 50.1 seconds
Started Apr 16 02:34:03 PM PDT 24
Finished Apr 16 02:34:54 PM PDT 24
Peak memory 573236 kb
Host smart-c2751321-d74f-466d-b235-6f762b1488aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311619093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2311619093
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2803321888
Short name T406
Test name
Test status
Simulation time 8622440061 ps
CPU time 27.72 seconds
Started Apr 16 02:34:02 PM PDT 24
Finished Apr 16 02:34:31 PM PDT 24
Peak memory 452896 kb
Host smart-9ec1ff42-008d-4d39-90d8-6e5f772b9fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803321888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2803321888
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2591924549
Short name T466
Test name
Test status
Simulation time 81368192 ps
CPU time 0.89 seconds
Started Apr 16 02:34:08 PM PDT 24
Finished Apr 16 02:34:10 PM PDT 24
Peak memory 203688 kb
Host smart-fc39146d-f919-4bb0-ba44-460a58d0a17a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591924549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2591924549
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3399347874
Short name T1041
Test name
Test status
Simulation time 324867367 ps
CPU time 4.55 seconds
Started Apr 16 02:34:00 PM PDT 24
Finished Apr 16 02:34:05 PM PDT 24
Peak memory 234140 kb
Host smart-2bc447b4-6630-40b7-98a1-fe7c5611d101
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399347874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3399347874
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2963023692
Short name T1059
Test name
Test status
Simulation time 8292198954 ps
CPU time 299.49 seconds
Started Apr 16 02:34:02 PM PDT 24
Finished Apr 16 02:39:02 PM PDT 24
Peak memory 1159120 kb
Host smart-37fd1e97-f70e-4898-ad02-e10c0cf01f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963023692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2963023692
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.2147523720
Short name T950
Test name
Test status
Simulation time 1112704292 ps
CPU time 4.5 seconds
Started Apr 16 02:34:07 PM PDT 24
Finished Apr 16 02:34:12 PM PDT 24
Peak memory 203908 kb
Host smart-284dfb34-40d5-4a98-8f0c-b088fcc2333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147523720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2147523720
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3125297983
Short name T756
Test name
Test status
Simulation time 2238047710 ps
CPU time 48.81 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:34:56 PM PDT 24
Peak memory 299108 kb
Host smart-c8e2288e-e024-4604-8891-45077f685d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125297983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3125297983
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3144057129
Short name T438
Test name
Test status
Simulation time 27602582730 ps
CPU time 388.66 seconds
Started Apr 16 02:34:08 PM PDT 24
Finished Apr 16 02:40:37 PM PDT 24
Peak memory 779188 kb
Host smart-e8756964-e12b-4cf3-abe2-1fc78be1303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144057129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3144057129
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.953245443
Short name T594
Test name
Test status
Simulation time 5915463888 ps
CPU time 33.39 seconds
Started Apr 16 02:34:03 PM PDT 24
Finished Apr 16 02:34:38 PM PDT 24
Peak memory 406864 kb
Host smart-677168c0-3e5d-4fa8-87a6-8cf33b8c240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953245443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.953245443
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.422158326
Short name T1334
Test name
Test status
Simulation time 6123623764 ps
CPU time 526.63 seconds
Started Apr 16 02:34:00 PM PDT 24
Finished Apr 16 02:42:48 PM PDT 24
Peak memory 1195108 kb
Host smart-6a480677-16cd-4884-9b0a-8a6bb64079fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422158326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.422158326
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1084993471
Short name T762
Test name
Test status
Simulation time 2014710215 ps
CPU time 8.79 seconds
Started Apr 16 02:34:03 PM PDT 24
Finished Apr 16 02:34:12 PM PDT 24
Peak memory 216028 kb
Host smart-e8d06de3-d75e-4d1c-909c-af9dd522951c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084993471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1084993471
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1153361729
Short name T299
Test name
Test status
Simulation time 598355399 ps
CPU time 3.11 seconds
Started Apr 16 02:34:07 PM PDT 24
Finished Apr 16 02:34:11 PM PDT 24
Peak memory 203952 kb
Host smart-154bcee2-807b-4cc7-a19a-9ca4c97b0e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153361729 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1153361729
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.774124072
Short name T894
Test name
Test status
Simulation time 10106708299 ps
CPU time 49.61 seconds
Started Apr 16 02:34:08 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 459936 kb
Host smart-2966b659-234d-4da3-9f3e-0afeff93d964
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774124072 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.774124072
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.2624185247
Short name T665
Test name
Test status
Simulation time 10069139638 ps
CPU time 73.38 seconds
Started Apr 16 02:34:07 PM PDT 24
Finished Apr 16 02:35:21 PM PDT 24
Peak memory 525608 kb
Host smart-2831ea82-069e-45bd-965b-357256acc526
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624185247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.2624185247
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1930759837
Short name T647
Test name
Test status
Simulation time 2230375615 ps
CPU time 2.97 seconds
Started Apr 16 02:34:10 PM PDT 24
Finished Apr 16 02:34:13 PM PDT 24
Peak memory 204084 kb
Host smart-bf6c45c0-3d9e-4d88-a543-618b8c370d10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930759837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1930759837
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.39698653
Short name T755
Test name
Test status
Simulation time 2039446884 ps
CPU time 5.63 seconds
Started Apr 16 02:34:09 PM PDT 24
Finished Apr 16 02:34:16 PM PDT 24
Peak memory 210052 kb
Host smart-3b1c55fc-6c2f-482f-87bd-df8f3c457d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39698653 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.39698653
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1743420959
Short name T1061
Test name
Test status
Simulation time 5428572801 ps
CPU time 6.33 seconds
Started Apr 16 02:34:08 PM PDT 24
Finished Apr 16 02:34:16 PM PDT 24
Peak memory 204004 kb
Host smart-3c792812-eaa9-456b-a0f5-c7c7d2a181f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743420959 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1743420959
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2529210156
Short name T104
Test name
Test status
Simulation time 5619816699 ps
CPU time 27.17 seconds
Started Apr 16 02:34:08 PM PDT 24
Finished Apr 16 02:34:36 PM PDT 24
Peak memory 204020 kb
Host smart-6e84679d-4a1f-43e3-bf4e-ef62d6a32f15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529210156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2529210156
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2812935474
Short name T1219
Test name
Test status
Simulation time 4755007043 ps
CPU time 25.82 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:34:33 PM PDT 24
Peak memory 228232 kb
Host smart-d45337ef-42ea-4ff2-9736-1d5daa234915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812935474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2812935474
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3309455202
Short name T1325
Test name
Test status
Simulation time 29082546806 ps
CPU time 187.69 seconds
Started Apr 16 02:34:03 PM PDT 24
Finished Apr 16 02:37:11 PM PDT 24
Peak memory 2428240 kb
Host smart-7965ad04-901e-4efd-b66f-458868a96441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309455202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3309455202
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1971010745
Short name T354
Test name
Test status
Simulation time 20092410086 ps
CPU time 1200.37 seconds
Started Apr 16 02:34:09 PM PDT 24
Finished Apr 16 02:54:10 PM PDT 24
Peak memory 4779172 kb
Host smart-8a127835-64ac-4df5-9dac-9ca446ddc8cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971010745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1971010745
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2307990347
Short name T597
Test name
Test status
Simulation time 1355928943 ps
CPU time 6.05 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:34:13 PM PDT 24
Peak memory 204048 kb
Host smart-82a028b1-be9d-4c60-8efd-2e5f90b9bd97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307990347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2307990347
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3193268712
Short name T1151
Test name
Test status
Simulation time 18347274 ps
CPU time 0.62 seconds
Started Apr 16 02:34:11 PM PDT 24
Finished Apr 16 02:34:12 PM PDT 24
Peak memory 203588 kb
Host smart-00adc22c-5cd3-45d3-a722-d26a16c6cc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193268712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3193268712
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2682419313
Short name T317
Test name
Test status
Simulation time 48552175 ps
CPU time 1.13 seconds
Started Apr 16 02:34:07 PM PDT 24
Finished Apr 16 02:34:09 PM PDT 24
Peak memory 204112 kb
Host smart-10e5898f-c957-4f9b-883c-0ec17fb4a7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682419313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2682419313
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2857036256
Short name T532
Test name
Test status
Simulation time 194521209 ps
CPU time 3.66 seconds
Started Apr 16 02:34:10 PM PDT 24
Finished Apr 16 02:34:15 PM PDT 24
Peak memory 239756 kb
Host smart-68cb17c9-6788-4b88-bb00-cd93fd511865
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857036256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2857036256
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2938097062
Short name T587
Test name
Test status
Simulation time 2563782692 ps
CPU time 24.93 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:34:32 PM PDT 24
Peak memory 238152 kb
Host smart-a3e0a97f-9ff6-47ec-9046-3ac63614733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938097062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2938097062
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3603053508
Short name T1029
Test name
Test status
Simulation time 2340621806 ps
CPU time 69.86 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:35:17 PM PDT 24
Peak memory 727428 kb
Host smart-8e5d18c7-d152-41df-b9a3-a236818088fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603053508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3603053508
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3771069906
Short name T456
Test name
Test status
Simulation time 393466965 ps
CPU time 0.85 seconds
Started Apr 16 02:34:12 PM PDT 24
Finished Apr 16 02:34:13 PM PDT 24
Peak memory 203516 kb
Host smart-c2bac78d-c30c-41ab-bd5b-c44e095f7fd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771069906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3771069906
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1695739424
Short name T1026
Test name
Test status
Simulation time 163248232 ps
CPU time 4.66 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:34:11 PM PDT 24
Peak memory 231892 kb
Host smart-2db19af1-8b56-491f-8413-b15a41700613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695739424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1695739424
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3078811508
Short name T353
Test name
Test status
Simulation time 7540119139 ps
CPU time 139.17 seconds
Started Apr 16 02:34:09 PM PDT 24
Finished Apr 16 02:36:29 PM PDT 24
Peak memory 727964 kb
Host smart-15b5544c-1ef6-4ab6-801a-18d408dce804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078811508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3078811508
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1076465599
Short name T514
Test name
Test status
Simulation time 470869611 ps
CPU time 19.65 seconds
Started Apr 16 02:34:14 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 203936 kb
Host smart-46137c9d-f5fc-428c-8ba1-bef56a4a4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076465599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1076465599
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3847782539
Short name T588
Test name
Test status
Simulation time 1215891356 ps
CPU time 53.3 seconds
Started Apr 16 02:34:12 PM PDT 24
Finished Apr 16 02:35:06 PM PDT 24
Peak memory 334404 kb
Host smart-d591ac5a-a0e0-4293-ac81-8e24ccb0a074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847782539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3847782539
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3287261749
Short name T1143
Test name
Test status
Simulation time 89307857 ps
CPU time 0.66 seconds
Started Apr 16 02:34:06 PM PDT 24
Finished Apr 16 02:34:08 PM PDT 24
Peak memory 203612 kb
Host smart-8a7b7838-0d92-4aad-919a-2869eb3d0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287261749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3287261749
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1901456995
Short name T300
Test name
Test status
Simulation time 6382979127 ps
CPU time 40.67 seconds
Started Apr 16 02:34:12 PM PDT 24
Finished Apr 16 02:34:53 PM PDT 24
Peak memory 596132 kb
Host smart-a7f6805b-04df-491e-9af7-69ba70a80f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901456995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1901456995
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2657883833
Short name T979
Test name
Test status
Simulation time 1544933236 ps
CPU time 21.36 seconds
Started Apr 16 02:34:08 PM PDT 24
Finished Apr 16 02:34:30 PM PDT 24
Peak memory 301516 kb
Host smart-618d01e8-425f-427f-9997-48926609b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657883833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2657883833
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2032921019
Short name T118
Test name
Test status
Simulation time 8811948627 ps
CPU time 374.33 seconds
Started Apr 16 02:34:09 PM PDT 24
Finished Apr 16 02:40:24 PM PDT 24
Peak memory 1801872 kb
Host smart-35bd7364-e7f3-4203-b56e-92024d6ad801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032921019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2032921019
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3041835586
Short name T349
Test name
Test status
Simulation time 3620268707 ps
CPU time 40.11 seconds
Started Apr 16 02:34:08 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 220448 kb
Host smart-570554fb-83ad-46b7-a250-81a0fa40c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041835586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3041835586
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.716226101
Short name T609
Test name
Test status
Simulation time 1195286252 ps
CPU time 3.25 seconds
Started Apr 16 02:34:09 PM PDT 24
Finished Apr 16 02:34:14 PM PDT 24
Peak memory 212180 kb
Host smart-a41a39f9-90e4-4120-9838-328a655ab11f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716226101 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.716226101
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.548935010
Short name T1201
Test name
Test status
Simulation time 10079928018 ps
CPU time 66.19 seconds
Started Apr 16 02:34:16 PM PDT 24
Finished Apr 16 02:35:23 PM PDT 24
Peak memory 520692 kb
Host smart-c376a9e7-003c-423b-a932-ec3c4fce740e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548935010 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.548935010
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2387524823
Short name T902
Test name
Test status
Simulation time 260961935 ps
CPU time 1.85 seconds
Started Apr 16 02:34:12 PM PDT 24
Finished Apr 16 02:34:15 PM PDT 24
Peak memory 203992 kb
Host smart-1c84c9d6-564c-4ab1-ad54-b1fb9d8286b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387524823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2387524823
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3367865873
Short name T694
Test name
Test status
Simulation time 3365076526 ps
CPU time 3.52 seconds
Started Apr 16 02:34:11 PM PDT 24
Finished Apr 16 02:34:15 PM PDT 24
Peak memory 204064 kb
Host smart-7cbc2038-930c-413d-b954-88ca473c2842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367865873 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3367865873
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2020299376
Short name T707
Test name
Test status
Simulation time 3254334670 ps
CPU time 4.33 seconds
Started Apr 16 02:34:15 PM PDT 24
Finished Apr 16 02:34:20 PM PDT 24
Peak memory 204088 kb
Host smart-fd40f89a-6dfe-4298-904a-d481a9a7eca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020299376 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2020299376
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1287909843
Short name T742
Test name
Test status
Simulation time 603807668 ps
CPU time 21.38 seconds
Started Apr 16 02:34:07 PM PDT 24
Finished Apr 16 02:34:29 PM PDT 24
Peak memory 203972 kb
Host smart-d99fe58b-6e66-4e9e-9489-404609c24c83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287909843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1287909843
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2509537863
Short name T1101
Test name
Test status
Simulation time 6538494324 ps
CPU time 29.3 seconds
Started Apr 16 02:34:11 PM PDT 24
Finished Apr 16 02:34:41 PM PDT 24
Peak memory 229888 kb
Host smart-303eceec-a2d3-47be-8523-2bbcd672efc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509537863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2509537863
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.4063773035
Short name T231
Test name
Test status
Simulation time 15339755000 ps
CPU time 126.89 seconds
Started Apr 16 02:34:11 PM PDT 24
Finished Apr 16 02:36:19 PM PDT 24
Peak memory 667424 kb
Host smart-a9695aff-b6c0-49c3-b18b-3fa6920f17bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063773035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.4063773035
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.385745560
Short name T1119
Test name
Test status
Simulation time 1204416668 ps
CPU time 5.67 seconds
Started Apr 16 02:34:09 PM PDT 24
Finished Apr 16 02:34:15 PM PDT 24
Peak memory 210548 kb
Host smart-a665f096-8c21-448b-9db7-151d108b4375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385745560 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.385745560
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.4100554889
Short name T422
Test name
Test status
Simulation time 76148582 ps
CPU time 0.58 seconds
Started Apr 16 02:34:19 PM PDT 24
Finished Apr 16 02:34:21 PM PDT 24
Peak memory 203560 kb
Host smart-5201167f-43c8-47be-8326-6714adc8aa07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100554889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.4100554889
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.464932138
Short name T1221
Test name
Test status
Simulation time 158432333 ps
CPU time 1.29 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:34:23 PM PDT 24
Peak memory 212348 kb
Host smart-b5df0568-e2dd-4fe1-81a8-22e4835ceb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464932138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.464932138
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3792359740
Short name T951
Test name
Test status
Simulation time 313150351 ps
CPU time 16.86 seconds
Started Apr 16 02:34:16 PM PDT 24
Finished Apr 16 02:34:33 PM PDT 24
Peak memory 269688 kb
Host smart-1139453e-e252-4046-941c-73a48d89e129
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792359740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3792359740
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1815257959
Short name T1243
Test name
Test status
Simulation time 6618376184 ps
CPU time 101.85 seconds
Started Apr 16 02:34:15 PM PDT 24
Finished Apr 16 02:35:58 PM PDT 24
Peak memory 528928 kb
Host smart-dcec1e47-d093-4550-8020-d93fca106943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815257959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1815257959
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1767615964
Short name T651
Test name
Test status
Simulation time 1388733457 ps
CPU time 40.64 seconds
Started Apr 16 02:34:10 PM PDT 24
Finished Apr 16 02:34:52 PM PDT 24
Peak memory 505384 kb
Host smart-23592b2b-80bb-4cff-8b34-0c8e574af146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767615964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1767615964
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2599137107
Short name T9
Test name
Test status
Simulation time 83652474 ps
CPU time 0.95 seconds
Started Apr 16 02:34:15 PM PDT 24
Finished Apr 16 02:34:17 PM PDT 24
Peak memory 203920 kb
Host smart-a0324ac5-7662-475e-8bac-f964dac97bf1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599137107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2599137107
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.113684754
Short name T700
Test name
Test status
Simulation time 171427873 ps
CPU time 4.47 seconds
Started Apr 16 02:34:16 PM PDT 24
Finished Apr 16 02:34:21 PM PDT 24
Peak memory 203936 kb
Host smart-6e4f8ace-7ab7-497e-a90d-93b9ef528a8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113684754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
113684754
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.175479855
Short name T868
Test name
Test status
Simulation time 27030515241 ps
CPU time 86.08 seconds
Started Apr 16 02:34:15 PM PDT 24
Finished Apr 16 02:35:42 PM PDT 24
Peak memory 922316 kb
Host smart-b567c906-ef42-4885-8337-a1e877d5e77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175479855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.175479855
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1016874349
Short name T1200
Test name
Test status
Simulation time 3074223552 ps
CPU time 8.4 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:34:31 PM PDT 24
Peak memory 204032 kb
Host smart-f695718d-8e2c-4bdf-ab70-8ee357b3f0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016874349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1016874349
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1105915870
Short name T1321
Test name
Test status
Simulation time 1768556843 ps
CPU time 36.66 seconds
Started Apr 16 02:34:20 PM PDT 24
Finished Apr 16 02:34:57 PM PDT 24
Peak memory 363132 kb
Host smart-6207ee36-97f6-46a3-a024-2c67c96d51db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105915870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1105915870
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.1574347028
Short name T560
Test name
Test status
Simulation time 28387635 ps
CPU time 0.67 seconds
Started Apr 16 02:34:15 PM PDT 24
Finished Apr 16 02:34:16 PM PDT 24
Peak memory 203628 kb
Host smart-4eb69b8e-5808-4b7a-92a1-b44675139930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574347028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1574347028
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1795933681
Short name T809
Test name
Test status
Simulation time 5322522963 ps
CPU time 46.52 seconds
Started Apr 16 02:34:16 PM PDT 24
Finished Apr 16 02:35:04 PM PDT 24
Peak memory 571080 kb
Host smart-3d35998e-574e-4e70-8357-73a24253e626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795933681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1795933681
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3371897731
Short name T93
Test name
Test status
Simulation time 3560903148 ps
CPU time 13.27 seconds
Started Apr 16 02:34:12 PM PDT 24
Finished Apr 16 02:34:26 PM PDT 24
Peak memory 278768 kb
Host smart-4332d473-0e2b-4679-98ce-c3b3be1e2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371897731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3371897731
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2153541246
Short name T251
Test name
Test status
Simulation time 40741084097 ps
CPU time 808.11 seconds
Started Apr 16 02:34:19 PM PDT 24
Finished Apr 16 02:47:48 PM PDT 24
Peak memory 1599344 kb
Host smart-6d609c95-221c-4fb3-a852-e96996993e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153541246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2153541246
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.414476141
Short name T1209
Test name
Test status
Simulation time 3809030808 ps
CPU time 32.15 seconds
Started Apr 16 02:34:19 PM PDT 24
Finished Apr 16 02:34:51 PM PDT 24
Peak memory 212252 kb
Host smart-e0d1b668-c9cb-4e34-bb8c-8173d004f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414476141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.414476141
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2805240490
Short name T398
Test name
Test status
Simulation time 3479043953 ps
CPU time 4.33 seconds
Started Apr 16 02:34:17 PM PDT 24
Finished Apr 16 02:34:22 PM PDT 24
Peak memory 212248 kb
Host smart-45b1ad53-3a92-416a-858e-b3eb3d99ebbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805240490 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2805240490
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3210081983
Short name T802
Test name
Test status
Simulation time 10069767514 ps
CPU time 68.07 seconds
Started Apr 16 02:34:17 PM PDT 24
Finished Apr 16 02:35:25 PM PDT 24
Peak memory 527820 kb
Host smart-67ef4b37-bfdf-4931-8bdb-745f34a9c10c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210081983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3210081983
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2355616208
Short name T719
Test name
Test status
Simulation time 10071282830 ps
CPU time 29.01 seconds
Started Apr 16 02:34:20 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 370760 kb
Host smart-6e637bb8-a7c1-4a2e-b3c7-e733f2b61afe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355616208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2355616208
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2990041188
Short name T1187
Test name
Test status
Simulation time 1703157738 ps
CPU time 1.79 seconds
Started Apr 16 02:34:15 PM PDT 24
Finished Apr 16 02:34:18 PM PDT 24
Peak memory 203944 kb
Host smart-af684258-dcaf-435f-ba0e-81f544795547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990041188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2990041188
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.904781888
Short name T959
Test name
Test status
Simulation time 2831358093 ps
CPU time 6.55 seconds
Started Apr 16 02:34:19 PM PDT 24
Finished Apr 16 02:34:26 PM PDT 24
Peak memory 208616 kb
Host smart-4c6aea39-20a3-444b-97c2-91b77a9a50d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904781888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.904781888
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2777331148
Short name T1168
Test name
Test status
Simulation time 3332518549 ps
CPU time 2.93 seconds
Started Apr 16 02:34:17 PM PDT 24
Finished Apr 16 02:34:21 PM PDT 24
Peak memory 204036 kb
Host smart-a051f8e0-366c-4d70-b5b7-21def92bd25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777331148 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2777331148
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2043698504
Short name T852
Test name
Test status
Simulation time 1265815558 ps
CPU time 27.85 seconds
Started Apr 16 02:34:23 PM PDT 24
Finished Apr 16 02:34:51 PM PDT 24
Peak memory 203988 kb
Host smart-59f3020b-aa25-41c5-8581-158d1405a642
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043698504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2043698504
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2638663822
Short name T1317
Test name
Test status
Simulation time 3947311261 ps
CPU time 15.28 seconds
Started Apr 16 02:34:22 PM PDT 24
Finished Apr 16 02:34:38 PM PDT 24
Peak memory 220312 kb
Host smart-23e89c14-8685-48a0-b95d-2a0bef1ea59d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638663822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2638663822
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.4060709704
Short name T1183
Test name
Test status
Simulation time 31508982285 ps
CPU time 35.58 seconds
Started Apr 16 02:34:17 PM PDT 24
Finished Apr 16 02:34:54 PM PDT 24
Peak memory 772396 kb
Host smart-164d81bf-9400-47d3-9019-23d9134a6997
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060709704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.4060709704
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1740263269
Short name T656
Test name
Test status
Simulation time 8352221506 ps
CPU time 256.15 seconds
Started Apr 16 02:34:23 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 2022136 kb
Host smart-a0e6f39b-7307-4fe0-8822-8bc00dea7c4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740263269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1740263269
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.200056561
Short name T1323
Test name
Test status
Simulation time 2789840344 ps
CPU time 6.54 seconds
Started Apr 16 02:34:18 PM PDT 24
Finished Apr 16 02:34:25 PM PDT 24
Peak memory 212208 kb
Host smart-8c131afd-e278-406e-96f7-06442dd5a689
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200056561 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.200056561
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3855421698
Short name T442
Test name
Test status
Simulation time 139530791 ps
CPU time 0.65 seconds
Started Apr 16 02:34:25 PM PDT 24
Finished Apr 16 02:34:27 PM PDT 24
Peak memory 203564 kb
Host smart-fb2776da-0783-4949-9bd0-dea942f5b64f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855421698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3855421698
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2008288146
Short name T119
Test name
Test status
Simulation time 778242211 ps
CPU time 1.4 seconds
Started Apr 16 02:34:27 PM PDT 24
Finished Apr 16 02:34:29 PM PDT 24
Peak memory 212312 kb
Host smart-9ff4e8bd-aca4-45af-947a-1cded0df2010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008288146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2008288146
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1696305960
Short name T924
Test name
Test status
Simulation time 1192556819 ps
CPU time 12.19 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 249132 kb
Host smart-73e07c3d-67d2-45a1-8f44-854e268b412e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696305960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1696305960
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1855135317
Short name T95
Test name
Test status
Simulation time 7517240081 ps
CPU time 110.41 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 553368 kb
Host smart-0d65a0c0-d3a4-4a5d-93f3-76783b75fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855135317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1855135317
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.71786095
Short name T1130
Test name
Test status
Simulation time 2455790156 ps
CPU time 72.95 seconds
Started Apr 16 02:34:22 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 402768 kb
Host smart-0b86b063-a509-4ed4-a431-8597c3a4d03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71786095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.71786095
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2288458834
Short name T486
Test name
Test status
Simulation time 168264186 ps
CPU time 0.89 seconds
Started Apr 16 02:34:19 PM PDT 24
Finished Apr 16 02:34:20 PM PDT 24
Peak memory 203740 kb
Host smart-09e669dd-1da5-4782-a2fc-eecedff0cfa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288458834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2288458834
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.253161530
Short name T884
Test name
Test status
Simulation time 186198175 ps
CPU time 10.33 seconds
Started Apr 16 02:34:20 PM PDT 24
Finished Apr 16 02:34:31 PM PDT 24
Peak memory 239288 kb
Host smart-68b8787d-551a-49a5-ac3d-55b7cc59e91f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253161530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
253161530
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1147443600
Short name T618
Test name
Test status
Simulation time 4563560524 ps
CPU time 107.28 seconds
Started Apr 16 02:34:23 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 1262220 kb
Host smart-feaa0f4d-4868-4c76-86ce-6695047dc469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147443600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1147443600
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3200840564
Short name T592
Test name
Test status
Simulation time 366787122 ps
CPU time 6.15 seconds
Started Apr 16 02:34:30 PM PDT 24
Finished Apr 16 02:34:38 PM PDT 24
Peak memory 204000 kb
Host smart-f93164ec-908b-4c8e-8398-efe1d13bdac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200840564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3200840564
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1226521826
Short name T3
Test name
Test status
Simulation time 993634770 ps
CPU time 17.69 seconds
Started Apr 16 02:34:26 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 304628 kb
Host smart-1a9948ea-a753-468a-8f59-e9446109bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226521826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1226521826
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.235860378
Short name T191
Test name
Test status
Simulation time 17637620 ps
CPU time 0.66 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:34:23 PM PDT 24
Peak memory 203688 kb
Host smart-f9ccc187-8281-40c3-9f9a-34621610dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235860378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.235860378
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2624275065
Short name T627
Test name
Test status
Simulation time 30539636416 ps
CPU time 55.39 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:35:17 PM PDT 24
Peak memory 213148 kb
Host smart-3350867a-20f0-46c6-92c2-95bffd9f2b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624275065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2624275065
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1519864130
Short name T178
Test name
Test status
Simulation time 7454719029 ps
CPU time 43.93 seconds
Started Apr 16 02:34:23 PM PDT 24
Finished Apr 16 02:35:08 PM PDT 24
Peak memory 276764 kb
Host smart-17764658-d57f-4b84-84f8-fd0ef7811b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519864130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1519864130
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3161103813
Short name T1240
Test name
Test status
Simulation time 8991773849 ps
CPU time 8.67 seconds
Started Apr 16 02:34:23 PM PDT 24
Finished Apr 16 02:34:32 PM PDT 24
Peak memory 220280 kb
Host smart-62fe3432-37bb-41be-bd6e-e91f29116cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161103813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3161103813
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.1464982080
Short name T547
Test name
Test status
Simulation time 3492502233 ps
CPU time 3.99 seconds
Started Apr 16 02:34:29 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 204084 kb
Host smart-7cbf5480-7a59-4aa6-9541-8b3e8fee4578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464982080 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.1464982080
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2288257235
Short name T416
Test name
Test status
Simulation time 10160947262 ps
CPU time 12.48 seconds
Started Apr 16 02:34:23 PM PDT 24
Finished Apr 16 02:34:37 PM PDT 24
Peak memory 274120 kb
Host smart-86400a8f-d570-4d89-861a-b6fd2aecb3fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288257235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2288257235
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3051924219
Short name T965
Test name
Test status
Simulation time 10074775308 ps
CPU time 31.96 seconds
Started Apr 16 02:34:24 PM PDT 24
Finished Apr 16 02:34:57 PM PDT 24
Peak memory 421044 kb
Host smart-22e47b6f-4061-404d-b907-4eeb0916932e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051924219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3051924219
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.823163329
Short name T804
Test name
Test status
Simulation time 1875589262 ps
CPU time 2.23 seconds
Started Apr 16 02:34:30 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 204020 kb
Host smart-d42be6fa-40ed-42dd-842c-deb9cb5beb32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823163329 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.823163329
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.4041649324
Short name T1078
Test name
Test status
Simulation time 4884259154 ps
CPU time 5.43 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:34:27 PM PDT 24
Peak memory 212204 kb
Host smart-c379eb29-2f13-4046-be06-7a4c2bd5ed66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041649324 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.4041649324
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1236180557
Short name T395
Test name
Test status
Simulation time 15863731270 ps
CPU time 200.81 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:37:43 PM PDT 24
Peak memory 2326588 kb
Host smart-1f4532d9-1442-4246-bf60-ead55a9ca6d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236180557 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1236180557
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.822210205
Short name T906
Test name
Test status
Simulation time 1192260786 ps
CPU time 21.52 seconds
Started Apr 16 02:34:19 PM PDT 24
Finished Apr 16 02:34:41 PM PDT 24
Peak memory 203908 kb
Host smart-d768f2d3-cae1-4954-bf4a-7db1c028db9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822210205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.822210205
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3309290279
Short name T340
Test name
Test status
Simulation time 2670689450 ps
CPU time 27.82 seconds
Started Apr 16 02:34:20 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 204096 kb
Host smart-cd91d73b-e317-4821-8976-2dba1f507255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309290279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3309290279
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.2787383564
Short name T954
Test name
Test status
Simulation time 34453845192 ps
CPU time 52.59 seconds
Started Apr 16 02:34:21 PM PDT 24
Finished Apr 16 02:35:15 PM PDT 24
Peak memory 1010864 kb
Host smart-47f3633c-9ab6-4f5d-b1b4-284447ecfd11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787383564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.2787383564
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.2862527521
Short name T970
Test name
Test status
Simulation time 21523466203 ps
CPU time 1278.12 seconds
Started Apr 16 02:34:22 PM PDT 24
Finished Apr 16 02:55:41 PM PDT 24
Peak memory 5230260 kb
Host smart-50b7ba2b-29b6-41a2-8a92-370d9a6c839d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862527521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.2862527521
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3690942722
Short name T1267
Test name
Test status
Simulation time 13876704922 ps
CPU time 6.32 seconds
Started Apr 16 02:34:23 PM PDT 24
Finished Apr 16 02:34:30 PM PDT 24
Peak memory 214812 kb
Host smart-db43077a-5c9e-4741-bc30-5657241bd34d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690942722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3690942722
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.3935734137
Short name T19
Test name
Test status
Simulation time 709990752 ps
CPU time 4.14 seconds
Started Apr 16 02:34:20 PM PDT 24
Finished Apr 16 02:34:25 PM PDT 24
Peak memory 203980 kb
Host smart-ebb5272e-c744-42c0-b3e8-6af940952f15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935734137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.3935734137
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2063795187
Short name T509
Test name
Test status
Simulation time 27422239 ps
CPU time 0.62 seconds
Started Apr 16 02:34:31 PM PDT 24
Finished Apr 16 02:34:33 PM PDT 24
Peak memory 203576 kb
Host smart-b642277f-aa37-4e17-b48f-5916e3da60c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063795187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2063795187
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3475371583
Short name T64
Test name
Test status
Simulation time 60635950 ps
CPU time 1.38 seconds
Started Apr 16 02:34:26 PM PDT 24
Finished Apr 16 02:34:28 PM PDT 24
Peak memory 212280 kb
Host smart-678d4dd1-732e-48e6-9279-2ec832c07b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475371583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3475371583
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1394334069
Short name T175
Test name
Test status
Simulation time 1801343580 ps
CPU time 9.95 seconds
Started Apr 16 02:34:25 PM PDT 24
Finished Apr 16 02:34:36 PM PDT 24
Peak memory 305052 kb
Host smart-6bd7a858-aa1b-470a-9453-2534cb681275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394334069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1394334069
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3576015767
Short name T1346
Test name
Test status
Simulation time 8283648434 ps
CPU time 62.28 seconds
Started Apr 16 02:34:30 PM PDT 24
Finished Apr 16 02:35:34 PM PDT 24
Peak memory 621316 kb
Host smart-93b5025d-62b0-4f20-9e49-742310b74584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576015767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3576015767
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2492833785
Short name T363
Test name
Test status
Simulation time 1652398042 ps
CPU time 46.64 seconds
Started Apr 16 02:34:24 PM PDT 24
Finished Apr 16 02:35:12 PM PDT 24
Peak memory 613892 kb
Host smart-0bc90ae7-50bf-4477-992d-94d21490a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492833785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2492833785
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2378724691
Short name T746
Test name
Test status
Simulation time 105426327 ps
CPU time 0.94 seconds
Started Apr 16 02:34:27 PM PDT 24
Finished Apr 16 02:34:29 PM PDT 24
Peak memory 203740 kb
Host smart-ff47b752-3d06-4c81-b345-8421f287c905
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378724691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2378724691
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.345592590
Short name T666
Test name
Test status
Simulation time 122058529 ps
CPU time 6.32 seconds
Started Apr 16 02:34:25 PM PDT 24
Finished Apr 16 02:34:32 PM PDT 24
Peak memory 221920 kb
Host smart-33f93f08-8578-49fc-9738-456040a83b63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345592590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
345592590
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1814448775
Short name T908
Test name
Test status
Simulation time 12205340738 ps
CPU time 222.91 seconds
Started Apr 16 02:34:24 PM PDT 24
Finished Apr 16 02:38:08 PM PDT 24
Peak memory 962288 kb
Host smart-b4fdb67f-6055-430a-b49c-5a611c144b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814448775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1814448775
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2138637798
Short name T1163
Test name
Test status
Simulation time 1238247809 ps
CPU time 11.76 seconds
Started Apr 16 02:34:29 PM PDT 24
Finished Apr 16 02:34:42 PM PDT 24
Peak memory 203944 kb
Host smart-b1cd78f1-7c19-4c92-85c1-06a7fa0ddc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138637798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2138637798
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2323063175
Short name T503
Test name
Test status
Simulation time 2476502934 ps
CPU time 60.3 seconds
Started Apr 16 02:34:29 PM PDT 24
Finished Apr 16 02:35:30 PM PDT 24
Peak memory 335272 kb
Host smart-fe5b02a2-fa0b-4fb4-a3d7-75da77dbde8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323063175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2323063175
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3865109002
Short name T1339
Test name
Test status
Simulation time 30672718 ps
CPU time 0.69 seconds
Started Apr 16 02:34:27 PM PDT 24
Finished Apr 16 02:34:29 PM PDT 24
Peak memory 203692 kb
Host smart-a2f9b0ce-78d3-42df-a35a-552a3c073bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865109002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3865109002
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1798831607
Short name T205
Test name
Test status
Simulation time 467398484 ps
CPU time 7.2 seconds
Started Apr 16 02:34:26 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 228392 kb
Host smart-ea7fdf4d-6780-4039-be6b-3fe80e5b8461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798831607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1798831607
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.773915487
Short name T690
Test name
Test status
Simulation time 4451915113 ps
CPU time 22.09 seconds
Started Apr 16 02:34:27 PM PDT 24
Finished Apr 16 02:34:50 PM PDT 24
Peak memory 324372 kb
Host smart-d72187d6-42f6-48e1-95a5-2e25c3377781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773915487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.773915487
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1020669197
Short name T1025
Test name
Test status
Simulation time 45939648286 ps
CPU time 1540.37 seconds
Started Apr 16 02:34:26 PM PDT 24
Finished Apr 16 03:00:08 PM PDT 24
Peak memory 1559132 kb
Host smart-c6bb848a-9d67-4907-94f2-40abcd299370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020669197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1020669197
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.443536051
Short name T1081
Test name
Test status
Simulation time 3098980040 ps
CPU time 3.57 seconds
Started Apr 16 02:34:31 PM PDT 24
Finished Apr 16 02:34:36 PM PDT 24
Peak memory 204040 kb
Host smart-19c06ddf-ff31-4fa3-a279-b08c1b93afa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443536051 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.443536051
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.4056226363
Short name T603
Test name
Test status
Simulation time 10077654804 ps
CPU time 71.06 seconds
Started Apr 16 02:34:30 PM PDT 24
Finished Apr 16 02:35:43 PM PDT 24
Peak memory 547392 kb
Host smart-a5b871e3-101d-4140-9d16-26402920dd3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056226363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.4056226363
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.611582233
Short name T893
Test name
Test status
Simulation time 1519231209 ps
CPU time 2.52 seconds
Started Apr 16 02:34:30 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 204012 kb
Host smart-a15fae0a-6e37-43c9-9311-c61ec7e29b34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611582233 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_hrst.611582233
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3342051682
Short name T938
Test name
Test status
Simulation time 6259015966 ps
CPU time 5.51 seconds
Started Apr 16 02:34:27 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 215568 kb
Host smart-81c1aa03-cce0-4abd-9ed1-7241f446188d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342051682 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3342051682
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.316991823
Short name T449
Test name
Test status
Simulation time 13197442828 ps
CPU time 7.93 seconds
Started Apr 16 02:34:27 PM PDT 24
Finished Apr 16 02:34:36 PM PDT 24
Peak memory 254848 kb
Host smart-c5a3c3f2-3700-47f2-a4e0-46ce2e9b71b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316991823 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.316991823
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3455125826
Short name T1049
Test name
Test status
Simulation time 3008476253 ps
CPU time 30.82 seconds
Started Apr 16 02:34:25 PM PDT 24
Finished Apr 16 02:34:57 PM PDT 24
Peak memory 204000 kb
Host smart-21749859-058a-41f9-9dc7-cab363211768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455125826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3455125826
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.4218161353
Short name T1269
Test name
Test status
Simulation time 50917373038 ps
CPU time 119.58 seconds
Started Apr 16 02:34:30 PM PDT 24
Finished Apr 16 02:36:31 PM PDT 24
Peak memory 841460 kb
Host smart-a5d367c3-bb23-4a76-be74-a04371b7b9bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218161353 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.4218161353
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.361885324
Short name T1044
Test name
Test status
Simulation time 2295386165 ps
CPU time 15.83 seconds
Started Apr 16 02:34:26 PM PDT 24
Finished Apr 16 02:34:43 PM PDT 24
Peak memory 222024 kb
Host smart-be42d58c-38f4-4306-b8be-30b44bde2f46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361885324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.361885324
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3671215755
Short name T753
Test name
Test status
Simulation time 56300634566 ps
CPU time 536.66 seconds
Started Apr 16 02:34:24 PM PDT 24
Finished Apr 16 02:43:21 PM PDT 24
Peak memory 4452308 kb
Host smart-a8b5a77e-06b0-4089-ad74-2b861f25261e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671215755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3671215755
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.1303647255
Short name T1011
Test name
Test status
Simulation time 18182336763 ps
CPU time 408.83 seconds
Started Apr 16 02:34:24 PM PDT 24
Finished Apr 16 02:41:14 PM PDT 24
Peak memory 1285432 kb
Host smart-ff497800-a2e5-456d-a6e1-2d088cc12ee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303647255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.1303647255
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2093067058
Short name T1051
Test name
Test status
Simulation time 1230089370 ps
CPU time 6.34 seconds
Started Apr 16 02:34:27 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 219392 kb
Host smart-6fa3f024-77ce-4a26-b704-9979a586395d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093067058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2093067058
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.4029190613
Short name T999
Test name
Test status
Simulation time 25849003 ps
CPU time 0.61 seconds
Started Apr 16 02:34:35 PM PDT 24
Finished Apr 16 02:34:36 PM PDT 24
Peak memory 203552 kb
Host smart-38c8c3a5-68e7-42e4-bfe2-7af80583a8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029190613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.4029190613
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1995129486
Short name T1205
Test name
Test status
Simulation time 131716523 ps
CPU time 1.05 seconds
Started Apr 16 02:34:36 PM PDT 24
Finished Apr 16 02:34:37 PM PDT 24
Peak memory 204048 kb
Host smart-ed9e2ac3-4eae-4877-a1d1-3828601609b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995129486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1995129486
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2569149048
Short name T1091
Test name
Test status
Simulation time 439324151 ps
CPU time 9.31 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 296456 kb
Host smart-ab3db207-7c44-427c-96d6-8a562745cbcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569149048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2569149048
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2469599836
Short name T89
Test name
Test status
Simulation time 4249195265 ps
CPU time 76.14 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:35:51 PM PDT 24
Peak memory 713336 kb
Host smart-f57dedab-24f8-4d72-9cc0-b881c18cb274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469599836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2469599836
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.2555291650
Short name T334
Test name
Test status
Simulation time 6899491164 ps
CPU time 39.99 seconds
Started Apr 16 02:34:31 PM PDT 24
Finished Apr 16 02:35:12 PM PDT 24
Peak memory 438724 kb
Host smart-3dc72348-6a97-437d-884d-bd3b8527fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555291650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2555291650
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.486673092
Short name T213
Test name
Test status
Simulation time 110744287 ps
CPU time 1.09 seconds
Started Apr 16 02:34:32 PM PDT 24
Finished Apr 16 02:34:34 PM PDT 24
Peak memory 203892 kb
Host smart-e0250c21-2d82-47b0-a62d-03188cf6506c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486673092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.486673092
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1600136342
Short name T763
Test name
Test status
Simulation time 111688930 ps
CPU time 2.74 seconds
Started Apr 16 02:34:38 PM PDT 24
Finished Apr 16 02:34:42 PM PDT 24
Peak memory 203888 kb
Host smart-83f13268-c044-404b-ba01-109eb2279b92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600136342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1600136342
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.845750339
Short name T1133
Test name
Test status
Simulation time 8228807941 ps
CPU time 74.66 seconds
Started Apr 16 02:34:28 PM PDT 24
Finished Apr 16 02:35:44 PM PDT 24
Peak memory 878408 kb
Host smart-89b4c205-f7c7-4a4d-baa1-d31125de2348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845750339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.845750339
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.443377903
Short name T94
Test name
Test status
Simulation time 1105118056 ps
CPU time 6.03 seconds
Started Apr 16 02:34:39 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 203932 kb
Host smart-86710304-eb75-457c-aded-63c47a372c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443377903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.443377903
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.3737459828
Short name T1149
Test name
Test status
Simulation time 4891916217 ps
CPU time 18.86 seconds
Started Apr 16 02:34:35 PM PDT 24
Finished Apr 16 02:34:54 PM PDT 24
Peak memory 281316 kb
Host smart-210b76cd-46ec-4e91-b496-a0db870b1e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737459828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3737459828
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.294314068
Short name T984
Test name
Test status
Simulation time 104457893 ps
CPU time 0.71 seconds
Started Apr 16 02:34:29 PM PDT 24
Finished Apr 16 02:34:30 PM PDT 24
Peak memory 203600 kb
Host smart-ffcde0af-195f-4cf6-9479-44a64e413e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294314068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.294314068
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.160735313
Short name T290
Test name
Test status
Simulation time 11889540773 ps
CPU time 297.82 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:39:32 PM PDT 24
Peak memory 1491316 kb
Host smart-a51f1230-3d45-4a71-a28b-68655b549725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160735313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.160735313
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1489471169
Short name T1212
Test name
Test status
Simulation time 1680939733 ps
CPU time 35.02 seconds
Started Apr 16 02:34:30 PM PDT 24
Finished Apr 16 02:35:07 PM PDT 24
Peak memory 342408 kb
Host smart-6f364e1d-8d5b-489c-a53a-8fa7fbb74d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489471169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1489471169
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.163733780
Short name T1280
Test name
Test status
Simulation time 7368151675 ps
CPU time 283.73 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:39:19 PM PDT 24
Peak memory 865796 kb
Host smart-a44b48e0-0520-4dbc-9fda-c6fef081b4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163733780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.163733780
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2477386606
Short name T614
Test name
Test status
Simulation time 6833081932 ps
CPU time 22.62 seconds
Started Apr 16 02:34:37 PM PDT 24
Finished Apr 16 02:35:00 PM PDT 24
Peak memory 212288 kb
Host smart-a0349b4a-ae37-4e02-aada-b8e4ae10bbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477386606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2477386606
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.165610812
Short name T845
Test name
Test status
Simulation time 781352760 ps
CPU time 3.71 seconds
Started Apr 16 02:34:38 PM PDT 24
Finished Apr 16 02:34:43 PM PDT 24
Peak memory 203996 kb
Host smart-52c233f0-ab3c-4246-8e26-0a5866c051eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165610812 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.165610812
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3021572385
Short name T1250
Test name
Test status
Simulation time 10512003558 ps
CPU time 9.38 seconds
Started Apr 16 02:34:33 PM PDT 24
Finished Apr 16 02:34:44 PM PDT 24
Peak memory 246520 kb
Host smart-2abedf74-19a7-4b34-a597-296dbd9758f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021572385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3021572385
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2330435511
Short name T433
Test name
Test status
Simulation time 10062335880 ps
CPU time 39.43 seconds
Started Apr 16 02:34:35 PM PDT 24
Finished Apr 16 02:35:15 PM PDT 24
Peak memory 402628 kb
Host smart-d9ac17fb-7fc8-42ab-9931-502e1c167060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330435511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2330435511
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1093551961
Short name T817
Test name
Test status
Simulation time 623728023 ps
CPU time 3 seconds
Started Apr 16 02:34:33 PM PDT 24
Finished Apr 16 02:34:38 PM PDT 24
Peak memory 204044 kb
Host smart-3f717e3e-91c4-46d1-a870-76f0c91276a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093551961 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1093551961
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.789584651
Short name T745
Test name
Test status
Simulation time 2164079028 ps
CPU time 5.78 seconds
Started Apr 16 02:34:38 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 204044 kb
Host smart-a8ea1fab-72d9-40a8-bfcc-e6563db29c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789584651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.789584651
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3055074452
Short name T1232
Test name
Test status
Simulation time 16137847901 ps
CPU time 197.96 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:37:53 PM PDT 24
Peak memory 2455792 kb
Host smart-7a990a6d-a9aa-4eff-81f6-4912305659c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055074452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3055074452
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3519117749
Short name T265
Test name
Test status
Simulation time 1012180268 ps
CPU time 40.12 seconds
Started Apr 16 02:34:35 PM PDT 24
Finished Apr 16 02:35:16 PM PDT 24
Peak memory 203984 kb
Host smart-f3b74dcd-57f6-47f5-bbc0-a67187836636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519117749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3519117749
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3454227162
Short name T226
Test name
Test status
Simulation time 1687614002 ps
CPU time 16.33 seconds
Started Apr 16 02:34:36 PM PDT 24
Finished Apr 16 02:34:53 PM PDT 24
Peak memory 218148 kb
Host smart-73768fa7-9066-4ab8-814a-d8369d3b36fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454227162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3454227162
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.4246274652
Short name T1184
Test name
Test status
Simulation time 59510800133 ps
CPU time 146.18 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 1857540 kb
Host smart-9545bc1f-a071-4719-845c-5c939a7282e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246274652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.4246274652
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3088458494
Short name T835
Test name
Test status
Simulation time 35034019588 ps
CPU time 1134.65 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:53:30 PM PDT 24
Peak memory 4261204 kb
Host smart-e09520d5-8ade-48c6-b4b2-834031e22cac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088458494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3088458494
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3047519522
Short name T6
Test name
Test status
Simulation time 9631353000 ps
CPU time 7.44 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:34:43 PM PDT 24
Peak memory 220264 kb
Host smart-e114f5e5-5e3c-48ab-9f1e-7063f692828a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047519522 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3047519522
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2740700097
Short name T572
Test name
Test status
Simulation time 17562628 ps
CPU time 0.62 seconds
Started Apr 16 02:34:45 PM PDT 24
Finished Apr 16 02:34:47 PM PDT 24
Peak memory 203560 kb
Host smart-8ebcccbb-eadb-47a2-96b8-fcc6b45eccdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740700097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2740700097
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1935234568
Short name T709
Test name
Test status
Simulation time 63830001 ps
CPU time 1.13 seconds
Started Apr 16 02:34:42 PM PDT 24
Finished Apr 16 02:34:44 PM PDT 24
Peak memory 212240 kb
Host smart-248c7384-3af6-43e8-9039-f394834de95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935234568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1935234568
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3762320606
Short name T259
Test name
Test status
Simulation time 1286813609 ps
CPU time 16.7 seconds
Started Apr 16 02:34:43 PM PDT 24
Finished Apr 16 02:35:01 PM PDT 24
Peak memory 270624 kb
Host smart-989fa9e3-6dda-4800-99ae-7912dfee72e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762320606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3762320606
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1991472619
Short name T56
Test name
Test status
Simulation time 6968016183 ps
CPU time 56.4 seconds
Started Apr 16 02:34:42 PM PDT 24
Finished Apr 16 02:35:40 PM PDT 24
Peak memory 608508 kb
Host smart-090b450a-47ab-45d7-82e6-ce12e09f555f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991472619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1991472619
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3248191558
Short name T439
Test name
Test status
Simulation time 24733859283 ps
CPU time 55.44 seconds
Started Apr 16 02:34:40 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 606380 kb
Host smart-81d4ae46-d44e-493b-a5c0-c592c519ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248191558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3248191558
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.379156703
Short name T1182
Test name
Test status
Simulation time 176143414 ps
CPU time 0.82 seconds
Started Apr 16 02:34:40 PM PDT 24
Finished Apr 16 02:34:41 PM PDT 24
Peak memory 203732 kb
Host smart-a784778e-434b-443b-b0fb-14cdfe9648ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379156703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.379156703
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2517492582
Short name T607
Test name
Test status
Simulation time 337849752 ps
CPU time 4.24 seconds
Started Apr 16 02:34:44 PM PDT 24
Finished Apr 16 02:34:50 PM PDT 24
Peak memory 203840 kb
Host smart-6d9b9833-e6cd-40f3-ada9-8dc0384ec91e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517492582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2517492582
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.686983465
Short name T1158
Test name
Test status
Simulation time 16213448105 ps
CPU time 110.22 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:36:25 PM PDT 24
Peak memory 1102524 kb
Host smart-8d625e7a-e500-4271-80a1-d911f6feea8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686983465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.686983465
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3209563002
Short name T71
Test name
Test status
Simulation time 470100178 ps
CPU time 7.13 seconds
Started Apr 16 02:34:43 PM PDT 24
Finished Apr 16 02:34:52 PM PDT 24
Peak memory 203996 kb
Host smart-f1cce2ff-bc65-49cf-a613-1a877c91c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209563002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3209563002
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3993498788
Short name T1283
Test name
Test status
Simulation time 2222426452 ps
CPU time 76.53 seconds
Started Apr 16 02:34:42 PM PDT 24
Finished Apr 16 02:36:00 PM PDT 24
Peak memory 348208 kb
Host smart-6ec9407a-6cb0-4129-b01d-5723e2b53ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993498788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3993498788
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3706970063
Short name T664
Test name
Test status
Simulation time 19093497 ps
CPU time 0.64 seconds
Started Apr 16 02:34:34 PM PDT 24
Finished Apr 16 02:34:36 PM PDT 24
Peak memory 203676 kb
Host smart-8bcc6b14-a9f9-483b-87fa-885dc3839699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706970063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3706970063
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.715688170
Short name T928
Test name
Test status
Simulation time 49576896722 ps
CPU time 124.1 seconds
Started Apr 16 02:34:41 PM PDT 24
Finished Apr 16 02:36:46 PM PDT 24
Peak memory 961528 kb
Host smart-ddaf526e-54f2-4128-8b8a-1a088e2b6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715688170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.715688170
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3142716052
Short name T297
Test name
Test status
Simulation time 981152382 ps
CPU time 46.11 seconds
Started Apr 16 02:34:35 PM PDT 24
Finished Apr 16 02:35:22 PM PDT 24
Peak memory 301024 kb
Host smart-3d1e4dee-521e-49fc-a24f-e8d0caf8a181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142716052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3142716052
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2793722937
Short name T49
Test name
Test status
Simulation time 40158450373 ps
CPU time 287.3 seconds
Started Apr 16 02:34:42 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 575512 kb
Host smart-6a3e06ad-b71d-47e8-8590-5ba20ab9fba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793722937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2793722937
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.316221205
Short name T862
Test name
Test status
Simulation time 536969263 ps
CPU time 17.64 seconds
Started Apr 16 02:34:41 PM PDT 24
Finished Apr 16 02:35:01 PM PDT 24
Peak memory 212436 kb
Host smart-ecc885ca-cf21-43c3-8ff0-70765ebf0345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316221205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.316221205
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1952129026
Short name T901
Test name
Test status
Simulation time 1129310302 ps
CPU time 4.89 seconds
Started Apr 16 02:34:42 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 204020 kb
Host smart-589046c8-751b-49c5-bc5a-441040f07298
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952129026 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1952129026
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3093770578
Short name T998
Test name
Test status
Simulation time 10164167690 ps
CPU time 13.26 seconds
Started Apr 16 02:34:42 PM PDT 24
Finished Apr 16 02:34:57 PM PDT 24
Peak memory 269828 kb
Host smart-32f1d9bb-18f8-430f-9bab-e88f29e0c370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093770578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3093770578
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3235174215
Short name T1241
Test name
Test status
Simulation time 10154129979 ps
CPU time 56.27 seconds
Started Apr 16 02:34:41 PM PDT 24
Finished Apr 16 02:35:38 PM PDT 24
Peak memory 502116 kb
Host smart-7ff22c66-c1e5-4db6-a3ad-5d4054e6d7f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235174215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3235174215
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3409628916
Short name T734
Test name
Test status
Simulation time 528107260 ps
CPU time 3 seconds
Started Apr 16 02:34:44 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 203912 kb
Host smart-c6e61140-0626-4f2d-9e25-ba72761e7990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409628916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3409628916
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1976618644
Short name T730
Test name
Test status
Simulation time 1590553112 ps
CPU time 3.58 seconds
Started Apr 16 02:34:40 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 204008 kb
Host smart-a5f19cbe-021d-4859-94b6-5fb582318bff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976618644 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1976618644
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3780998702
Short name T1045
Test name
Test status
Simulation time 20497240044 ps
CPU time 13.36 seconds
Started Apr 16 02:34:43 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 361492 kb
Host smart-557c8fe9-4632-4299-b13d-20f0819a3dbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780998702 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3780998702
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1193025777
Short name T859
Test name
Test status
Simulation time 1521907200 ps
CPU time 19.29 seconds
Started Apr 16 02:34:43 PM PDT 24
Finished Apr 16 02:35:04 PM PDT 24
Peak memory 204004 kb
Host smart-84c28fe3-b167-4d7a-be9d-968fca95185f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193025777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1193025777
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.2131177848
Short name T1284
Test name
Test status
Simulation time 501876661 ps
CPU time 10.35 seconds
Started Apr 16 02:34:43 PM PDT 24
Finished Apr 16 02:34:55 PM PDT 24
Peak memory 203920 kb
Host smart-42b81873-c485-4b92-a013-eaa4f915c2b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131177848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.2131177848
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.1179885229
Short name T434
Test name
Test status
Simulation time 51896464945 ps
CPU time 43.36 seconds
Started Apr 16 02:34:41 PM PDT 24
Finished Apr 16 02:35:26 PM PDT 24
Peak memory 749408 kb
Host smart-0e3c30e1-8470-456c-9090-7daff44a2245
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179885229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.1179885229
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1115945999
Short name T980
Test name
Test status
Simulation time 6919729092 ps
CPU time 173.4 seconds
Started Apr 16 02:34:41 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 1702896 kb
Host smart-3a7beae1-2ad9-4b62-80cf-8ed218d26796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115945999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1115945999
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.36300476
Short name T904
Test name
Test status
Simulation time 1071964006 ps
CPU time 5.82 seconds
Started Apr 16 02:34:42 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 204012 kb
Host smart-d0dacdda-92b7-40a8-8584-b1589fe4becb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300476 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_timeout.36300476
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2822272841
Short name T903
Test name
Test status
Simulation time 21378054 ps
CPU time 0.62 seconds
Started Apr 16 02:32:05 PM PDT 24
Finished Apr 16 02:32:07 PM PDT 24
Peak memory 203596 kb
Host smart-5174970d-10ff-49df-84b2-b29e65f1512b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822272841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2822272841
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3570124331
Short name T267
Test name
Test status
Simulation time 84252707 ps
CPU time 1.28 seconds
Started Apr 16 02:31:53 PM PDT 24
Finished Apr 16 02:31:56 PM PDT 24
Peak memory 204044 kb
Host smart-07a2266a-addc-47c2-9ec1-f0bddc9c7045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570124331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3570124331
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.989974685
Short name T1037
Test name
Test status
Simulation time 249716016 ps
CPU time 4.52 seconds
Started Apr 16 02:31:54 PM PDT 24
Finished Apr 16 02:32:00 PM PDT 24
Peak memory 253056 kb
Host smart-ee34bf0c-d12e-4d58-baec-ab3a2c5aced3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989974685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.989974685
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.276822339
Short name T749
Test name
Test status
Simulation time 9122016277 ps
CPU time 153.19 seconds
Started Apr 16 02:31:52 PM PDT 24
Finished Apr 16 02:34:26 PM PDT 24
Peak memory 689244 kb
Host smart-5d255e1c-6bce-49ef-b23e-221c12a68ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276822339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.276822339
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3141506390
Short name T1166
Test name
Test status
Simulation time 1535363604 ps
CPU time 45.59 seconds
Started Apr 16 02:31:54 PM PDT 24
Finished Apr 16 02:32:41 PM PDT 24
Peak memory 522412 kb
Host smart-379a844a-682d-4bbf-90a7-937e2457cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141506390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3141506390
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1428037540
Short name T962
Test name
Test status
Simulation time 111240977 ps
CPU time 0.93 seconds
Started Apr 16 02:31:54 PM PDT 24
Finished Apr 16 02:31:57 PM PDT 24
Peak memory 203752 kb
Host smart-c97bd0ab-5d1a-4575-a7bd-13aabcb62475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428037540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1428037540
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3969995212
Short name T326
Test name
Test status
Simulation time 330099712 ps
CPU time 7.09 seconds
Started Apr 16 02:31:58 PM PDT 24
Finished Apr 16 02:32:07 PM PDT 24
Peak memory 223128 kb
Host smart-bcc90d79-50be-40fb-89d2-54d273820dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969995212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3969995212
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1541121800
Short name T87
Test name
Test status
Simulation time 4005432990 ps
CPU time 317.1 seconds
Started Apr 16 02:31:55 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 1190716 kb
Host smart-12c1ffb1-eeee-4d15-a0d1-3f3d2014e4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541121800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1541121800
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.4203706851
Short name T396
Test name
Test status
Simulation time 1788701186 ps
CPU time 18.2 seconds
Started Apr 16 02:31:58 PM PDT 24
Finished Apr 16 02:32:17 PM PDT 24
Peak memory 204024 kb
Host smart-d134fef2-2651-450d-9c7c-cecd8c6726c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203706851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.4203706851
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3444815776
Short name T975
Test name
Test status
Simulation time 1506955824 ps
CPU time 72.92 seconds
Started Apr 16 02:32:00 PM PDT 24
Finished Apr 16 02:33:13 PM PDT 24
Peak memory 357260 kb
Host smart-d3656541-985c-4aac-b663-ee42d70a5208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444815776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3444815776
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.1590887978
Short name T189
Test name
Test status
Simulation time 29258618 ps
CPU time 0.79 seconds
Started Apr 16 02:31:53 PM PDT 24
Finished Apr 16 02:31:55 PM PDT 24
Peak memory 203624 kb
Host smart-8040f8ff-2528-49a5-b081-385bd719aacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590887978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1590887978
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3147433961
Short name T1298
Test name
Test status
Simulation time 14813967098 ps
CPU time 23.27 seconds
Started Apr 16 02:31:54 PM PDT 24
Finished Apr 16 02:32:18 PM PDT 24
Peak memory 413236 kb
Host smart-81efefaf-0c9e-417f-a673-15fb32c9468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147433961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3147433961
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.385237591
Short name T605
Test name
Test status
Simulation time 1031278013 ps
CPU time 20.28 seconds
Started Apr 16 02:31:49 PM PDT 24
Finished Apr 16 02:32:10 PM PDT 24
Peak memory 309584 kb
Host smart-b1270da5-5f35-4987-8362-10f1685fe032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385237591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.385237591
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.636975011
Short name T254
Test name
Test status
Simulation time 14072741213 ps
CPU time 371.34 seconds
Started Apr 16 02:31:54 PM PDT 24
Finished Apr 16 02:38:07 PM PDT 24
Peak memory 1143372 kb
Host smart-e55461e5-ad8a-40a7-85ed-8253dc347c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636975011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.636975011
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.4147644472
Short name T62
Test name
Test status
Simulation time 2205132203 ps
CPU time 25.41 seconds
Started Apr 16 02:31:58 PM PDT 24
Finished Apr 16 02:32:25 PM PDT 24
Peak memory 212332 kb
Host smart-15aed512-eb04-4f00-b0aa-569173609a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147644472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.4147644472
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2675560377
Short name T115
Test name
Test status
Simulation time 40796358 ps
CPU time 0.83 seconds
Started Apr 16 02:32:05 PM PDT 24
Finished Apr 16 02:32:07 PM PDT 24
Peak memory 221040 kb
Host smart-6a4fcd2b-106b-4ddf-afb8-75eab047d832
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675560377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2675560377
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3366528948
Short name T837
Test name
Test status
Simulation time 970999357 ps
CPU time 3.85 seconds
Started Apr 16 02:32:00 PM PDT 24
Finished Apr 16 02:32:04 PM PDT 24
Peak memory 204008 kb
Host smart-e7951855-810c-4846-bd41-a0d5944f1a8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366528948 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3366528948
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1760472398
Short name T1313
Test name
Test status
Simulation time 10143320421 ps
CPU time 27.67 seconds
Started Apr 16 02:31:57 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 331708 kb
Host smart-b27a9f57-e8a3-47e8-8dd7-806ea7980ca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760472398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1760472398
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3882747295
Short name T366
Test name
Test status
Simulation time 10032863183 ps
CPU time 91.36 seconds
Started Apr 16 02:31:56 PM PDT 24
Finished Apr 16 02:33:28 PM PDT 24
Peak memory 556568 kb
Host smart-42ba21bd-fefa-48a4-aea2-810c50d85794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882747295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3882747295
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3304138210
Short name T783
Test name
Test status
Simulation time 1686619198 ps
CPU time 2.44 seconds
Started Apr 16 02:31:57 PM PDT 24
Finished Apr 16 02:32:01 PM PDT 24
Peak memory 203936 kb
Host smart-614d7f85-f2c6-4e1f-aad0-5ae3064bb33d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304138210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3304138210
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1082703157
Short name T743
Test name
Test status
Simulation time 1709512264 ps
CPU time 4.02 seconds
Started Apr 16 02:31:53 PM PDT 24
Finished Apr 16 02:31:59 PM PDT 24
Peak memory 204000 kb
Host smart-5eb25b14-b191-4379-99af-a1645b5b1e36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082703157 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1082703157
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.1168715966
Short name T703
Test name
Test status
Simulation time 18846050257 ps
CPU time 56.41 seconds
Started Apr 16 02:31:57 PM PDT 24
Finished Apr 16 02:32:55 PM PDT 24
Peak memory 899696 kb
Host smart-524602fd-b3b3-4eaa-aa51-1634175d7091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168715966 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.1168715966
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2528274620
Short name T678
Test name
Test status
Simulation time 3529690879 ps
CPU time 11.67 seconds
Started Apr 16 02:31:57 PM PDT 24
Finished Apr 16 02:32:10 PM PDT 24
Peak memory 204016 kb
Host smart-569fe10e-e292-449d-acfa-064edc41ebfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528274620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2528274620
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3195656633
Short name T417
Test name
Test status
Simulation time 1233027187 ps
CPU time 22.64 seconds
Started Apr 16 02:31:52 PM PDT 24
Finished Apr 16 02:32:16 PM PDT 24
Peak memory 215980 kb
Host smart-80881d10-8602-4f60-ae7a-45afe35080ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195656633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3195656633
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.147124722
Short name T1001
Test name
Test status
Simulation time 23378695624 ps
CPU time 14.98 seconds
Started Apr 16 02:31:55 PM PDT 24
Finished Apr 16 02:32:11 PM PDT 24
Peak memory 269712 kb
Host smart-91cc1b6a-a9fa-4328-908c-920541e2f9da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147124722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.147124722
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1162099439
Short name T437
Test name
Test status
Simulation time 1424720064 ps
CPU time 6.56 seconds
Started Apr 16 02:31:59 PM PDT 24
Finished Apr 16 02:32:06 PM PDT 24
Peak memory 212168 kb
Host smart-3eb4d1b1-740f-4b35-a4cc-37b3c377d4c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162099439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1162099439
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3010004589
Short name T106
Test name
Test status
Simulation time 18655469 ps
CPU time 0.6 seconds
Started Apr 16 02:34:53 PM PDT 24
Finished Apr 16 02:34:55 PM PDT 24
Peak memory 203524 kb
Host smart-46edded1-9a23-4c11-b1e4-21e52b5c84c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010004589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3010004589
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2913252815
Short name T681
Test name
Test status
Simulation time 133662917 ps
CPU time 1.67 seconds
Started Apr 16 02:34:48 PM PDT 24
Finished Apr 16 02:34:50 PM PDT 24
Peak memory 212308 kb
Host smart-60bb5e60-ca54-4f05-989d-a213e338fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913252815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2913252815
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.55720502
Short name T282
Test name
Test status
Simulation time 180538450 ps
CPU time 3.75 seconds
Started Apr 16 02:34:46 PM PDT 24
Finished Apr 16 02:34:51 PM PDT 24
Peak memory 233944 kb
Host smart-db734846-7acd-4468-9785-e16a1d5b82f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55720502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty
.55720502
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.3452225188
Short name T1005
Test name
Test status
Simulation time 1600371519 ps
CPU time 51.44 seconds
Started Apr 16 02:34:49 PM PDT 24
Finished Apr 16 02:35:41 PM PDT 24
Peak memory 553592 kb
Host smart-95f1222c-2882-469b-ba94-6f55d361413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452225188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3452225188
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2186648417
Short name T273
Test name
Test status
Simulation time 9566865064 ps
CPU time 64.82 seconds
Started Apr 16 02:34:47 PM PDT 24
Finished Apr 16 02:35:53 PM PDT 24
Peak memory 730156 kb
Host smart-604cddca-852a-48ea-af4a-86484762acc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186648417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2186648417
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.787259044
Short name T778
Test name
Test status
Simulation time 71948274 ps
CPU time 0.87 seconds
Started Apr 16 02:34:46 PM PDT 24
Finished Apr 16 02:34:48 PM PDT 24
Peak memory 203684 kb
Host smart-b4985b38-0b78-4dbd-ab1f-746552e991f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787259044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.787259044
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3074172305
Short name T523
Test name
Test status
Simulation time 268084311 ps
CPU time 3.26 seconds
Started Apr 16 02:34:53 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 223680 kb
Host smart-3ac9bc41-68cb-4bb9-ac80-126be38113be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074172305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3074172305
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.4121859298
Short name T430
Test name
Test status
Simulation time 4073320243 ps
CPU time 307.04 seconds
Started Apr 16 02:34:48 PM PDT 24
Finished Apr 16 02:39:56 PM PDT 24
Peak memory 1204584 kb
Host smart-95406a43-dcc1-4a53-9c69-2def258c6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121859298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.4121859298
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2018260794
Short name T217
Test name
Test status
Simulation time 510141088 ps
CPU time 6.24 seconds
Started Apr 16 02:34:46 PM PDT 24
Finished Apr 16 02:34:54 PM PDT 24
Peak memory 203244 kb
Host smart-0569d7b7-a3cc-4300-b16f-cef9e7f97330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018260794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2018260794
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1436905107
Short name T789
Test name
Test status
Simulation time 1130185851 ps
CPU time 19.55 seconds
Started Apr 16 02:34:50 PM PDT 24
Finished Apr 16 02:35:10 PM PDT 24
Peak memory 311912 kb
Host smart-28a4a985-8310-4c24-8132-667a33f8e2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436905107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1436905107
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.2887882018
Short name T1338
Test name
Test status
Simulation time 99099355 ps
CPU time 0.65 seconds
Started Apr 16 02:34:45 PM PDT 24
Finished Apr 16 02:34:48 PM PDT 24
Peak memory 203648 kb
Host smart-b714c27a-adfc-4491-9b05-b139541c4b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887882018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2887882018
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3749923695
Short name T427
Test name
Test status
Simulation time 6828926351 ps
CPU time 143.92 seconds
Started Apr 16 02:34:47 PM PDT 24
Finished Apr 16 02:37:12 PM PDT 24
Peak memory 304160 kb
Host smart-27a28bcf-2bdc-4c74-9d63-ce7e9a09e6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749923695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3749923695
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1262205281
Short name T836
Test name
Test status
Simulation time 1877201528 ps
CPU time 93.2 seconds
Started Apr 16 02:34:47 PM PDT 24
Finished Apr 16 02:36:22 PM PDT 24
Peak memory 363912 kb
Host smart-7f945f55-d0d7-42a2-a075-59858348e9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262205281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1262205281
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2083196692
Short name T1167
Test name
Test status
Simulation time 2480191115 ps
CPU time 13.26 seconds
Started Apr 16 02:34:48 PM PDT 24
Finished Apr 16 02:35:02 PM PDT 24
Peak memory 214592 kb
Host smart-d01cffaa-c070-4e24-a261-bc1d1ccf6350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083196692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2083196692
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1137976164
Short name T1094
Test name
Test status
Simulation time 2445824631 ps
CPU time 2.64 seconds
Started Apr 16 02:34:53 PM PDT 24
Finished Apr 16 02:34:57 PM PDT 24
Peak memory 204044 kb
Host smart-e17e280e-7636-4d7a-9b35-7a5deaf843d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137976164 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1137976164
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2472120375
Short name T688
Test name
Test status
Simulation time 10081992562 ps
CPU time 69.99 seconds
Started Apr 16 02:34:49 PM PDT 24
Finished Apr 16 02:36:00 PM PDT 24
Peak memory 501488 kb
Host smart-22b3bf3c-00ec-47cf-8feb-2a97ea1baae7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472120375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2472120375
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.413328779
Short name T1237
Test name
Test status
Simulation time 10075442004 ps
CPU time 77.24 seconds
Started Apr 16 02:34:47 PM PDT 24
Finished Apr 16 02:36:05 PM PDT 24
Peak memory 621896 kb
Host smart-f82c5581-9e51-40e7-a0dc-65870caf5f8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413328779 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.413328779
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.66073666
Short name T24
Test name
Test status
Simulation time 486686121 ps
CPU time 1.63 seconds
Started Apr 16 02:34:47 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 203908 kb
Host smart-e3367f1d-fb86-4881-b453-02751f29281b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66073666 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.i2c_target_hrst.66073666
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.375285069
Short name T669
Test name
Test status
Simulation time 6482785398 ps
CPU time 3.39 seconds
Started Apr 16 02:34:46 PM PDT 24
Finished Apr 16 02:34:51 PM PDT 24
Peak memory 207356 kb
Host smart-590204ce-b077-4532-b5a9-ae1ee398800a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375285069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.375285069
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1160944222
Short name T1031
Test name
Test status
Simulation time 3675030487 ps
CPU time 7.45 seconds
Started Apr 16 02:34:46 PM PDT 24
Finished Apr 16 02:34:55 PM PDT 24
Peak memory 204016 kb
Host smart-3f7db156-7cfe-4706-9e15-639dede94dd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160944222 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1160944222
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2461077908
Short name T1074
Test name
Test status
Simulation time 1327191895 ps
CPU time 9.84 seconds
Started Apr 16 02:34:48 PM PDT 24
Finished Apr 16 02:34:59 PM PDT 24
Peak memory 204012 kb
Host smart-efe51c21-6de2-4ab5-bb4d-31cfe55d2a59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461077908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2461077908
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.340037045
Short name T121
Test name
Test status
Simulation time 745433973 ps
CPU time 12.06 seconds
Started Apr 16 02:34:45 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 208408 kb
Host smart-23491f94-75e2-4044-ac04-23d784b53885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340037045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.340037045
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1211181613
Short name T1289
Test name
Test status
Simulation time 39124615599 ps
CPU time 38.96 seconds
Started Apr 16 02:34:46 PM PDT 24
Finished Apr 16 02:35:26 PM PDT 24
Peak memory 762548 kb
Host smart-b61a34bf-03a8-4292-bf5f-8f0190b986d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211181613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1211181613
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3357772010
Short name T747
Test name
Test status
Simulation time 25328877245 ps
CPU time 654.89 seconds
Started Apr 16 02:34:45 PM PDT 24
Finished Apr 16 02:45:41 PM PDT 24
Peak memory 3137820 kb
Host smart-61894d86-3352-4d30-9a90-e76f9df5b8dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357772010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3357772010
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1866887882
Short name T1171
Test name
Test status
Simulation time 2650537638 ps
CPU time 6.67 seconds
Started Apr 16 02:34:52 PM PDT 24
Finished Apr 16 02:34:59 PM PDT 24
Peak memory 216116 kb
Host smart-1042e7d9-ac24-469a-b147-2e0d1a4424a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866887882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1866887882
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1147773838
Short name T1342
Test name
Test status
Simulation time 47967081 ps
CPU time 0.62 seconds
Started Apr 16 02:34:58 PM PDT 24
Finished Apr 16 02:35:00 PM PDT 24
Peak memory 203576 kb
Host smart-a29a33db-a6eb-44e2-8568-9671f0f9c167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147773838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1147773838
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3878714390
Short name T1360
Test name
Test status
Simulation time 137962576 ps
CPU time 1.14 seconds
Started Apr 16 02:34:53 PM PDT 24
Finished Apr 16 02:34:55 PM PDT 24
Peak memory 204120 kb
Host smart-f5e2779e-fd0d-4b46-88f4-46999a02c7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878714390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3878714390
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2876806988
Short name T925
Test name
Test status
Simulation time 1863614439 ps
CPU time 9.29 seconds
Started Apr 16 02:34:49 PM PDT 24
Finished Apr 16 02:34:59 PM PDT 24
Peak memory 294052 kb
Host smart-7ccc2620-5ba4-4938-a92f-eb0cf2dfb58a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876806988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2876806988
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.565949176
Short name T55
Test name
Test status
Simulation time 3836856476 ps
CPU time 146.33 seconds
Started Apr 16 02:34:52 PM PDT 24
Finished Apr 16 02:37:20 PM PDT 24
Peak memory 682224 kb
Host smart-28a577d6-5817-4634-b3b2-26ce001b6ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565949176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.565949176
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3285863102
Short name T319
Test name
Test status
Simulation time 1859124988 ps
CPU time 135.46 seconds
Started Apr 16 02:34:53 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 653736 kb
Host smart-cc548a4c-fe5f-4d29-bed6-7737e1e9006f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285863102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3285863102
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2747836982
Short name T332
Test name
Test status
Simulation time 681032314 ps
CPU time 1.08 seconds
Started Apr 16 02:34:50 PM PDT 24
Finished Apr 16 02:34:52 PM PDT 24
Peak memory 203936 kb
Host smart-a6533f0f-5646-48f6-b79b-da2a793d38f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747836982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2747836982
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2930086308
Short name T4
Test name
Test status
Simulation time 798459474 ps
CPU time 3.76 seconds
Started Apr 16 02:34:52 PM PDT 24
Finished Apr 16 02:34:56 PM PDT 24
Peak memory 203916 kb
Host smart-c75abedb-b786-4c05-8d2f-916cf6df6a7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930086308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2930086308
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3222503187
Short name T566
Test name
Test status
Simulation time 4353542363 ps
CPU time 328.3 seconds
Started Apr 16 02:34:49 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 1230920 kb
Host smart-40566f3d-af1c-4d80-a6a5-69e72a6ea1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222503187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3222503187
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2074979181
Short name T646
Test name
Test status
Simulation time 2018184131 ps
CPU time 8.05 seconds
Started Apr 16 02:34:55 PM PDT 24
Finished Apr 16 02:35:04 PM PDT 24
Peak memory 203936 kb
Host smart-c3b4536a-2c5f-40a4-bd53-4aeaa80a91f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074979181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2074979181
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.583052278
Short name T467
Test name
Test status
Simulation time 1157865126 ps
CPU time 49.93 seconds
Started Apr 16 02:34:55 PM PDT 24
Finished Apr 16 02:35:46 PM PDT 24
Peak memory 297600 kb
Host smart-a31c9eee-7d08-4b4e-8c63-d5ffe73a74bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583052278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.583052278
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2958161004
Short name T192
Test name
Test status
Simulation time 28650282 ps
CPU time 0.67 seconds
Started Apr 16 02:34:45 PM PDT 24
Finished Apr 16 02:34:47 PM PDT 24
Peak memory 203648 kb
Host smart-5e32b4a2-e4e3-4314-9579-476f5235dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958161004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2958161004
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3230097892
Short name T1256
Test name
Test status
Simulation time 50196083290 ps
CPU time 286.87 seconds
Started Apr 16 02:34:51 PM PDT 24
Finished Apr 16 02:39:39 PM PDT 24
Peak memory 1264188 kb
Host smart-1a54ac86-5f71-4939-8c72-8b32f1e50cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230097892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3230097892
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3609352014
Short name T451
Test name
Test status
Simulation time 1675434785 ps
CPU time 28.42 seconds
Started Apr 16 02:34:50 PM PDT 24
Finished Apr 16 02:35:19 PM PDT 24
Peak memory 361284 kb
Host smart-ae527842-fc30-489f-8cb2-7252ceda571c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609352014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3609352014
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.854063523
Short name T167
Test name
Test status
Simulation time 19197956945 ps
CPU time 324.95 seconds
Started Apr 16 02:34:52 PM PDT 24
Finished Apr 16 02:40:19 PM PDT 24
Peak memory 1466080 kb
Host smart-388f1230-3245-4603-8e09-48b7a51e1868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854063523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.854063523
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.3009041432
Short name T613
Test name
Test status
Simulation time 652158778 ps
CPU time 10.42 seconds
Started Apr 16 02:35:09 PM PDT 24
Finished Apr 16 02:35:21 PM PDT 24
Peak memory 215460 kb
Host smart-9b2f1c03-d180-4a76-b317-af85338702d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009041432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3009041432
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.720190586
Short name T604
Test name
Test status
Simulation time 1046272505 ps
CPU time 3.88 seconds
Started Apr 16 02:34:55 PM PDT 24
Finished Apr 16 02:35:00 PM PDT 24
Peak memory 212376 kb
Host smart-29dc1525-79fa-4529-8887-2f2617460de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720190586 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.720190586
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3358741226
Short name T1273
Test name
Test status
Simulation time 10061784416 ps
CPU time 56.44 seconds
Started Apr 16 02:34:50 PM PDT 24
Finished Apr 16 02:35:47 PM PDT 24
Peak memory 470076 kb
Host smart-95f82cd1-2c7e-4a55-8fe9-2b832dd59340
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358741226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3358741226
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.66172104
Short name T766
Test name
Test status
Simulation time 10073972798 ps
CPU time 72.55 seconds
Started Apr 16 02:34:51 PM PDT 24
Finished Apr 16 02:36:05 PM PDT 24
Peak memory 562404 kb
Host smart-02785f20-a07a-463a-ba22-84dbdac817eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66172104 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_fifo_reset_tx.66172104
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1428485518
Short name T706
Test name
Test status
Simulation time 1813121574 ps
CPU time 2.4 seconds
Started Apr 16 02:34:56 PM PDT 24
Finished Apr 16 02:34:59 PM PDT 24
Peak memory 204016 kb
Host smart-c2f69ec2-f322-42fd-827d-effb6d9e1f10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428485518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1428485518
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1207264558
Short name T887
Test name
Test status
Simulation time 2532887203 ps
CPU time 5.5 seconds
Started Apr 16 02:34:51 PM PDT 24
Finished Apr 16 02:34:57 PM PDT 24
Peak memory 216356 kb
Host smart-ca44e0e7-d4b3-4967-bd3b-1bf807b33b2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207264558 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1207264558
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3101138544
Short name T662
Test name
Test status
Simulation time 14985053266 ps
CPU time 6.89 seconds
Started Apr 16 02:34:50 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 231332 kb
Host smart-839db7cc-22c2-48f6-a8db-0ec14561769b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101138544 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3101138544
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.403345125
Short name T264
Test name
Test status
Simulation time 863053203 ps
CPU time 9.99 seconds
Started Apr 16 02:34:52 PM PDT 24
Finished Apr 16 02:35:03 PM PDT 24
Peak memory 203980 kb
Host smart-a3923be0-0e85-44ff-8c88-8960e05bc4bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403345125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.403345125
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2813083387
Short name T1227
Test name
Test status
Simulation time 1529344579 ps
CPU time 60.06 seconds
Started Apr 16 02:34:52 PM PDT 24
Finished Apr 16 02:35:54 PM PDT 24
Peak memory 205112 kb
Host smart-e86397fd-bdc9-4bf8-8d2d-5d01eb4a68ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813083387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2813083387
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.4135572042
Short name T1238
Test name
Test status
Simulation time 33140789995 ps
CPU time 39.42 seconds
Started Apr 16 02:34:52 PM PDT 24
Finished Apr 16 02:35:32 PM PDT 24
Peak memory 787552 kb
Host smart-0d23ce6b-0a90-4cd1-81b9-13613b1edc42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135572042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.4135572042
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3530638733
Short name T1028
Test name
Test status
Simulation time 5411821333 ps
CPU time 6.52 seconds
Started Apr 16 02:34:51 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 210956 kb
Host smart-52ea1ccc-6152-44cd-b97c-7e477eaf8dbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530638733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3530638733
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3434838168
Short name T120
Test name
Test status
Simulation time 19728599 ps
CPU time 0.61 seconds
Started Apr 16 02:35:02 PM PDT 24
Finished Apr 16 02:35:04 PM PDT 24
Peak memory 203516 kb
Host smart-66fee4fd-ec70-468a-a31e-9a542de22205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434838168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3434838168
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1989358035
Short name T684
Test name
Test status
Simulation time 843015558 ps
CPU time 1.66 seconds
Started Apr 16 02:34:55 PM PDT 24
Finished Apr 16 02:34:58 PM PDT 24
Peak memory 212264 kb
Host smart-1f860a4c-7744-4e3f-bde2-6d54deb98e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989358035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1989358035
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3194815018
Short name T60
Test name
Test status
Simulation time 263540035 ps
CPU time 13.5 seconds
Started Apr 16 02:34:56 PM PDT 24
Finished Apr 16 02:35:11 PM PDT 24
Peak memory 259468 kb
Host smart-d937f772-7bf0-427d-bb08-2adf326677c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194815018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3194815018
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.487870221
Short name T397
Test name
Test status
Simulation time 5338623791 ps
CPU time 32.21 seconds
Started Apr 16 02:34:59 PM PDT 24
Finished Apr 16 02:35:32 PM PDT 24
Peak memory 417136 kb
Host smart-02c9c98d-f9c5-4753-b55e-bf63b95c4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487870221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.487870221
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2643473322
Short name T1207
Test name
Test status
Simulation time 1746158835 ps
CPU time 52.05 seconds
Started Apr 16 02:34:57 PM PDT 24
Finished Apr 16 02:35:50 PM PDT 24
Peak memory 638336 kb
Host smart-68daa5d7-0405-411d-9897-42a3b36a281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643473322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2643473322
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.643915865
Short name T640
Test name
Test status
Simulation time 93464865 ps
CPU time 0.89 seconds
Started Apr 16 02:34:59 PM PDT 24
Finished Apr 16 02:35:01 PM PDT 24
Peak memory 203684 kb
Host smart-8f9a0589-1cc9-4c54-bc04-9bc971e0dd7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643915865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.643915865
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.875303119
Short name T1092
Test name
Test status
Simulation time 958626287 ps
CPU time 9.22 seconds
Started Apr 16 02:35:00 PM PDT 24
Finished Apr 16 02:35:10 PM PDT 24
Peak memory 203860 kb
Host smart-669511a1-e7e7-40da-93ba-ab6cd9e054f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875303119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
875303119
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1691352753
Short name T919
Test name
Test status
Simulation time 31180335319 ps
CPU time 116.92 seconds
Started Apr 16 02:34:58 PM PDT 24
Finished Apr 16 02:36:56 PM PDT 24
Peak memory 1136480 kb
Host smart-8ed34a55-1402-4676-ae32-c9af16f823af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691352753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1691352753
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.56276581
Short name T953
Test name
Test status
Simulation time 716883181 ps
CPU time 4.58 seconds
Started Apr 16 02:35:02 PM PDT 24
Finished Apr 16 02:35:07 PM PDT 24
Peak memory 203932 kb
Host smart-0bf84bae-5c2a-4635-9b8b-dcff82c3d42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56276581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.56276581
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3529748334
Short name T821
Test name
Test status
Simulation time 2025429397 ps
CPU time 27.93 seconds
Started Apr 16 02:35:05 PM PDT 24
Finished Apr 16 02:35:34 PM PDT 24
Peak memory 326212 kb
Host smart-e92701b2-6975-4f1a-ad09-7a5da261a523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529748334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3529748334
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.2978324325
Short name T96
Test name
Test status
Simulation time 80223494 ps
CPU time 0.7 seconds
Started Apr 16 02:34:56 PM PDT 24
Finished Apr 16 02:34:57 PM PDT 24
Peak memory 203692 kb
Host smart-c16b042a-908e-42ea-bd03-bb7c662a3981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978324325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.2978324325
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1598210571
Short name T1197
Test name
Test status
Simulation time 7055697913 ps
CPU time 399.17 seconds
Started Apr 16 02:34:58 PM PDT 24
Finished Apr 16 02:41:38 PM PDT 24
Peak memory 789580 kb
Host smart-104e2874-557a-40e1-9ab7-58ee1ed13013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598210571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1598210571
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2944035314
Short name T767
Test name
Test status
Simulation time 6393117326 ps
CPU time 30.9 seconds
Started Apr 16 02:34:58 PM PDT 24
Finished Apr 16 02:35:30 PM PDT 24
Peak memory 284604 kb
Host smart-401bda84-fa26-481b-9db7-04b3a8bf3f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944035314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2944035314
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.927971192
Short name T772
Test name
Test status
Simulation time 4482600355 ps
CPU time 20.26 seconds
Started Apr 16 02:34:57 PM PDT 24
Finished Apr 16 02:35:18 PM PDT 24
Peak memory 212192 kb
Host smart-4e10928b-66c9-419d-a801-333dcaf308ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927971192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.927971192
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2765288264
Short name T311
Test name
Test status
Simulation time 2216541640 ps
CPU time 2.72 seconds
Started Apr 16 02:35:02 PM PDT 24
Finished Apr 16 02:35:05 PM PDT 24
Peak memory 204088 kb
Host smart-38ad540a-9ed9-4f34-9500-c5b863a03c04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765288264 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2765288264
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.749082349
Short name T1194
Test name
Test status
Simulation time 10557177820 ps
CPU time 10.78 seconds
Started Apr 16 02:35:04 PM PDT 24
Finished Apr 16 02:35:15 PM PDT 24
Peak memory 262804 kb
Host smart-4b275442-a7be-440e-82b0-dd7654075c8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749082349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.749082349
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3087110280
Short name T1318
Test name
Test status
Simulation time 880480715 ps
CPU time 2.14 seconds
Started Apr 16 02:35:05 PM PDT 24
Finished Apr 16 02:35:09 PM PDT 24
Peak memory 203996 kb
Host smart-5c9cf88f-d5b8-4726-89d2-7f3809bab48b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087110280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3087110280
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1649856965
Short name T1260
Test name
Test status
Simulation time 2571277402 ps
CPU time 3.76 seconds
Started Apr 16 02:35:01 PM PDT 24
Finished Apr 16 02:35:06 PM PDT 24
Peak memory 204100 kb
Host smart-94dbe560-80ac-456b-86ec-21d66b3bc19d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649856965 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1649856965
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2201755273
Short name T557
Test name
Test status
Simulation time 20527802130 ps
CPU time 39.02 seconds
Started Apr 16 02:35:05 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 747856 kb
Host smart-e79548d5-c222-4fd8-9f30-de00680d4bba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201755273 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2201755273
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2381572950
Short name T101
Test name
Test status
Simulation time 2168083233 ps
CPU time 29.84 seconds
Started Apr 16 02:34:58 PM PDT 24
Finished Apr 16 02:35:28 PM PDT 24
Peak memory 204036 kb
Host smart-7e6b4011-db31-4f3d-8d25-2a753e2bcfbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381572950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2381572950
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1537802176
Short name T329
Test name
Test status
Simulation time 1331034292 ps
CPU time 21.52 seconds
Started Apr 16 02:35:06 PM PDT 24
Finished Apr 16 02:35:28 PM PDT 24
Peak memory 220208 kb
Host smart-7d82bbef-5fe1-44a6-9a7c-3e101f3e0ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537802176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1537802176
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1580720505
Short name T945
Test name
Test status
Simulation time 68522482146 ps
CPU time 1998.13 seconds
Started Apr 16 02:34:57 PM PDT 24
Finished Apr 16 03:08:17 PM PDT 24
Peak memory 10387816 kb
Host smart-bd8a9ba1-735b-4774-9b04-9b9f8da6f6ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580720505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1580720505
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1470957647
Short name T260
Test name
Test status
Simulation time 17810680273 ps
CPU time 107.81 seconds
Started Apr 16 02:35:02 PM PDT 24
Finished Apr 16 02:36:51 PM PDT 24
Peak memory 1196816 kb
Host smart-347c8028-1f95-4771-9758-978c77825075
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470957647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1470957647
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.388104305
Short name T1287
Test name
Test status
Simulation time 5267093160 ps
CPU time 6.42 seconds
Started Apr 16 02:35:01 PM PDT 24
Finished Apr 16 02:35:09 PM PDT 24
Peak memory 212276 kb
Host smart-dc2a61e1-29df-4952-9ced-74165482c16f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388104305 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.388104305
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3601918336
Short name T593
Test name
Test status
Simulation time 17178725 ps
CPU time 0.59 seconds
Started Apr 16 02:35:10 PM PDT 24
Finished Apr 16 02:35:12 PM PDT 24
Peak memory 203564 kb
Host smart-bc26ea1b-24aa-41cb-90d4-b0ae1c668f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601918336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3601918336
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2223638584
Short name T933
Test name
Test status
Simulation time 75597809 ps
CPU time 1.63 seconds
Started Apr 16 02:35:05 PM PDT 24
Finished Apr 16 02:35:08 PM PDT 24
Peak memory 212252 kb
Host smart-aeffe8bc-f74c-4740-b73e-65aa0f51f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223638584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2223638584
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2117613630
Short name T316
Test name
Test status
Simulation time 297975304 ps
CPU time 15.28 seconds
Started Apr 16 02:35:06 PM PDT 24
Finished Apr 16 02:35:22 PM PDT 24
Peak memory 264844 kb
Host smart-a90e5be6-27c6-4a27-8f28-c88f30dc54d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117613630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2117613630
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.25740208
Short name T5
Test name
Test status
Simulation time 10337405714 ps
CPU time 64.83 seconds
Started Apr 16 02:35:07 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 720964 kb
Host smart-ea4917ea-c848-4f52-9889-1cf042557820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25740208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.25740208
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2891414083
Short name T1305
Test name
Test status
Simulation time 3203787550 ps
CPU time 65.61 seconds
Started Apr 16 02:35:03 PM PDT 24
Finished Apr 16 02:36:10 PM PDT 24
Peak memory 693856 kb
Host smart-61d85ad4-d42a-4d76-8c1c-b1ceb75a9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891414083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2891414083
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3247055090
Short name T177
Test name
Test status
Simulation time 267500880 ps
CPU time 1.12 seconds
Started Apr 16 02:35:03 PM PDT 24
Finished Apr 16 02:35:05 PM PDT 24
Peak memory 203936 kb
Host smart-3d4cbd1b-29fc-4034-87f0-767ebcdd5914
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247055090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3247055090
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.4214707174
Short name T861
Test name
Test status
Simulation time 133791820 ps
CPU time 2.93 seconds
Started Apr 16 02:35:06 PM PDT 24
Finished Apr 16 02:35:10 PM PDT 24
Peak memory 203892 kb
Host smart-c490c144-f3bf-484f-bc0c-ecaa376d1d93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214707174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.4214707174
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1727973418
Short name T1290
Test name
Test status
Simulation time 9566000361 ps
CPU time 82.83 seconds
Started Apr 16 02:35:01 PM PDT 24
Finished Apr 16 02:36:25 PM PDT 24
Peak memory 889128 kb
Host smart-69e974e8-6e79-4305-a3ad-d387fb7339e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727973418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1727973418
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.599071429
Short name T897
Test name
Test status
Simulation time 4400384363 ps
CPU time 11.78 seconds
Started Apr 16 02:35:06 PM PDT 24
Finished Apr 16 02:35:19 PM PDT 24
Peak memory 204024 kb
Host smart-b3c4e9e9-85d7-4ff6-8d73-c2ad91399ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599071429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.599071429
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.626177441
Short name T77
Test name
Test status
Simulation time 9284122510 ps
CPU time 19.76 seconds
Started Apr 16 02:35:09 PM PDT 24
Finished Apr 16 02:35:30 PM PDT 24
Peak memory 269128 kb
Host smart-61bb0ee2-4e7c-4e49-b8f1-755ebb4e0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626177441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.626177441
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3149967117
Short name T1244
Test name
Test status
Simulation time 78391046 ps
CPU time 0.68 seconds
Started Apr 16 02:35:03 PM PDT 24
Finished Apr 16 02:35:05 PM PDT 24
Peak memory 203648 kb
Host smart-0da024ee-db49-46e1-aa53-480c7dfa427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149967117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3149967117
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.341412626
Short name T207
Test name
Test status
Simulation time 738586358 ps
CPU time 2.53 seconds
Started Apr 16 02:35:05 PM PDT 24
Finished Apr 16 02:35:09 PM PDT 24
Peak memory 230392 kb
Host smart-3d578bd6-5544-4edc-8ca9-73b8754bbeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341412626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.341412626
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2231927210
Short name T1121
Test name
Test status
Simulation time 3293799011 ps
CPU time 84.35 seconds
Started Apr 16 02:35:00 PM PDT 24
Finished Apr 16 02:36:25 PM PDT 24
Peak memory 301520 kb
Host smart-a8fe71f6-0a74-4e81-a62e-ff424a611b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231927210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2231927210
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.2442475371
Short name T239
Test name
Test status
Simulation time 27419752265 ps
CPU time 770.35 seconds
Started Apr 16 02:35:08 PM PDT 24
Finished Apr 16 02:48:00 PM PDT 24
Peak memory 2998492 kb
Host smart-1506dfed-5cb0-4c01-8d3b-02b9e325c6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442475371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.2442475371
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2560137243
Short name T1141
Test name
Test status
Simulation time 1495562180 ps
CPU time 16.08 seconds
Started Apr 16 02:35:07 PM PDT 24
Finished Apr 16 02:35:25 PM PDT 24
Peak memory 212288 kb
Host smart-f7b5e4ff-a2f3-4450-9514-a435c17bc584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560137243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2560137243
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1802089480
Short name T1218
Test name
Test status
Simulation time 624224489 ps
CPU time 2.67 seconds
Started Apr 16 02:35:07 PM PDT 24
Finished Apr 16 02:35:10 PM PDT 24
Peak memory 203848 kb
Host smart-16a9320f-6253-4b16-9469-af44315f004f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802089480 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1802089480
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.64890262
Short name T611
Test name
Test status
Simulation time 10403614822 ps
CPU time 11.29 seconds
Started Apr 16 02:35:09 PM PDT 24
Finished Apr 16 02:35:22 PM PDT 24
Peak memory 278448 kb
Host smart-a1d75f59-8b77-4380-ac12-9c1cd08349b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64890262 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_acq.64890262
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1286436695
Short name T1087
Test name
Test status
Simulation time 10318092375 ps
CPU time 12.98 seconds
Started Apr 16 02:35:08 PM PDT 24
Finished Apr 16 02:35:22 PM PDT 24
Peak memory 273612 kb
Host smart-8cb99104-43cd-4936-b491-a43e9e09be3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286436695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1286436695
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3800654463
Short name T577
Test name
Test status
Simulation time 835910564 ps
CPU time 2.57 seconds
Started Apr 16 02:35:09 PM PDT 24
Finished Apr 16 02:35:12 PM PDT 24
Peak memory 203304 kb
Host smart-e4843ba6-dd59-4aaa-8a26-6be7ea582d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800654463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3800654463
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2216587521
Short name T1294
Test name
Test status
Simulation time 897855589 ps
CPU time 4.19 seconds
Started Apr 16 02:35:08 PM PDT 24
Finished Apr 16 02:35:14 PM PDT 24
Peak memory 203288 kb
Host smart-40be8dc6-42f4-4ebd-aa13-646908175b60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216587521 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2216587521
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1298731081
Short name T1353
Test name
Test status
Simulation time 14057454938 ps
CPU time 8.31 seconds
Started Apr 16 02:35:07 PM PDT 24
Finished Apr 16 02:35:17 PM PDT 24
Peak memory 243548 kb
Host smart-759e3c75-180e-486e-b4aa-6c301ea87a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298731081 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1298731081
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2992987069
Short name T815
Test name
Test status
Simulation time 8721088947 ps
CPU time 37.59 seconds
Started Apr 16 02:35:06 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 204028 kb
Host smart-75b1a37d-2649-4f34-9eeb-7f2a03c4d53d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992987069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2992987069
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3211358064
Short name T674
Test name
Test status
Simulation time 5590948481 ps
CPU time 55.42 seconds
Started Apr 16 02:35:04 PM PDT 24
Finished Apr 16 02:36:00 PM PDT 24
Peak memory 206772 kb
Host smart-d00fc2b5-3ea8-4dab-9f86-7c06e6dc022a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211358064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3211358064
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1600938628
Short name T21
Test name
Test status
Simulation time 27190257080 ps
CPU time 14.21 seconds
Started Apr 16 02:35:07 PM PDT 24
Finished Apr 16 02:35:22 PM PDT 24
Peak memory 402440 kb
Host smart-2e1ca990-96d9-4bb4-b50f-92e3827b01bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600938628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1600938628
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2960455719
Short name T1090
Test name
Test status
Simulation time 17465872619 ps
CPU time 1021.92 seconds
Started Apr 16 02:35:07 PM PDT 24
Finished Apr 16 02:52:10 PM PDT 24
Peak memory 3992152 kb
Host smart-3173a07f-0e57-4028-96fb-9a91440493eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960455719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2960455719
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2321582811
Short name T359
Test name
Test status
Simulation time 1130815485 ps
CPU time 5.9 seconds
Started Apr 16 02:35:08 PM PDT 24
Finished Apr 16 02:35:15 PM PDT 24
Peak memory 215560 kb
Host smart-fa27e9b0-1b7c-43cb-94eb-fd1aafaa8c0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321582811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2321582811
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3014756130
Short name T1155
Test name
Test status
Simulation time 88503082 ps
CPU time 0.65 seconds
Started Apr 16 02:35:16 PM PDT 24
Finished Apr 16 02:35:17 PM PDT 24
Peak memory 203568 kb
Host smart-d152ee7e-5158-4e5a-8a29-8fe6fc0bad19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014756130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3014756130
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2956788896
Short name T936
Test name
Test status
Simulation time 232915033 ps
CPU time 1.21 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:35:14 PM PDT 24
Peak memory 204084 kb
Host smart-b7d4208f-89d0-40d5-8ac7-e0a4581fb50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956788896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2956788896
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.766092176
Short name T443
Test name
Test status
Simulation time 314626464 ps
CPU time 6.82 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:35:19 PM PDT 24
Peak memory 269816 kb
Host smart-c468855a-f16c-4366-bbe3-9c8da9da46eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766092176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.766092176
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.4231816666
Short name T414
Test name
Test status
Simulation time 2224477999 ps
CPU time 56.56 seconds
Started Apr 16 02:35:10 PM PDT 24
Finished Apr 16 02:36:08 PM PDT 24
Peak memory 645864 kb
Host smart-13526b86-fa4b-49ca-9844-66d8115f7e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231816666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.4231816666
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2413406523
Short name T972
Test name
Test status
Simulation time 5118116115 ps
CPU time 85.82 seconds
Started Apr 16 02:35:10 PM PDT 24
Finished Apr 16 02:36:37 PM PDT 24
Peak memory 496260 kb
Host smart-a9be6450-a7ea-45c5-beec-82ef17d159a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413406523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2413406523
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.349952151
Short name T529
Test name
Test status
Simulation time 130940661 ps
CPU time 1.03 seconds
Started Apr 16 02:35:14 PM PDT 24
Finished Apr 16 02:35:15 PM PDT 24
Peak memory 203736 kb
Host smart-4ae4d9ac-02ab-43c0-a9f1-32fac5d2ca7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349952151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.349952151
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.499880579
Short name T633
Test name
Test status
Simulation time 127084047 ps
CPU time 3.09 seconds
Started Apr 16 02:35:13 PM PDT 24
Finished Apr 16 02:35:17 PM PDT 24
Peak memory 203920 kb
Host smart-882d0f0e-392e-419f-ad75-d4d0f1271ad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499880579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
499880579
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1959172844
Short name T751
Test name
Test status
Simulation time 13150427567 ps
CPU time 292.01 seconds
Started Apr 16 02:35:04 PM PDT 24
Finished Apr 16 02:39:57 PM PDT 24
Peak memory 1096528 kb
Host smart-217177b6-4f8c-4171-a5eb-142f939b9ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959172844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1959172844
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1775355912
Short name T371
Test name
Test status
Simulation time 396028973 ps
CPU time 5.13 seconds
Started Apr 16 02:35:15 PM PDT 24
Finished Apr 16 02:35:21 PM PDT 24
Peak memory 203992 kb
Host smart-9f5dafa0-5ad3-472f-b3d8-d667a2bd2e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775355912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1775355912
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1292999401
Short name T455
Test name
Test status
Simulation time 19655421462 ps
CPU time 21.74 seconds
Started Apr 16 02:35:15 PM PDT 24
Finished Apr 16 02:35:37 PM PDT 24
Peak memory 326212 kb
Host smart-eeafa41e-50e9-4a14-b34e-67d0883ff026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292999401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1292999401
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.2721698927
Short name T193
Test name
Test status
Simulation time 214729300 ps
CPU time 0.7 seconds
Started Apr 16 02:35:06 PM PDT 24
Finished Apr 16 02:35:08 PM PDT 24
Peak memory 203660 kb
Host smart-f439ce31-97e0-4083-9653-a28a4a23463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721698927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2721698927
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.299101900
Short name T76
Test name
Test status
Simulation time 47937802739 ps
CPU time 234.2 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:39:07 PM PDT 24
Peak memory 203988 kb
Host smart-de3b6e5c-d3c7-4791-ba28-52d69875e747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299101900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.299101900
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2545885742
Short name T830
Test name
Test status
Simulation time 4987724838 ps
CPU time 24.47 seconds
Started Apr 16 02:35:10 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 317896 kb
Host smart-9ae7456b-9415-4edd-955c-3e670f3cf978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545885742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2545885742
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.58245230
Short name T256
Test name
Test status
Simulation time 23494255799 ps
CPU time 193.12 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 857536 kb
Host smart-8f0fcb75-3955-4fb6-8f9b-38c54b61c7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58245230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.58245230
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2432438783
Short name T1177
Test name
Test status
Simulation time 1690516232 ps
CPU time 7.38 seconds
Started Apr 16 02:35:14 PM PDT 24
Finished Apr 16 02:35:23 PM PDT 24
Peak memory 219876 kb
Host smart-773b05a3-22c8-4add-bb55-bda0733b6163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432438783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2432438783
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1888438847
Short name T1173
Test name
Test status
Simulation time 2260406767 ps
CPU time 2.88 seconds
Started Apr 16 02:35:15 PM PDT 24
Finished Apr 16 02:35:18 PM PDT 24
Peak memory 204028 kb
Host smart-0c889122-4323-460e-9712-08429e30074d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888438847 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1888438847
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3046521206
Short name T51
Test name
Test status
Simulation time 10161070300 ps
CPU time 14.53 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:35:26 PM PDT 24
Peak memory 274848 kb
Host smart-6e78cfda-c4c2-4de6-b4ed-119aaf7d0df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046521206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3046521206
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.913104267
Short name T92
Test name
Test status
Simulation time 1001815240 ps
CPU time 1.8 seconds
Started Apr 16 02:35:16 PM PDT 24
Finished Apr 16 02:35:19 PM PDT 24
Peak memory 203988 kb
Host smart-e5e7901a-a17a-4ebe-b34a-1628d6387846
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913104267 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_hrst.913104267
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2636279331
Short name T1057
Test name
Test status
Simulation time 2080568244 ps
CPU time 5.6 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:35:18 PM PDT 24
Peak memory 203996 kb
Host smart-04be8403-e500-4ba3-81f6-c4ed0e9645ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636279331 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2636279331
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.759335077
Short name T714
Test name
Test status
Simulation time 20777445270 ps
CPU time 24.86 seconds
Started Apr 16 02:35:14 PM PDT 24
Finished Apr 16 02:35:40 PM PDT 24
Peak memory 521000 kb
Host smart-b2e010fe-09fa-4f5b-b4bc-4638ecb97b27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759335077 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.759335077
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3712716309
Short name T1169
Test name
Test status
Simulation time 1802318372 ps
CPU time 15.92 seconds
Started Apr 16 02:35:10 PM PDT 24
Finished Apr 16 02:35:28 PM PDT 24
Peak memory 204008 kb
Host smart-34ca2085-a6a6-413d-a872-882f97c5c0db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712716309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3712716309
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1222592370
Short name T723
Test name
Test status
Simulation time 5467126771 ps
CPU time 22.48 seconds
Started Apr 16 02:35:12 PM PDT 24
Finished Apr 16 02:35:35 PM PDT 24
Peak memory 224192 kb
Host smart-83b750d2-e434-4ce4-81ad-120b077c92a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222592370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1222592370
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.4248000497
Short name T1174
Test name
Test status
Simulation time 16411284737 ps
CPU time 30.55 seconds
Started Apr 16 02:35:14 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 203992 kb
Host smart-2eb02629-bd31-4c7a-a6b5-35f913096b85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248000497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.4248000497
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.583817134
Short name T805
Test name
Test status
Simulation time 34460451614 ps
CPU time 211.17 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 1821820 kb
Host smart-603a4204-8b5a-4e61-8783-67fff3a13e28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583817134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.583817134
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.531971215
Short name T796
Test name
Test status
Simulation time 4087135704 ps
CPU time 5.58 seconds
Started Apr 16 02:35:11 PM PDT 24
Finished Apr 16 02:35:18 PM PDT 24
Peak memory 204080 kb
Host smart-8489db08-7776-447b-8beb-d47bdd0ecd24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531971215 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.531971215
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.3937010333
Short name T18
Test name
Test status
Simulation time 2534746926 ps
CPU time 5.07 seconds
Started Apr 16 02:35:12 PM PDT 24
Finished Apr 16 02:35:18 PM PDT 24
Peak memory 204056 kb
Host smart-e1fd42b0-bb0a-4518-9e32-a5a1c928153d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937010333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.3937010333
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.202452126
Short name T738
Test name
Test status
Simulation time 33466354 ps
CPU time 0.6 seconds
Started Apr 16 02:35:22 PM PDT 24
Finished Apr 16 02:35:23 PM PDT 24
Peak memory 203592 kb
Host smart-8a43668f-78f5-4a6b-add5-517aa71ef5ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202452126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.202452126
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.168298538
Short name T823
Test name
Test status
Simulation time 62274715 ps
CPU time 1.51 seconds
Started Apr 16 02:35:25 PM PDT 24
Finished Apr 16 02:35:27 PM PDT 24
Peak memory 212296 kb
Host smart-e175a297-9213-45bc-9542-da5ea2076d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168298538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.168298538
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3900279926
Short name T1224
Test name
Test status
Simulation time 697462585 ps
CPU time 6.29 seconds
Started Apr 16 02:35:16 PM PDT 24
Finished Apr 16 02:35:24 PM PDT 24
Peak memory 277388 kb
Host smart-61101a82-4ee7-4372-91c4-7fcd246d63b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900279926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3900279926
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2347055757
Short name T987
Test name
Test status
Simulation time 9174008834 ps
CPU time 86.25 seconds
Started Apr 16 02:35:17 PM PDT 24
Finished Apr 16 02:36:44 PM PDT 24
Peak memory 774884 kb
Host smart-f2efe9f0-29d3-47a0-9af7-c99a90729c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347055757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2347055757
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3789982778
Short name T1126
Test name
Test status
Simulation time 2113650160 ps
CPU time 144.05 seconds
Started Apr 16 02:35:16 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 631540 kb
Host smart-074310e6-6773-49ef-b537-0763d837d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789982778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3789982778
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.744029821
Short name T1233
Test name
Test status
Simulation time 340394822 ps
CPU time 0.92 seconds
Started Apr 16 02:35:17 PM PDT 24
Finished Apr 16 02:35:19 PM PDT 24
Peak memory 203644 kb
Host smart-a2b399a9-0d64-4360-8bcf-f88f95625070
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744029821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.744029821
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3963866440
Short name T444
Test name
Test status
Simulation time 4478004462 ps
CPU time 324.74 seconds
Started Apr 16 02:35:19 PM PDT 24
Finished Apr 16 02:40:45 PM PDT 24
Peak memory 1249072 kb
Host smart-ae11a435-7003-43bf-af52-f02aba42ae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963866440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3963866440
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2428255574
Short name T223
Test name
Test status
Simulation time 301282268 ps
CPU time 7.73 seconds
Started Apr 16 02:35:27 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 204012 kb
Host smart-68bd014d-5fac-49af-a105-8475c5a14224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428255574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2428255574
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2837793227
Short name T973
Test name
Test status
Simulation time 2983728948 ps
CPU time 36.54 seconds
Started Apr 16 02:35:23 PM PDT 24
Finished Apr 16 02:36:00 PM PDT 24
Peak memory 426884 kb
Host smart-fcc678d5-4cd0-4257-b3cc-125938cfd381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837793227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2837793227
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2511171187
Short name T194
Test name
Test status
Simulation time 46985397 ps
CPU time 0.66 seconds
Started Apr 16 02:35:16 PM PDT 24
Finished Apr 16 02:35:18 PM PDT 24
Peak memory 203640 kb
Host smart-5f4cb6c9-907e-4ccd-b6b4-01ab577b25d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511171187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2511171187
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.4281047164
Short name T492
Test name
Test status
Simulation time 49572392481 ps
CPU time 639.56 seconds
Started Apr 16 02:35:21 PM PDT 24
Finished Apr 16 02:46:01 PM PDT 24
Peak memory 204232 kb
Host smart-0edc4055-72e8-45bb-b472-7f1fb6c052bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281047164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4281047164
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.4038372167
Short name T590
Test name
Test status
Simulation time 1579571433 ps
CPU time 24.25 seconds
Started Apr 16 02:35:14 PM PDT 24
Finished Apr 16 02:35:39 PM PDT 24
Peak memory 317844 kb
Host smart-bd615df0-f6f8-441e-b956-d6cfc3311c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038372167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.4038372167
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.606926266
Short name T163
Test name
Test status
Simulation time 15088973205 ps
CPU time 613.7 seconds
Started Apr 16 02:35:22 PM PDT 24
Finished Apr 16 02:45:36 PM PDT 24
Peak memory 2090268 kb
Host smart-34263d12-4865-4d48-8ea5-942776c72dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606926266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.606926266
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3051078374
Short name T378
Test name
Test status
Simulation time 565437733 ps
CPU time 23.75 seconds
Started Apr 16 02:35:21 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 212196 kb
Host smart-b76a49ea-a635-45b9-a689-d31f54d95a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051078374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3051078374
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2503406159
Short name T1356
Test name
Test status
Simulation time 4015708397 ps
CPU time 4.28 seconds
Started Apr 16 02:35:36 PM PDT 24
Finished Apr 16 02:35:41 PM PDT 24
Peak memory 204096 kb
Host smart-7910e1a6-0094-4951-89b1-4937ccb680d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503406159 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2503406159
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.70701820
Short name T645
Test name
Test status
Simulation time 10057083048 ps
CPU time 29.02 seconds
Started Apr 16 02:35:20 PM PDT 24
Finished Apr 16 02:35:49 PM PDT 24
Peak memory 397248 kb
Host smart-487b74b7-d0d0-49ff-83f5-f14ad510f995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70701820 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_fifo_reset_tx.70701820
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2627384042
Short name T991
Test name
Test status
Simulation time 1717605390 ps
CPU time 2.02 seconds
Started Apr 16 02:35:20 PM PDT 24
Finished Apr 16 02:35:23 PM PDT 24
Peak memory 204004 kb
Host smart-69515420-8da4-4690-b118-59b2b834a2c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627384042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2627384042
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2368631247
Short name T271
Test name
Test status
Simulation time 3486927631 ps
CPU time 7.92 seconds
Started Apr 16 02:35:21 PM PDT 24
Finished Apr 16 02:35:30 PM PDT 24
Peak memory 204092 kb
Host smart-ffb9fb48-d94f-4416-a45b-5dc253e46472
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368631247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2368631247
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.313990773
Short name T531
Test name
Test status
Simulation time 14483794019 ps
CPU time 22.96 seconds
Started Apr 16 02:35:22 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 513332 kb
Host smart-b2b6f771-01f0-4e00-b051-66510dcd0783
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313990773 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.313990773
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3242229793
Short name T1204
Test name
Test status
Simulation time 2679208735 ps
CPU time 21.42 seconds
Started Apr 16 02:35:22 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 204064 kb
Host smart-e616a7e4-5536-467a-99b9-fd0b404a0bb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242229793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3242229793
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1971901126
Short name T1303
Test name
Test status
Simulation time 2621381249 ps
CPU time 52.18 seconds
Started Apr 16 02:35:23 PM PDT 24
Finished Apr 16 02:36:16 PM PDT 24
Peak memory 206964 kb
Host smart-cb126a25-e732-4ee8-b740-d1cab3f8313c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971901126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1971901126
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3589760197
Short name T562
Test name
Test status
Simulation time 39237898836 ps
CPU time 564.98 seconds
Started Apr 16 02:35:23 PM PDT 24
Finished Apr 16 02:44:49 PM PDT 24
Peak memory 4932728 kb
Host smart-299c0d20-3abb-4ad0-8a8c-41147e46d0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589760197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3589760197
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.4029487412
Short name T1132
Test name
Test status
Simulation time 9580724599 ps
CPU time 170.6 seconds
Started Apr 16 02:35:23 PM PDT 24
Finished Apr 16 02:38:14 PM PDT 24
Peak memory 1750172 kb
Host smart-9980da9d-b632-40af-ab8d-afd68674e866
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029487412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.4029487412
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2171228303
Short name T12
Test name
Test status
Simulation time 2330552084 ps
CPU time 6.15 seconds
Started Apr 16 02:35:28 PM PDT 24
Finished Apr 16 02:35:35 PM PDT 24
Peak memory 209916 kb
Host smart-80a350e9-31c8-47f2-ad08-fadc1229fda7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171228303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2171228303
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2194210329
Short name T1248
Test name
Test status
Simulation time 16112222 ps
CPU time 0.62 seconds
Started Apr 16 02:35:26 PM PDT 24
Finished Apr 16 02:35:28 PM PDT 24
Peak memory 203560 kb
Host smart-97d1dab7-a6e5-4c88-83f5-b38c64ce1a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194210329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2194210329
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2404975329
Short name T1252
Test name
Test status
Simulation time 105556003 ps
CPU time 1.4 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:35:34 PM PDT 24
Peak memory 212340 kb
Host smart-b803c92d-231c-450a-a7d6-e5ec86164ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404975329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2404975329
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3157200806
Short name T382
Test name
Test status
Simulation time 336093622 ps
CPU time 5.98 seconds
Started Apr 16 02:35:27 PM PDT 24
Finished Apr 16 02:35:35 PM PDT 24
Peak memory 271664 kb
Host smart-75dfb9e5-783a-414b-800d-cba143c670e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157200806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3157200806
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2515362211
Short name T504
Test name
Test status
Simulation time 10643458884 ps
CPU time 76 seconds
Started Apr 16 02:35:36 PM PDT 24
Finished Apr 16 02:36:53 PM PDT 24
Peak memory 707296 kb
Host smart-cef6f767-150f-498c-99d5-cd822cf002c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515362211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2515362211
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.492827555
Short name T1358
Test name
Test status
Simulation time 5650411693 ps
CPU time 45.36 seconds
Started Apr 16 02:35:30 PM PDT 24
Finished Apr 16 02:36:17 PM PDT 24
Peak memory 556504 kb
Host smart-2c88bffc-78f7-4324-ad5b-f81d077d3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492827555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.492827555
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.351668892
Short name T412
Test name
Test status
Simulation time 143018371 ps
CPU time 3.65 seconds
Started Apr 16 02:35:28 PM PDT 24
Finished Apr 16 02:35:33 PM PDT 24
Peak memory 224656 kb
Host smart-25c90086-345b-4f22-bcc6-cc82e93e77c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351668892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
351668892
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.289341494
Short name T1033
Test name
Test status
Simulation time 11116741041 ps
CPU time 69.39 seconds
Started Apr 16 02:35:24 PM PDT 24
Finished Apr 16 02:36:34 PM PDT 24
Peak memory 868916 kb
Host smart-4b9ae812-f1d9-47f3-bdbb-9ab1ec0fef42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289341494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.289341494
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.2707711845
Short name T663
Test name
Test status
Simulation time 517037297 ps
CPU time 2.09 seconds
Started Apr 16 02:35:30 PM PDT 24
Finished Apr 16 02:35:33 PM PDT 24
Peak memory 203992 kb
Host smart-5f00537d-60d9-4278-b427-69d3aed229ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707711845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.2707711845
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2382820844
Short name T842
Test name
Test status
Simulation time 23262495269 ps
CPU time 26.8 seconds
Started Apr 16 02:35:25 PM PDT 24
Finished Apr 16 02:35:53 PM PDT 24
Peak memory 374008 kb
Host smart-4c2fd8cb-a3bf-41e4-9343-7a34c20f6f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382820844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2382820844
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.817876179
Short name T43
Test name
Test status
Simulation time 28788494 ps
CPU time 0.67 seconds
Started Apr 16 02:35:22 PM PDT 24
Finished Apr 16 02:35:24 PM PDT 24
Peak memory 203664 kb
Host smart-a872c4ef-770d-485c-a673-46bbb10c940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817876179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.817876179
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3567743009
Short name T1096
Test name
Test status
Simulation time 29370354826 ps
CPU time 283.37 seconds
Started Apr 16 02:35:32 PM PDT 24
Finished Apr 16 02:40:17 PM PDT 24
Peak memory 203956 kb
Host smart-d43b5b14-5e1f-4364-ab47-6af539766156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567743009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3567743009
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1007632284
Short name T1139
Test name
Test status
Simulation time 1579571754 ps
CPU time 83.07 seconds
Started Apr 16 02:35:28 PM PDT 24
Finished Apr 16 02:36:52 PM PDT 24
Peak memory 401588 kb
Host smart-9203efb5-daef-4056-9eca-a7bf295829a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007632284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1007632284
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.10710080
Short name T1036
Test name
Test status
Simulation time 31067469855 ps
CPU time 997.16 seconds
Started Apr 16 02:35:28 PM PDT 24
Finished Apr 16 02:52:06 PM PDT 24
Peak memory 1489036 kb
Host smart-cf554de9-229e-4c44-a898-fdb5c5e77f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10710080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.10710080
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.4167996574
Short name T242
Test name
Test status
Simulation time 1060903274 ps
CPU time 19.57 seconds
Started Apr 16 02:35:25 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 220384 kb
Host smart-767ec404-7f2c-4f25-b76f-a97e0ac9a631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167996574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.4167996574
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.3204137583
Short name T881
Test name
Test status
Simulation time 2437099716 ps
CPU time 5.1 seconds
Started Apr 16 02:35:26 PM PDT 24
Finished Apr 16 02:35:33 PM PDT 24
Peak memory 205412 kb
Host smart-4a4d8ff6-3cf8-4912-92a9-7a3d7154e935
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204137583 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.3204137583
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1665709712
Short name T469
Test name
Test status
Simulation time 10077982401 ps
CPU time 77.99 seconds
Started Apr 16 02:35:28 PM PDT 24
Finished Apr 16 02:36:47 PM PDT 24
Peak memory 522360 kb
Host smart-a8ef0303-acd7-4684-bf16-ea417a66da8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665709712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1665709712
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.47120184
Short name T599
Test name
Test status
Simulation time 10144187760 ps
CPU time 29.55 seconds
Started Apr 16 02:35:30 PM PDT 24
Finished Apr 16 02:36:00 PM PDT 24
Peak memory 352484 kb
Host smart-c8017936-df77-49a1-ba14-7339db459a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47120184 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_fifo_reset_tx.47120184
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.1712657721
Short name T306
Test name
Test status
Simulation time 366456239 ps
CPU time 2.04 seconds
Started Apr 16 02:35:26 PM PDT 24
Finished Apr 16 02:35:30 PM PDT 24
Peak memory 204008 kb
Host smart-4bedd3a2-ca46-499f-af41-97c9a4c3a041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712657721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.1712657721
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1753012809
Short name T1249
Test name
Test status
Simulation time 8031346969 ps
CPU time 4.36 seconds
Started Apr 16 02:35:36 PM PDT 24
Finished Apr 16 02:35:42 PM PDT 24
Peak memory 219044 kb
Host smart-0a49db5b-c69b-4455-b11e-d7304e1f3298
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753012809 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1753012809
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2707124218
Short name T752
Test name
Test status
Simulation time 3942087873 ps
CPU time 4.19 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 204084 kb
Host smart-0496a941-387f-4fc6-80af-054b3c6f554f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707124218 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2707124218
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.730956125
Short name T891
Test name
Test status
Simulation time 1398085883 ps
CPU time 25.59 seconds
Started Apr 16 02:35:29 PM PDT 24
Finished Apr 16 02:35:55 PM PDT 24
Peak memory 203964 kb
Host smart-bc252c94-d348-40b6-b994-d5790b7c7798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730956125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.730956125
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.4096930362
Short name T827
Test name
Test status
Simulation time 808803438 ps
CPU time 32.54 seconds
Started Apr 16 02:35:36 PM PDT 24
Finished Apr 16 02:36:10 PM PDT 24
Peak memory 204040 kb
Host smart-766672bf-6360-45fe-ba1b-1db371257e46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096930362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.4096930362
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2086954953
Short name T1117
Test name
Test status
Simulation time 9167997154 ps
CPU time 19.64 seconds
Started Apr 16 02:35:25 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 204084 kb
Host smart-63e471a8-bf87-4351-8636-309ebb1edc46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086954953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2086954953
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.23040704
Short name T462
Test name
Test status
Simulation time 11699236399 ps
CPU time 364.12 seconds
Started Apr 16 02:35:26 PM PDT 24
Finished Apr 16 02:41:32 PM PDT 24
Peak memory 2165472 kb
Host smart-41d8cc77-f98b-40bc-aae5-41f104987fc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23040704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_stretch.23040704
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2249221448
Short name T408
Test name
Test status
Simulation time 5346809053 ps
CPU time 6.52 seconds
Started Apr 16 02:35:30 PM PDT 24
Finished Apr 16 02:35:38 PM PDT 24
Peak memory 212280 kb
Host smart-cb2104ff-06d6-45e4-9279-54eb6c3cb283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249221448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2249221448
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.28286203
Short name T1062
Test name
Test status
Simulation time 27351193 ps
CPU time 0.64 seconds
Started Apr 16 02:35:32 PM PDT 24
Finished Apr 16 02:35:35 PM PDT 24
Peak memory 203576 kb
Host smart-aa02b0ba-a7af-46c6-bbed-78b1cd342f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.28286203
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.446962831
Short name T781
Test name
Test status
Simulation time 425823423 ps
CPU time 1.56 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:35:34 PM PDT 24
Peak memory 212284 kb
Host smart-26f09677-d14a-4353-8bd2-131c2ed9809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446962831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.446962831
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.4078433237
Short name T660
Test name
Test status
Simulation time 818629982 ps
CPU time 16.25 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:35:56 PM PDT 24
Peak memory 270004 kb
Host smart-053a3207-bc48-475c-9eb8-06a18f14c92e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078433237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.4078433237
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2578383167
Short name T58
Test name
Test status
Simulation time 1618225235 ps
CPU time 44.97 seconds
Started Apr 16 02:35:43 PM PDT 24
Finished Apr 16 02:36:28 PM PDT 24
Peak memory 477228 kb
Host smart-4ad54c6d-f7e2-4820-ae69-e85e46e6165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578383167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2578383167
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.284605939
Short name T1314
Test name
Test status
Simulation time 616237660 ps
CPU time 0.84 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:35:33 PM PDT 24
Peak memory 203664 kb
Host smart-5d0f7ed5-6e4c-4131-b13b-07dbd478420b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284605939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.284605939
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2838034124
Short name T553
Test name
Test status
Simulation time 858960586 ps
CPU time 9.89 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:35:50 PM PDT 24
Peak memory 235568 kb
Host smart-484eb9f0-c51f-4b15-b89e-f20521ab7e69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838034124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2838034124
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2889126684
Short name T499
Test name
Test status
Simulation time 8378800983 ps
CPU time 109.92 seconds
Started Apr 16 02:35:30 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 1166092 kb
Host smart-907937a4-5093-4bd5-8bba-067450848db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889126684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2889126684
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1173627083
Short name T617
Test name
Test status
Simulation time 334188889 ps
CPU time 13.28 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:35:47 PM PDT 24
Peak memory 203932 kb
Host smart-f4ee8fde-1d1e-451e-9160-90457212efb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173627083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1173627083
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.3812740034
Short name T39
Test name
Test status
Simulation time 2830898406 ps
CPU time 68.77 seconds
Started Apr 16 02:35:33 PM PDT 24
Finished Apr 16 02:36:44 PM PDT 24
Peak memory 406500 kb
Host smart-be2dafee-8b48-4898-abfc-4ef9749ea4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812740034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3812740034
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3774091481
Short name T543
Test name
Test status
Simulation time 196367136 ps
CPU time 0.66 seconds
Started Apr 16 02:35:36 PM PDT 24
Finished Apr 16 02:35:38 PM PDT 24
Peak memory 203692 kb
Host smart-bc78a842-8fb8-44e9-a684-ff77f19448f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774091481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3774091481
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3233631891
Short name T634
Test name
Test status
Simulation time 809287454 ps
CPU time 3.29 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 214076 kb
Host smart-448c0123-21ae-49a2-b4f3-5e1570edbf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233631891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3233631891
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2589604400
Short name T494
Test name
Test status
Simulation time 5135851356 ps
CPU time 23.12 seconds
Started Apr 16 02:35:26 PM PDT 24
Finished Apr 16 02:35:51 PM PDT 24
Peak memory 306312 kb
Host smart-ee3bab3d-6d70-448d-8f9a-e750872f2813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589604400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2589604400
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.145094261
Short name T40
Test name
Test status
Simulation time 858438784 ps
CPU time 37.89 seconds
Started Apr 16 02:35:33 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 212276 kb
Host smart-8a0247c1-613d-4ebb-9dc0-7b3129aad686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145094261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.145094261
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2933574973
Short name T792
Test name
Test status
Simulation time 2398479697 ps
CPU time 2.89 seconds
Started Apr 16 02:35:33 PM PDT 24
Finished Apr 16 02:35:38 PM PDT 24
Peak memory 204016 kb
Host smart-3cf1e660-6afa-4df0-952c-32f29ab2c57e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933574973 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2933574973
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1670112005
Short name T1229
Test name
Test status
Simulation time 10047897304 ps
CPU time 71.06 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:36:52 PM PDT 24
Peak memory 503512 kb
Host smart-2158f11e-253a-42a9-9f6f-ef37c482da5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670112005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1670112005
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2161979071
Short name T1246
Test name
Test status
Simulation time 10689891959 ps
CPU time 9.91 seconds
Started Apr 16 02:35:33 PM PDT 24
Finished Apr 16 02:35:44 PM PDT 24
Peak memory 254752 kb
Host smart-0be839c2-3e34-46a1-ad9e-fd92ff8829f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161979071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2161979071
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1804816
Short name T1040
Test name
Test status
Simulation time 1536631375 ps
CPU time 2.48 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:35:43 PM PDT 24
Peak memory 204024 kb
Host smart-7702e31b-d34b-4eee-9cfb-692b4a7d4da8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804816 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.i2c_target_hrst.1804816
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.4183301797
Short name T624
Test name
Test status
Simulation time 3069302132 ps
CPU time 4.74 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 204068 kb
Host smart-3f4b1ee5-a4dd-4a58-88f7-3f45a57633af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183301797 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.4183301797
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3397347428
Short name T589
Test name
Test status
Simulation time 20597981035 ps
CPU time 27.21 seconds
Started Apr 16 02:35:38 PM PDT 24
Finished Apr 16 02:36:06 PM PDT 24
Peak memory 575276 kb
Host smart-7bdc6127-5d0d-4a70-9e0e-688bfc99b8ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397347428 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3397347428
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3290763738
Short name T369
Test name
Test status
Simulation time 4080607286 ps
CPU time 32.49 seconds
Started Apr 16 02:35:33 PM PDT 24
Finished Apr 16 02:36:07 PM PDT 24
Peak memory 203988 kb
Host smart-34dcca5d-f66e-41a9-b50c-d8dc2a95eda7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290763738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3290763738
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.2208899154
Short name T407
Test name
Test status
Simulation time 901936559 ps
CPU time 15.81 seconds
Started Apr 16 02:35:32 PM PDT 24
Finished Apr 16 02:35:50 PM PDT 24
Peak memory 210028 kb
Host smart-aff01ae8-ff98-4208-ac44-e5ceff738bd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208899154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.2208899154
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.2769998120
Short name T309
Test name
Test status
Simulation time 55492189619 ps
CPU time 1544.49 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 03:01:18 PM PDT 24
Peak memory 8700832 kb
Host smart-62e1c3c9-dba2-47dd-b1d6-3fa38b9f1f0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769998120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.2769998120
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1597438130
Short name T1042
Test name
Test status
Simulation time 31465229059 ps
CPU time 192.61 seconds
Started Apr 16 02:35:35 PM PDT 24
Finished Apr 16 02:38:49 PM PDT 24
Peak memory 1711456 kb
Host smart-34bc983a-5a3e-46ef-9a75-41a2c495d340
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597438130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1597438130
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1769285940
Short name T575
Test name
Test status
Simulation time 2218552762 ps
CPU time 6.1 seconds
Started Apr 16 02:35:35 PM PDT 24
Finished Apr 16 02:35:42 PM PDT 24
Peak memory 220212 kb
Host smart-d4e3998b-718c-4f74-a7b1-9a93e09f77d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769285940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1769285940
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1094420102
Short name T1113
Test name
Test status
Simulation time 18391567 ps
CPU time 0.6 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:35:40 PM PDT 24
Peak memory 203512 kb
Host smart-e98c5248-c4d1-45ba-92dc-2a5d9cae2113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094420102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1094420102
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2106090092
Short name T452
Test name
Test status
Simulation time 91168810 ps
CPU time 1.66 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:35:42 PM PDT 24
Peak memory 212192 kb
Host smart-4cdc567e-3bb1-4134-a015-b0e4a488da15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106090092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2106090092
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1674659562
Short name T304
Test name
Test status
Simulation time 154956743 ps
CPU time 3.34 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:35:36 PM PDT 24
Peak memory 229184 kb
Host smart-f112693e-5dc2-48ec-b099-9eba35ef7e52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674659562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1674659562
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2489002328
Short name T814
Test name
Test status
Simulation time 7821942173 ps
CPU time 116.61 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 480464 kb
Host smart-597357bb-98d4-4799-8c50-afebf812b9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489002328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2489002328
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.4155519735
Short name T546
Test name
Test status
Simulation time 2419793197 ps
CPU time 79.87 seconds
Started Apr 16 02:35:31 PM PDT 24
Finished Apr 16 02:36:53 PM PDT 24
Peak memory 499152 kb
Host smart-a1a52e70-d8f5-41af-a6ff-0594c29f4b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155519735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.4155519735
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.109220471
Short name T955
Test name
Test status
Simulation time 556071494 ps
CPU time 1.03 seconds
Started Apr 16 02:35:29 PM PDT 24
Finished Apr 16 02:35:31 PM PDT 24
Peak memory 203900 kb
Host smart-6e15bebd-c1c0-41e7-985f-3e9be48cefa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109220471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.109220471
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.682031611
Short name T636
Test name
Test status
Simulation time 350400911 ps
CPU time 8.78 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:35:50 PM PDT 24
Peak memory 203876 kb
Host smart-91cc85ed-3613-45aa-82b8-45d774eff768
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682031611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
682031611
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.938831027
Short name T568
Test name
Test status
Simulation time 4712020570 ps
CPU time 110.01 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:37:30 PM PDT 24
Peak memory 1233076 kb
Host smart-85eecb3f-994d-442c-9000-e836cdd2583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938831027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.938831027
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.22553733
Short name T508
Test name
Test status
Simulation time 693629193 ps
CPU time 9.18 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:35:49 PM PDT 24
Peak memory 203960 kb
Host smart-db8a7c4d-6cb7-4a8c-b333-3cd9afb562be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22553733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.22553733
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.4253084326
Short name T520
Test name
Test status
Simulation time 4922162757 ps
CPU time 23.6 seconds
Started Apr 16 02:35:43 PM PDT 24
Finished Apr 16 02:36:08 PM PDT 24
Peak memory 292772 kb
Host smart-8379277f-59f7-44d2-8c7d-7bb0f0a91f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253084326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.4253084326
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3369583607
Short name T225
Test name
Test status
Simulation time 18025578 ps
CPU time 0.71 seconds
Started Apr 16 02:35:33 PM PDT 24
Finished Apr 16 02:35:35 PM PDT 24
Peak memory 203672 kb
Host smart-b01fe1df-b743-433d-a1dc-a26c015d80e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369583607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3369583607
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2726604486
Short name T67
Test name
Test status
Simulation time 12449356492 ps
CPU time 1629.03 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 03:02:48 PM PDT 24
Peak memory 2454928 kb
Host smart-12ada847-038b-4bac-8470-dda28fc2b914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726604486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2726604486
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2373586982
Short name T971
Test name
Test status
Simulation time 7771814922 ps
CPU time 23.88 seconds
Started Apr 16 02:35:33 PM PDT 24
Finished Apr 16 02:35:58 PM PDT 24
Peak memory 315252 kb
Host smart-706cf257-b378-4b99-9335-f4191c0cfa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373586982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2373586982
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.3642753005
Short name T255
Test name
Test status
Simulation time 145202819435 ps
CPU time 1709.04 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 03:04:10 PM PDT 24
Peak memory 1979572 kb
Host smart-55681f8d-d206-4521-bd23-ef1d4895b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642753005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.3642753005
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.351432691
Short name T886
Test name
Test status
Simulation time 7463165303 ps
CPU time 28.13 seconds
Started Apr 16 02:35:42 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 212312 kb
Host smart-803b1544-9f9e-4773-90c1-f81b44886606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351432691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.351432691
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.380488894
Short name T596
Test name
Test status
Simulation time 4734850742 ps
CPU time 4.9 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:47 PM PDT 24
Peak memory 205032 kb
Host smart-9b7c5034-6ab9-4a75-8c10-427d5890aa1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380488894 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.380488894
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1158517272
Short name T1264
Test name
Test status
Simulation time 10706299305 ps
CPU time 10.65 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:35:52 PM PDT 24
Peak memory 279976 kb
Host smart-05ec4af7-6431-4313-98db-966104b03bda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158517272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1158517272
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2977607872
Short name T389
Test name
Test status
Simulation time 10085669715 ps
CPU time 9.61 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:52 PM PDT 24
Peak memory 262724 kb
Host smart-d22a26a0-3d86-4bc5-946e-a5c46c4d12c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977607872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2977607872
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1627404514
Short name T1154
Test name
Test status
Simulation time 544800451 ps
CPU time 2.94 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 204036 kb
Host smart-0fdae6cc-9bd0-4e2f-b98f-b173b5d6e7fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627404514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1627404514
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3820752248
Short name T8
Test name
Test status
Simulation time 3217793126 ps
CPU time 4.03 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:46 PM PDT 24
Peak memory 205564 kb
Host smart-bef091df-8b94-4103-9955-fdcf47288802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820752248 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3820752248
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1258329246
Short name T418
Test name
Test status
Simulation time 14632755056 ps
CPU time 54.24 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 986968 kb
Host smart-6d8d361c-3244-41b6-b88c-e665ba01da5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258329246 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1258329246
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1259073248
Short name T1274
Test name
Test status
Simulation time 3917614386 ps
CPU time 10.92 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:53 PM PDT 24
Peak memory 204008 kb
Host smart-5f8983a3-c86c-42e1-b8d3-4bd8438def2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259073248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1259073248
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3323330155
Short name T327
Test name
Test status
Simulation time 1145625595 ps
CPU time 18.92 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:36:00 PM PDT 24
Peak memory 216352 kb
Host smart-b97833bd-8d7a-439f-9cb0-d53a898efb21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323330155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3323330155
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1921647641
Short name T573
Test name
Test status
Simulation time 30086300686 ps
CPU time 27.24 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:36:08 PM PDT 24
Peak memory 633340 kb
Host smart-6b409ea4-0cb2-4a0e-a392-4b09e67f4474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921647641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1921647641
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3608721986
Short name T1054
Test name
Test status
Simulation time 14352298722 ps
CPU time 699.38 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:47:21 PM PDT 24
Peak memory 3645928 kb
Host smart-1a6b40e6-8598-403b-9f82-a73fbf420cd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608721986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3608721986
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1729912986
Short name T850
Test name
Test status
Simulation time 2814537909 ps
CPU time 6.24 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:49 PM PDT 24
Peak memory 204072 kb
Host smart-7335c93c-2cda-452f-a041-359c9044f514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729912986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1729912986
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3185190898
Short name T491
Test name
Test status
Simulation time 16136895 ps
CPU time 0.59 seconds
Started Apr 16 02:35:48 PM PDT 24
Finished Apr 16 02:35:49 PM PDT 24
Peak memory 203592 kb
Host smart-d72e40a5-e1ea-4779-96bc-b9f772932efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185190898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3185190898
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2450039363
Short name T482
Test name
Test status
Simulation time 70914826 ps
CPU time 1.74 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:44 PM PDT 24
Peak memory 204120 kb
Host smart-607155a1-22aa-48a4-9180-914672f1c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450039363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2450039363
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.750464208
Short name T615
Test name
Test status
Simulation time 284670045 ps
CPU time 13.48 seconds
Started Apr 16 02:35:45 PM PDT 24
Finished Apr 16 02:35:59 PM PDT 24
Peak memory 250000 kb
Host smart-1ff4924c-eb3a-446b-a73b-b096da7014a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750464208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.750464208
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2978414277
Short name T549
Test name
Test status
Simulation time 1790531648 ps
CPU time 90.84 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 422532 kb
Host smart-839289aa-c15b-4737-acfe-a78561b59986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978414277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2978414277
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1285619718
Short name T764
Test name
Test status
Simulation time 1319262581 ps
CPU time 93.73 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 531484 kb
Host smart-f94deb12-1171-4cfa-b699-6436b9f9f833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285619718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1285619718
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3771425202
Short name T1350
Test name
Test status
Simulation time 193303932 ps
CPU time 1.21 seconds
Started Apr 16 02:35:43 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 203884 kb
Host smart-eae963da-5bd4-4741-a8f7-97a1302ecfe7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771425202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3771425202
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2170390376
Short name T313
Test name
Test status
Simulation time 759287070 ps
CPU time 3.58 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:35:45 PM PDT 24
Peak memory 203824 kb
Host smart-3315a439-d4b6-443e-94b8-497710b0af4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170390376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2170390376
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3673048292
Short name T241
Test name
Test status
Simulation time 3555017959 ps
CPU time 237.82 seconds
Started Apr 16 02:35:43 PM PDT 24
Finished Apr 16 02:39:42 PM PDT 24
Peak memory 1021092 kb
Host smart-23c200d1-3be2-49d4-aac9-61cfbf5ffe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673048292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3673048292
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.4131408327
Short name T323
Test name
Test status
Simulation time 2209135110 ps
CPU time 26.75 seconds
Started Apr 16 02:35:49 PM PDT 24
Finished Apr 16 02:36:17 PM PDT 24
Peak memory 204036 kb
Host smart-572d849f-c0e7-4b93-a45a-012768af362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131408327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.4131408327
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3070880186
Short name T272
Test name
Test status
Simulation time 1046735928 ps
CPU time 20.18 seconds
Started Apr 16 02:35:45 PM PDT 24
Finished Apr 16 02:36:06 PM PDT 24
Peak memory 362076 kb
Host smart-49be8ae7-cfff-4924-9e59-13c7774ca5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070880186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3070880186
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1977922373
Short name T1098
Test name
Test status
Simulation time 29703425 ps
CPU time 0.69 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:43 PM PDT 24
Peak memory 203672 kb
Host smart-4eb01320-52ed-4571-be07-47063a1d1540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977922373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1977922373
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1353167459
Short name T943
Test name
Test status
Simulation time 353768900 ps
CPU time 15.71 seconds
Started Apr 16 02:35:41 PM PDT 24
Finished Apr 16 02:35:58 PM PDT 24
Peak memory 263828 kb
Host smart-60c5cd9a-d075-44bc-8060-eaca8042228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353167459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1353167459
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2240027055
Short name T429
Test name
Test status
Simulation time 968617054 ps
CPU time 16.95 seconds
Started Apr 16 02:35:39 PM PDT 24
Finished Apr 16 02:35:56 PM PDT 24
Peak memory 252848 kb
Host smart-c6120066-a5c7-4b6f-9451-1d1740fe7e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240027055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2240027055
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3704612016
Short name T162
Test name
Test status
Simulation time 37129166794 ps
CPU time 895.98 seconds
Started Apr 16 02:35:42 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 1941772 kb
Host smart-d3f728ec-dfc1-4760-bc2f-3cbba9be0d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704612016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3704612016
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3524997760
Short name T1180
Test name
Test status
Simulation time 556222354 ps
CPU time 10.03 seconds
Started Apr 16 02:35:43 PM PDT 24
Finished Apr 16 02:35:54 PM PDT 24
Peak memory 220436 kb
Host smart-b537af90-9eb1-4c2c-bde1-97f8f6b53811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524997760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3524997760
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2446312965
Short name T1010
Test name
Test status
Simulation time 1199340462 ps
CPU time 5.15 seconds
Started Apr 16 02:35:45 PM PDT 24
Finished Apr 16 02:35:51 PM PDT 24
Peak memory 212212 kb
Host smart-44cd9b8f-7657-4ca2-ad21-a31ade2fe7ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446312965 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2446312965
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1400988212
Short name T795
Test name
Test status
Simulation time 10029593999 ps
CPU time 32.35 seconds
Started Apr 16 02:35:47 PM PDT 24
Finished Apr 16 02:36:20 PM PDT 24
Peak memory 345280 kb
Host smart-43eac7b8-b62c-4a76-8f97-148485e34f33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400988212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1400988212
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3460170229
Short name T35
Test name
Test status
Simulation time 10058411243 ps
CPU time 70.87 seconds
Started Apr 16 02:35:47 PM PDT 24
Finished Apr 16 02:36:59 PM PDT 24
Peak memory 549152 kb
Host smart-c1e4d6a7-7b8b-4087-89fd-4f9ffefb1bfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460170229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3460170229
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.3163656336
Short name T507
Test name
Test status
Simulation time 516218655 ps
CPU time 2.83 seconds
Started Apr 16 02:35:46 PM PDT 24
Finished Apr 16 02:35:50 PM PDT 24
Peak memory 204032 kb
Host smart-de84d8f3-f271-4692-9585-9e355c7af704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163656336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.3163656336
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1563204731
Short name T288
Test name
Test status
Simulation time 464223374 ps
CPU time 2.83 seconds
Started Apr 16 02:35:46 PM PDT 24
Finished Apr 16 02:35:50 PM PDT 24
Peak memory 204000 kb
Host smart-6cfd5d79-3071-4382-8383-3a670e26aedd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563204731 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1563204731
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2677542270
Short name T230
Test name
Test status
Simulation time 10257705868 ps
CPU time 16 seconds
Started Apr 16 02:35:40 PM PDT 24
Finished Apr 16 02:35:57 PM PDT 24
Peak memory 437024 kb
Host smart-d02db067-eaac-406f-a08a-8b2dde2701d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677542270 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2677542270
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3292659693
Short name T812
Test name
Test status
Simulation time 837674254 ps
CPU time 29.59 seconds
Started Apr 16 02:35:43 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 204020 kb
Host smart-7b801c3b-8df1-43b1-bb3b-49a3974983cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292659693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3292659693
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.3148361776
Short name T454
Test name
Test status
Simulation time 1542418556 ps
CPU time 62.06 seconds
Started Apr 16 02:35:45 PM PDT 24
Finished Apr 16 02:36:48 PM PDT 24
Peak memory 207264 kb
Host smart-9e560870-c596-4b39-9a29-7f7f1863a748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148361776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.3148361776
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2687944797
Short name T944
Test name
Test status
Simulation time 43788211193 ps
CPU time 717.75 seconds
Started Apr 16 02:35:43 PM PDT 24
Finished Apr 16 02:47:42 PM PDT 24
Peak memory 5849520 kb
Host smart-d4630819-19b2-43a0-aec3-61b3dc0c23c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687944797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2687944797
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.496180762
Short name T720
Test name
Test status
Simulation time 2824878518 ps
CPU time 6.23 seconds
Started Apr 16 02:35:46 PM PDT 24
Finished Apr 16 02:35:53 PM PDT 24
Peak memory 219276 kb
Host smart-aaf05cbc-b6ae-417d-886e-424c1c7c51dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496180762 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.496180762
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.2496237218
Short name T819
Test name
Test status
Simulation time 762969497 ps
CPU time 4.89 seconds
Started Apr 16 02:35:46 PM PDT 24
Finished Apr 16 02:35:52 PM PDT 24
Peak memory 204000 kb
Host smart-5cf30d96-ef36-4bc2-bab9-0a3f19245fce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496237218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.2496237218
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.69296385
Short name T776
Test name
Test status
Simulation time 87892653 ps
CPU time 0.62 seconds
Started Apr 16 02:32:12 PM PDT 24
Finished Apr 16 02:32:14 PM PDT 24
Peak memory 203612 kb
Host smart-d6c60f6b-2901-49d2-b203-c17ce74937fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69296385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.69296385
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2910409073
Short name T1186
Test name
Test status
Simulation time 119431852 ps
CPU time 1.61 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:32:06 PM PDT 24
Peak memory 212240 kb
Host smart-dddb8dda-31bb-489c-aaad-8813eb472ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910409073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2910409073
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3913548673
Short name T658
Test name
Test status
Simulation time 234019065 ps
CPU time 11.96 seconds
Started Apr 16 02:32:11 PM PDT 24
Finished Apr 16 02:32:24 PM PDT 24
Peak memory 251096 kb
Host smart-00712c88-3f6c-4b57-9f21-9ff488cba43f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913548673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3913548673
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3292060277
Short name T1050
Test name
Test status
Simulation time 1540579010 ps
CPU time 31.4 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 253668 kb
Host smart-0ef64853-a7d9-4180-8f87-ccae9feb6b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292060277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3292060277
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1495829865
Short name T294
Test name
Test status
Simulation time 1884132555 ps
CPU time 76.17 seconds
Started Apr 16 02:32:02 PM PDT 24
Finished Apr 16 02:33:18 PM PDT 24
Peak memory 489916 kb
Host smart-65167d08-9e95-4f18-85d1-b0f726eeab02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495829865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1495829865
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2075636459
Short name T463
Test name
Test status
Simulation time 338774625 ps
CPU time 0.77 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:32:05 PM PDT 24
Peak memory 203724 kb
Host smart-3c2ee01a-426f-41a6-a474-3d6c88ac9cd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075636459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2075636459
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.752702511
Short name T1345
Test name
Test status
Simulation time 1526149874 ps
CPU time 10.27 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:32:15 PM PDT 24
Peak memory 203896 kb
Host smart-2408e0b1-be15-42dd-bc7f-59101e80d300
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752702511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.752702511
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2702481373
Short name T168
Test name
Test status
Simulation time 3953366754 ps
CPU time 91.57 seconds
Started Apr 16 02:32:10 PM PDT 24
Finished Apr 16 02:33:43 PM PDT 24
Peak memory 1145476 kb
Host smart-57f695ef-b409-49c8-97d9-4ac78a6c4f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702481373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2702481373
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3894892928
Short name T216
Test name
Test status
Simulation time 335442549 ps
CPU time 13.23 seconds
Started Apr 16 02:32:14 PM PDT 24
Finished Apr 16 02:32:28 PM PDT 24
Peak memory 203928 kb
Host smart-4d97148e-69be-47e5-83cd-d062cf9d7262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894892928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3894892928
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.40819542
Short name T1282
Test name
Test status
Simulation time 3902577621 ps
CPU time 33.16 seconds
Started Apr 16 02:32:10 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 331472 kb
Host smart-d94024aa-41ab-4e70-a08e-f476fd7bc78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40819542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.40819542
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2547258905
Short name T1144
Test name
Test status
Simulation time 46047077 ps
CPU time 0.64 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:32:06 PM PDT 24
Peak memory 203616 kb
Host smart-591f4611-cb52-4cf2-8ffa-7691f5090dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547258905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2547258905
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3840140825
Short name T1043
Test name
Test status
Simulation time 48211445628 ps
CPU time 1490.3 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:56:55 PM PDT 24
Peak memory 2201772 kb
Host smart-a40064be-01b1-4d9d-ad51-bb035854e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840140825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3840140825
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3655254349
Short name T576
Test name
Test status
Simulation time 2625736446 ps
CPU time 20.52 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:32:25 PM PDT 24
Peak memory 294712 kb
Host smart-58320acc-ae07-4a5c-a824-fd69b1b0a27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655254349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3655254349
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.550712909
Short name T180
Test name
Test status
Simulation time 9980253946 ps
CPU time 430.84 seconds
Started Apr 16 02:32:04 PM PDT 24
Finished Apr 16 02:39:16 PM PDT 24
Peak memory 2486696 kb
Host smart-5c6af93e-8e56-4ed9-ab4f-9215c3b10659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550712909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.550712909
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1088218314
Short name T1316
Test name
Test status
Simulation time 2823493897 ps
CPU time 30.64 seconds
Started Apr 16 02:32:10 PM PDT 24
Finished Apr 16 02:32:41 PM PDT 24
Peak memory 212216 kb
Host smart-0eb9571c-f7de-414c-acef-b2834f86ec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088218314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1088218314
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1687713134
Short name T114
Test name
Test status
Simulation time 150962965 ps
CPU time 0.84 seconds
Started Apr 16 02:32:12 PM PDT 24
Finished Apr 16 02:32:14 PM PDT 24
Peak memory 221096 kb
Host smart-f2154c9b-decd-462f-986e-0d33007a5a29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687713134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1687713134
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.646285630
Short name T516
Test name
Test status
Simulation time 10023062431 ps
CPU time 59.88 seconds
Started Apr 16 02:32:02 PM PDT 24
Finished Apr 16 02:33:02 PM PDT 24
Peak memory 482572 kb
Host smart-6ac2a1ce-7bb8-45e3-8a56-21f6f48601ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646285630 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.646285630
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3984233218
Short name T978
Test name
Test status
Simulation time 10221441757 ps
CPU time 20.67 seconds
Started Apr 16 02:32:03 PM PDT 24
Finished Apr 16 02:32:24 PM PDT 24
Peak memory 340256 kb
Host smart-a629df32-5fef-482c-ad56-6211ddbc246a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984233218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3984233218
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.978553844
Short name T285
Test name
Test status
Simulation time 776082189 ps
CPU time 1.99 seconds
Started Apr 16 02:32:09 PM PDT 24
Finished Apr 16 02:32:11 PM PDT 24
Peak memory 203996 kb
Host smart-0df03abe-70dc-4bba-a9a3-50fe82211bd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978553844 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.978553844
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.117795007
Short name T1228
Test name
Test status
Simulation time 1419765259 ps
CPU time 6.48 seconds
Started Apr 16 02:32:02 PM PDT 24
Finished Apr 16 02:32:09 PM PDT 24
Peak memory 220220 kb
Host smart-187f9753-ec3a-4fc1-9e03-b36ff4218f26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117795007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.117795007
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3025712201
Short name T542
Test name
Test status
Simulation time 16390119616 ps
CPU time 129.59 seconds
Started Apr 16 02:32:11 PM PDT 24
Finished Apr 16 02:34:21 PM PDT 24
Peak memory 1777456 kb
Host smart-41eead3b-78ee-45d8-9ac4-7cf906557b13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025712201 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3025712201
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1479364541
Short name T997
Test name
Test status
Simulation time 1585951916 ps
CPU time 13.13 seconds
Started Apr 16 02:32:03 PM PDT 24
Finished Apr 16 02:32:17 PM PDT 24
Peak memory 203928 kb
Host smart-06429c64-f508-460f-8964-3d426ff6e1d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479364541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1479364541
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1875000880
Short name T1104
Test name
Test status
Simulation time 1249716309 ps
CPU time 49.85 seconds
Started Apr 16 02:32:02 PM PDT 24
Finished Apr 16 02:32:53 PM PDT 24
Peak memory 205552 kb
Host smart-e07ac6da-3a61-43d5-9c87-69f1705a3e74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875000880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1875000880
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1175681318
Short name T883
Test name
Test status
Simulation time 27049605093 ps
CPU time 22.93 seconds
Started Apr 16 02:32:03 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 550268 kb
Host smart-2b28bb36-217f-4fd8-bdb7-a3f92d4bca87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175681318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1175681318
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1583313985
Short name T1058
Test name
Test status
Simulation time 1238314492 ps
CPU time 6.13 seconds
Started Apr 16 02:32:03 PM PDT 24
Finished Apr 16 02:32:10 PM PDT 24
Peak memory 212160 kb
Host smart-8860dc34-5599-42e6-9b84-0e6b9df44785
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583313985 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1583313985
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3661429654
Short name T471
Test name
Test status
Simulation time 16144685 ps
CPU time 0.64 seconds
Started Apr 16 02:35:55 PM PDT 24
Finished Apr 16 02:35:56 PM PDT 24
Peak memory 203600 kb
Host smart-4e693c34-80fa-423f-9e6f-c8366b041c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661429654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3661429654
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.4033408054
Short name T279
Test name
Test status
Simulation time 903799855 ps
CPU time 1.79 seconds
Started Apr 16 02:35:59 PM PDT 24
Finished Apr 16 02:36:01 PM PDT 24
Peak memory 212236 kb
Host smart-b55a83af-8997-4ad3-9a3a-c85a33fd24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033408054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.4033408054
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3315568676
Short name T810
Test name
Test status
Simulation time 441958778 ps
CPU time 8.04 seconds
Started Apr 16 02:35:46 PM PDT 24
Finished Apr 16 02:35:55 PM PDT 24
Peak memory 296788 kb
Host smart-537e629d-30ec-47f4-beb0-637d2c4d965a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315568676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3315568676
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2532538581
Short name T1047
Test name
Test status
Simulation time 23201839141 ps
CPU time 49.48 seconds
Started Apr 16 02:35:51 PM PDT 24
Finished Apr 16 02:36:41 PM PDT 24
Peak memory 607328 kb
Host smart-c59d8d8d-42bb-4228-baf2-31a333e024f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532538581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2532538581
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3957186641
Short name T425
Test name
Test status
Simulation time 1461367625 ps
CPU time 102.98 seconds
Started Apr 16 02:35:49 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 552956 kb
Host smart-d165a8cf-063b-410b-b1f1-db9f60a692bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957186641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3957186641
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1294107600
Short name T1258
Test name
Test status
Simulation time 306735325 ps
CPU time 1.02 seconds
Started Apr 16 02:35:49 PM PDT 24
Finished Apr 16 02:35:51 PM PDT 24
Peak memory 203952 kb
Host smart-87f5a30b-3647-41f8-863f-869cc2ec43e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294107600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1294107600
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2028568008
Short name T341
Test name
Test status
Simulation time 197000664 ps
CPU time 3.9 seconds
Started Apr 16 02:35:47 PM PDT 24
Finished Apr 16 02:35:51 PM PDT 24
Peak memory 230416 kb
Host smart-102777a5-1875-4382-ac70-37de04f8db9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028568008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2028568008
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1468104883
Short name T931
Test name
Test status
Simulation time 13667431255 ps
CPU time 248.61 seconds
Started Apr 16 02:35:46 PM PDT 24
Finished Apr 16 02:39:55 PM PDT 24
Peak memory 1053144 kb
Host smart-cdceca18-4052-44d7-9050-50a1778eff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468104883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1468104883
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1096146357
Short name T808
Test name
Test status
Simulation time 842065952 ps
CPU time 6.52 seconds
Started Apr 16 02:35:56 PM PDT 24
Finished Apr 16 02:36:03 PM PDT 24
Peak memory 203992 kb
Host smart-80b4b6cd-6d9b-4f83-8c51-6b645b77e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096146357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1096146357
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3880906871
Short name T1347
Test name
Test status
Simulation time 2373014785 ps
CPU time 24.51 seconds
Started Apr 16 02:35:51 PM PDT 24
Finished Apr 16 02:36:16 PM PDT 24
Peak memory 328704 kb
Host smart-c39d6e25-632b-4163-bc69-cc9b6d680290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880906871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3880906871
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3237539932
Short name T1162
Test name
Test status
Simulation time 84420152 ps
CPU time 0.68 seconds
Started Apr 16 02:35:48 PM PDT 24
Finished Apr 16 02:35:50 PM PDT 24
Peak memory 203648 kb
Host smart-4a01795f-cf8e-4f34-864d-3a7082bde56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237539932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3237539932
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3895752699
Short name T278
Test name
Test status
Simulation time 2888781815 ps
CPU time 34.02 seconds
Started Apr 16 02:35:52 PM PDT 24
Finished Apr 16 02:36:28 PM PDT 24
Peak memory 548536 kb
Host smart-5c17322b-69f0-49c9-9b90-0fcf3e8e1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895752699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3895752699
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2959590829
Short name T801
Test name
Test status
Simulation time 1287672641 ps
CPU time 22.74 seconds
Started Apr 16 02:35:46 PM PDT 24
Finished Apr 16 02:36:09 PM PDT 24
Peak memory 292340 kb
Host smart-131b7bb6-8e38-459f-9ce2-f2907bf0fa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959590829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2959590829
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.134730397
Short name T50
Test name
Test status
Simulation time 14116895232 ps
CPU time 329.29 seconds
Started Apr 16 02:36:00 PM PDT 24
Finished Apr 16 02:41:30 PM PDT 24
Peak memory 1107276 kb
Host smart-4ab84579-deba-45c2-8f14-81ec39f04b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134730397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.134730397
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1740820026
Short name T1053
Test name
Test status
Simulation time 3261635801 ps
CPU time 13.27 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 220376 kb
Host smart-d3b12d20-463b-42ff-a9f9-f3efc6b26167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740820026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1740820026
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.19453464
Short name T28
Test name
Test status
Simulation time 928030133 ps
CPU time 4.19 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:36:03 PM PDT 24
Peak memory 212196 kb
Host smart-645bf1c0-fe3e-4949-9ab5-698d7b78a5d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453464 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_bad_addr.19453464
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2565920586
Short name T993
Test name
Test status
Simulation time 10048751524 ps
CPU time 63.48 seconds
Started Apr 16 02:35:53 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 485888 kb
Host smart-29e52a20-9d82-4139-8044-bd4d656b8d85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565920586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2565920586
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.158358967
Short name T799
Test name
Test status
Simulation time 10056321089 ps
CPU time 55.56 seconds
Started Apr 16 02:35:51 PM PDT 24
Finished Apr 16 02:36:47 PM PDT 24
Peak memory 494332 kb
Host smart-c6a14cc6-404d-4d49-a516-c32bf46be208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158358967 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.158358967
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1375364896
Short name T524
Test name
Test status
Simulation time 315833417 ps
CPU time 1.88 seconds
Started Apr 16 02:35:53 PM PDT 24
Finished Apr 16 02:35:56 PM PDT 24
Peak memory 204028 kb
Host smart-7509f58f-af50-4a7b-8348-276fcfd8d47f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375364896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1375364896
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1912471902
Short name T1310
Test name
Test status
Simulation time 4979169297 ps
CPU time 5.83 seconds
Started Apr 16 02:35:55 PM PDT 24
Finished Apr 16 02:36:02 PM PDT 24
Peak memory 212260 kb
Host smart-aded386d-9206-4d9d-ad38-0e949177090f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912471902 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1912471902
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.3304557960
Short name T370
Test name
Test status
Simulation time 18841832803 ps
CPU time 7.96 seconds
Started Apr 16 02:35:52 PM PDT 24
Finished Apr 16 02:36:01 PM PDT 24
Peak memory 231840 kb
Host smart-efdf5b86-8b49-4f62-8a73-42fcb7ead28a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304557960 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3304557960
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.4136040175
Short name T441
Test name
Test status
Simulation time 3607347242 ps
CPU time 33.8 seconds
Started Apr 16 02:35:54 PM PDT 24
Finished Apr 16 02:36:29 PM PDT 24
Peak memory 204044 kb
Host smart-cb3d2479-1529-4f20-a765-06cdce874ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136040175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.4136040175
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2219743804
Short name T556
Test name
Test status
Simulation time 3231627756 ps
CPU time 32.87 seconds
Started Apr 16 02:35:51 PM PDT 24
Finished Apr 16 02:36:24 PM PDT 24
Peak memory 204048 kb
Host smart-77511e67-59c9-4c53-a7c7-fa1ebe77374f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219743804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2219743804
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.470443066
Short name T479
Test name
Test status
Simulation time 64110329530 ps
CPU time 2106.84 seconds
Started Apr 16 02:35:56 PM PDT 24
Finished Apr 16 03:11:04 PM PDT 24
Peak memory 10813416 kb
Host smart-b11b291c-646a-472f-b3d4-d9e344a78300
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470443066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.470443066
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.467095769
Short name T1266
Test name
Test status
Simulation time 3819146203 ps
CPU time 26.38 seconds
Started Apr 16 02:35:59 PM PDT 24
Finished Apr 16 02:36:26 PM PDT 24
Peak memory 528608 kb
Host smart-822aee7c-2129-4c1a-88a8-75444814dcaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467095769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.467095769
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3969282793
Short name T174
Test name
Test status
Simulation time 5636063963 ps
CPU time 6.04 seconds
Started Apr 16 02:35:54 PM PDT 24
Finished Apr 16 02:36:01 PM PDT 24
Peak memory 220280 kb
Host smart-139ac332-afcb-41c8-b3d6-181bdf7f9481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969282793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3969282793
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3150860391
Short name T343
Test name
Test status
Simulation time 23004344 ps
CPU time 0.66 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 203552 kb
Host smart-58e7b91b-7873-4325-9386-b1483bd59e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150860391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3150860391
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2532983089
Short name T339
Test name
Test status
Simulation time 67012218 ps
CPU time 1.23 seconds
Started Apr 16 02:35:59 PM PDT 24
Finished Apr 16 02:36:01 PM PDT 24
Peak memory 212208 kb
Host smart-db9e29b8-898b-4546-ac74-3f290ed4f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532983089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2532983089
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1875982205
Short name T431
Test name
Test status
Simulation time 464335535 ps
CPU time 24.19 seconds
Started Apr 16 02:35:59 PM PDT 24
Finished Apr 16 02:36:24 PM PDT 24
Peak memory 304740 kb
Host smart-14b7dee1-24af-4b21-aea9-23b0a6587481
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875982205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1875982205
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.329476670
Short name T337
Test name
Test status
Simulation time 6220415492 ps
CPU time 89.53 seconds
Started Apr 16 02:35:55 PM PDT 24
Finished Apr 16 02:37:26 PM PDT 24
Peak memory 321204 kb
Host smart-d4f1d6de-8f7a-4026-aeb7-eb5d9c2fe3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329476670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.329476670
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.670554101
Short name T654
Test name
Test status
Simulation time 4934324810 ps
CPU time 36.04 seconds
Started Apr 16 02:35:56 PM PDT 24
Finished Apr 16 02:36:32 PM PDT 24
Peak memory 447644 kb
Host smart-85835dc4-7420-491e-8253-c8fec53327b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670554101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.670554101
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.291556015
Short name T338
Test name
Test status
Simulation time 131513818 ps
CPU time 0.98 seconds
Started Apr 16 02:35:55 PM PDT 24
Finished Apr 16 02:35:56 PM PDT 24
Peak memory 203720 kb
Host smart-fdf16857-831b-4947-b2aa-352cb6b577f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291556015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.291556015
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2106216145
Short name T210
Test name
Test status
Simulation time 223145122 ps
CPU time 5.98 seconds
Started Apr 16 02:35:58 PM PDT 24
Finished Apr 16 02:36:05 PM PDT 24
Peak memory 203904 kb
Host smart-ed694337-221b-43e2-b4bd-fa933c290155
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106216145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2106216145
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2538840853
Short name T196
Test name
Test status
Simulation time 6557920340 ps
CPU time 234.18 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:39:53 PM PDT 24
Peak memory 988264 kb
Host smart-8725c711-614b-4a64-95c9-3e9aa3d82b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538840853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2538840853
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3740872119
Short name T602
Test name
Test status
Simulation time 322299929 ps
CPU time 4.25 seconds
Started Apr 16 02:36:08 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 203908 kb
Host smart-e6ec346d-84c2-4bff-bcba-85ecde922aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740872119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3740872119
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2470428307
Short name T1337
Test name
Test status
Simulation time 1348029808 ps
CPU time 20.78 seconds
Started Apr 16 02:36:03 PM PDT 24
Finished Apr 16 02:36:24 PM PDT 24
Peak memory 321232 kb
Host smart-b81ed524-22ac-4a5f-94bc-944edf215b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470428307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2470428307
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2864758928
Short name T1340
Test name
Test status
Simulation time 106269598 ps
CPU time 0.67 seconds
Started Apr 16 02:35:55 PM PDT 24
Finished Apr 16 02:35:56 PM PDT 24
Peak memory 203680 kb
Host smart-e16593ac-86f4-49cd-aad4-183dba7ce07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864758928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2864758928
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2976351720
Short name T394
Test name
Test status
Simulation time 74848070881 ps
CPU time 1463.2 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 03:00:21 PM PDT 24
Peak memory 2604124 kb
Host smart-5eef626a-cfd3-4733-b0df-f027ed7eb736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976351720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2976351720
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2832766544
Short name T1032
Test name
Test status
Simulation time 916972611 ps
CPU time 18.74 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:36:16 PM PDT 24
Peak memory 310008 kb
Host smart-d44dfa29-87c9-45ad-8f3f-fafe7434771e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832766544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2832766544
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2815545349
Short name T232
Test name
Test status
Simulation time 47780215050 ps
CPU time 711.52 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:47:49 PM PDT 24
Peak memory 2546536 kb
Host smart-f9814a4e-df36-4f2a-b674-8782608abb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815545349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2815545349
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1238771153
Short name T61
Test name
Test status
Simulation time 2436594229 ps
CPU time 12.05 seconds
Started Apr 16 02:35:56 PM PDT 24
Finished Apr 16 02:36:09 PM PDT 24
Peak memory 214884 kb
Host smart-5e9f1634-ade8-44af-a618-06c9981a1b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238771153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1238771153
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1978153340
Short name T1055
Test name
Test status
Simulation time 1595829882 ps
CPU time 4.48 seconds
Started Apr 16 02:36:02 PM PDT 24
Finished Apr 16 02:36:08 PM PDT 24
Peak memory 212172 kb
Host smart-0c96a6ee-14c3-4d65-9841-39e34e90e2ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978153340 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1978153340
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.559614629
Short name T541
Test name
Test status
Simulation time 10087562791 ps
CPU time 22.06 seconds
Started Apr 16 02:36:01 PM PDT 24
Finished Apr 16 02:36:24 PM PDT 24
Peak memory 320964 kb
Host smart-246e515f-4150-4174-ac9f-d95c516ec9df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559614629 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.559614629
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1713852182
Short name T501
Test name
Test status
Simulation time 10323400546 ps
CPU time 6.88 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:36:17 PM PDT 24
Peak memory 233388 kb
Host smart-d7abe20a-427d-4c25-a2a5-756a0adeca3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713852182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1713852182
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3065181035
Short name T786
Test name
Test status
Simulation time 9025741223 ps
CPU time 3.37 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 204996 kb
Host smart-dfdfd5ee-31c0-4d2e-afcc-2e7f40781aed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065181035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3065181035
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2205819016
Short name T670
Test name
Test status
Simulation time 4053940958 ps
CPU time 5.05 seconds
Started Apr 16 02:35:56 PM PDT 24
Finished Apr 16 02:36:02 PM PDT 24
Peak memory 205152 kb
Host smart-46c27430-6bf1-45f0-872b-e357e3155376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205819016 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2205819016
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3677672051
Short name T912
Test name
Test status
Simulation time 3389820961 ps
CPU time 2.62 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:36:01 PM PDT 24
Peak memory 203964 kb
Host smart-16c91442-7b13-4d6f-acd7-5bca08689285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677672051 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3677672051
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2629781033
Short name T105
Test name
Test status
Simulation time 1612601430 ps
CPU time 13.78 seconds
Started Apr 16 02:35:56 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 204020 kb
Host smart-71b2ec0f-0c17-46e2-8372-b97cd055886f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629781033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2629781033
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2547120295
Short name T544
Test name
Test status
Simulation time 8999727749 ps
CPU time 11.08 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:36:09 PM PDT 24
Peak memory 214616 kb
Host smart-b1978968-b286-4ac6-8c0b-2c92a1bad5a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547120295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2547120295
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1497137873
Short name T511
Test name
Test status
Simulation time 56699827150 ps
CPU time 63.35 seconds
Started Apr 16 02:35:57 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 958248 kb
Host smart-5563f1db-5175-433f-8b1d-c71a92fba26a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497137873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1497137873
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3836464452
Short name T261
Test name
Test status
Simulation time 25072075488 ps
CPU time 145.91 seconds
Started Apr 16 02:36:01 PM PDT 24
Finished Apr 16 02:38:28 PM PDT 24
Peak memory 1441380 kb
Host smart-0a3510a2-8125-4303-881c-c397a5539c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836464452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3836464452
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2028359897
Short name T864
Test name
Test status
Simulation time 2948339314 ps
CPU time 6.62 seconds
Started Apr 16 02:36:04 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 204056 kb
Host smart-6014be68-f325-4e91-9663-56a2d7fbbc64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028359897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2028359897
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2553698033
Short name T863
Test name
Test status
Simulation time 15797338 ps
CPU time 0.63 seconds
Started Apr 16 02:36:11 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 203588 kb
Host smart-2563e34a-1615-436c-b803-7e93d1f1011c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553698033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2553698033
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2310898232
Short name T457
Test name
Test status
Simulation time 128773940 ps
CPU time 1.59 seconds
Started Apr 16 02:36:04 PM PDT 24
Finished Apr 16 02:36:06 PM PDT 24
Peak memory 212292 kb
Host smart-b7800a59-7e25-46a8-8c5b-499cc0861c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310898232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2310898232
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1752448983
Short name T473
Test name
Test status
Simulation time 329815996 ps
CPU time 6.9 seconds
Started Apr 16 02:36:15 PM PDT 24
Finished Apr 16 02:36:22 PM PDT 24
Peak memory 272208 kb
Host smart-200193cb-0fe9-4806-a42c-9dc3b88bcafa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752448983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1752448983
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.515572668
Short name T1295
Test name
Test status
Simulation time 5057444493 ps
CPU time 24.4 seconds
Started Apr 16 02:36:07 PM PDT 24
Finished Apr 16 02:36:32 PM PDT 24
Peak memory 231736 kb
Host smart-5fe16459-fff4-4f40-bc4e-131e7bc47304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515572668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.515572668
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2582567414
Short name T1152
Test name
Test status
Simulation time 1656915106 ps
CPU time 53.94 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:37:04 PM PDT 24
Peak memory 565684 kb
Host smart-8889a6d1-c5fb-4b59-9e26-61b1b5ca9420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582567414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2582567414
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.20978738
Short name T513
Test name
Test status
Simulation time 292639842 ps
CPU time 1.06 seconds
Started Apr 16 02:36:03 PM PDT 24
Finished Apr 16 02:36:04 PM PDT 24
Peak memory 203972 kb
Host smart-423871ce-5f50-4043-b0ee-6ffad27c0dc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt
.20978738
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1579495109
Short name T1271
Test name
Test status
Simulation time 207072292 ps
CPU time 2.78 seconds
Started Apr 16 02:36:04 PM PDT 24
Finished Apr 16 02:36:08 PM PDT 24
Peak memory 203944 kb
Host smart-167b0562-514b-4bfd-9e3c-997a4a858407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579495109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1579495109
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2729659450
Short name T472
Test name
Test status
Simulation time 5356306299 ps
CPU time 62.62 seconds
Started Apr 16 02:36:00 PM PDT 24
Finished Apr 16 02:37:04 PM PDT 24
Peak memory 809172 kb
Host smart-313e1ac8-fd04-4cc4-8de5-5046b21e89c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729659450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2729659450
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3729720146
Short name T375
Test name
Test status
Simulation time 3048460946 ps
CPU time 22.26 seconds
Started Apr 16 02:36:10 PM PDT 24
Finished Apr 16 02:36:33 PM PDT 24
Peak memory 204000 kb
Host smart-68e95f9c-33a3-41c6-8c71-650152d24513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729720146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3729720146
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2213869783
Short name T1116
Test name
Test status
Simulation time 1162704615 ps
CPU time 50.19 seconds
Started Apr 16 02:36:08 PM PDT 24
Finished Apr 16 02:37:00 PM PDT 24
Peak memory 326376 kb
Host smart-094e8be7-af39-4ede-8b50-7cd40abd41ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213869783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2213869783
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2142600312
Short name T771
Test name
Test status
Simulation time 55206500 ps
CPU time 0.67 seconds
Started Apr 16 02:36:10 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 203588 kb
Host smart-82e41dcb-345b-41ff-9f1c-bb8bdba2b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142600312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2142600312
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3258918327
Short name T336
Test name
Test status
Simulation time 1119196163 ps
CPU time 25.5 seconds
Started Apr 16 02:36:05 PM PDT 24
Finished Apr 16 02:36:32 PM PDT 24
Peak memory 276840 kb
Host smart-0d94361e-64b0-468d-89a0-8a7f87a8939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258918327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3258918327
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.270082149
Short name T198
Test name
Test status
Simulation time 3965872153 ps
CPU time 87.96 seconds
Started Apr 16 02:36:01 PM PDT 24
Finished Apr 16 02:37:30 PM PDT 24
Peak memory 388000 kb
Host smart-da06fb2e-db00-4253-8afd-16e08cd0235c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270082149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.270082149
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.1993394238
Short name T257
Test name
Test status
Simulation time 12042750618 ps
CPU time 1354.1 seconds
Started Apr 16 02:36:06 PM PDT 24
Finished Apr 16 02:58:41 PM PDT 24
Peak memory 2439288 kb
Host smart-ba0bcaaa-3f20-4d4d-a992-aef301ba77c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993394238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1993394238
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1436325296
Short name T376
Test name
Test status
Simulation time 1663998676 ps
CPU time 11.14 seconds
Started Apr 16 02:36:06 PM PDT 24
Finished Apr 16 02:36:18 PM PDT 24
Peak memory 220020 kb
Host smart-76f9fc48-b02a-4f29-b95d-cd4d566edeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436325296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1436325296
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.729074429
Short name T1324
Test name
Test status
Simulation time 357054714 ps
CPU time 2.13 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:36:12 PM PDT 24
Peak memory 204048 kb
Host smart-c8b373fd-b2d3-4afb-b8bb-edc054a9d2be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729074429 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.729074429
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1167389519
Short name T785
Test name
Test status
Simulation time 10358878913 ps
CPU time 13.86 seconds
Started Apr 16 02:36:04 PM PDT 24
Finished Apr 16 02:36:18 PM PDT 24
Peak memory 286908 kb
Host smart-43ddfc60-b383-4b8c-8b82-d091674a9400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167389519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1167389519
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.542479119
Short name T484
Test name
Test status
Simulation time 10547045870 ps
CPU time 13.92 seconds
Started Apr 16 02:36:06 PM PDT 24
Finished Apr 16 02:36:20 PM PDT 24
Peak memory 290564 kb
Host smart-a65d6428-00da-4e5b-8b55-632a6d19feb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542479119 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.542479119
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1112736166
Short name T1084
Test name
Test status
Simulation time 5643592860 ps
CPU time 2.25 seconds
Started Apr 16 02:36:11 PM PDT 24
Finished Apr 16 02:36:15 PM PDT 24
Peak memory 204072 kb
Host smart-d09ce95a-2fa9-4e5f-bdfe-27e48f480572
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112736166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1112736166
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2121285804
Short name T348
Test name
Test status
Simulation time 1707850630 ps
CPU time 4.05 seconds
Started Apr 16 02:36:06 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 204004 kb
Host smart-cb47ef58-1c1f-4aab-894f-2053b8831509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121285804 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2121285804
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3729316231
Short name T1003
Test name
Test status
Simulation time 16848063432 ps
CPU time 33.44 seconds
Started Apr 16 02:36:05 PM PDT 24
Finished Apr 16 02:36:39 PM PDT 24
Peak memory 656028 kb
Host smart-1e35674c-b51c-424f-bd20-5341e0504c1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729316231 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3729316231
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2737599216
Short name T384
Test name
Test status
Simulation time 2185958616 ps
CPU time 13.1 seconds
Started Apr 16 02:36:06 PM PDT 24
Finished Apr 16 02:36:20 PM PDT 24
Peak memory 204080 kb
Host smart-6ea10aa1-90e5-4a8b-be72-b2d4caabee0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737599216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2737599216
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.1171387977
Short name T539
Test name
Test status
Simulation time 17458727983 ps
CPU time 26.84 seconds
Started Apr 16 02:36:07 PM PDT 24
Finished Apr 16 02:36:34 PM PDT 24
Peak memory 236692 kb
Host smart-4eeba055-6105-40bf-9ae9-670ad58005d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171387977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.1171387977
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3869728107
Short name T1178
Test name
Test status
Simulation time 17261704163 ps
CPU time 8.71 seconds
Started Apr 16 02:36:07 PM PDT 24
Finished Apr 16 02:36:16 PM PDT 24
Peak memory 204004 kb
Host smart-a08667e6-dc56-4fb8-9fa3-968dc8f81577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869728107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3869728107
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1840342008
Short name T1341
Test name
Test status
Simulation time 20592335817 ps
CPU time 425.09 seconds
Started Apr 16 02:36:14 PM PDT 24
Finished Apr 16 02:43:20 PM PDT 24
Peak memory 2567364 kb
Host smart-83c4279c-96de-44bd-aca3-efc18879447f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840342008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1840342008
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.740850720
Short name T818
Test name
Test status
Simulation time 5227898284 ps
CPU time 6.23 seconds
Started Apr 16 02:36:06 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 213440 kb
Host smart-cb7262dc-cb85-4956-8e56-dc042aab1319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740850720 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.740850720
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.3547036508
Short name T698
Test name
Test status
Simulation time 617578209 ps
CPU time 4.64 seconds
Started Apr 16 02:36:06 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 204060 kb
Host smart-36c7b1fa-4e08-4a9b-9753-ea587f9cc2ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547036508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.3547036508
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.288862660
Short name T800
Test name
Test status
Simulation time 21512399 ps
CPU time 0.61 seconds
Started Apr 16 02:36:24 PM PDT 24
Finished Apr 16 02:36:26 PM PDT 24
Peak memory 203400 kb
Host smart-ba18dd8d-7dae-4235-9a4d-ce7430ae0c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288862660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.288862660
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.927102911
Short name T1330
Test name
Test status
Simulation time 182588589 ps
CPU time 1.55 seconds
Started Apr 16 02:36:08 PM PDT 24
Finished Apr 16 02:36:11 PM PDT 24
Peak memory 220440 kb
Host smart-8617f1b9-489f-42fc-96ad-c1594d0eabad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927102911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.927102911
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2061490419
Short name T1135
Test name
Test status
Simulation time 416679370 ps
CPU time 3.98 seconds
Started Apr 16 02:36:12 PM PDT 24
Finished Apr 16 02:36:16 PM PDT 24
Peak memory 246624 kb
Host smart-7da58ade-ecf8-49c7-ac43-fe103718c5b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061490419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2061490419
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1185675281
Short name T909
Test name
Test status
Simulation time 18017213608 ps
CPU time 80.8 seconds
Started Apr 16 02:36:10 PM PDT 24
Finished Apr 16 02:37:32 PM PDT 24
Peak memory 743924 kb
Host smart-0319473d-5f47-457b-b8ca-3364c4bb861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185675281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1185675281
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.357682384
Short name T1302
Test name
Test status
Simulation time 1429413584 ps
CPU time 94.75 seconds
Started Apr 16 02:36:10 PM PDT 24
Finished Apr 16 02:37:46 PM PDT 24
Peak memory 507520 kb
Host smart-efc28a97-b655-4117-be30-2466b40c5eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357682384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.357682384
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.1559039626
Short name T372
Test name
Test status
Simulation time 160414427 ps
CPU time 1.05 seconds
Started Apr 16 02:36:10 PM PDT 24
Finished Apr 16 02:36:13 PM PDT 24
Peak memory 203868 kb
Host smart-01c93907-9056-4c28-a8f7-b1b85aefc5dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559039626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.1559039626
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1093286499
Short name T1277
Test name
Test status
Simulation time 262700255 ps
CPU time 2.77 seconds
Started Apr 16 02:36:10 PM PDT 24
Finished Apr 16 02:36:14 PM PDT 24
Peak memory 203920 kb
Host smart-dc8e2af0-8ff8-4188-9d2f-f186aaf92349
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093286499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1093286499
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1060196349
Short name T1281
Test name
Test status
Simulation time 4440653380 ps
CPU time 129.68 seconds
Started Apr 16 02:36:11 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 714176 kb
Host smart-0c311d0d-8be0-46c2-8ed0-290a9ed3679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060196349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1060196349
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.4039887651
Short name T517
Test name
Test status
Simulation time 276217179 ps
CPU time 4.59 seconds
Started Apr 16 02:36:17 PM PDT 24
Finished Apr 16 02:36:22 PM PDT 24
Peak memory 203924 kb
Host smart-58c87338-e613-48ba-970b-060af3c15e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039887651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.4039887651
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.900390594
Short name T447
Test name
Test status
Simulation time 3297871943 ps
CPU time 26.21 seconds
Started Apr 16 02:36:14 PM PDT 24
Finished Apr 16 02:36:41 PM PDT 24
Peak memory 358456 kb
Host smart-6fec365a-dd3d-410a-a305-36b1bd67371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900390594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.900390594
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.4101109474
Short name T1188
Test name
Test status
Simulation time 206370426 ps
CPU time 0.63 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:24 PM PDT 24
Peak memory 203404 kb
Host smart-bea1337a-763d-4b6d-8d34-9b7800895000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101109474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.4101109474
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.810922221
Short name T885
Test name
Test status
Simulation time 2848033767 ps
CPU time 30.41 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:36:41 PM PDT 24
Peak memory 463340 kb
Host smart-a7baa439-1091-4cd1-bad9-fad510c1039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810922221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.810922221
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.306465481
Short name T840
Test name
Test status
Simulation time 1444922401 ps
CPU time 24.88 seconds
Started Apr 16 02:36:10 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 318620 kb
Host smart-60b74ab9-a143-4637-9050-1ed5680f5ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306465481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.306465481
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.2644333364
Short name T1235
Test name
Test status
Simulation time 7747537734 ps
CPU time 307.12 seconds
Started Apr 16 02:36:16 PM PDT 24
Finished Apr 16 02:41:24 PM PDT 24
Peak memory 1608236 kb
Host smart-f1986d0e-fe30-4527-b89e-8f22c0d86f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644333364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.2644333364
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.713369149
Short name T934
Test name
Test status
Simulation time 425180688 ps
CPU time 19.49 seconds
Started Apr 16 02:36:11 PM PDT 24
Finished Apr 16 02:36:32 PM PDT 24
Peak memory 212212 kb
Host smart-a006fcca-8c79-4df7-bc54-951d2325cb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713369149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.713369149
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3408500583
Short name T994
Test name
Test status
Simulation time 682630558 ps
CPU time 2.22 seconds
Started Apr 16 02:36:16 PM PDT 24
Finished Apr 16 02:36:19 PM PDT 24
Peak memory 203996 kb
Host smart-a4e5b6ca-419c-451a-9a32-8401403e8731
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408500583 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3408500583
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.4046529144
Short name T982
Test name
Test status
Simulation time 10076550435 ps
CPU time 65.02 seconds
Started Apr 16 02:36:13 PM PDT 24
Finished Apr 16 02:37:19 PM PDT 24
Peak memory 501332 kb
Host smart-78063830-324d-4ff3-9d46-996fa834f5a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046529144 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.4046529144
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1533408675
Short name T415
Test name
Test status
Simulation time 10101361576 ps
CPU time 64.07 seconds
Started Apr 16 02:36:24 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 567564 kb
Host smart-390e81e2-c225-417a-ace5-ebc23a32d0ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533408675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1533408675
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.4140400722
Short name T25
Test name
Test status
Simulation time 1515938518 ps
CPU time 2.16 seconds
Started Apr 16 02:36:16 PM PDT 24
Finished Apr 16 02:36:19 PM PDT 24
Peak memory 203984 kb
Host smart-bbd2579b-99c0-484c-881a-ffca20e9d3dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140400722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.4140400722
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1667337156
Short name T1278
Test name
Test status
Simulation time 5017450546 ps
CPU time 5.95 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:30 PM PDT 24
Peak memory 212012 kb
Host smart-1254b2c2-16c5-4cb5-8ca2-7a79eb2672d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667337156 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1667337156
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1538490739
Short name T708
Test name
Test status
Simulation time 18210801023 ps
CPU time 267.3 seconds
Started Apr 16 02:36:11 PM PDT 24
Finished Apr 16 02:40:39 PM PDT 24
Peak memory 2871852 kb
Host smart-9c489238-fc4d-47b1-9981-13b2763e09f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538490739 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1538490739
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3045557481
Short name T1300
Test name
Test status
Simulation time 8792002006 ps
CPU time 11.26 seconds
Started Apr 16 02:36:09 PM PDT 24
Finished Apr 16 02:36:21 PM PDT 24
Peak memory 204096 kb
Host smart-df2e8231-35a3-42af-80a8-121373d6f6c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045557481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3045557481
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.308002611
Short name T839
Test name
Test status
Simulation time 10653203473 ps
CPU time 22.62 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:47 PM PDT 24
Peak memory 220192 kb
Host smart-0b30822b-5479-4250-b4d9-633a8bda61cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308002611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_stress_all.308002611
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2952796096
Short name T528
Test name
Test status
Simulation time 444775962 ps
CPU time 7.53 seconds
Started Apr 16 02:36:11 PM PDT 24
Finished Apr 16 02:36:20 PM PDT 24
Peak memory 204008 kb
Host smart-1a8a72cf-f73e-49ea-a8bb-26adfcd31df3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952796096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2952796096
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2253010406
Short name T32
Test name
Test status
Simulation time 59326112024 ps
CPU time 1884.63 seconds
Started Apr 16 02:36:11 PM PDT 24
Finished Apr 16 03:07:37 PM PDT 24
Peak memory 10040544 kb
Host smart-de1fe15c-259e-43b6-b0f7-4fa4c14e9bf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253010406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2253010406
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2338546509
Short name T770
Test name
Test status
Simulation time 29183037032 ps
CPU time 168.81 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:39:13 PM PDT 24
Peak memory 1449940 kb
Host smart-0121fa60-98cc-46ac-aa0e-b9f8ba6d00f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338546509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2338546509
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2679127031
Short name T1239
Test name
Test status
Simulation time 22662788 ps
CPU time 0.61 seconds
Started Apr 16 02:36:20 PM PDT 24
Finished Apr 16 02:36:21 PM PDT 24
Peak memory 203544 kb
Host smart-dfcbe038-2c56-4876-98bd-81f2d7a54098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679127031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2679127031
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2696072352
Short name T608
Test name
Test status
Simulation time 55364950 ps
CPU time 1.6 seconds
Started Apr 16 02:36:21 PM PDT 24
Finished Apr 16 02:36:24 PM PDT 24
Peak memory 212272 kb
Host smart-b610d50d-af13-49ef-a1c7-0531dd230de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696072352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2696072352
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1656809423
Short name T976
Test name
Test status
Simulation time 1844684355 ps
CPU time 4.67 seconds
Started Apr 16 02:36:16 PM PDT 24
Finished Apr 16 02:36:22 PM PDT 24
Peak memory 226980 kb
Host smart-83ee4aed-c5aa-481e-998e-43e3fb8f4f7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656809423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1656809423
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3001394919
Short name T70
Test name
Test status
Simulation time 2123680029 ps
CPU time 61.14 seconds
Started Apr 16 02:36:14 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 582316 kb
Host smart-fef4defc-69a5-4ff5-a9da-b679fca20154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001394919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3001394919
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.1131400891
Short name T1093
Test name
Test status
Simulation time 1813883808 ps
CPU time 128.77 seconds
Started Apr 16 02:36:16 PM PDT 24
Finished Apr 16 02:38:26 PM PDT 24
Peak memory 593948 kb
Host smart-2f53b0b6-eace-4908-ab32-d40eda687d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131400891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1131400891
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2790805611
Short name T1075
Test name
Test status
Simulation time 95315946 ps
CPU time 0.92 seconds
Started Apr 16 02:36:16 PM PDT 24
Finished Apr 16 02:36:18 PM PDT 24
Peak memory 203680 kb
Host smart-02e2d35d-3049-4c66-9714-ffd81df46b71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790805611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2790805611
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3194206055
Short name T307
Test name
Test status
Simulation time 698696889 ps
CPU time 3.32 seconds
Started Apr 16 02:36:13 PM PDT 24
Finished Apr 16 02:36:17 PM PDT 24
Peak memory 219816 kb
Host smart-0fc67c57-3f91-4602-bac2-0c27413eb613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194206055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3194206055
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2822408975
Short name T295
Test name
Test status
Simulation time 4225942429 ps
CPU time 122.66 seconds
Started Apr 16 02:36:15 PM PDT 24
Finished Apr 16 02:38:19 PM PDT 24
Peak memory 1183920 kb
Host smart-85dffd26-a39a-4f44-bb92-9fc0fc0905c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822408975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2822408975
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2891997860
Short name T526
Test name
Test status
Simulation time 988281745 ps
CPU time 19.85 seconds
Started Apr 16 02:36:18 PM PDT 24
Finished Apr 16 02:36:39 PM PDT 24
Peak memory 203904 kb
Host smart-f55807e4-231d-4cce-963d-d5f945441842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891997860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2891997860
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3110539559
Short name T522
Test name
Test status
Simulation time 18787715643 ps
CPU time 93.23 seconds
Started Apr 16 02:36:20 PM PDT 24
Finished Apr 16 02:37:54 PM PDT 24
Peak memory 418840 kb
Host smart-2605495b-3175-4e04-8c49-95e7b65fbe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110539559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3110539559
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2012449579
Short name T1008
Test name
Test status
Simulation time 26544472 ps
CPU time 0.67 seconds
Started Apr 16 02:36:14 PM PDT 24
Finished Apr 16 02:36:15 PM PDT 24
Peak memory 203660 kb
Host smart-50924e92-e4a6-47d8-96bb-824976474446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012449579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2012449579
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3973495805
Short name T958
Test name
Test status
Simulation time 11753398448 ps
CPU time 115.7 seconds
Started Apr 16 02:36:15 PM PDT 24
Finished Apr 16 02:38:12 PM PDT 24
Peak memory 212244 kb
Host smart-f2315b22-7e6e-43fd-8156-6d44c129947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973495805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3973495805
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2116474826
Short name T1102
Test name
Test status
Simulation time 11218435914 ps
CPU time 21.23 seconds
Started Apr 16 02:36:15 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 314712 kb
Host smart-bd0dceb2-e5d0-4aca-9f77-21a174c47eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116474826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2116474826
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.3790769239
Short name T1319
Test name
Test status
Simulation time 2071484763 ps
CPU time 20.28 seconds
Started Apr 16 02:36:15 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 212208 kb
Host smart-aa8680b4-2a74-43cc-95ca-515ba976f208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790769239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3790769239
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2953523181
Short name T630
Test name
Test status
Simulation time 2222954202 ps
CPU time 2.84 seconds
Started Apr 16 02:36:20 PM PDT 24
Finished Apr 16 02:36:24 PM PDT 24
Peak memory 204088 kb
Host smart-8a498ad3-991d-4549-877c-ccbea81e513a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953523181 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2953523181
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1946761024
Short name T1097
Test name
Test status
Simulation time 10178880844 ps
CPU time 69.26 seconds
Started Apr 16 02:36:21 PM PDT 24
Finished Apr 16 02:37:31 PM PDT 24
Peak memory 538632 kb
Host smart-7ea390a9-b0b7-4f7d-86ea-a4f54771808e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946761024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1946761024
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3440418688
Short name T642
Test name
Test status
Simulation time 10254080605 ps
CPU time 13.14 seconds
Started Apr 16 02:36:22 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 298884 kb
Host smart-f5595013-8702-4a18-9878-db9bb524d284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440418688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3440418688
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3570079371
Short name T741
Test name
Test status
Simulation time 1209982691 ps
CPU time 2.04 seconds
Started Apr 16 02:36:22 PM PDT 24
Finished Apr 16 02:36:25 PM PDT 24
Peak memory 204012 kb
Host smart-a3a75f10-0ad7-43e2-bb1f-ef0236bc11b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570079371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3570079371
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3196215195
Short name T1086
Test name
Test status
Simulation time 790349754 ps
CPU time 4.05 seconds
Started Apr 16 02:36:18 PM PDT 24
Finished Apr 16 02:36:23 PM PDT 24
Peak memory 204040 kb
Host smart-4118feba-3af1-457f-8b97-e7e668fcf2e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196215195 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3196215195
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.182993367
Short name T536
Test name
Test status
Simulation time 21394554390 ps
CPU time 56.83 seconds
Started Apr 16 02:36:21 PM PDT 24
Finished Apr 16 02:37:19 PM PDT 24
Peak memory 850028 kb
Host smart-35ff80e0-78db-40da-bacb-dfcd9235e733
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182993367 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.182993367
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2845525644
Short name T387
Test name
Test status
Simulation time 4898551848 ps
CPU time 19.45 seconds
Started Apr 16 02:36:19 PM PDT 24
Finished Apr 16 02:36:39 PM PDT 24
Peak memory 204036 kb
Host smart-9ddc5e5f-61cf-44d7-bbdc-c4440c7a0c79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845525644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2845525644
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.988974812
Short name T691
Test name
Test status
Simulation time 586192220 ps
CPU time 21.45 seconds
Started Apr 16 02:36:22 PM PDT 24
Finished Apr 16 02:36:44 PM PDT 24
Peak memory 204032 kb
Host smart-25c9f6f6-1acb-444f-b525-28f493b020da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988974812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.988974812
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3635860215
Short name T386
Test name
Test status
Simulation time 16086635518 ps
CPU time 29 seconds
Started Apr 16 02:36:19 PM PDT 24
Finished Apr 16 02:36:49 PM PDT 24
Peak memory 204012 kb
Host smart-7ad3b9cf-7d86-4acf-ac4a-2c88b9aaf70e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635860215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3635860215
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2072709593
Short name T1111
Test name
Test status
Simulation time 6131493350 ps
CPU time 336.73 seconds
Started Apr 16 02:36:20 PM PDT 24
Finished Apr 16 02:41:58 PM PDT 24
Peak memory 1314440 kb
Host smart-1e9fea6f-7776-4411-b765-edd112ad3946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072709593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2072709593
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2382592096
Short name T854
Test name
Test status
Simulation time 1348373687 ps
CPU time 7.06 seconds
Started Apr 16 02:36:20 PM PDT 24
Finished Apr 16 02:36:28 PM PDT 24
Peak memory 218408 kb
Host smart-d6fa2c29-8917-466b-bd15-f32cc5d850aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382592096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2382592096
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.3100279161
Short name T826
Test name
Test status
Simulation time 6742808416 ps
CPU time 4.99 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:29 PM PDT 24
Peak memory 204116 kb
Host smart-6711ef06-cfbb-4276-8e65-c863843de8cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100279161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.3100279161
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.771752003
Short name T1109
Test name
Test status
Simulation time 44755276 ps
CPU time 0.59 seconds
Started Apr 16 02:36:29 PM PDT 24
Finished Apr 16 02:36:30 PM PDT 24
Peak memory 203556 kb
Host smart-e3544e97-6bb4-4c1a-b72b-a3cb41f0841e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771752003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.771752003
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1897177164
Short name T1208
Test name
Test status
Simulation time 434056707 ps
CPU time 1.62 seconds
Started Apr 16 02:36:24 PM PDT 24
Finished Apr 16 02:36:27 PM PDT 24
Peak memory 220416 kb
Host smart-37b3ffed-245e-427a-a743-3f301d18e6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897177164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1897177164
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2577353727
Short name T940
Test name
Test status
Simulation time 388690981 ps
CPU time 9.27 seconds
Started Apr 16 02:36:20 PM PDT 24
Finished Apr 16 02:36:31 PM PDT 24
Peak memory 220556 kb
Host smart-1b4ed4d9-68a0-40ae-9559-ba3fc59721eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577353727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2577353727
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2590702287
Short name T598
Test name
Test status
Simulation time 2040636515 ps
CPU time 42.48 seconds
Started Apr 16 02:36:26 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 504172 kb
Host smart-39cb56d1-d895-4795-b744-f3e3203fe267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590702287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2590702287
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2097815464
Short name T1147
Test name
Test status
Simulation time 1919869835 ps
CPU time 51.98 seconds
Started Apr 16 02:36:21 PM PDT 24
Finished Apr 16 02:37:14 PM PDT 24
Peak memory 629608 kb
Host smart-8714d734-a027-4a94-87f2-8e9ba689f68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097815464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2097815464
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.505588441
Short name T990
Test name
Test status
Simulation time 106955212 ps
CPU time 0.94 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:25 PM PDT 24
Peak memory 203644 kb
Host smart-3f5358dd-fb92-4680-9c24-95db58b3b4ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505588441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.505588441
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1419886642
Short name T565
Test name
Test status
Simulation time 1425564068 ps
CPU time 4.39 seconds
Started Apr 16 02:36:25 PM PDT 24
Finished Apr 16 02:36:30 PM PDT 24
Peak memory 230584 kb
Host smart-1bb356dc-6d81-41f8-ba24-cbf4f61adc7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419886642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1419886642
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.354616781
Short name T1292
Test name
Test status
Simulation time 2977310745 ps
CPU time 86.98 seconds
Started Apr 16 02:36:19 PM PDT 24
Finished Apr 16 02:37:46 PM PDT 24
Peak memory 941720 kb
Host smart-212d80a0-667f-4f13-979a-3403a00394ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354616781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.354616781
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1813412674
Short name T869
Test name
Test status
Simulation time 856921264 ps
CPU time 6.84 seconds
Started Apr 16 02:36:26 PM PDT 24
Finished Apr 16 02:36:34 PM PDT 24
Peak memory 203920 kb
Host smart-2a0bdffd-b7c9-41df-9fb1-a28a045f9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813412674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1813412674
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.1655509990
Short name T1291
Test name
Test status
Simulation time 3277416505 ps
CPU time 73.25 seconds
Started Apr 16 02:36:24 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 343456 kb
Host smart-7ae6a29c-0557-4da0-9afc-b3449cca97c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655509990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.1655509990
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.879356201
Short name T527
Test name
Test status
Simulation time 87165994 ps
CPU time 0.65 seconds
Started Apr 16 02:36:22 PM PDT 24
Finished Apr 16 02:36:23 PM PDT 24
Peak memory 203664 kb
Host smart-281490a8-dc37-4242-b792-5df3d0630a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879356201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.879356201
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.150335867
Short name T496
Test name
Test status
Simulation time 7134630195 ps
CPU time 24.49 seconds
Started Apr 16 02:36:26 PM PDT 24
Finished Apr 16 02:36:51 PM PDT 24
Peak memory 228464 kb
Host smart-b7dfc7ea-5244-4544-9a4a-ec6564ba1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150335867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.150335867
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2865152759
Short name T367
Test name
Test status
Simulation time 5489543515 ps
CPU time 23.97 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:48 PM PDT 24
Peak memory 378488 kb
Host smart-c251196d-a464-4cb2-ae24-61b0a28bc540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865152759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2865152759
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.368508860
Short name T275
Test name
Test status
Simulation time 965785345 ps
CPU time 33.86 seconds
Started Apr 16 02:36:26 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 212236 kb
Host smart-6a22d95b-de78-4cc5-9ae5-056b9f3c1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368508860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.368508860
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.508894263
Short name T1270
Test name
Test status
Simulation time 1390363788 ps
CPU time 3.67 seconds
Started Apr 16 02:36:25 PM PDT 24
Finished Apr 16 02:36:30 PM PDT 24
Peak memory 203984 kb
Host smart-66fb9379-f71e-4814-b236-9650eccf7ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508894263 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.508894263
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2200202123
Short name T1216
Test name
Test status
Simulation time 10085304151 ps
CPU time 53.18 seconds
Started Apr 16 02:36:24 PM PDT 24
Finished Apr 16 02:37:18 PM PDT 24
Peak memory 461128 kb
Host smart-12a0d126-f94d-4561-904f-7dbecb335894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200202123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2200202123
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.756353668
Short name T963
Test name
Test status
Simulation time 10230081726 ps
CPU time 14.68 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:39 PM PDT 24
Peak memory 300128 kb
Host smart-f431bba9-9fb4-445e-a8ab-5d7e56c957d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756353668 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_tx.756353668
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.3624702620
Short name T564
Test name
Test status
Simulation time 619553280 ps
CPU time 2.11 seconds
Started Apr 16 02:36:24 PM PDT 24
Finished Apr 16 02:36:27 PM PDT 24
Peak memory 203956 kb
Host smart-31cf9b4c-af3c-4e79-a29f-d1f3afef6d26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624702620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.3624702620
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2780475066
Short name T661
Test name
Test status
Simulation time 3006718612 ps
CPU time 7.33 seconds
Started Apr 16 02:36:24 PM PDT 24
Finished Apr 16 02:36:33 PM PDT 24
Peak memory 204080 kb
Host smart-3bb5aa6d-72e5-4158-aa5f-45ecddeee011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780475066 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2780475066
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3373757979
Short name T831
Test name
Test status
Simulation time 8642238594 ps
CPU time 27.75 seconds
Started Apr 16 02:36:26 PM PDT 24
Finished Apr 16 02:36:55 PM PDT 24
Peak memory 515456 kb
Host smart-f6879e6f-2886-4b1d-9a6f-4952c967f807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373757979 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3373757979
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2755555443
Short name T1136
Test name
Test status
Simulation time 1808303705 ps
CPU time 14.08 seconds
Started Apr 16 02:36:25 PM PDT 24
Finished Apr 16 02:36:40 PM PDT 24
Peak memory 204012 kb
Host smart-4b0f8f75-16ef-410d-a84a-e746a70f1895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755555443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2755555443
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.1622080116
Short name T1214
Test name
Test status
Simulation time 2509831852 ps
CPU time 12.07 seconds
Started Apr 16 02:36:27 PM PDT 24
Finished Apr 16 02:36:40 PM PDT 24
Peak memory 208180 kb
Host smart-3c1fdb2f-f2df-4a25-a3b3-78bc0eb34a96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622080116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.1622080116
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.711924450
Short name T875
Test name
Test status
Simulation time 47055486241 ps
CPU time 1060.71 seconds
Started Apr 16 02:36:27 PM PDT 24
Finished Apr 16 02:54:09 PM PDT 24
Peak memory 6866868 kb
Host smart-0de1c0d7-c111-4b74-982b-c8d8039409c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711924450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.711924450
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1771535667
Short name T777
Test name
Test status
Simulation time 19368437984 ps
CPU time 247.45 seconds
Started Apr 16 02:36:25 PM PDT 24
Finished Apr 16 02:40:34 PM PDT 24
Peak memory 1138708 kb
Host smart-1c22ca49-219f-4af7-8795-43108e0ec857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771535667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1771535667
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.366562534
Short name T1146
Test name
Test status
Simulation time 7354964868 ps
CPU time 5.44 seconds
Started Apr 16 02:36:23 PM PDT 24
Finished Apr 16 02:36:29 PM PDT 24
Peak memory 204032 kb
Host smart-d278a38a-7dc0-4cb3-b776-c3076e74b58e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366562534 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.366562534
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3061793929
Short name T779
Test name
Test status
Simulation time 27657610 ps
CPU time 0.63 seconds
Started Apr 16 02:36:34 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 203588 kb
Host smart-7325070e-9957-47d0-acb5-f8d16eac905c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061793929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3061793929
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3805574352
Short name T612
Test name
Test status
Simulation time 107146805 ps
CPU time 1.54 seconds
Started Apr 16 02:36:28 PM PDT 24
Finished Apr 16 02:36:31 PM PDT 24
Peak memory 212296 kb
Host smart-fc30a1ce-25b9-44a1-baf5-3bd2cc8d9b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805574352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3805574352
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.124249417
Short name T197
Test name
Test status
Simulation time 429461236 ps
CPU time 7.45 seconds
Started Apr 16 02:36:31 PM PDT 24
Finished Apr 16 02:36:39 PM PDT 24
Peak memory 287928 kb
Host smart-cbc77021-64c7-4e68-9fa4-742e7b65267f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124249417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.124249417
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1727877640
Short name T48
Test name
Test status
Simulation time 2363172278 ps
CPU time 178.25 seconds
Started Apr 16 02:36:29 PM PDT 24
Finished Apr 16 02:39:29 PM PDT 24
Peak memory 729768 kb
Host smart-9181d13a-8788-487e-ac6d-8b2bbcb2ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727877640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1727877640
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1045399236
Short name T726
Test name
Test status
Simulation time 3280270108 ps
CPU time 77.78 seconds
Started Apr 16 02:36:30 PM PDT 24
Finished Apr 16 02:37:49 PM PDT 24
Peak memory 728164 kb
Host smart-5edafeed-f7f4-457d-a5be-aa574a7ccc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045399236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1045399236
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2465041604
Short name T1046
Test name
Test status
Simulation time 108848862 ps
CPU time 1 seconds
Started Apr 16 02:36:30 PM PDT 24
Finished Apr 16 02:36:32 PM PDT 24
Peak memory 203940 kb
Host smart-1afc027c-a576-406b-81c6-e72d16955a62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465041604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2465041604
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.408575882
Short name T1019
Test name
Test status
Simulation time 575005428 ps
CPU time 3.84 seconds
Started Apr 16 02:36:29 PM PDT 24
Finished Apr 16 02:36:34 PM PDT 24
Peak memory 203920 kb
Host smart-00060904-faf1-400c-b554-d8475acba2a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408575882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
408575882
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.545336598
Short name T1191
Test name
Test status
Simulation time 16876660282 ps
CPU time 301.84 seconds
Started Apr 16 02:36:29 PM PDT 24
Finished Apr 16 02:41:31 PM PDT 24
Peak memory 1106100 kb
Host smart-0acf607a-adaf-4e94-a4e7-b5d847824bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545336598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.545336598
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1031227699
Short name T895
Test name
Test status
Simulation time 401329679 ps
CPU time 4.76 seconds
Started Apr 16 02:36:37 PM PDT 24
Finished Apr 16 02:36:42 PM PDT 24
Peak memory 204016 kb
Host smart-fe4f2a99-0cab-4a65-8b26-094d316ab057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031227699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1031227699
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.1374307605
Short name T791
Test name
Test status
Simulation time 7689190659 ps
CPU time 68.62 seconds
Started Apr 16 02:36:40 PM PDT 24
Finished Apr 16 02:37:50 PM PDT 24
Peak memory 301860 kb
Host smart-e4e729a0-39c0-48cb-9afc-4a677bd3acde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374307605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.1374307605
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3938396981
Short name T1157
Test name
Test status
Simulation time 22996155 ps
CPU time 0.62 seconds
Started Apr 16 02:36:30 PM PDT 24
Finished Apr 16 02:36:31 PM PDT 24
Peak memory 203680 kb
Host smart-ac17e2dc-126a-4211-a067-f6d4cf7ac22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938396981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3938396981
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.4151503577
Short name T957
Test name
Test status
Simulation time 5218526931 ps
CPU time 70.55 seconds
Started Apr 16 02:36:30 PM PDT 24
Finished Apr 16 02:37:41 PM PDT 24
Peak memory 805004 kb
Host smart-976ef23d-1db1-490c-9179-ebeb6551f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151503577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.4151503577
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.546129364
Short name T880
Test name
Test status
Simulation time 2216054813 ps
CPU time 50.06 seconds
Started Apr 16 02:36:31 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 291584 kb
Host smart-22ab6077-4017-4790-9223-014d327c04c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546129364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.546129364
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2682545074
Short name T252
Test name
Test status
Simulation time 7436687414 ps
CPU time 84.86 seconds
Started Apr 16 02:36:31 PM PDT 24
Finished Apr 16 02:37:57 PM PDT 24
Peak memory 281900 kb
Host smart-6d2ebc04-f661-42c6-a1b5-ad3b2b40fa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682545074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2682545074
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2059343639
Short name T86
Test name
Test status
Simulation time 1238651609 ps
CPU time 9.58 seconds
Started Apr 16 02:36:31 PM PDT 24
Finished Apr 16 02:36:42 PM PDT 24
Peak memory 220448 kb
Host smart-8cd5e304-2a27-46c0-8100-80e817500eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059343639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2059343639
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2761927048
Short name T913
Test name
Test status
Simulation time 6414890910 ps
CPU time 3.77 seconds
Started Apr 16 02:36:40 PM PDT 24
Finished Apr 16 02:36:45 PM PDT 24
Peak memory 203824 kb
Host smart-cb259dfe-6f99-4afa-abca-313343a31a11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761927048 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2761927048
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.209968324
Short name T874
Test name
Test status
Simulation time 10352495702 ps
CPU time 9.76 seconds
Started Apr 16 02:36:37 PM PDT 24
Finished Apr 16 02:36:47 PM PDT 24
Peak memory 251500 kb
Host smart-3f63c8b7-aea7-45b5-a691-f55e71c501e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209968324 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.209968324
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2315707882
Short name T59
Test name
Test status
Simulation time 10245166719 ps
CPU time 6 seconds
Started Apr 16 02:36:35 PM PDT 24
Finished Apr 16 02:36:41 PM PDT 24
Peak memory 243640 kb
Host smart-c33f1a12-5445-481a-a5e8-87842b062fbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315707882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2315707882
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.348783262
Short name T1242
Test name
Test status
Simulation time 478209550 ps
CPU time 2.49 seconds
Started Apr 16 02:36:35 PM PDT 24
Finished Apr 16 02:36:38 PM PDT 24
Peak memory 203980 kb
Host smart-5ddcd76d-f70b-408d-991e-81c52db44ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348783262 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.348783262
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.628194145
Short name T907
Test name
Test status
Simulation time 714473635 ps
CPU time 3.43 seconds
Started Apr 16 02:36:31 PM PDT 24
Finished Apr 16 02:36:35 PM PDT 24
Peak memory 203956 kb
Host smart-371a67cf-e789-4a28-a669-8dc7fa4043dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628194145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.628194145
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2639177052
Short name T1159
Test name
Test status
Simulation time 15594793212 ps
CPU time 28.4 seconds
Started Apr 16 02:36:28 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 585556 kb
Host smart-f70385f7-8635-4e18-b1c6-a3d8147046f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639177052 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2639177052
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2705180085
Short name T103
Test name
Test status
Simulation time 862187869 ps
CPU time 11.17 seconds
Started Apr 16 02:36:31 PM PDT 24
Finished Apr 16 02:36:42 PM PDT 24
Peak memory 203968 kb
Host smart-5cc0784e-74da-447e-b44b-8607bfe2f3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705180085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2705180085
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.226638381
Short name T1131
Test name
Test status
Simulation time 1866119656 ps
CPU time 20.6 seconds
Started Apr 16 02:36:30 PM PDT 24
Finished Apr 16 02:36:51 PM PDT 24
Peak memory 233364 kb
Host smart-ccb70f73-b257-40e5-a809-2ff8bc013108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226638381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.226638381
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3674235597
Short name T671
Test name
Test status
Simulation time 60592894139 ps
CPU time 634.7 seconds
Started Apr 16 02:36:29 PM PDT 24
Finished Apr 16 02:47:05 PM PDT 24
Peak memory 4845320 kb
Host smart-9b4517e8-1dcb-4634-bcec-a08217815b5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674235597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3674235597
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2865216358
Short name T1172
Test name
Test status
Simulation time 17025062288 ps
CPU time 759.01 seconds
Started Apr 16 02:36:32 PM PDT 24
Finished Apr 16 02:49:12 PM PDT 24
Peak memory 1916128 kb
Host smart-24a970cf-3421-4739-8ea1-4b6ec03d7d77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865216358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2865216358
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2111459708
Short name T1220
Test name
Test status
Simulation time 1515770288 ps
CPU time 6.92 seconds
Started Apr 16 02:36:38 PM PDT 24
Finished Apr 16 02:36:45 PM PDT 24
Peak memory 204040 kb
Host smart-d7faff3a-2d98-4368-b18b-797743f47f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111459708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2111459708
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2269911065
Short name T682
Test name
Test status
Simulation time 51027834 ps
CPU time 0.63 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 02:36:47 PM PDT 24
Peak memory 203556 kb
Host smart-b7331755-c1aa-4107-bae5-6aa1b9d039e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269911065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2269911065
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1767942558
Short name T937
Test name
Test status
Simulation time 600522195 ps
CPU time 1.6 seconds
Started Apr 16 02:36:42 PM PDT 24
Finished Apr 16 02:36:45 PM PDT 24
Peak memory 212172 kb
Host smart-4a2d1d7f-1347-4ce6-a49b-5ef6d4bab1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767942558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1767942558
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.304266097
Short name T1301
Test name
Test status
Simulation time 421402494 ps
CPU time 13.9 seconds
Started Apr 16 02:36:34 PM PDT 24
Finished Apr 16 02:36:49 PM PDT 24
Peak memory 258900 kb
Host smart-88dbf3cf-e580-4bb4-951e-2678a81d2c4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304266097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.304266097
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2923963065
Short name T921
Test name
Test status
Simulation time 1779175743 ps
CPU time 51.51 seconds
Started Apr 16 02:36:40 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 608864 kb
Host smart-44db4205-311a-45cd-a6f2-10f112a5bb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923963065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2923963065
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.812840800
Short name T1006
Test name
Test status
Simulation time 3668876468 ps
CPU time 62.25 seconds
Started Apr 16 02:36:36 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 641040 kb
Host smart-7aab28a3-45de-41d6-b355-ac67af25a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812840800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.812840800
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2622279136
Short name T1073
Test name
Test status
Simulation time 338232825 ps
CPU time 0.91 seconds
Started Apr 16 02:36:35 PM PDT 24
Finished Apr 16 02:36:37 PM PDT 24
Peak memory 203728 kb
Host smart-d76cdc65-e231-4f42-9792-6597e8c61250
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622279136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2622279136
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1187374933
Short name T209
Test name
Test status
Simulation time 482260882 ps
CPU time 6.59 seconds
Started Apr 16 02:36:38 PM PDT 24
Finished Apr 16 02:36:45 PM PDT 24
Peak memory 203952 kb
Host smart-deacf02a-048c-40ad-aeb2-e358d921a932
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187374933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1187374933
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2489590168
Short name T668
Test name
Test status
Simulation time 3181420145 ps
CPU time 211.27 seconds
Started Apr 16 02:36:34 PM PDT 24
Finished Apr 16 02:40:05 PM PDT 24
Peak memory 930724 kb
Host smart-92c4aeca-dd29-47f5-94a7-b4fc4ee1a748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489590168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2489590168
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1527722224
Short name T325
Test name
Test status
Simulation time 638703087 ps
CPU time 26.75 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 02:37:14 PM PDT 24
Peak memory 203836 kb
Host smart-c85d7d99-9ec1-407e-877c-58e22878b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527722224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1527722224
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.151550475
Short name T1265
Test name
Test status
Simulation time 8901021327 ps
CPU time 32.22 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 02:37:19 PM PDT 24
Peak memory 348220 kb
Host smart-2d6bd833-2a78-46e0-8b74-a9caae15e312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151550475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.151550475
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.662547136
Short name T190
Test name
Test status
Simulation time 101366301 ps
CPU time 0.72 seconds
Started Apr 16 02:36:34 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 203684 kb
Host smart-416beba9-d70f-4a9b-93db-de0bde337245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662547136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.662547136
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3073911724
Short name T68
Test name
Test status
Simulation time 24980192939 ps
CPU time 45.48 seconds
Started Apr 16 02:36:39 PM PDT 24
Finished Apr 16 02:37:26 PM PDT 24
Peak memory 231844 kb
Host smart-80530d47-3e20-4198-864e-6d7b70236eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073911724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3073911724
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3783083861
Short name T834
Test name
Test status
Simulation time 1076903694 ps
CPU time 21.52 seconds
Started Apr 16 02:36:40 PM PDT 24
Finished Apr 16 02:37:03 PM PDT 24
Peak memory 301172 kb
Host smart-5286625d-1535-43ab-9893-fee0a50456d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783083861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3783083861
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.311972509
Short name T1354
Test name
Test status
Simulation time 723660457 ps
CPU time 15.84 seconds
Started Apr 16 02:36:41 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 212280 kb
Host smart-29073387-1fb9-4790-8679-155835df2acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311972509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.311972509
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3649392421
Short name T344
Test name
Test status
Simulation time 1013748058 ps
CPU time 4.48 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:36:52 PM PDT 24
Peak memory 204864 kb
Host smart-e8a82a7a-6aa8-4af6-9a77-e3cef3f98dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649392421 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3649392421
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3694070435
Short name T872
Test name
Test status
Simulation time 10675882007 ps
CPU time 4.36 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:36:49 PM PDT 24
Peak memory 229900 kb
Host smart-61e1c871-daa8-4a5e-98a4-a9bb512ec5ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694070435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3694070435
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2951734487
Short name T1067
Test name
Test status
Simulation time 10101316495 ps
CPU time 32.46 seconds
Started Apr 16 02:36:39 PM PDT 24
Finished Apr 16 02:37:12 PM PDT 24
Peak memory 381004 kb
Host smart-fc246209-34ee-43e1-abf3-f30dd0ffb321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951734487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2951734487
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1032314823
Short name T1296
Test name
Test status
Simulation time 2126220885 ps
CPU time 2.19 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:36:48 PM PDT 24
Peak memory 203992 kb
Host smart-92b1b7a0-7f0b-4e9b-ba33-7934c1b87ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032314823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1032314823
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2438414612
Short name T1142
Test name
Test status
Simulation time 884152878 ps
CPU time 4.49 seconds
Started Apr 16 02:36:39 PM PDT 24
Finished Apr 16 02:36:44 PM PDT 24
Peak memory 204020 kb
Host smart-b63d2d84-f584-46c1-9351-35018c1c88fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438414612 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2438414612
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.4116562880
Short name T31
Test name
Test status
Simulation time 19149607493 ps
CPU time 262.9 seconds
Started Apr 16 02:36:40 PM PDT 24
Finished Apr 16 02:41:04 PM PDT 24
Peak memory 2703584 kb
Host smart-58fd79fd-5097-47d7-b3e2-7ebd4d9f9084
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116562880 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.4116562880
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.670368984
Short name T744
Test name
Test status
Simulation time 4423866941 ps
CPU time 21.76 seconds
Started Apr 16 02:36:41 PM PDT 24
Finished Apr 16 02:37:04 PM PDT 24
Peak memory 204016 kb
Host smart-fd689d66-1449-4430-ad70-3e0ece2261c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670368984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.670368984
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.153399688
Short name T1198
Test name
Test status
Simulation time 2102899596 ps
CPU time 30.94 seconds
Started Apr 16 02:36:41 PM PDT 24
Finished Apr 16 02:37:14 PM PDT 24
Peak memory 236928 kb
Host smart-c1980a55-f088-425d-b0af-717718c67fed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153399688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.153399688
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.846476146
Short name T550
Test name
Test status
Simulation time 23336676952 ps
CPU time 67.5 seconds
Started Apr 16 02:36:40 PM PDT 24
Finished Apr 16 02:37:49 PM PDT 24
Peak memory 954496 kb
Host smart-05b05569-0816-4327-8ab1-8b95a4259d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846476146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.846476146
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3122897436
Short name T1016
Test name
Test status
Simulation time 20881778087 ps
CPU time 83.47 seconds
Started Apr 16 02:36:40 PM PDT 24
Finished Apr 16 02:38:05 PM PDT 24
Peak memory 890464 kb
Host smart-168d500a-7af2-4b34-941c-c2ab59116b0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122897436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3122897436
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1617224887
Short name T806
Test name
Test status
Simulation time 4965094033 ps
CPU time 6.59 seconds
Started Apr 16 02:36:42 PM PDT 24
Finished Apr 16 02:36:50 PM PDT 24
Peak memory 219356 kb
Host smart-3454064d-1842-4890-93e8-ac00e595e0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617224887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1617224887
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.830889925
Short name T736
Test name
Test status
Simulation time 28260694 ps
CPU time 0.63 seconds
Started Apr 16 02:36:50 PM PDT 24
Finished Apr 16 02:36:51 PM PDT 24
Peak memory 203604 kb
Host smart-fba205ed-d6c4-42f5-b6a0-690e7f0f6c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830889925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.830889925
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.4211388727
Short name T567
Test name
Test status
Simulation time 93878033 ps
CPU time 1.47 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:36:49 PM PDT 24
Peak memory 212324 kb
Host smart-ddf0d53b-f18d-490c-996c-fd1b1129b1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211388727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.4211388727
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1798361251
Short name T986
Test name
Test status
Simulation time 238576414 ps
CPU time 5.05 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:36:52 PM PDT 24
Peak memory 249652 kb
Host smart-fc873f02-4070-4327-bd40-23a3cead995a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798361251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1798361251
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3206375981
Short name T824
Test name
Test status
Simulation time 6912182468 ps
CPU time 67.74 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:37:53 PM PDT 24
Peak memory 597536 kb
Host smart-392c798e-6d96-42e9-b828-1319fb6ac070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206375981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3206375981
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2118288199
Short name T1192
Test name
Test status
Simulation time 2200588178 ps
CPU time 163.31 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:39:30 PM PDT 24
Peak memory 710904 kb
Host smart-78d20edb-1c4b-4d18-ac4d-b4b19e5406d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118288199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2118288199
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3071749454
Short name T648
Test name
Test status
Simulation time 488910942 ps
CPU time 0.92 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:36:46 PM PDT 24
Peak memory 203744 kb
Host smart-e99aa72d-82b8-4239-beb9-8f65499c5cf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071749454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3071749454
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.16598212
Short name T63
Test name
Test status
Simulation time 301386592 ps
CPU time 7.11 seconds
Started Apr 16 02:36:47 PM PDT 24
Finished Apr 16 02:36:55 PM PDT 24
Peak memory 203948 kb
Host smart-db336bb5-dad3-4262-8d09-fba89e8c915f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16598212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.16598212
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1335185730
Short name T1206
Test name
Test status
Simulation time 19119767048 ps
CPU time 142.1 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:39:08 PM PDT 24
Peak memory 1320872 kb
Host smart-5dc82617-e14d-4fa0-bfcf-acf1f5c0ea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335185730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1335185730
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2147035273
Short name T616
Test name
Test status
Simulation time 690492556 ps
CPU time 5.26 seconds
Started Apr 16 02:36:49 PM PDT 24
Finished Apr 16 02:36:55 PM PDT 24
Peak memory 203936 kb
Host smart-c017e2e5-cef3-4f69-9d89-0c42d9a6da80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147035273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2147035273
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2208591632
Short name T825
Test name
Test status
Simulation time 1309374835 ps
CPU time 19.61 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 278096 kb
Host smart-4d8d6ca3-22d0-4a6a-8ed1-4d0afa6d2335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208591632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2208591632
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_perf.648393471
Short name T629
Test name
Test status
Simulation time 350700873 ps
CPU time 5.01 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:36:52 PM PDT 24
Peak memory 236688 kb
Host smart-10df356e-d47b-498f-ba6e-840edb8f1dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648393471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.648393471
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2485965655
Short name T1189
Test name
Test status
Simulation time 12886465389 ps
CPU time 17 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 02:37:03 PM PDT 24
Peak memory 260712 kb
Host smart-1a0e6de5-cec3-4cd4-9c91-57f24b4a284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485965655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2485965655
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1848081935
Short name T475
Test name
Test status
Simulation time 15001612903 ps
CPU time 372.73 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 02:42:59 PM PDT 24
Peak memory 1758520 kb
Host smart-9f6ac8ad-bdcd-41ce-8940-8f1f0f9503e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848081935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1848081935
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.896581012
Short name T487
Test name
Test status
Simulation time 3343948675 ps
CPU time 8.21 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:36:56 PM PDT 24
Peak memory 220476 kb
Host smart-6adb8db0-dc0a-4224-ab51-33cb42917475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896581012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.896581012
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1679217924
Short name T324
Test name
Test status
Simulation time 4520231910 ps
CPU time 3.8 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:36:49 PM PDT 24
Peak memory 204092 kb
Host smart-6787131a-c4ef-4fe1-a05b-23c09915887f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679217924 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1679217924
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3495860814
Short name T85
Test name
Test status
Simulation time 10126671493 ps
CPU time 8.78 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:36:53 PM PDT 24
Peak memory 277708 kb
Host smart-da5c8b77-411f-4070-81ad-380b777974f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495860814 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3495860814
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1954483887
Short name T57
Test name
Test status
Simulation time 10197906837 ps
CPU time 16.02 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:37:04 PM PDT 24
Peak memory 300044 kb
Host smart-0f7ca23b-e101-45d1-8211-4485217fc4f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954483887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1954483887
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3854237076
Short name T1309
Test name
Test status
Simulation time 502063589 ps
CPU time 2.65 seconds
Started Apr 16 02:36:50 PM PDT 24
Finished Apr 16 02:36:53 PM PDT 24
Peak memory 203988 kb
Host smart-8b44befe-a3c0-452f-b0ae-b3ba28ab5586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854237076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3854237076
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.286448737
Short name T1231
Test name
Test status
Simulation time 1646343196 ps
CPU time 7.14 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:36:55 PM PDT 24
Peak memory 220192 kb
Host smart-15bbaecd-8d3a-40ea-96e5-2534a2a823c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286448737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.286448737
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.3164929462
Short name T90
Test name
Test status
Simulation time 13374377811 ps
CPU time 12.97 seconds
Started Apr 16 02:36:48 PM PDT 24
Finished Apr 16 02:37:02 PM PDT 24
Peak memory 357660 kb
Host smart-404e60e4-b4ca-4de5-873c-5162737c35d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164929462 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.3164929462
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.905205700
Short name T877
Test name
Test status
Simulation time 1204865172 ps
CPU time 22.98 seconds
Started Apr 16 02:36:44 PM PDT 24
Finished Apr 16 02:37:09 PM PDT 24
Peak memory 203960 kb
Host smart-f674dcda-9ecd-4fc1-a374-8668bfc376b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905205700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.905205700
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2877432411
Short name T16
Test name
Test status
Simulation time 3233711346 ps
CPU time 30.35 seconds
Started Apr 16 02:36:46 PM PDT 24
Finished Apr 16 02:37:17 PM PDT 24
Peak memory 222888 kb
Host smart-6bced91e-edaf-48d4-a92e-dd7352e5e58a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877432411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2877432411
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.352599944
Short name T512
Test name
Test status
Simulation time 47902417149 ps
CPU time 124.89 seconds
Started Apr 16 02:36:48 PM PDT 24
Finished Apr 16 02:38:53 PM PDT 24
Peak memory 1834572 kb
Host smart-bd970e7b-3a60-4b23-83ee-8eeaf95a13a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352599944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.352599944
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.221114198
Short name T360
Test name
Test status
Simulation time 27977740158 ps
CPU time 2142.01 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 03:12:28 PM PDT 24
Peak memory 3497116 kb
Host smart-670580ff-baac-4bab-9ee5-90d6bdde3eee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221114198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.221114198
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.877244288
Short name T1127
Test name
Test status
Simulation time 1249283995 ps
CPU time 6.46 seconds
Started Apr 16 02:36:45 PM PDT 24
Finished Apr 16 02:36:53 PM PDT 24
Peak memory 217480 kb
Host smart-9c55cb76-de22-4228-bbb5-b1cbe36132e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877244288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.877244288
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.986688793
Short name T689
Test name
Test status
Simulation time 16428873 ps
CPU time 0.65 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:36:57 PM PDT 24
Peak memory 203388 kb
Host smart-272450dd-8820-479b-85fe-19d1111574be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986688793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.986688793
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.152670842
Short name T1122
Test name
Test status
Simulation time 71624112 ps
CPU time 1.31 seconds
Started Apr 16 02:36:56 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 212284 kb
Host smart-2e1fd28d-0ac3-4ef0-b731-20e14d4a7232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152670842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.152670842
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1013722998
Short name T1226
Test name
Test status
Simulation time 902036624 ps
CPU time 11.52 seconds
Started Apr 16 02:36:53 PM PDT 24
Finished Apr 16 02:37:05 PM PDT 24
Peak memory 246112 kb
Host smart-f710cfc7-0633-4eaa-ac9f-d41e414ab8c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013722998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1013722998
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2012396585
Short name T932
Test name
Test status
Simulation time 1552428653 ps
CPU time 43.94 seconds
Started Apr 16 02:36:48 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 577780 kb
Host smart-cbc5c4dc-374e-4054-a693-7bf763ee9073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012396585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2012396585
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.414857952
Short name T448
Test name
Test status
Simulation time 2301982763 ps
CPU time 66.85 seconds
Started Apr 16 02:36:49 PM PDT 24
Finished Apr 16 02:37:57 PM PDT 24
Peak memory 589624 kb
Host smart-3a7bf2a4-c747-4968-96b4-b9a367bd70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414857952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.414857952
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.173090422
Short name T212
Test name
Test status
Simulation time 272678651 ps
CPU time 1.05 seconds
Started Apr 16 02:36:51 PM PDT 24
Finished Apr 16 02:36:53 PM PDT 24
Peak memory 203540 kb
Host smart-a23df04c-8af7-416b-a2b5-e41bd472679c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173090422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm
t.173090422
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3430529902
Short name T1276
Test name
Test status
Simulation time 164910530 ps
CPU time 3.93 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 203932 kb
Host smart-3b5b7cc0-d83b-497e-a087-c04389877f9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430529902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3430529902
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3772899294
Short name T586
Test name
Test status
Simulation time 23566056674 ps
CPU time 131.54 seconds
Started Apr 16 02:36:50 PM PDT 24
Finished Apr 16 02:39:03 PM PDT 24
Peak memory 1211680 kb
Host smart-ede21786-782f-4eea-a34d-fe57a4d59fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772899294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3772899294
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3380936405
Short name T1150
Test name
Test status
Simulation time 228174721 ps
CPU time 2.83 seconds
Started Apr 16 02:36:56 PM PDT 24
Finished Apr 16 02:37:00 PM PDT 24
Peak memory 203976 kb
Host smart-8a7b61be-1c84-4b8e-b537-fdc9d9400ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380936405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3380936405
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3864899548
Short name T983
Test name
Test status
Simulation time 5238408492 ps
CPU time 31.36 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:37:26 PM PDT 24
Peak memory 405864 kb
Host smart-2df3d3f3-b8d6-490b-bcec-eb8213a21e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864899548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3864899548
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3964010595
Short name T1344
Test name
Test status
Simulation time 64217804 ps
CPU time 0.67 seconds
Started Apr 16 02:36:53 PM PDT 24
Finished Apr 16 02:36:55 PM PDT 24
Peak memory 203620 kb
Host smart-052873f8-99ae-4714-a8db-96baf75c51e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964010595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3964010595
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.544418040
Short name T580
Test name
Test status
Simulation time 1810304976 ps
CPU time 38.26 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:37:34 PM PDT 24
Peak memory 265380 kb
Host smart-7c64c314-2a0a-4ad9-ad2e-be01c7edf65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544418040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.544418040
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.197599079
Short name T803
Test name
Test status
Simulation time 5852990803 ps
CPU time 23.56 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:37:19 PM PDT 24
Peak memory 297304 kb
Host smart-5a68bd57-a948-4f97-ad1a-b3cf4f80aa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197599079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.197599079
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2520122390
Short name T236
Test name
Test status
Simulation time 11400267182 ps
CPU time 462.64 seconds
Started Apr 16 02:36:51 PM PDT 24
Finished Apr 16 02:44:35 PM PDT 24
Peak memory 2113664 kb
Host smart-e1b5083a-10b5-4dbe-84e8-3c7862e564a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520122390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2520122390
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.4010942278
Short name T574
Test name
Test status
Simulation time 2179441428 ps
CPU time 25.65 seconds
Started Apr 16 02:36:53 PM PDT 24
Finished Apr 16 02:37:19 PM PDT 24
Peak memory 212308 kb
Host smart-678e461d-6e5d-44da-9f29-307728b82b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010942278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.4010942278
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3785178739
Short name T1120
Test name
Test status
Simulation time 624077211 ps
CPU time 3.09 seconds
Started Apr 16 02:36:49 PM PDT 24
Finished Apr 16 02:36:53 PM PDT 24
Peak memory 204040 kb
Host smart-ed74f360-a356-4338-9685-ab8214a4449f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785178739 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3785178739
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3355632595
Short name T822
Test name
Test status
Simulation time 10070767951 ps
CPU time 63.93 seconds
Started Apr 16 02:36:51 PM PDT 24
Finished Apr 16 02:37:56 PM PDT 24
Peak memory 499532 kb
Host smart-965b2bed-7f1e-4d23-93f0-8aedb07eccfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355632595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3355632595
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1983268978
Short name T37
Test name
Test status
Simulation time 10117062917 ps
CPU time 33.25 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 383544 kb
Host smart-29c0ef69-7df8-47b3-9d99-e5f4e9bf5434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983268978 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1983268978
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1015969943
Short name T849
Test name
Test status
Simulation time 1527210780 ps
CPU time 2.35 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 203996 kb
Host smart-62b5e2ab-56fc-4226-a760-abc6fbfca3d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015969943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1015969943
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2407878482
Short name T638
Test name
Test status
Simulation time 4287201825 ps
CPU time 5.27 seconds
Started Apr 16 02:36:56 PM PDT 24
Finished Apr 16 02:37:02 PM PDT 24
Peak memory 206500 kb
Host smart-af3fa61f-a83e-4aa6-bd4c-afe1096b5515
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407878482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2407878482
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1488021436
Short name T335
Test name
Test status
Simulation time 8931590960 ps
CPU time 30.44 seconds
Started Apr 16 02:36:51 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 603788 kb
Host smart-c74f1517-9b98-41f2-bf14-46dc1c0ef6f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488021436 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1488021436
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2254809944
Short name T917
Test name
Test status
Simulation time 641059081 ps
CPU time 8.28 seconds
Started Apr 16 02:36:48 PM PDT 24
Finished Apr 16 02:36:57 PM PDT 24
Peak memory 203988 kb
Host smart-911c8f3e-b308-46b6-86d7-3743a6bbefa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254809944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2254809944
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1606893534
Short name T1004
Test name
Test status
Simulation time 1029820829 ps
CPU time 18.56 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 214252 kb
Host smart-233a78bc-911a-45fb-91d2-ecd750235cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606893534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1606893534
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2734284820
Short name T199
Test name
Test status
Simulation time 16193836832 ps
CPU time 8.64 seconds
Started Apr 16 02:36:50 PM PDT 24
Finished Apr 16 02:36:59 PM PDT 24
Peak memory 204060 kb
Host smart-0c598c0f-99c6-4881-ae94-968e4daf9f71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734284820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2734284820
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1358383856
Short name T1203
Test name
Test status
Simulation time 14869796486 ps
CPU time 218.49 seconds
Started Apr 16 02:36:52 PM PDT 24
Finished Apr 16 02:40:31 PM PDT 24
Peak memory 895968 kb
Host smart-75e43266-5795-4402-8092-259d4aed9e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358383856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1358383856
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.4091828240
Short name T373
Test name
Test status
Simulation time 6680804434 ps
CPU time 7.11 seconds
Started Apr 16 02:36:49 PM PDT 24
Finished Apr 16 02:36:57 PM PDT 24
Peak memory 216568 kb
Host smart-3ce86c9e-59b1-437b-a0d6-fcfb5df08f46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091828240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.4091828240
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3258847899
Short name T1085
Test name
Test status
Simulation time 15330770 ps
CPU time 0.66 seconds
Started Apr 16 02:32:13 PM PDT 24
Finished Apr 16 02:32:14 PM PDT 24
Peak memory 203788 kb
Host smart-1cf2961f-b673-4b1d-8205-4e58e018af1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258847899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3258847899
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2746681424
Short name T280
Test name
Test status
Simulation time 173346900 ps
CPU time 1.32 seconds
Started Apr 16 02:32:09 PM PDT 24
Finished Apr 16 02:32:11 PM PDT 24
Peak memory 212328 kb
Host smart-f3a1dcaa-4f65-40a5-b60f-e38304311d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746681424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2746681424
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2545511328
Short name T655
Test name
Test status
Simulation time 1329236455 ps
CPU time 9.66 seconds
Started Apr 16 02:32:09 PM PDT 24
Finished Apr 16 02:32:20 PM PDT 24
Peak memory 297332 kb
Host smart-d1756c48-8beb-4378-a3b5-724ca69b1ef8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545511328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2545511328
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.637178145
Short name T436
Test name
Test status
Simulation time 5737457522 ps
CPU time 100.3 seconds
Started Apr 16 02:32:09 PM PDT 24
Finished Apr 16 02:33:50 PM PDT 24
Peak memory 548316 kb
Host smart-9ee2453d-f9c8-4b64-8a70-52896eff6ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637178145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.637178145
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1899978534
Short name T1322
Test name
Test status
Simulation time 2503689627 ps
CPU time 35.84 seconds
Started Apr 16 02:32:11 PM PDT 24
Finished Apr 16 02:32:47 PM PDT 24
Peak memory 436912 kb
Host smart-4dd3cc18-0a57-4ea3-9b78-4f0891fd1900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899978534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1899978534
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3138906212
Short name T345
Test name
Test status
Simulation time 461896691 ps
CPU time 0.87 seconds
Started Apr 16 02:32:09 PM PDT 24
Finished Apr 16 02:32:11 PM PDT 24
Peak memory 203724 kb
Host smart-12997209-fc97-493a-918a-035cecacfbaa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138906212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3138906212
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3319562739
Short name T365
Test name
Test status
Simulation time 225824867 ps
CPU time 5.36 seconds
Started Apr 16 02:32:11 PM PDT 24
Finished Apr 16 02:32:17 PM PDT 24
Peak memory 240012 kb
Host smart-c06e10a5-00ac-43f7-823e-8bfdf6750bc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319562739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3319562739
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.4176805627
Short name T172
Test name
Test status
Simulation time 54039897215 ps
CPU time 84.08 seconds
Started Apr 16 02:32:11 PM PDT 24
Finished Apr 16 02:33:36 PM PDT 24
Peak memory 1079864 kb
Host smart-0109fa16-9c24-44fa-ab1c-a0f3771e6c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176805627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.4176805627
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2637398828
Short name T1145
Test name
Test status
Simulation time 2350423127 ps
CPU time 5.24 seconds
Started Apr 16 02:32:13 PM PDT 24
Finished Apr 16 02:32:19 PM PDT 24
Peak memory 204000 kb
Host smart-bb7adf86-bf32-415e-8c4d-2fe168cd64e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637398828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2637398828
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1601509350
Short name T477
Test name
Test status
Simulation time 6688263212 ps
CPU time 73.47 seconds
Started Apr 16 02:32:14 PM PDT 24
Finished Apr 16 02:33:28 PM PDT 24
Peak memory 317652 kb
Host smart-95967b21-0b72-4987-a43e-9c06086b9eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601509350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1601509350
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.67998625
Short name T320
Test name
Test status
Simulation time 52736815 ps
CPU time 0.63 seconds
Started Apr 16 02:32:10 PM PDT 24
Finished Apr 16 02:32:11 PM PDT 24
Peak memory 203652 kb
Host smart-5b8cf6e6-2dd0-45b7-81c1-3ea9055ed73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67998625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.67998625
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.2855650112
Short name T716
Test name
Test status
Simulation time 902026502 ps
CPU time 11.07 seconds
Started Apr 16 02:32:08 PM PDT 24
Finished Apr 16 02:32:20 PM PDT 24
Peak memory 244632 kb
Host smart-27ae6528-9a1a-43c1-96cf-e3e74ba1d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855650112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2855650112
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2146262956
Short name T757
Test name
Test status
Simulation time 2039467002 ps
CPU time 33.19 seconds
Started Apr 16 02:32:09 PM PDT 24
Finished Apr 16 02:32:42 PM PDT 24
Peak memory 297736 kb
Host smart-2f34fd19-d4bd-4f9f-88d6-2069b5f75715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146262956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2146262956
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.3783526562
Short name T600
Test name
Test status
Simulation time 71017801755 ps
CPU time 2249 seconds
Started Apr 16 02:32:15 PM PDT 24
Finished Apr 16 03:09:45 PM PDT 24
Peak memory 2165820 kb
Host smart-72dce5e2-7c31-4689-bfd3-4f12f3919ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783526562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.3783526562
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1359272425
Short name T240
Test name
Test status
Simulation time 750408847 ps
CPU time 17.51 seconds
Started Apr 16 02:32:08 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 212176 kb
Host smart-7852e256-d9f3-4efd-a836-ef503f96cca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359272425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1359272425
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3733025349
Short name T702
Test name
Test status
Simulation time 1924397677 ps
CPU time 4.14 seconds
Started Apr 16 02:32:15 PM PDT 24
Finished Apr 16 02:32:21 PM PDT 24
Peak memory 212156 kb
Host smart-735a31e6-9d4f-4fab-a436-288ebbdfe152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733025349 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3733025349
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.308065139
Short name T248
Test name
Test status
Simulation time 10129008681 ps
CPU time 33.39 seconds
Started Apr 16 02:32:15 PM PDT 24
Finished Apr 16 02:32:49 PM PDT 24
Peak memory 340484 kb
Host smart-98fa1531-c6fe-4d4b-a159-0c4cbd071368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308065139 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.308065139
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3521724344
Short name T939
Test name
Test status
Simulation time 10066014371 ps
CPU time 65.74 seconds
Started Apr 16 02:32:14 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 527680 kb
Host smart-5eff5824-8b55-4567-9cc8-a4a9768dc595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521724344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3521724344
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.795339718
Short name T245
Test name
Test status
Simulation time 281038118 ps
CPU time 2.08 seconds
Started Apr 16 02:32:15 PM PDT 24
Finished Apr 16 02:32:18 PM PDT 24
Peak memory 204008 kb
Host smart-954b8584-2c71-41d4-9452-078e529e5e6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795339718 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.795339718
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2192823321
Short name T540
Test name
Test status
Simulation time 781781264 ps
CPU time 4.49 seconds
Started Apr 16 02:32:15 PM PDT 24
Finished Apr 16 02:32:21 PM PDT 24
Peak memory 204024 kb
Host smart-eb2d524a-b9c9-418c-9030-91f9225d7d1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192823321 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2192823321
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1934111333
Short name T352
Test name
Test status
Simulation time 11776140183 ps
CPU time 17.64 seconds
Started Apr 16 02:32:13 PM PDT 24
Finished Apr 16 02:32:31 PM PDT 24
Peak memory 466560 kb
Host smart-a9d3bec6-2203-4faf-a2c1-8f50a20bc02e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934111333 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1934111333
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.4285226731
Short name T896
Test name
Test status
Simulation time 2211631305 ps
CPU time 12.52 seconds
Started Apr 16 02:32:13 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 204008 kb
Host smart-5c73a3eb-ab9b-4325-b3c3-28bf684dc676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285226731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.4285226731
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.4138828742
Short name T1272
Test name
Test status
Simulation time 793038800 ps
CPU time 10.32 seconds
Started Apr 16 02:32:12 PM PDT 24
Finished Apr 16 02:32:23 PM PDT 24
Peak memory 209828 kb
Host smart-4a66237d-0347-4a98-a9cb-45d39cc581c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138828742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.4138828742
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.736238379
Short name T1343
Test name
Test status
Simulation time 71976053196 ps
CPU time 2730.29 seconds
Started Apr 16 02:32:12 PM PDT 24
Finished Apr 16 03:17:44 PM PDT 24
Peak memory 12821200 kb
Host smart-13726bba-7aeb-4921-bac5-df614bb4ff2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736238379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.736238379
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1377578018
Short name T878
Test name
Test status
Simulation time 23309329611 ps
CPU time 1249.55 seconds
Started Apr 16 02:32:14 PM PDT 24
Finished Apr 16 02:53:05 PM PDT 24
Peak memory 5001220 kb
Host smart-617366b3-0912-4206-90b5-178a674d3728
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377578018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1377578018
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1098283136
Short name T685
Test name
Test status
Simulation time 3169238983 ps
CPU time 7.41 seconds
Started Apr 16 02:32:15 PM PDT 24
Finished Apr 16 02:32:23 PM PDT 24
Peak memory 212288 kb
Host smart-91af5fb3-17e0-4d13-8c79-31e1f806c0db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098283136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1098283136
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.739478906
Short name T357
Test name
Test status
Simulation time 86733572 ps
CPU time 0.62 seconds
Started Apr 16 02:32:20 PM PDT 24
Finished Apr 16 02:32:22 PM PDT 24
Peak memory 203552 kb
Host smart-3f41c2ed-3a61-427a-b8f6-06082bbafa96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739478906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.739478906
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2874979895
Short name T927
Test name
Test status
Simulation time 684567043 ps
CPU time 1.53 seconds
Started Apr 16 02:32:20 PM PDT 24
Finished Apr 16 02:32:22 PM PDT 24
Peak memory 212260 kb
Host smart-f6336de0-3f7b-4164-a00e-cde70c986a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874979895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2874979895
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2903282305
Short name T1099
Test name
Test status
Simulation time 663586231 ps
CPU time 7.6 seconds
Started Apr 16 02:32:17 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 229336 kb
Host smart-c1c182ad-5922-4b58-b611-9cd9aa806963
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903282305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2903282305
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3081749107
Short name T538
Test name
Test status
Simulation time 15047735028 ps
CPU time 100.18 seconds
Started Apr 16 02:32:21 PM PDT 24
Finished Apr 16 02:34:02 PM PDT 24
Peak memory 578252 kb
Host smart-05f540a0-3664-4d68-a8f3-b9dc605d4860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081749107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3081749107
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3793512008
Short name T1076
Test name
Test status
Simulation time 4237211545 ps
CPU time 71.12 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:33:30 PM PDT 24
Peak memory 468208 kb
Host smart-b42bc658-c267-4ea5-8564-656265531743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793512008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3793512008
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3372253126
Short name T75
Test name
Test status
Simulation time 637254379 ps
CPU time 1.15 seconds
Started Apr 16 02:32:19 PM PDT 24
Finished Apr 16 02:32:21 PM PDT 24
Peak memory 203916 kb
Host smart-9d57ff91-4ed8-4a43-9c8e-510cfdaa549a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372253126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3372253126
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2064039259
Short name T844
Test name
Test status
Simulation time 1104396449 ps
CPU time 3.93 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:32:23 PM PDT 24
Peak memory 230816 kb
Host smart-8085f013-5141-464b-839b-8f3681709e72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064039259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2064039259
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.395142126
Short name T170
Test name
Test status
Simulation time 19569260274 ps
CPU time 108.23 seconds
Started Apr 16 02:32:15 PM PDT 24
Finished Apr 16 02:34:04 PM PDT 24
Peak memory 1201336 kb
Host smart-542ed978-99ac-4393-921f-6e2a6f610a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395142126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.395142126
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1238665826
Short name T1261
Test name
Test status
Simulation time 571766442 ps
CPU time 4.65 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:32:23 PM PDT 24
Peak memory 203968 kb
Host smart-cfb465e2-7a2c-4386-9e66-7251bb9464b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238665826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1238665826
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2503933167
Short name T1060
Test name
Test status
Simulation time 922039214 ps
CPU time 47.5 seconds
Started Apr 16 02:32:17 PM PDT 24
Finished Apr 16 02:33:06 PM PDT 24
Peak memory 359124 kb
Host smart-380f9f7b-e7be-4085-a66e-71abbdbc45e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503933167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2503933167
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3733901025
Short name T1161
Test name
Test status
Simulation time 20796162 ps
CPU time 0.74 seconds
Started Apr 16 02:32:14 PM PDT 24
Finished Apr 16 02:32:16 PM PDT 24
Peak memory 203668 kb
Host smart-e2f79da4-9602-4804-b953-403c8ea117c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733901025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3733901025
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3447050284
Short name T1070
Test name
Test status
Simulation time 19521127490 ps
CPU time 95.83 seconds
Started Apr 16 02:32:17 PM PDT 24
Finished Apr 16 02:33:54 PM PDT 24
Peak memory 771568 kb
Host smart-687c97c3-c466-4e83-9af2-64c7db945840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447050284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3447050284
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.127790035
Short name T610
Test name
Test status
Simulation time 911690784 ps
CPU time 15.44 seconds
Started Apr 16 02:32:14 PM PDT 24
Finished Apr 16 02:32:30 PM PDT 24
Peak memory 330400 kb
Host smart-69beacba-b1f1-4d5a-96c0-461d9c159a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127790035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.127790035
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2221522590
Short name T81
Test name
Test status
Simulation time 7943284806 ps
CPU time 101.98 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:34:01 PM PDT 24
Peak memory 464244 kb
Host smart-0d4ebec8-cd11-4d26-91bd-d7a3533bdc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221522590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2221522590
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.727428938
Short name T794
Test name
Test status
Simulation time 766552207 ps
CPU time 35.64 seconds
Started Apr 16 02:32:19 PM PDT 24
Finished Apr 16 02:32:55 PM PDT 24
Peak memory 212240 kb
Host smart-9b41acb6-2e75-4037-a281-3306157eb6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727428938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.727428938
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3185863254
Short name T941
Test name
Test status
Simulation time 602214930 ps
CPU time 3.01 seconds
Started Apr 16 02:32:17 PM PDT 24
Finished Apr 16 02:32:20 PM PDT 24
Peak memory 203976 kb
Host smart-f76eacc2-7a70-4496-8e08-49b38fc3e263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185863254 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3185863254
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2979436378
Short name T1275
Test name
Test status
Simulation time 10039394690 ps
CPU time 80.71 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:33:39 PM PDT 24
Peak memory 523816 kb
Host smart-1b60a4ca-8f24-41f5-a6e7-68798d5404fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979436378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2979436378
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3813150866
Short name T715
Test name
Test status
Simulation time 10404076057 ps
CPU time 10.42 seconds
Started Apr 16 02:32:19 PM PDT 24
Finished Apr 16 02:32:30 PM PDT 24
Peak memory 281240 kb
Host smart-5be80b53-f3c0-4284-95c8-0388fd246c1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813150866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3813150866
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.2347980968
Short name T263
Test name
Test status
Simulation time 511493621 ps
CPU time 2.65 seconds
Started Apr 16 02:32:19 PM PDT 24
Finished Apr 16 02:32:22 PM PDT 24
Peak memory 203936 kb
Host smart-537730cf-1dcd-4f71-8647-fb06b4a81fde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347980968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.2347980968
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3685966415
Short name T200
Test name
Test status
Simulation time 2600968847 ps
CPU time 4.14 seconds
Started Apr 16 02:32:16 PM PDT 24
Finished Apr 16 02:32:21 PM PDT 24
Peak memory 205248 kb
Host smart-2d6c01b6-a914-4484-817f-dc8d5eded12e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685966415 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3685966415
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1178182765
Short name T291
Test name
Test status
Simulation time 14092808366 ps
CPU time 153.01 seconds
Started Apr 16 02:32:21 PM PDT 24
Finished Apr 16 02:34:55 PM PDT 24
Peak memory 1901404 kb
Host smart-c9b282c5-15bd-4806-a4bd-3450297f0326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178182765 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1178182765
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1958944397
Short name T1052
Test name
Test status
Simulation time 884940607 ps
CPU time 34.09 seconds
Started Apr 16 02:32:17 PM PDT 24
Finished Apr 16 02:32:52 PM PDT 24
Peak memory 203996 kb
Host smart-b10a677b-92c9-4c24-a367-99980d156ce3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958944397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1958944397
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.508273704
Short name T551
Test name
Test status
Simulation time 5714123503 ps
CPU time 73.87 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:33:32 PM PDT 24
Peak memory 206764 kb
Host smart-ac2bbd3f-52a4-4469-8574-d1229c85433e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508273704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_rd.508273704
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.55214399
Short name T355
Test name
Test status
Simulation time 52255354268 ps
CPU time 36.9 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:32:56 PM PDT 24
Peak memory 749736 kb
Host smart-92ba16dc-98f2-437b-92ea-05d8978da0af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55214399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stress_wr.55214399
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.3848845751
Short name T244
Test name
Test status
Simulation time 28417499273 ps
CPU time 924.35 seconds
Started Apr 16 02:32:19 PM PDT 24
Finished Apr 16 02:47:44 PM PDT 24
Peak memory 2261728 kb
Host smart-457982be-0fbb-416d-a19c-2a3e255912b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848845751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.3848845751
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.221605568
Short name T750
Test name
Test status
Simulation time 1303767540 ps
CPU time 6.22 seconds
Started Apr 16 02:32:20 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 212196 kb
Host smart-ecced84b-2072-408f-90e7-e75f13000c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221605568 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.221605568
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.3365020951
Short name T17
Test name
Test status
Simulation time 7329655443 ps
CPU time 6.09 seconds
Started Apr 16 02:32:17 PM PDT 24
Finished Apr 16 02:32:24 PM PDT 24
Peak memory 204076 kb
Host smart-ae6cbf2e-6916-4f9b-8159-116bbbb47f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365020951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.3365020951
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.596727442
Short name T790
Test name
Test status
Simulation time 43045778 ps
CPU time 0.59 seconds
Started Apr 16 02:32:25 PM PDT 24
Finished Apr 16 02:32:27 PM PDT 24
Peak memory 203548 kb
Host smart-a4e915df-1085-4413-b620-e57f7f629ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596727442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.596727442
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.4037946251
Short name T793
Test name
Test status
Simulation time 69873596 ps
CPU time 1.45 seconds
Started Apr 16 02:32:30 PM PDT 24
Finished Apr 16 02:32:32 PM PDT 24
Peak memory 212268 kb
Host smart-fec50ca3-6dc3-4428-91c2-c2e4acea5101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037946251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4037946251
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.448854608
Short name T701
Test name
Test status
Simulation time 1582537795 ps
CPU time 6.91 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:32:30 PM PDT 24
Peak memory 285948 kb
Host smart-55fe759d-e6f2-49a7-9f54-8b76f23b9ea0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448854608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.448854608
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2005542628
Short name T331
Test name
Test status
Simulation time 2460201602 ps
CPU time 65.06 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 670604 kb
Host smart-1bfcf491-be3d-404e-8f71-b4688dbbfb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005542628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2005542628
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3768183291
Short name T388
Test name
Test status
Simulation time 2357541650 ps
CPU time 79.54 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:33:43 PM PDT 24
Peak memory 732788 kb
Host smart-bca0eff6-e6d6-40dd-aab1-7d77b1266dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768183291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3768183291
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.454243269
Short name T333
Test name
Test status
Simulation time 343027915 ps
CPU time 1.26 seconds
Started Apr 16 02:32:36 PM PDT 24
Finished Apr 16 02:32:39 PM PDT 24
Peak memory 203876 kb
Host smart-07c41633-f946-4c72-bc3a-20365af7c838
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454243269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.454243269
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1621358593
Short name T426
Test name
Test status
Simulation time 122756689 ps
CPU time 2.88 seconds
Started Apr 16 02:32:30 PM PDT 24
Finished Apr 16 02:32:34 PM PDT 24
Peak memory 203964 kb
Host smart-1cf7a43c-60f3-4cff-997a-591b3c163204
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621358593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1621358593
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2783620627
Short name T988
Test name
Test status
Simulation time 8454394891 ps
CPU time 305.04 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:37:28 PM PDT 24
Peak memory 1133624 kb
Host smart-41884521-0586-4e97-b231-3da39124db8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783620627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2783620627
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3186903071
Short name T960
Test name
Test status
Simulation time 1014036335 ps
CPU time 10.25 seconds
Started Apr 16 02:32:26 PM PDT 24
Finished Apr 16 02:32:37 PM PDT 24
Peak memory 203956 kb
Host smart-7aa41a72-77c0-4673-85c2-2e551dcc98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186903071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3186903071
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1073957295
Short name T1114
Test name
Test status
Simulation time 6781478280 ps
CPU time 87.08 seconds
Started Apr 16 02:32:21 PM PDT 24
Finished Apr 16 02:33:49 PM PDT 24
Peak memory 348616 kb
Host smart-41f27304-7a05-4872-8105-e78b5b282e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073957295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1073957295
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.680127566
Short name T1259
Test name
Test status
Simulation time 16904003 ps
CPU time 0.65 seconds
Started Apr 16 02:32:19 PM PDT 24
Finished Apr 16 02:32:20 PM PDT 24
Peak memory 203656 kb
Host smart-3e86af72-4236-4aaa-9ef9-bbfb0983ebb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680127566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.680127566
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3220129206
Short name T1355
Test name
Test status
Simulation time 26527345056 ps
CPU time 83 seconds
Started Apr 16 02:32:18 PM PDT 24
Finished Apr 16 02:33:42 PM PDT 24
Peak memory 355548 kb
Host smart-3121cb23-2e9d-4858-874b-eef55341fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220129206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3220129206
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.3894153034
Short name T1288
Test name
Test status
Simulation time 39685864813 ps
CPU time 943.18 seconds
Started Apr 16 02:32:24 PM PDT 24
Finished Apr 16 02:48:08 PM PDT 24
Peak memory 2039280 kb
Host smart-7d2fcbfe-1066-4cd7-bd74-087d62d02e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894153034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.3894153034
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.637850480
Short name T969
Test name
Test status
Simulation time 2615519491 ps
CPU time 12.67 seconds
Started Apr 16 02:32:36 PM PDT 24
Finished Apr 16 02:32:50 PM PDT 24
Peak memory 216820 kb
Host smart-104996bd-765c-4d66-bfa8-4cfed91ff938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637850480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.637850480
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3200733459
Short name T453
Test name
Test status
Simulation time 3915872088 ps
CPU time 4.42 seconds
Started Apr 16 02:32:23 PM PDT 24
Finished Apr 16 02:32:28 PM PDT 24
Peak memory 212256 kb
Host smart-dfb2c281-743a-4bbc-91cd-9c95e289fc4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200733459 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3200733459
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2172577503
Short name T773
Test name
Test status
Simulation time 10058920080 ps
CPU time 71.88 seconds
Started Apr 16 02:32:36 PM PDT 24
Finished Apr 16 02:33:49 PM PDT 24
Peak memory 528800 kb
Host smart-082d6fe2-7f06-4168-890d-93c0f3b9211d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172577503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2172577503
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2109147477
Short name T424
Test name
Test status
Simulation time 10392995332 ps
CPU time 17.23 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:32:40 PM PDT 24
Peak memory 312688 kb
Host smart-1da62daa-a9c3-4e54-a348-6cd387184f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109147477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2109147477
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.734356012
Short name T15
Test name
Test status
Simulation time 361269528 ps
CPU time 2.1 seconds
Started Apr 16 02:32:21 PM PDT 24
Finished Apr 16 02:32:24 PM PDT 24
Peak memory 203996 kb
Host smart-153a7cce-f3f0-45df-93a1-21f0ab74e399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734356012 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.734356012
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1063140691
Short name T1251
Test name
Test status
Simulation time 1453518277 ps
CPU time 6.72 seconds
Started Apr 16 02:32:36 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 210664 kb
Host smart-a7493a79-8e16-448c-89e2-87183715ffdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063140691 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1063140691
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1581927697
Short name T1195
Test name
Test status
Simulation time 8717063634 ps
CPU time 9.91 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:32:33 PM PDT 24
Peak memory 260580 kb
Host smart-24d9f609-9490-416b-a244-5f08f3526568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581927697 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1581927697
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1278354165
Short name T679
Test name
Test status
Simulation time 1293327878 ps
CPU time 51.72 seconds
Started Apr 16 02:32:23 PM PDT 24
Finished Apr 16 02:33:16 PM PDT 24
Peak memory 204036 kb
Host smart-3762e429-53df-43c5-8e99-9713b43495df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278354165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1278354165
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3379778212
Short name T268
Test name
Test status
Simulation time 585784795 ps
CPU time 5.1 seconds
Started Apr 16 02:32:30 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 203976 kb
Host smart-4bc52125-8eee-4539-8c69-61002d1ca861
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379778212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3379778212
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2747724747
Short name T269
Test name
Test status
Simulation time 13509308859 ps
CPU time 12.51 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 204020 kb
Host smart-002ff6ad-d6be-47d8-95c7-ef46e89ca5ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747724747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2747724747
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1197906303
Short name T759
Test name
Test status
Simulation time 1165357711 ps
CPU time 5.9 seconds
Started Apr 16 02:32:24 PM PDT 24
Finished Apr 16 02:32:31 PM PDT 24
Peak memory 204040 kb
Host smart-4ce9ada8-431a-4b5b-9bd8-dd2127cbd866
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197906303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1197906303
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.1882992631
Short name T1329
Test name
Test status
Simulation time 572627934 ps
CPU time 3.12 seconds
Started Apr 16 02:32:22 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 203944 kb
Host smart-2229bdbe-71d5-4a9b-a481-5a6c391ff77c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882992631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.i2c_target_unexp_stop.1882992631
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.881493166
Short name T718
Test name
Test status
Simulation time 16593334 ps
CPU time 0.62 seconds
Started Apr 16 02:32:32 PM PDT 24
Finished Apr 16 02:32:34 PM PDT 24
Peak memory 203528 kb
Host smart-6a241910-9350-466f-8e9a-751e1b6cae9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881493166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.881493166
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2446827065
Short name T1066
Test name
Test status
Simulation time 267621204 ps
CPU time 1.6 seconds
Started Apr 16 02:32:27 PM PDT 24
Finished Apr 16 02:32:30 PM PDT 24
Peak memory 204092 kb
Host smart-b77c9637-17d0-404e-8ab1-6e33a5156f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446827065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2446827065
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.98977933
Short name T555
Test name
Test status
Simulation time 269736008 ps
CPU time 13.22 seconds
Started Apr 16 02:32:26 PM PDT 24
Finished Apr 16 02:32:40 PM PDT 24
Peak memory 256644 kb
Host smart-bd0fb6f1-7934-4725-b0ec-b33e317c700f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98977933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.98977933
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.890717541
Short name T1014
Test name
Test status
Simulation time 5374673475 ps
CPU time 38.35 seconds
Started Apr 16 02:32:28 PM PDT 24
Finished Apr 16 02:33:07 PM PDT 24
Peak memory 418028 kb
Host smart-5cf04029-b195-4ebd-9656-7648f6f0a750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890717541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.890717541
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2888966700
Short name T1110
Test name
Test status
Simulation time 6186251579 ps
CPU time 164.64 seconds
Started Apr 16 02:32:26 PM PDT 24
Finished Apr 16 02:35:12 PM PDT 24
Peak memory 694552 kb
Host smart-ec2bc305-70f7-4f10-af28-eb9048b31f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888966700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2888966700
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.4199698651
Short name T318
Test name
Test status
Simulation time 550969279 ps
CPU time 1.11 seconds
Started Apr 16 02:32:36 PM PDT 24
Finished Apr 16 02:32:38 PM PDT 24
Peak memory 203544 kb
Host smart-dbcd40b6-aacb-4efc-b859-f9eacf57d699
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199698651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.4199698651
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.4103253458
Short name T1333
Test name
Test status
Simulation time 149259521 ps
CPU time 7.13 seconds
Started Apr 16 02:32:26 PM PDT 24
Finished Apr 16 02:32:34 PM PDT 24
Peak memory 203964 kb
Host smart-dbfac971-c16a-4348-8a61-3b4c2cfaf8c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103253458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
4103253458
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3526081111
Short name T711
Test name
Test status
Simulation time 3177297142 ps
CPU time 69.38 seconds
Started Apr 16 02:32:26 PM PDT 24
Finished Apr 16 02:33:36 PM PDT 24
Peak memory 994108 kb
Host smart-2b48e269-18e8-45f4-932e-1ea6c37497dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526081111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3526081111
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.3877671972
Short name T461
Test name
Test status
Simulation time 278254092 ps
CPU time 3.87 seconds
Started Apr 16 02:32:31 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 203932 kb
Host smart-bb7f7ae1-5fb8-49ed-8b5f-493e9341d75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877671972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.3877671972
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1311424950
Short name T46
Test name
Test status
Simulation time 1631216421 ps
CPU time 30.31 seconds
Started Apr 16 02:32:32 PM PDT 24
Finished Apr 16 02:33:04 PM PDT 24
Peak memory 341484 kb
Host smart-1936a591-6992-48a8-9b0f-b700a8b5de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311424950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1311424950
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.415010463
Short name T1299
Test name
Test status
Simulation time 60574417 ps
CPU time 0.69 seconds
Started Apr 16 02:32:27 PM PDT 24
Finished Apr 16 02:32:29 PM PDT 24
Peak memory 203648 kb
Host smart-be5a7c8c-b8f5-40ba-9785-ff78e73090e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415010463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.415010463
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3564417812
Short name T692
Test name
Test status
Simulation time 26958149689 ps
CPU time 267 seconds
Started Apr 16 02:32:30 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 228532 kb
Host smart-b79e9f50-a1fd-4e8f-9163-909d1d3bc38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564417812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3564417812
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2679237805
Short name T667
Test name
Test status
Simulation time 7073470274 ps
CPU time 23.07 seconds
Started Apr 16 02:32:28 PM PDT 24
Finished Apr 16 02:32:52 PM PDT 24
Peak memory 304344 kb
Host smart-015cb57c-49c3-497f-a6d0-b4886a2d9105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679237805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2679237805
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.53429179
Short name T1020
Test name
Test status
Simulation time 92122541928 ps
CPU time 3032.98 seconds
Started Apr 16 02:32:26 PM PDT 24
Finished Apr 16 03:23:00 PM PDT 24
Peak memory 1356476 kb
Host smart-a1421f6e-1ca8-424a-911f-beab6d3dd004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53429179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.53429179
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1705183908
Short name T235
Test name
Test status
Simulation time 541037224 ps
CPU time 24.72 seconds
Started Apr 16 02:32:27 PM PDT 24
Finished Apr 16 02:32:53 PM PDT 24
Peak memory 212156 kb
Host smart-e28ed85a-3a5d-4df8-afab-5df0388374b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705183908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1705183908
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2742843816
Short name T330
Test name
Test status
Simulation time 730302293 ps
CPU time 3.92 seconds
Started Apr 16 02:32:34 PM PDT 24
Finished Apr 16 02:32:39 PM PDT 24
Peak memory 203944 kb
Host smart-028de07e-f84d-4b6c-83ff-bb11312883ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742843816 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2742843816
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.4253550646
Short name T1079
Test name
Test status
Simulation time 10368763457 ps
CPU time 12.66 seconds
Started Apr 16 02:32:27 PM PDT 24
Finished Apr 16 02:32:40 PM PDT 24
Peak memory 270132 kb
Host smart-e1a795b4-c8bb-4737-a827-8a4e84eacd32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253550646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.4253550646
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.4026578809
Short name T1215
Test name
Test status
Simulation time 10335519055 ps
CPU time 11.64 seconds
Started Apr 16 02:32:25 PM PDT 24
Finished Apr 16 02:32:38 PM PDT 24
Peak memory 265140 kb
Host smart-930553e5-2dcb-4281-aa09-b35093cd9a99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026578809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.4026578809
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.447527489
Short name T1124
Test name
Test status
Simulation time 1302444754 ps
CPU time 2.7 seconds
Started Apr 16 02:32:32 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 203972 kb
Host smart-961ee422-72d2-4b61-86c3-4b01d25b2d7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447527489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.447527489
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3518138212
Short name T606
Test name
Test status
Simulation time 2829903281 ps
CPU time 3.25 seconds
Started Apr 16 02:32:27 PM PDT 24
Finished Apr 16 02:32:31 PM PDT 24
Peak memory 204040 kb
Host smart-0a42d7ec-8034-4053-a7bf-8706d8f65cce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518138212 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3518138212
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.4182769536
Short name T1175
Test name
Test status
Simulation time 2504826244 ps
CPU time 3.28 seconds
Started Apr 16 02:32:30 PM PDT 24
Finished Apr 16 02:32:34 PM PDT 24
Peak memory 204072 kb
Host smart-b12c842f-2eab-42bb-a9fe-d87043fb1a53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182769536 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.4182769536
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.4046662338
Short name T1009
Test name
Test status
Simulation time 2134785890 ps
CPU time 38.6 seconds
Started Apr 16 02:32:25 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 203992 kb
Host smart-04274855-fed8-4089-8fac-c1785d167a17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046662338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.4046662338
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3206894137
Short name T780
Test name
Test status
Simulation time 1062079118 ps
CPU time 18.58 seconds
Started Apr 16 02:32:30 PM PDT 24
Finished Apr 16 02:32:49 PM PDT 24
Peak memory 218232 kb
Host smart-50011223-e739-4b8b-9747-eca08b43a6fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206894137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3206894137
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.17906361
Short name T301
Test name
Test status
Simulation time 6767566236 ps
CPU time 5.35 seconds
Started Apr 16 02:32:28 PM PDT 24
Finished Apr 16 02:32:34 PM PDT 24
Peak memory 204036 kb
Host smart-a9e07300-94cf-4b49-9c7d-ee53863a8b6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17906361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stress_wr.17906361
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3530625556
Short name T625
Test name
Test status
Simulation time 18225687509 ps
CPU time 930.72 seconds
Started Apr 16 02:32:28 PM PDT 24
Finished Apr 16 02:48:00 PM PDT 24
Peak memory 2155000 kb
Host smart-627589d0-4f93-41f8-bc47-43c28b6d8ebb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530625556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3530625556
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2590236627
Short name T287
Test name
Test status
Simulation time 23634254377 ps
CPU time 7.63 seconds
Started Apr 16 02:32:30 PM PDT 24
Finished Apr 16 02:32:39 PM PDT 24
Peak memory 218728 kb
Host smart-c7fcbbf9-7978-4a38-b646-11a9aa2fc357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590236627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2590236627
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.107614767
Short name T1263
Test name
Test status
Simulation time 15074526 ps
CPU time 0.61 seconds
Started Apr 16 02:32:38 PM PDT 24
Finished Apr 16 02:32:40 PM PDT 24
Peak memory 203580 kb
Host smart-db5a6725-c6b5-4eb0-9ab5-90551f56cb6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107614767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.107614767
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.4060999379
Short name T1222
Test name
Test status
Simulation time 48969943 ps
CPU time 1.41 seconds
Started Apr 16 02:32:32 PM PDT 24
Finished Apr 16 02:32:35 PM PDT 24
Peak memory 212328 kb
Host smart-38fe618b-dea2-43e2-be48-f2be8a839cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060999379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.4060999379
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3295178551
Short name T1027
Test name
Test status
Simulation time 277050071 ps
CPU time 6.25 seconds
Started Apr 16 02:32:34 PM PDT 24
Finished Apr 16 02:32:41 PM PDT 24
Peak memory 262932 kb
Host smart-908df72a-a7a0-4cbd-a415-2b73c7e8f38a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295178551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3295178551
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3022090202
Short name T1359
Test name
Test status
Simulation time 7517406863 ps
CPU time 126.94 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:34:49 PM PDT 24
Peak memory 654888 kb
Host smart-67e7af67-7494-4bbf-87ce-36e8ad64a2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022090202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3022090202
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.613369931
Short name T1199
Test name
Test status
Simulation time 1886866116 ps
CPU time 62.63 seconds
Started Apr 16 02:32:34 PM PDT 24
Finished Apr 16 02:33:38 PM PDT 24
Peak memory 661204 kb
Host smart-f41797ac-3236-47fe-9557-c7b4cdf3b6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613369931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.613369931
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2821624056
Short name T947
Test name
Test status
Simulation time 411868427 ps
CPU time 0.97 seconds
Started Apr 16 02:32:36 PM PDT 24
Finished Apr 16 02:32:38 PM PDT 24
Peak memory 203692 kb
Host smart-62101616-5e96-4407-aa07-1d9be4015974
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821624056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2821624056
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2369331385
Short name T1083
Test name
Test status
Simulation time 605952864 ps
CPU time 7.46 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:32:50 PM PDT 24
Peak memory 203964 kb
Host smart-ed0170f9-0a03-4c4c-ac75-12dab1bd9220
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369331385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2369331385
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1694562848
Short name T1230
Test name
Test status
Simulation time 16014851799 ps
CPU time 91.13 seconds
Started Apr 16 02:32:40 PM PDT 24
Finished Apr 16 02:34:12 PM PDT 24
Peak memory 977576 kb
Host smart-7c8f6cf0-7230-4ff3-b2b5-1c03323aa3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694562848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1694562848
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.259660743
Short name T696
Test name
Test status
Simulation time 678457732 ps
CPU time 4.79 seconds
Started Apr 16 02:32:38 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 203956 kb
Host smart-5e4e194f-aef9-43c7-a51c-f9b912ef060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259660743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.259660743
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2720819400
Short name T569
Test name
Test status
Simulation time 4709888810 ps
CPU time 49.66 seconds
Started Apr 16 02:32:38 PM PDT 24
Finished Apr 16 02:33:29 PM PDT 24
Peak memory 310316 kb
Host smart-d81bb37d-b5f5-41f3-b341-203683e0fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720819400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2720819400
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3255354916
Short name T1211
Test name
Test status
Simulation time 31091147 ps
CPU time 0.68 seconds
Started Apr 16 02:32:31 PM PDT 24
Finished Apr 16 02:32:32 PM PDT 24
Peak memory 203640 kb
Host smart-150e63d8-c80c-4890-b16c-c09d60701b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255354916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3255354916
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2940616956
Short name T1196
Test name
Test status
Simulation time 5957620139 ps
CPU time 241.22 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:36:43 PM PDT 24
Peak memory 219340 kb
Host smart-4e546ee4-c1eb-4e3a-9b88-d0ccd97ada83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940616956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2940616956
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1039457933
Short name T561
Test name
Test status
Simulation time 2938385340 ps
CPU time 25.38 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:33:07 PM PDT 24
Peak memory 315700 kb
Host smart-52e302f1-71ed-4c43-abba-a3470657bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039457933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1039457933
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2961386035
Short name T91
Test name
Test status
Simulation time 15936608197 ps
CPU time 1101.03 seconds
Started Apr 16 02:32:40 PM PDT 24
Finished Apr 16 02:51:03 PM PDT 24
Peak memory 3360276 kb
Host smart-86ae1771-7129-4498-b63f-b9114151a596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961386035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2961386035
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2144615427
Short name T675
Test name
Test status
Simulation time 636890910 ps
CPU time 10.48 seconds
Started Apr 16 02:32:31 PM PDT 24
Finished Apr 16 02:32:43 PM PDT 24
Peak memory 228200 kb
Host smart-d96417ef-e003-4c02-aa00-781e6fb54803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144615427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2144615427
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1173902357
Short name T974
Test name
Test status
Simulation time 4200773061 ps
CPU time 4.5 seconds
Started Apr 16 02:32:38 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 212232 kb
Host smart-58f4a936-0e47-4e16-b673-9684b0f61e03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173902357 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1173902357
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.127079699
Short name T464
Test name
Test status
Simulation time 10842963171 ps
CPU time 6.03 seconds
Started Apr 16 02:32:33 PM PDT 24
Finished Apr 16 02:32:41 PM PDT 24
Peak memory 246540 kb
Host smart-7a7888ae-2317-4f36-9ede-992defd9ef6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127079699 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.127079699
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1296583699
Short name T1021
Test name
Test status
Simulation time 10779258306 ps
CPU time 3.93 seconds
Started Apr 16 02:32:40 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 234572 kb
Host smart-670fd32c-0a1d-44b0-b414-4c6ffa6e4c0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296583699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1296583699
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3655050084
Short name T1063
Test name
Test status
Simulation time 388995623 ps
CPU time 2.37 seconds
Started Apr 16 02:32:39 PM PDT 24
Finished Apr 16 02:32:42 PM PDT 24
Peak memory 203972 kb
Host smart-61570a94-d429-4640-b2f4-1a6fc719adb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655050084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3655050084
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1957022114
Short name T724
Test name
Test status
Simulation time 852027866 ps
CPU time 4.26 seconds
Started Apr 16 02:32:32 PM PDT 24
Finished Apr 16 02:32:38 PM PDT 24
Peak memory 207784 kb
Host smart-d6af45f7-1f47-44b8-9164-073bea5b515c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957022114 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1957022114
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2064733793
Short name T1080
Test name
Test status
Simulation time 15585541307 ps
CPU time 11.09 seconds
Started Apr 16 02:32:31 PM PDT 24
Finished Apr 16 02:32:43 PM PDT 24
Peak memory 325184 kb
Host smart-b02c4c8c-fee5-488e-8ad4-2d559e0b99c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064733793 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2064733793
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3321201661
Short name T38
Test name
Test status
Simulation time 559876598 ps
CPU time 7.32 seconds
Started Apr 16 02:32:36 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 203976 kb
Host smart-e23e171e-c13d-44a8-9399-e51653018d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321201661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3321201661
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.4240941193
Short name T926
Test name
Test status
Simulation time 2725848251 ps
CPU time 19.06 seconds
Started Apr 16 02:32:34 PM PDT 24
Finished Apr 16 02:32:55 PM PDT 24
Peak memory 228716 kb
Host smart-4841f78a-a388-45df-bb7d-240870f8175e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240941193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.4240941193
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2545119481
Short name T1137
Test name
Test status
Simulation time 33971443436 ps
CPU time 47.15 seconds
Started Apr 16 02:32:32 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 926884 kb
Host smart-ef9f84d1-a3bc-4a9d-bff0-87e47a6d6200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545119481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2545119481
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.3687545337
Short name T942
Test name
Test status
Simulation time 6998030837 ps
CPU time 81.1 seconds
Started Apr 16 02:32:41 PM PDT 24
Finished Apr 16 02:34:03 PM PDT 24
Peak memory 1113208 kb
Host smart-6a31e0df-c771-4c69-859f-b1b160f40a03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687545337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.3687545337
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3119810700
Short name T1125
Test name
Test status
Simulation time 5687714344 ps
CPU time 6.56 seconds
Started Apr 16 02:32:34 PM PDT 24
Finished Apr 16 02:32:42 PM PDT 24
Peak memory 212272 kb
Host smart-11a98295-a240-4069-920e-88a002b471a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119810700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3119810700
Directory /workspace/9.i2c_target_timeout/latest
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