Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	940970	1			T1	2		T2	3		T3	91
all_values[1]	940970	1			T1	2		T2	3		T3	91
all_values[2]	940970	1			T1	2		T2	3		T3	91
all_values[3]	940970	1			T1	2		T2	3		T3	91
all_values[4]	940970	1			T1	2		T2	3		T3	91
all_values[5]	940970	1			T1	2		T2	3		T3	91
all_values[6]	940970	1			T1	2		T2	3		T3	91
all_values[7]	940970	1			T1	2		T2	3		T3	91
all_values[8]	940970	1			T1	2		T2	3		T3	91
all_values[9]	940970	1			T1	2		T2	3		T3	91
all_values[10]	940970	1			T1	2		T2	3		T3	91
all_values[11]	940970	1			T1	2		T2	3		T3	91
all_values[12]	940970	1			T1	2		T2	3		T3	91
all_values[13]	940970	1			T1	2		T2	3		T3	91
all_values[14]	940970	1			T1	2		T2	3		T3	91

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10168595

1

T1

26

T2

37

T3

1161

auto[1]

3945955

1

T1

4

T2

8

T3

204

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13177073

1

T1

30

T2

45

T3

1365

auto[1]

937477

1

T6

100191

T44

3969

T77

272

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	115536	1			T2	1		T3	16		T6	988
all_values[0]	auto[0]	auto[1]	7398	1			T6	423		T44	8		T77	12
all_values[0]	auto[1]	auto[0]	770509	1			T1	2		T2	2		T3	75
all_values[0]	auto[1]	auto[1]	47527	1			T6	6256		T44	276		T77	8
all_values[1]	auto[0]	auto[0]	874184	1			T1	2		T2	3		T3	91
all_values[1]	auto[0]	auto[1]	66009	1			T6	6676		T44	280		T78	14641
all_values[1]	auto[1]	auto[0]	562	1			T45	27		T56	1		T210	38
all_values[1]	auto[1]	auto[1]	215	1			T6	4		T44	4		T78	3
all_values[2]	auto[0]	auto[0]	872294	1			T1	2		T2	3		T3	91
all_values[2]	auto[0]	auto[1]	68464	1			T6	6677		T44	280		T77	19
all_values[2]	auto[1]	auto[1]	212	1			T6	3		T44	4		T77	1
all_values[3]	auto[0]	auto[0]	889291	1			T1	2		T2	3		T3	91
all_values[3]	auto[0]	auto[1]	51443	1			T6	6675		T44	278		T77	13
all_values[3]	auto[1]	auto[1]	236	1			T6	3		T44	4		T77	5
all_values[4]	auto[0]	auto[0]	870891	1			T1	2		T2	3		T3	91
all_values[4]	auto[0]	auto[1]	69831	1			T6	6678		T44	279		T77	17
all_values[4]	auto[1]	auto[0]	13	1			T211	1		T212	1		T213	1
all_values[4]	auto[1]	auto[1]	235	1			T6	2		T44	5		T77	3
all_values[5]	auto[0]	auto[0]	874708	1			T1	2		T2	3		T3	91
all_values[5]	auto[0]	auto[1]	66015	1			T6	6677		T77	14		T78	14640
all_values[5]	auto[1]	auto[1]	247	1			T6	2		T77	6		T78	2
all_values[6]	auto[0]	auto[0]	230675	1			T1	2		T2	2		T3	86
all_values[6]	auto[0]	auto[1]	10899	1			T6	153		T44	263		T77	16
all_values[6]	auto[1]	auto[0]	658370	1			T2	1		T3	5		T6	2
all_values[6]	auto[1]	auto[1]	41026	1			T6	6526		T44	21		T77	3
all_values[7]	auto[0]	auto[0]	850962	1			T1	2		T2	2		T3	67
all_values[7]	auto[0]	auto[1]	56662	1			T6	6367		T44	193		T77	15
all_values[7]	auto[1]	auto[0]	30373	1			T2	1		T3	24		T6	320
all_values[7]	auto[1]	auto[1]	2973	1			T6	313		T44	90		T77	3
all_values[8]	auto[0]	auto[0]	187782	1			T1	2		T2	2		T3	85
all_values[8]	auto[0]	auto[1]	8698	1			T6	58		T44	227		T77	15
all_values[8]	auto[1]	auto[0]	686639	1			T2	1		T3	6		T6	132
all_values[8]	auto[1]	auto[1]	57851	1			T6	6622		T44	55		T77	4
all_values[9]	auto[0]	auto[0]	218368	1			T1	2		T2	2		T3	86
all_values[9]	auto[0]	auto[1]	11993	1			T6	200		T44	257		T77	18
all_values[9]	auto[1]	auto[0]	662575	1			T2	1		T3	5		T6	1
all_values[9]	auto[1]	auto[1]	48034	1			T6	6480		T44	25		T77	2
all_values[10]	auto[0]	auto[0]	871161	1			T1	2		T2	3		T3	91
all_values[10]	auto[0]	auto[1]	69604	1			T6	6675		T44	282		T77	18
all_values[10]	auto[1]	auto[1]	205	1			T6	3		T44	2		T77	2
all_values[11]	auto[0]	auto[0]	3043	1			T2	1		T3	2		T5	1
all_values[11]	auto[0]	auto[1]	473	1			T6	24		T44	8		T77	13
all_values[11]	auto[1]	auto[0]	877981	1			T1	2		T2	2		T3	89
all_values[11]	auto[1]	auto[1]	59473	1			T6	6656		T44	276		T77	7
all_values[12]	auto[0]	auto[0]	889293	1			T1	2		T2	3		T3	91
all_values[12]	auto[0]	auto[1]	51486	1			T6	6675		T44	279		T77	17
all_values[12]	auto[1]	auto[1]	191	1			T6	4		T44	5		T77	1
all_values[13]	auto[0]	auto[0]	870946	1			T1	2		T2	3		T3	91
all_values[13]	auto[0]	auto[1]	69779	1			T6	6678		T44	278		T77	14
all_values[13]	auto[1]	auto[1]	245	1			T6	2		T44	6		T77	6
all_values[14]	auto[0]	auto[0]	870917	1			T1	2		T2	3		T3	91
all_values[14]	auto[0]	auto[1]	69790	1			T6	6677		T44	276		T77	14
all_values[14]	auto[1]	auto[1]	263	1			T6	2		T44	8		T77	6