ASSERT | PROPERTIES | SEQUENCES | |
Total | 441 | 0 | 10 |
Category 0 | 441 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 441 | 0 | 10 |
Severity 0 | 441 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 441 | 100.00 |
Uncovered | 6 | 1.36 |
Success | 435 | 98.64 |
Failure | 0 | 0.00 |
Incomplete | 1 | 0.23 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.i2c_core.u_fifos.AcqWriteStableBeforeHandshake_A | 0 | 0 | 444141709 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.FmtWriteStableBeforeHandshake_A | 0 | 0 | 444141709 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.TxWriteStableBeforeHandshake_A | 0 | 0 | 444141709 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.LockArbDecision_A | 0 | 0 | 444141709 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.NoReadyValidNoGrant_A | 0 | 0 | 444141709 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqStaysHighUntilGranted0_M | 0 | 0 | 444141709 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.RoundRobin_A | 0 | 0 | 444141709 | 487 | 0 | 1313 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 444759395 | 251568 | 251568 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 444759395 | 247 | 247 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 444759395 | 252 | 252 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 444759395 | 187 | 187 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 444759395 | 22 | 22 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 444759395 | 137 | 137 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 444759395 | 66 | 66 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 444759395 | 3743 | 3743 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 444759395 | 3689840 | 3689840 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 444759395 | 33246677 | 33246677 | 1456 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 444759395 | 251568 | 251568 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 444759395 | 247 | 247 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 444759395 | 252 | 252 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 444759395 | 187 | 187 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 444759395 | 22 | 22 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 444759395 | 137 | 137 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 444759395 | 66 | 66 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 444759395 | 3743 | 3743 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 444759395 | 3689840 | 3689840 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 444759395 | 33246677 | 33246677 | 1456 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |