Group : i2c_env_pkg::i2c_scl_stretch_cg
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Group : i2c_env_pkg::i2c_scl_stretch_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv


Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group i2c_env_pkg::i2c_scl_stretch_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_fifo_size 2 0 2 100.00 100 1 1 0
cp_host_mode_stretch 1 0 1 100.00 100 1 1 0
cp_target_scl_stretch_addr_write 1 0 1 100.00 100 1 1 0
cp_tx_fifo_size 2 0 2 100.00 100 1 1 0


Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_target_scl_stretch_read 4 0 4 100.00 100 1 1 0


Summary for Variable cp_acq_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_acq_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 109729792 1 T1 1076 T4 5183 T5 97668
empty 81591270 1 T2 6383 T5 1215 T6 539407


Summary for Variable cp_host_mode_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stretch 52826130 1 T2 1211 T6 529746 T8 30097


Summary for Variable cp_target_scl_stretch_addr_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_target_scl_stretch_addr_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
addr_write_byte_stretch 563009 1 T19 16014 T20 1499 T21 2401


Summary for Variable cp_tx_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_tx_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 43033644 1 T1 902 T4 4173 T5 96819
empty 148287446 1 T1 174 T2 6383 T4 1010


Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for cp_target_scl_stretch_read

Bins
cp_acq_fifo_sizecp_tx_fifo_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
empty not_empty 116 1 T243 116 - - - -
empty empty 1229753 1 T5 1215 T28 139 T32 9368


User Defined Cross Bins for cp_target_scl_stretch_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_byte_stretch 448600 1 T1 174 T4 1010 T5 849
scl_stretch_read_request 43482104 1 T1 1076 T4 5183 T5 97668

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