Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	940970	1			T1	2		T2	3		T3	91
all_pins[1]	940970	1			T1	2		T2	3		T3	91
all_pins[2]	940970	1			T1	2		T2	3		T3	91
all_pins[3]	940970	1			T1	2		T2	3		T3	91
all_pins[4]	940970	1			T1	2		T2	3		T3	91
all_pins[5]	940970	1			T1	2		T2	3		T3	91
all_pins[6]	940970	1			T1	2		T2	3		T3	91
all_pins[7]	940970	1			T1	2		T2	3		T3	91
all_pins[8]	940970	1			T1	2		T2	3		T3	91
all_pins[9]	940970	1			T1	2		T2	3		T3	91
all_pins[10]	940970	1			T1	2		T2	3		T3	91
all_pins[11]	940970	1			T1	2		T2	3		T3	91
all_pins[12]	940970	1			T1	2		T2	3		T3	91
all_pins[13]	940970	1			T1	2		T2	3		T3	91
all_pins[14]	940970	1			T1	2		T2	3		T3	91

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10174271	1			T1	26		T2	37		T3	1359
values[0x1]	3940279	1			T1	4		T2	8		T3	6
transitions[0x0=>0x1]	3187391	1			T1	4		T2	5		T3	6
transitions[0x1=>0x0]	3186351	1			T1	3		T2	4		T3	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	126439	1			T2	1		T3	91		T6	1417
all_pins[0]	values[0x1]	814531	1			T1	2		T2	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	813804	1			T1	2		T2	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	105	1			T6	2		T44	3		T78	1
all_pins[1]	values[0x0]	940138	1			T1	2		T2	3		T3	91
all_pins[1]	values[0x1]	832	1			T6	2		T44	4		T45	32
all_pins[1]	transitions[0x0=>0x1]	793	1			T6	1		T44	2		T45	32
all_pins[1]	transitions[0x1=>0x0]	67	1			T78	1		T73	2		T121	1
all_pins[2]	values[0x0]	940864	1			T1	2		T2	3		T3	91
all_pins[2]	values[0x1]	106	1			T6	1		T44	2		T78	1
all_pins[2]	transitions[0x0=>0x1]	85	1			T44	1		T78	1		T73	2
all_pins[2]	transitions[0x1=>0x0]	86	1			T44	1		T77	4		T73	2
all_pins[3]	values[0x0]	940863	1			T1	2		T2	3		T3	91
all_pins[3]	values[0x1]	107	1			T6	1		T44	2		T77	4
all_pins[3]	transitions[0x0=>0x1]	91	1			T6	1		T44	2		T77	4
all_pins[3]	transitions[0x1=>0x0]	127	1			T3	1		T44	1		T77	2
all_pins[4]	values[0x0]	940827	1			T1	2		T2	3		T3	90
all_pins[4]	values[0x1]	143	1			T3	1		T44	1		T77	2
all_pins[4]	transitions[0x0=>0x1]	116	1			T3	1		T44	1		T77	1
all_pins[4]	transitions[0x1=>0x0]	103	1			T77	2		T78	2		T73	1
all_pins[5]	values[0x0]	940840	1			T1	2		T2	3		T3	91
all_pins[5]	values[0x1]	130	1			T77	3		T78	2		T73	2
all_pins[5]	transitions[0x0=>0x1]	104	1			T77	3		T78	2		T73	2
all_pins[5]	transitions[0x1=>0x0]	698956	1			T2	1		T6	6528		T8	17
all_pins[6]	values[0x0]	241988	1			T1	2		T2	2		T3	91
all_pins[6]	values[0x1]	698982	1			T2	1		T6	6528		T8	17
all_pins[6]	transitions[0x0=>0x1]	678672	1			T6	6208		T8	11		T9	8
all_pins[6]	transitions[0x1=>0x0]	16378	1			T6	331		T8	20		T9	43
all_pins[7]	values[0x0]	904282	1			T1	2		T2	2		T3	91
all_pins[7]	values[0x1]	36688	1			T2	1		T6	651		T8	26
all_pins[7]	transitions[0x0=>0x1]	13423	1			T6	265		T8	19		T9	41
all_pins[7]	transitions[0x1=>0x0]	721000	1			T6	6365		T8	35		T9	20
all_pins[8]	values[0x0]	196705	1			T1	2		T2	2		T3	91
all_pins[8]	values[0x1]	744265	1			T2	1		T6	6751		T8	42
all_pins[8]	transitions[0x0=>0x1]	35999	1			T6	275		T8	34		T9	18
all_pins[8]	transitions[0x1=>0x0]	2282	1			T3	5		T6	5		T7	1
all_pins[9]	values[0x0]	230422	1			T1	2		T2	2		T3	86
all_pins[9]	values[0x1]	710548	1			T2	1		T3	5		T6	6481
all_pins[9]	transitions[0x0=>0x1]	710524	1			T2	1		T3	5		T6	6480
all_pins[9]	transitions[0x1=>0x0]	68	1			T6	1		T44	2		T77	1
all_pins[10]	values[0x0]	940878	1			T1	2		T2	3		T3	91
all_pins[10]	values[0x1]	92	1			T6	2		T44	2		T77	1
all_pins[10]	transitions[0x0=>0x1]	63	1			T6	1		T44	1		T77	1
all_pins[10]	transitions[0x1=>0x0]	933485	1			T1	2		T2	2		T4	2
all_pins[11]	values[0x0]	7456	1			T2	1		T3	91		T5	1
all_pins[11]	values[0x1]	933514	1			T1	2		T2	2		T4	2
all_pins[11]	transitions[0x0=>0x1]	933480	1			T1	2		T2	2		T4	2
all_pins[11]	transitions[0x1=>0x0]	61	1			T6	2		T44	2		T121	2
all_pins[12]	values[0x0]	940875	1			T1	2		T2	3		T3	91
all_pins[12]	values[0x1]	95	1			T6	3		T44	4		T73	1
all_pins[12]	transitions[0x0=>0x1]	80	1			T6	3		T44	4		T73	1
all_pins[12]	transitions[0x1=>0x0]	98	1			T6	1		T44	1		T77	1
all_pins[13]	values[0x0]	940857	1			T1	2		T2	3		T3	91
all_pins[13]	values[0x1]	113	1			T6	1		T44	1		T77	1
all_pins[13]	transitions[0x0=>0x1]	76	1			T6	1		T77	1		T73	2
all_pins[13]	transitions[0x1=>0x0]	96	1			T44	3		T77	2		T78	2
all_pins[14]	values[0x0]	940837	1			T1	2		T2	3		T3	91
all_pins[14]	values[0x1]	133	1			T44	4		T77	2		T78	2
all_pins[14]	transitions[0x0=>0x1]	81	1			T44	3		T77	1		T73	1
all_pins[14]	transitions[0x1=>0x0]	813439	1			T1	1		T2	1		T4	1