Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	514	1			T6	7		T44	8		T77	7
all_values[1]	514	1			T6	7		T44	8		T77	7
all_values[2]	514	1			T6	7		T44	8		T77	7
all_values[3]	514	1			T6	7		T44	8		T77	7
all_values[4]	514	1			T6	7		T44	8		T77	7
all_values[5]	514	1			T6	7		T44	8		T77	7
all_values[6]	514	1			T6	7		T44	8		T77	7
all_values[7]	514	1			T6	7		T44	8		T77	7
all_values[8]	514	1			T6	7		T44	8		T77	7
all_values[9]	514	1			T6	7		T44	8		T77	7
all_values[10]	514	1			T6	7		T44	8		T77	7
all_values[11]	514	1			T6	7		T44	8		T77	7
all_values[12]	514	1			T6	7		T44	8		T77	7
all_values[13]	514	1			T6	7		T44	8		T77	7
all_values[14]	514	1			T6	7		T44	8		T77	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4001

1

T6

41

T44

50

T77

56

auto[1]

3709

1

T6

64

T44

70

T77

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T6

9

T44

15

T77

15

auto[1]

6525

1

T6

96

T44

105

T77

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4534

1

T6

55

T44

70

T77

64

auto[1]

3176

1

T6

50

T44

50

T77

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	54	1			T78	1		T73	1		T121	1
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T6	2		T73	2		T177	3
all_values[0]	auto[0]	auto[1]	auto[0]	32	1			T6	1		T78	3		T178	1
all_values[0]	auto[0]	auto[1]	auto[1]	124	1			T6	1		T44	5		T77	2
all_values[0]	auto[1]	auto[0]	auto[1]	118	1			T6	3		T44	2		T77	4
all_values[0]	auto[1]	auto[1]	auto[1]	93	1			T44	1		T77	1		T73	5
all_values[1]	auto[0]	auto[0]	auto[0]	41	1			T77	2		T87	4		T93	2
all_values[1]	auto[0]	auto[0]	auto[1]	112	1			T6	1		T44	4		T78	3
all_values[1]	auto[0]	auto[1]	auto[0]	34	1			T77	5		T238	2		T178	2
all_values[1]	auto[0]	auto[1]	auto[1]	125	1			T6	2		T44	1		T73	5
all_values[1]	auto[1]	auto[0]	auto[1]	97	1			T6	1		T73	1		T121	1
all_values[1]	auto[1]	auto[1]	auto[1]	105	1			T6	3		T44	3		T78	1
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T73	3		T121	1		T177	3
all_values[2]	auto[0]	auto[0]	auto[1]	129	1			T6	3		T44	3		T77	2
all_values[2]	auto[0]	auto[1]	auto[0]	34	1			T73	2		T121	1		T178	1
all_values[2]	auto[0]	auto[1]	auto[1]	103	1			T6	1		T44	1		T77	4
all_values[2]	auto[1]	auto[0]	auto[1]	111	1			T44	2		T77	1		T78	2
all_values[2]	auto[1]	auto[1]	auto[1]	101	1			T6	3		T44	2		T78	1
all_values[3]	auto[0]	auto[0]	auto[0]	52	1			T44	1		T78	4		T73	2
all_values[3]	auto[0]	auto[0]	auto[1]	121	1			T6	1		T73	2		T121	3
all_values[3]	auto[0]	auto[1]	auto[0]	42	1			T6	2		T44	1		T77	2
all_values[3]	auto[0]	auto[1]	auto[1]	99	1			T44	3		T77	1		T73	2
all_values[3]	auto[1]	auto[0]	auto[1]	114	1			T6	2		T44	2		T73	3
all_values[3]	auto[1]	auto[1]	auto[1]	86	1			T6	2		T44	1		T77	4
all_values[4]	auto[0]	auto[0]	auto[0]	32	1			T177	1		T87	1		T239	2
all_values[4]	auto[0]	auto[0]	auto[1]	115	1			T6	4		T44	2		T77	1
all_values[4]	auto[0]	auto[1]	auto[0]	26	1			T78	1		T238	1		T93	1
all_values[4]	auto[0]	auto[1]	auto[1]	106	1			T6	1		T44	1		T77	3
all_values[4]	auto[1]	auto[0]	auto[1]	126	1			T44	4		T77	1		T73	2
all_values[4]	auto[1]	auto[1]	auto[1]	109	1			T6	2		T44	1		T77	2
all_values[5]	auto[0]	auto[0]	auto[0]	45	1			T44	2		T78	1		T121	1
all_values[5]	auto[0]	auto[0]	auto[1]	100	1			T77	1		T73	3		T121	3
all_values[5]	auto[0]	auto[1]	auto[0]	41	1			T6	1		T44	6		T78	1
all_values[5]	auto[0]	auto[1]	auto[1]	110	1			T6	4		T77	2		T78	1
all_values[5]	auto[1]	auto[0]	auto[1]	96	1			T6	1		T73	1		T177	5
all_values[5]	auto[1]	auto[1]	auto[1]	122	1			T6	1		T77	4		T78	1
all_values[6]	auto[0]	auto[0]	auto[0]	24	1			T77	1		T78	2		T121	1
all_values[6]	auto[0]	auto[0]	auto[1]	113	1			T77	3		T73	2		T121	2
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T6	1		T78	2		T238	1
all_values[6]	auto[0]	auto[1]	auto[1]	127	1			T6	3		T44	3		T77	1
all_values[6]	auto[1]	auto[0]	auto[1]	133	1			T44	2		T77	2		T73	6
all_values[6]	auto[1]	auto[1]	auto[1]	88	1			T6	3		T44	3		T121	2
all_values[7]	auto[0]	auto[0]	auto[0]	52	1			T77	2		T73	2		T177	3
all_values[7]	auto[0]	auto[0]	auto[1]	126	1			T6	4		T44	2		T78	2
all_values[7]	auto[0]	auto[1]	auto[0]	33	1			T44	1		T78	1		T177	1
all_values[7]	auto[0]	auto[1]	auto[1]	111	1			T44	2		T77	2		T73	3
all_values[7]	auto[1]	auto[0]	auto[1]	99	1			T6	1		T44	2		T78	1
all_values[7]	auto[1]	auto[1]	auto[1]	93	1			T6	2		T44	1		T77	3
all_values[8]	auto[0]	auto[0]	auto[0]	49	1			T77	1		T121	3		T177	1
all_values[8]	auto[0]	auto[0]	auto[1]	110	1			T6	3		T44	3		T77	1
all_values[8]	auto[0]	auto[1]	auto[0]	29	1			T44	2		T239	1		T178	2
all_values[8]	auto[0]	auto[1]	auto[1]	113	1			T6	1		T44	1		T77	2
all_values[8]	auto[1]	auto[0]	auto[1]	115	1			T6	1		T44	1		T77	2
all_values[8]	auto[1]	auto[1]	auto[1]	98	1			T6	2		T44	1		T77	1
all_values[9]	auto[0]	auto[0]	auto[0]	44	1			T44	1		T176	2		T240	1
all_values[9]	auto[0]	auto[0]	auto[1]	100	1			T6	1		T44	2		T77	5
all_values[9]	auto[0]	auto[1]	auto[0]	31	1			T44	1		T78	1		T176	1
all_values[9]	auto[0]	auto[1]	auto[1]	115	1			T6	2		T44	1		T73	4
all_values[9]	auto[1]	auto[0]	auto[1]	114	1			T44	1		T77	2		T73	2
all_values[9]	auto[1]	auto[1]	auto[1]	110	1			T6	4		T44	2		T78	1
all_values[10]	auto[0]	auto[0]	auto[0]	55	1			T6	1		T78	1		T121	1
all_values[10]	auto[0]	auto[0]	auto[1]	112	1			T77	4		T73	3		T121	1
all_values[10]	auto[0]	auto[1]	auto[0]	35	1			T6	1		T78	1		T73	2
all_values[10]	auto[0]	auto[1]	auto[1]	107	1			T6	2		T44	6		T77	1
all_values[10]	auto[1]	auto[0]	auto[1]	115	1			T73	3		T177	2		T238	1
all_values[10]	auto[1]	auto[1]	auto[1]	90	1			T6	3		T44	2		T77	2
all_values[11]	auto[0]	auto[0]	auto[0]	54	1			T78	1		T121	6		T177	1
all_values[11]	auto[0]	auto[0]	auto[1]	90	1			T6	2		T44	2		T77	1
all_values[11]	auto[0]	auto[1]	auto[0]	37	1			T121	1		T177	1		T238	1
all_values[11]	auto[0]	auto[1]	auto[1]	124	1			T6	1		T44	3		T77	2
all_values[11]	auto[1]	auto[0]	auto[1]	102	1			T6	2		T44	1		T77	3
all_values[11]	auto[1]	auto[1]	auto[1]	107	1			T6	2		T44	2		T77	1
all_values[12]	auto[0]	auto[0]	auto[0]	53	1			T77	2		T73	2		T121	1
all_values[12]	auto[0]	auto[0]	auto[1]	109	1			T44	1		T77	4		T73	3
all_values[12]	auto[0]	auto[1]	auto[0]	39	1			T6	1		T78	4		T177	1
all_values[12]	auto[0]	auto[1]	auto[1]	122	1			T6	2		T44	2		T73	3
all_values[12]	auto[1]	auto[0]	auto[1]	102	1			T44	1		T77	1		T73	1
all_values[12]	auto[1]	auto[1]	auto[1]	89	1			T6	4		T44	4		T73	2
all_values[13]	auto[0]	auto[0]	auto[0]	45	1			T87	1		T93	1		T176	1
all_values[13]	auto[0]	auto[0]	auto[1]	100	1			T44	1		T77	3		T78	2
all_values[13]	auto[0]	auto[1]	auto[0]	40	1			T238	1		T93	1		T176	1
all_values[13]	auto[0]	auto[1]	auto[1]	114	1			T6	2		T44	2		T77	1
all_values[13]	auto[1]	auto[0]	auto[1]	127	1			T6	4		T44	4		T77	2
all_values[13]	auto[1]	auto[1]	auto[1]	88	1			T6	1		T44	1		T77	1
all_values[14]	auto[0]	auto[0]	auto[0]	43	1			T78	2		T241	2		T176	2
all_values[14]	auto[0]	auto[0]	auto[1]	103	1			T6	1		T44	3		T77	3
all_values[14]	auto[0]	auto[1]	auto[0]	24	1			T6	1		T176	3		T239	2
all_values[14]	auto[0]	auto[1]	auto[1]	116	1			T6	2		T44	1		T78	1
all_values[14]	auto[1]	auto[0]	auto[1]	120	1			T6	3		T44	1		T77	2
all_values[14]	auto[1]	auto[1]	auto[1]	108	1			T44	3		T77	2		T78	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal