Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.73 97.85 92.37 97.66 89.57 95.18 98.67 91.81


Total test records in report: 1476
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html
T1312 /workspace/coverage/default/28.i2c_host_perf.3463963000 Apr 18 03:14:44 PM PDT 24 Apr 18 03:22:06 PM PDT 24 47362544510 ps
T1313 /workspace/coverage/default/13.i2c_host_may_nack.1668741390 Apr 18 03:10:10 PM PDT 24 Apr 18 03:10:16 PM PDT 24 686901467 ps
T1314 /workspace/coverage/default/16.i2c_host_fifo_full.908970747 Apr 18 03:11:14 PM PDT 24 Apr 18 03:12:10 PM PDT 24 1072155539 ps
T1315 /workspace/coverage/default/28.i2c_host_stress_all.736349108 Apr 18 03:14:44 PM PDT 24 Apr 18 03:26:33 PM PDT 24 81173000782 ps
T1316 /workspace/coverage/default/39.i2c_target_stretch.3692373774 Apr 18 03:17:41 PM PDT 24 Apr 18 03:28:41 PM PDT 24 22387889144 ps
T1317 /workspace/coverage/default/48.i2c_target_stress_wr.2959281456 Apr 18 03:20:03 PM PDT 24 Apr 18 03:20:49 PM PDT 24 20465866324 ps
T1318 /workspace/coverage/default/17.i2c_host_stretch_timeout.303873170 Apr 18 03:11:26 PM PDT 24 Apr 18 03:11:53 PM PDT 24 2724630817 ps
T1319 /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2865318405 Apr 18 03:19:03 PM PDT 24 Apr 18 03:20:04 PM PDT 24 10041013084 ps
T1320 /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.933954217 Apr 18 03:18:25 PM PDT 24 Apr 18 03:18:26 PM PDT 24 267539064 ps
T1321 /workspace/coverage/default/10.i2c_target_smoke.2259394893 Apr 18 03:08:43 PM PDT 24 Apr 18 03:09:28 PM PDT 24 4525932821 ps
T1322 /workspace/coverage/default/36.i2c_target_stress_rd.1823146981 Apr 18 03:16:57 PM PDT 24 Apr 18 03:17:13 PM PDT 24 7670064279 ps
T1323 /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2187927340 Apr 18 03:16:53 PM PDT 24 Apr 18 03:16:57 PM PDT 24 173592229 ps
T1324 /workspace/coverage/default/16.i2c_alert_test.1427538952 Apr 18 03:11:16 PM PDT 24 Apr 18 03:11:17 PM PDT 24 30011558 ps
T1325 /workspace/coverage/default/39.i2c_host_error_intr.2075158858 Apr 18 03:17:40 PM PDT 24 Apr 18 03:17:42 PM PDT 24 192733744 ps
T1326 /workspace/coverage/default/5.i2c_alert_test.2646282464 Apr 18 03:06:52 PM PDT 24 Apr 18 03:06:53 PM PDT 24 47476401 ps
T1327 /workspace/coverage/default/18.i2c_target_timeout.3183891047 Apr 18 03:11:51 PM PDT 24 Apr 18 03:11:57 PM PDT 24 4862130011 ps
T1328 /workspace/coverage/default/1.i2c_host_may_nack.2875920703 Apr 18 03:04:34 PM PDT 24 Apr 18 03:04:53 PM PDT 24 936212341 ps
T1329 /workspace/coverage/default/45.i2c_host_mode_toggle.746571347 Apr 18 03:19:22 PM PDT 24 Apr 18 03:20:23 PM PDT 24 5551887906 ps
T1330 /workspace/coverage/default/42.i2c_host_stretch_timeout.2255833985 Apr 18 03:18:23 PM PDT 24 Apr 18 03:18:48 PM PDT 24 2023348600 ps
T202 /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2320401906 Apr 18 03:12:17 PM PDT 24 Apr 18 03:12:32 PM PDT 24 10103555502 ps
T1331 /workspace/coverage/default/37.i2c_host_smoke.3769537701 Apr 18 03:17:04 PM PDT 24 Apr 18 03:17:35 PM PDT 24 3564592074 ps
T1332 /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1908457193 Apr 18 03:09:05 PM PDT 24 Apr 18 03:09:06 PM PDT 24 160180031 ps
T1333 /workspace/coverage/default/41.i2c_target_stress_wr.3170709456 Apr 18 03:18:11 PM PDT 24 Apr 18 03:21:54 PM PDT 24 65056743388 ps
T1334 /workspace/coverage/default/8.i2c_host_smoke.1711728493 Apr 18 03:07:45 PM PDT 24 Apr 18 03:08:36 PM PDT 24 4134284021 ps
T1335 /workspace/coverage/default/23.i2c_target_unexp_stop.1944103711 Apr 18 03:13:24 PM PDT 24 Apr 18 03:13:29 PM PDT 24 896407671 ps
T1336 /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3092109714 Apr 18 03:10:23 PM PDT 24 Apr 18 03:10:50 PM PDT 24 10269352549 ps
T1337 /workspace/coverage/default/30.i2c_target_stress_rd.1039188326 Apr 18 03:15:26 PM PDT 24 Apr 18 03:15:38 PM PDT 24 1635385847 ps
T1338 /workspace/coverage/default/44.i2c_host_stress_all.3106682385 Apr 18 03:18:58 PM PDT 24 Apr 18 03:20:18 PM PDT 24 3934376584 ps
T1339 /workspace/coverage/default/44.i2c_host_mode_toggle.1364511235 Apr 18 03:19:06 PM PDT 24 Apr 18 03:19:22 PM PDT 24 6173407099 ps
T1340 /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1770112966 Apr 18 03:03:39 PM PDT 24 Apr 18 03:04:09 PM PDT 24 10136619254 ps
T1341 /workspace/coverage/default/33.i2c_host_override.3429968648 Apr 18 03:16:07 PM PDT 24 Apr 18 03:16:08 PM PDT 24 240094137 ps
T1342 /workspace/coverage/default/23.i2c_host_override.3200919770 Apr 18 03:13:09 PM PDT 24 Apr 18 03:13:10 PM PDT 24 23231592 ps
T1343 /workspace/coverage/default/27.i2c_host_fifo_watermark.724615970 Apr 18 03:14:26 PM PDT 24 Apr 18 03:15:26 PM PDT 24 2808478910 ps
T113 /workspace/coverage/default/0.i2c_sec_cm.1403869801 Apr 18 03:03:49 PM PDT 24 Apr 18 03:03:50 PM PDT 24 244251461 ps
T1344 /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3115242229 Apr 18 03:14:50 PM PDT 24 Apr 18 03:14:54 PM PDT 24 10360665591 ps
T1345 /workspace/coverage/default/34.i2c_target_timeout.2148254502 Apr 18 03:16:27 PM PDT 24 Apr 18 03:16:34 PM PDT 24 4630756246 ps
T1346 /workspace/coverage/default/40.i2c_target_intr_stress_wr.2427207231 Apr 18 03:17:56 PM PDT 24 Apr 18 03:22:55 PM PDT 24 21968240846 ps
T1347 /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1409213907 Apr 18 03:16:36 PM PDT 24 Apr 18 03:16:37 PM PDT 24 404556469 ps
T1348 /workspace/coverage/default/19.i2c_target_smoke.1697998032 Apr 18 03:12:09 PM PDT 24 Apr 18 03:12:29 PM PDT 24 837325032 ps
T1349 /workspace/coverage/default/21.i2c_host_override.2286951594 Apr 18 03:12:36 PM PDT 24 Apr 18 03:12:37 PM PDT 24 17314534 ps
T1350 /workspace/coverage/default/21.i2c_target_stress_wr.240096051 Apr 18 03:12:43 PM PDT 24 Apr 18 03:14:19 PM PDT 24 49318928274 ps
T1351 /workspace/coverage/default/4.i2c_target_bad_addr.2786394882 Apr 18 03:06:14 PM PDT 24 Apr 18 03:06:18 PM PDT 24 710711875 ps
T1352 /workspace/coverage/default/32.i2c_host_fifo_overflow.4096703290 Apr 18 03:15:51 PM PDT 24 Apr 18 03:16:33 PM PDT 24 8671483395 ps
T1353 /workspace/coverage/default/12.i2c_target_intr_stress_wr.2969527634 Apr 18 03:09:40 PM PDT 24 Apr 18 03:16:24 PM PDT 24 22015563843 ps
T1354 /workspace/coverage/default/1.i2c_host_perf.889885957 Apr 18 03:04:15 PM PDT 24 Apr 18 03:04:36 PM PDT 24 7178151609 ps
T1355 /workspace/coverage/default/33.i2c_target_stress_wr.4265496757 Apr 18 03:16:12 PM PDT 24 Apr 18 03:24:21 PM PDT 24 47087630997 ps
T1356 /workspace/coverage/default/7.i2c_alert_test.1741921132 Apr 18 03:07:45 PM PDT 24 Apr 18 03:07:46 PM PDT 24 19159245 ps
T1357 /workspace/coverage/default/2.i2c_target_fifo_reset_tx.266377297 Apr 18 03:05:05 PM PDT 24 Apr 18 03:05:33 PM PDT 24 10224466853 ps
T1358 /workspace/coverage/default/0.i2c_alert_test.3112226293 Apr 18 03:03:51 PM PDT 24 Apr 18 03:03:52 PM PDT 24 51877735 ps
T1359 /workspace/coverage/default/12.i2c_host_stretch_timeout.3999408695 Apr 18 03:09:33 PM PDT 24 Apr 18 03:09:45 PM PDT 24 2836382672 ps
T1360 /workspace/coverage/default/15.i2c_target_stress_wr.2647673094 Apr 18 03:10:41 PM PDT 24 Apr 18 03:10:48 PM PDT 24 12239785501 ps
T1361 /workspace/coverage/default/46.i2c_host_override.2896046209 Apr 18 03:19:28 PM PDT 24 Apr 18 03:19:29 PM PDT 24 406106103 ps
T1362 /workspace/coverage/default/48.i2c_host_override.2688605434 Apr 18 03:20:00 PM PDT 24 Apr 18 03:20:01 PM PDT 24 27070748 ps
T1363 /workspace/coverage/default/48.i2c_target_intr_smoke.969832277 Apr 18 03:20:05 PM PDT 24 Apr 18 03:20:11 PM PDT 24 1412268260 ps
T1364 /workspace/coverage/default/5.i2c_host_mode_toggle.1751950021 Apr 18 03:06:55 PM PDT 24 Apr 18 03:07:16 PM PDT 24 5163838649 ps
T1365 /workspace/coverage/default/36.i2c_target_stretch.1245615207 Apr 18 03:16:58 PM PDT 24 Apr 18 03:17:12 PM PDT 24 6265751807 ps
T1366 /workspace/coverage/default/21.i2c_target_hrst.592056515 Apr 18 03:12:53 PM PDT 24 Apr 18 03:12:56 PM PDT 24 789318971 ps
T1367 /workspace/coverage/default/21.i2c_target_bad_addr.3740199373 Apr 18 03:12:50 PM PDT 24 Apr 18 03:12:53 PM PDT 24 560889885 ps
T1368 /workspace/coverage/default/29.i2c_host_override.4014417676 Apr 18 03:15:02 PM PDT 24 Apr 18 03:15:03 PM PDT 24 18008926 ps
T1369 /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3040437459 Apr 18 03:15:37 PM PDT 24 Apr 18 03:15:38 PM PDT 24 217330931 ps
T1370 /workspace/coverage/default/8.i2c_target_stretch.2267976403 Apr 18 03:08:00 PM PDT 24 Apr 18 03:10:09 PM PDT 24 36703327117 ps
T1371 /workspace/coverage/default/31.i2c_target_stretch.1885963951 Apr 18 03:15:42 PM PDT 24 Apr 18 03:16:28 PM PDT 24 8874424517 ps
T1372 /workspace/coverage/default/18.i2c_target_stretch.2178812206 Apr 18 03:11:50 PM PDT 24 Apr 18 03:46:34 PM PDT 24 36511408068 ps
T74 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.66088786 Apr 18 02:23:47 PM PDT 24 Apr 18 02:23:49 PM PDT 24 177862903 ps
T181 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2380318285 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:56 PM PDT 24 22659019 ps
T75 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1777117809 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:57 PM PDT 24 175093350 ps
T76 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1953679179 Apr 18 02:24:16 PM PDT 24 Apr 18 02:24:17 PM PDT 24 24439154 ps
T159 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2318927575 Apr 18 02:23:49 PM PDT 24 Apr 18 02:23:51 PM PDT 24 135030396 ps
T1373 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2543360856 Apr 18 02:23:47 PM PDT 24 Apr 18 02:23:49 PM PDT 24 74061303 ps
T160 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2057789939 Apr 18 02:23:52 PM PDT 24 Apr 18 02:23:54 PM PDT 24 31944908 ps
T1374 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2350907911 Apr 18 02:24:32 PM PDT 24 Apr 18 02:24:33 PM PDT 24 129295175 ps
T209 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.809112793 Apr 18 02:23:56 PM PDT 24 Apr 18 02:23:58 PM PDT 24 89580988 ps
T1375 /workspace/coverage/cover_reg_top/6.i2c_intr_test.4270456590 Apr 18 02:23:51 PM PDT 24 Apr 18 02:23:52 PM PDT 24 53855020 ps
T106 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3819136314 Apr 18 02:23:50 PM PDT 24 Apr 18 02:23:52 PM PDT 24 121788347 ps
T107 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3100202042 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:48 PM PDT 24 68537374 ps
T161 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.267461902 Apr 18 02:23:45 PM PDT 24 Apr 18 02:23:47 PM PDT 24 157229724 ps
T162 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3716725755 Apr 18 02:23:53 PM PDT 24 Apr 18 02:23:54 PM PDT 24 36973975 ps
T108 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2598127606 Apr 18 02:24:07 PM PDT 24 Apr 18 02:24:09 PM PDT 24 92671471 ps
T163 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1140261502 Apr 18 02:24:12 PM PDT 24 Apr 18 02:24:14 PM PDT 24 59492097 ps
T164 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3972649771 Apr 18 02:23:42 PM PDT 24 Apr 18 02:23:43 PM PDT 24 19268807 ps
T165 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3071604797 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:02 PM PDT 24 140502514 ps
T122 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2669428330 Apr 18 02:24:17 PM PDT 24 Apr 18 02:24:18 PM PDT 24 32507558 ps
T124 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3580441416 Apr 18 02:23:54 PM PDT 24 Apr 18 02:23:57 PM PDT 24 128319752 ps
T123 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.234677351 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:56 PM PDT 24 35245186 ps
T125 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.443558153 Apr 18 02:24:13 PM PDT 24 Apr 18 02:24:16 PM PDT 24 425508532 ps
T144 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1757370408 Apr 18 02:23:48 PM PDT 24 Apr 18 02:23:49 PM PDT 24 47147927 ps
T1376 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.4037979319 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:56 PM PDT 24 69534161 ps
T127 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3944019102 Apr 18 02:24:00 PM PDT 24 Apr 18 02:24:01 PM PDT 24 81037142 ps
T126 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2343539177 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:58 PM PDT 24 83201949 ps
T142 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4015013230 Apr 18 02:23:51 PM PDT 24 Apr 18 02:23:53 PM PDT 24 166261122 ps
T130 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.463878655 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:04 PM PDT 24 148816254 ps
T1377 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3066379854 Apr 18 02:24:25 PM PDT 24 Apr 18 02:24:27 PM PDT 24 35396848 ps
T243 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3615880858 Apr 18 02:23:40 PM PDT 24 Apr 18 02:23:41 PM PDT 24 20802716 ps
T1378 /workspace/coverage/cover_reg_top/37.i2c_intr_test.2754518706 Apr 18 02:24:25 PM PDT 24 Apr 18 02:24:26 PM PDT 24 16401114 ps
T128 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1905092252 Apr 18 02:24:17 PM PDT 24 Apr 18 02:24:19 PM PDT 24 118877594 ps
T143 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1502088230 Apr 18 02:23:53 PM PDT 24 Apr 18 02:23:54 PM PDT 24 28986066 ps
T129 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.207496913 Apr 18 02:23:57 PM PDT 24 Apr 18 02:23:59 PM PDT 24 79281752 ps
T1379 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.315577542 Apr 18 02:24:16 PM PDT 24 Apr 18 02:24:17 PM PDT 24 38348519 ps
T145 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.4281866787 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:47 PM PDT 24 247050162 ps
T135 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3763880510 Apr 18 02:23:52 PM PDT 24 Apr 18 02:23:54 PM PDT 24 119674950 ps
T1380 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3895994403 Apr 18 02:24:22 PM PDT 24 Apr 18 02:24:23 PM PDT 24 55612743 ps
T1381 /workspace/coverage/cover_reg_top/24.i2c_intr_test.170510532 Apr 18 02:24:32 PM PDT 24 Apr 18 02:24:33 PM PDT 24 20955324 ps
T1382 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3583495031 Apr 18 02:23:42 PM PDT 24 Apr 18 02:23:44 PM PDT 24 55618212 ps
T1383 /workspace/coverage/cover_reg_top/45.i2c_intr_test.4213676491 Apr 18 02:24:23 PM PDT 24 Apr 18 02:24:24 PM PDT 24 58452820 ps
T1384 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.341329145 Apr 18 02:24:11 PM PDT 24 Apr 18 02:24:12 PM PDT 24 36038956 ps
T1385 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1866848449 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:03 PM PDT 24 68988322 ps
T1386 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2585396819 Apr 18 02:24:17 PM PDT 24 Apr 18 02:24:18 PM PDT 24 47378356 ps
T1387 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1211576735 Apr 18 02:24:11 PM PDT 24 Apr 18 02:24:13 PM PDT 24 27352217 ps
T1388 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3973427343 Apr 18 02:24:14 PM PDT 24 Apr 18 02:24:15 PM PDT 24 17807227 ps
T1389 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1664539527 Apr 18 02:23:45 PM PDT 24 Apr 18 02:23:46 PM PDT 24 52819046 ps
T1390 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1139269526 Apr 18 02:24:06 PM PDT 24 Apr 18 02:24:07 PM PDT 24 27788514 ps
T1391 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1169442464 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:03 PM PDT 24 143824876 ps
T146 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1487996616 Apr 18 02:24:19 PM PDT 24 Apr 18 02:24:20 PM PDT 24 26682659 ps
T1392 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3048100697 Apr 18 02:24:25 PM PDT 24 Apr 18 02:24:27 PM PDT 24 38133989 ps
T1393 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3009121687 Apr 18 02:23:49 PM PDT 24 Apr 18 02:23:50 PM PDT 24 33375741 ps
T1394 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3301189572 Apr 18 02:23:59 PM PDT 24 Apr 18 02:24:00 PM PDT 24 43921470 ps
T1395 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1387814838 Apr 18 02:24:06 PM PDT 24 Apr 18 02:24:07 PM PDT 24 26747328 ps
T1396 /workspace/coverage/cover_reg_top/21.i2c_intr_test.3961137170 Apr 18 02:24:18 PM PDT 24 Apr 18 02:24:19 PM PDT 24 19350941 ps
T1397 /workspace/coverage/cover_reg_top/4.i2c_intr_test.135128485 Apr 18 02:23:45 PM PDT 24 Apr 18 02:23:47 PM PDT 24 25705615 ps
T214 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.770410709 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:03 PM PDT 24 161537614 ps
T1398 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3691428694 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:48 PM PDT 24 82877925 ps
T1399 /workspace/coverage/cover_reg_top/48.i2c_intr_test.4261895637 Apr 18 02:24:22 PM PDT 24 Apr 18 02:24:23 PM PDT 24 40472361 ps
T166 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4031265002 Apr 18 02:24:13 PM PDT 24 Apr 18 02:24:14 PM PDT 24 38203229 ps
T167 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.595595004 Apr 18 02:23:49 PM PDT 24 Apr 18 02:23:50 PM PDT 24 71418019 ps
T168 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3081021217 Apr 18 02:23:39 PM PDT 24 Apr 18 02:23:42 PM PDT 24 1004583747 ps
T169 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3684990888 Apr 18 02:24:00 PM PDT 24 Apr 18 02:24:02 PM PDT 24 51271686 ps
T1400 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1848206062 Apr 18 02:23:57 PM PDT 24 Apr 18 02:23:59 PM PDT 24 49572862 ps
T1401 /workspace/coverage/cover_reg_top/18.i2c_intr_test.4237738598 Apr 18 02:24:19 PM PDT 24 Apr 18 02:24:20 PM PDT 24 35123826 ps
T198 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3543183085 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:04 PM PDT 24 149413600 ps
T1402 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3358452353 Apr 18 02:24:31 PM PDT 24 Apr 18 02:24:33 PM PDT 24 56142849 ps
T1403 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1510815156 Apr 18 02:24:23 PM PDT 24 Apr 18 02:24:24 PM PDT 24 34681459 ps
T1404 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2828969636 Apr 18 02:24:20 PM PDT 24 Apr 18 02:24:21 PM PDT 24 26502951 ps
T131 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.661608927 Apr 18 02:24:05 PM PDT 24 Apr 18 02:24:07 PM PDT 24 44017018 ps
T1405 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2786738336 Apr 18 02:23:43 PM PDT 24 Apr 18 02:23:46 PM PDT 24 50681704 ps
T1406 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4088529725 Apr 18 02:23:53 PM PDT 24 Apr 18 02:23:55 PM PDT 24 126734821 ps
T1407 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2629796781 Apr 18 02:24:33 PM PDT 24 Apr 18 02:24:34 PM PDT 24 14899449 ps
T136 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.273671348 Apr 18 02:23:56 PM PDT 24 Apr 18 02:23:59 PM PDT 24 127139480 ps
T147 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4022946086 Apr 18 02:23:53 PM PDT 24 Apr 18 02:23:55 PM PDT 24 43424791 ps
T148 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3616132787 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:49 PM PDT 24 510707469 ps
T1408 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1628335579 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:57 PM PDT 24 233596120 ps
T1409 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3678420561 Apr 18 02:24:17 PM PDT 24 Apr 18 02:24:19 PM PDT 24 121555006 ps
T154 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3763628914 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:51 PM PDT 24 125552241 ps
T132 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3437431123 Apr 18 02:24:17 PM PDT 24 Apr 18 02:24:19 PM PDT 24 253946956 ps
T1410 /workspace/coverage/cover_reg_top/43.i2c_intr_test.871912425 Apr 18 02:24:20 PM PDT 24 Apr 18 02:24:21 PM PDT 24 21586698 ps
T138 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.343658049 Apr 18 02:23:40 PM PDT 24 Apr 18 02:23:42 PM PDT 24 82216614 ps
T1411 /workspace/coverage/cover_reg_top/3.i2c_intr_test.476914212 Apr 18 02:23:44 PM PDT 24 Apr 18 02:23:45 PM PDT 24 20818967 ps
T1412 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1972457799 Apr 18 02:23:50 PM PDT 24 Apr 18 02:23:51 PM PDT 24 16646047 ps
T133 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.646631585 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:50 PM PDT 24 605861750 ps
T1413 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3281898552 Apr 18 02:23:39 PM PDT 24 Apr 18 02:23:40 PM PDT 24 38970016 ps
T137 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4255129278 Apr 18 02:23:45 PM PDT 24 Apr 18 02:23:48 PM PDT 24 290527019 ps
T1414 /workspace/coverage/cover_reg_top/35.i2c_intr_test.686986847 Apr 18 02:24:22 PM PDT 24 Apr 18 02:24:23 PM PDT 24 17239479 ps
T149 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.122471378 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:48 PM PDT 24 87148962 ps
T1415 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.352730459 Apr 18 02:23:39 PM PDT 24 Apr 18 02:23:41 PM PDT 24 57766073 ps
T1416 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2331775042 Apr 18 02:24:24 PM PDT 24 Apr 18 02:24:25 PM PDT 24 19476937 ps
T1417 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3136796360 Apr 18 02:24:25 PM PDT 24 Apr 18 02:24:27 PM PDT 24 34303161 ps
T1418 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4134197460 Apr 18 02:24:02 PM PDT 24 Apr 18 02:24:03 PM PDT 24 188256826 ps
T1419 /workspace/coverage/cover_reg_top/20.i2c_intr_test.4127806119 Apr 18 02:24:16 PM PDT 24 Apr 18 02:24:17 PM PDT 24 42369101 ps
T1420 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1421472641 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:48 PM PDT 24 22494716 ps
T1421 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1963297822 Apr 18 02:23:59 PM PDT 24 Apr 18 02:24:01 PM PDT 24 183797033 ps
T1422 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3993166015 Apr 18 02:24:12 PM PDT 24 Apr 18 02:24:13 PM PDT 24 54664639 ps
T1423 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2972463692 Apr 18 02:24:20 PM PDT 24 Apr 18 02:24:23 PM PDT 24 255901065 ps
T1424 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.976675619 Apr 18 02:23:39 PM PDT 24 Apr 18 02:23:42 PM PDT 24 157517905 ps
T150 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2882125691 Apr 18 02:23:50 PM PDT 24 Apr 18 02:23:52 PM PDT 24 414710310 ps
T1425 /workspace/coverage/cover_reg_top/0.i2c_intr_test.4267289396 Apr 18 02:23:38 PM PDT 24 Apr 18 02:23:40 PM PDT 24 16407332 ps
T151 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2665346165 Apr 18 02:23:47 PM PDT 24 Apr 18 02:23:49 PM PDT 24 56883699 ps
T1426 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3516185931 Apr 18 02:24:18 PM PDT 24 Apr 18 02:24:19 PM PDT 24 295414896 ps
T1427 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1033019871 Apr 18 02:24:02 PM PDT 24 Apr 18 02:24:04 PM PDT 24 160332387 ps
T1428 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2313398595 Apr 18 02:23:50 PM PDT 24 Apr 18 02:23:53 PM PDT 24 1623292847 ps
T1429 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1174243285 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:02 PM PDT 24 194085315 ps
T1430 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4190914487 Apr 18 02:23:56 PM PDT 24 Apr 18 02:23:58 PM PDT 24 135498201 ps
T1431 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3569318098 Apr 18 02:24:02 PM PDT 24 Apr 18 02:24:03 PM PDT 24 44531971 ps
T1432 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3043697281 Apr 18 02:24:26 PM PDT 24 Apr 18 02:24:27 PM PDT 24 35586208 ps
T1433 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1982945051 Apr 18 02:23:47 PM PDT 24 Apr 18 02:23:50 PM PDT 24 436474944 ps
T1434 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.839367858 Apr 18 02:23:56 PM PDT 24 Apr 18 02:24:00 PM PDT 24 791681794 ps
T1435 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4202246445 Apr 18 02:23:57 PM PDT 24 Apr 18 02:23:58 PM PDT 24 24589657 ps
T1436 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.613784949 Apr 18 02:23:50 PM PDT 24 Apr 18 02:23:53 PM PDT 24 105208097 ps
T218 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4213161978 Apr 18 02:23:49 PM PDT 24 Apr 18 02:23:51 PM PDT 24 41618826 ps
T1437 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1503142818 Apr 18 02:23:53 PM PDT 24 Apr 18 02:23:54 PM PDT 24 18223402 ps
T152 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4047745036 Apr 18 02:23:49 PM PDT 24 Apr 18 02:23:51 PM PDT 24 37545367 ps
T1438 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2424415951 Apr 18 02:23:56 PM PDT 24 Apr 18 02:23:58 PM PDT 24 67491368 ps
T140 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.806358194 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:04 PM PDT 24 542376924 ps
T1439 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2962391209 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:03 PM PDT 24 68805157 ps
T1440 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3610487912 Apr 18 02:24:20 PM PDT 24 Apr 18 02:24:21 PM PDT 24 45671893 ps
T1441 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1448009101 Apr 18 02:23:54 PM PDT 24 Apr 18 02:23:56 PM PDT 24 107526922 ps
T1442 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3319929898 Apr 18 02:23:45 PM PDT 24 Apr 18 02:23:47 PM PDT 24 55809794 ps
T1443 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3185829345 Apr 18 02:24:16 PM PDT 24 Apr 18 02:24:17 PM PDT 24 35885096 ps
T1444 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1478624529 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:48 PM PDT 24 24990557 ps
T1445 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3233232322 Apr 18 02:23:51 PM PDT 24 Apr 18 02:23:52 PM PDT 24 74630315 ps
T139 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2300960701 Apr 18 02:24:17 PM PDT 24 Apr 18 02:24:20 PM PDT 24 1004015244 ps
T1446 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1679471780 Apr 18 02:24:13 PM PDT 24 Apr 18 02:24:14 PM PDT 24 35469380 ps
T1447 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1208653718 Apr 18 02:23:56 PM PDT 24 Apr 18 02:23:58 PM PDT 24 36686702 ps
T1448 /workspace/coverage/cover_reg_top/1.i2c_intr_test.643752690 Apr 18 02:23:47 PM PDT 24 Apr 18 02:23:48 PM PDT 24 14779573 ps
T153 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.776261460 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:47 PM PDT 24 22042493 ps
T1449 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3056185196 Apr 18 02:24:01 PM PDT 24 Apr 18 02:24:02 PM PDT 24 41053113 ps
T134 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2466339741 Apr 18 02:23:49 PM PDT 24 Apr 18 02:23:52 PM PDT 24 664314304 ps
T1450 /workspace/coverage/cover_reg_top/8.i2c_intr_test.2581859077 Apr 18 02:23:51 PM PDT 24 Apr 18 02:23:52 PM PDT 24 15508916 ps
T1451 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3848678914 Apr 18 02:23:39 PM PDT 24 Apr 18 02:23:41 PM PDT 24 40982157 ps
T155 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2835303207 Apr 18 02:23:57 PM PDT 24 Apr 18 02:23:59 PM PDT 24 15415610 ps
T1452 /workspace/coverage/cover_reg_top/34.i2c_intr_test.4147173692 Apr 18 02:24:33 PM PDT 24 Apr 18 02:24:35 PM PDT 24 15479067 ps
T1453 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3575765439 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:56 PM PDT 24 154937279 ps
T1454 /workspace/coverage/cover_reg_top/33.i2c_intr_test.2347359710 Apr 18 02:24:21 PM PDT 24 Apr 18 02:24:22 PM PDT 24 49821366 ps
T1455 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1539685011 Apr 18 02:24:24 PM PDT 24 Apr 18 02:24:25 PM PDT 24 27534667 ps
T1456 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2022056662 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:56 PM PDT 24 61139711 ps
T1457 /workspace/coverage/cover_reg_top/9.i2c_intr_test.76338946 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:56 PM PDT 24 17179913 ps
T1458 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3875096965 Apr 18 02:24:04 PM PDT 24 Apr 18 02:24:05 PM PDT 24 99687819 ps
T1459 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2360241585 Apr 18 02:23:56 PM PDT 24 Apr 18 02:23:58 PM PDT 24 48616687 ps
T1460 /workspace/coverage/cover_reg_top/44.i2c_intr_test.833715373 Apr 18 02:24:32 PM PDT 24 Apr 18 02:24:34 PM PDT 24 16763314 ps
T157 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1660500329 Apr 18 02:24:10 PM PDT 24 Apr 18 02:24:11 PM PDT 24 61631075 ps
T1461 /workspace/coverage/cover_reg_top/22.i2c_intr_test.644601903 Apr 18 02:24:20 PM PDT 24 Apr 18 02:24:22 PM PDT 24 29052924 ps
T158 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.983977484 Apr 18 02:23:56 PM PDT 24 Apr 18 02:23:57 PM PDT 24 37586688 ps
T1462 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.918715958 Apr 18 02:23:58 PM PDT 24 Apr 18 02:23:59 PM PDT 24 16729272 ps
T1463 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.425492387 Apr 18 02:23:55 PM PDT 24 Apr 18 02:23:57 PM PDT 24 130336838 ps
T1464 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.592746876 Apr 18 02:23:57 PM PDT 24 Apr 18 02:23:58 PM PDT 24 41046754 ps
T156 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.705542886 Apr 18 02:23:47 PM PDT 24 Apr 18 02:23:48 PM PDT 24 39875166 ps
T1465 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1452074700 Apr 18 02:24:22 PM PDT 24 Apr 18 02:24:23 PM PDT 24 19877885 ps
T1466 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.4263225324 Apr 18 02:24:07 PM PDT 24 Apr 18 02:24:08 PM PDT 24 35456220 ps
T1467 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1312925383 Apr 18 02:24:33 PM PDT 24 Apr 18 02:24:34 PM PDT 24 24391306 ps
T1468 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3010571093 Apr 18 02:24:11 PM PDT 24 Apr 18 02:24:13 PM PDT 24 51377171 ps
T1469 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2948134678 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:49 PM PDT 24 98385447 ps
T1470 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2721725269 Apr 18 02:24:20 PM PDT 24 Apr 18 02:24:22 PM PDT 24 34346818 ps
T1471 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.4023119513 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:48 PM PDT 24 29633239 ps
T1472 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1032321738 Apr 18 02:24:06 PM PDT 24 Apr 18 02:24:07 PM PDT 24 16816843 ps
T1473 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1783549382 Apr 18 02:23:46 PM PDT 24 Apr 18 02:23:47 PM PDT 24 78360897 ps
T1474 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3244413688 Apr 18 02:23:51 PM PDT 24 Apr 18 02:23:54 PM PDT 24 559963015 ps
T1475 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1832004876 Apr 18 02:24:25 PM PDT 24 Apr 18 02:24:26 PM PDT 24 16345172 ps
T1476 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2261028721 Apr 18 02:24:21 PM PDT 24 Apr 18 02:24:22 PM PDT 24 21291103 ps

Test location /workspace/coverage/default/49.i2c_host_stress_all.2108602058
Short name T6
Test name
Test status
Simulation time 14929872164 ps
CPU time 406.85 seconds
Started Apr 18 03:20:13 PM PDT 24
Finished Apr 18 03:27:00 PM PDT 24
Peak memory 1580080 kb
Host smart-97902e98-5a71-4521-85a2-0c386f43fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108602058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2108602058
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2811987923
Short name T5
Test name
Test status
Simulation time 10087567901 ps
CPU time 67.79 seconds
Started Apr 18 03:20:23 PM PDT 24
Finished Apr 18 03:21:31 PM PDT 24
Peak memory 454824 kb
Host smart-58dee7b6-3274-44e7-aa6a-c0c80f747256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811987923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2811987923
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3929380988
Short name T14
Test name
Test status
Simulation time 9664495920 ps
CPU time 9.97 seconds
Started Apr 18 03:04:15 PM PDT 24
Finished Apr 18 03:04:25 PM PDT 24
Peak memory 204192 kb
Host smart-60ed0c0c-ce7a-4310-a9f7-e59f0fd66047
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929380988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3929380988
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.443558153
Short name T125
Test name
Test status
Simulation time 425508532 ps
CPU time 2.54 seconds
Started Apr 18 02:24:13 PM PDT 24
Finished Apr 18 02:24:16 PM PDT 24
Peak memory 203664 kb
Host smart-40a58afa-289d-4747-90c0-77e8220841e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443558153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.443558153
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2482167955
Short name T19
Test name
Test status
Simulation time 31557935809 ps
CPU time 268.14 seconds
Started Apr 18 03:12:06 PM PDT 24
Finished Apr 18 03:16:34 PM PDT 24
Peak memory 2936208 kb
Host smart-c51ce17e-3c6a-49e0-9abf-2671b16fc0d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482167955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2482167955
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3305798311
Short name T73
Test name
Test status
Simulation time 12952825742 ps
CPU time 393.31 seconds
Started Apr 18 03:06:12 PM PDT 24
Finished Apr 18 03:12:46 PM PDT 24
Peak memory 1642196 kb
Host smart-60500df1-be37-4bfe-b42f-268b9a04f658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305798311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3305798311
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_override.421949114
Short name T185
Test name
Test status
Simulation time 30803731 ps
CPU time 0.66 seconds
Started Apr 18 03:12:15 PM PDT 24
Finished Apr 18 03:12:17 PM PDT 24
Peak memory 203668 kb
Host smart-a57c90a6-3cec-4438-8447-efb135c89b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421949114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.421949114
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3876715512
Short name T3
Test name
Test status
Simulation time 6693552861 ps
CPU time 20.51 seconds
Started Apr 18 03:10:34 PM PDT 24
Finished Apr 18 03:10:56 PM PDT 24
Peak memory 204020 kb
Host smart-bf127735-e3be-4683-8ecd-1840d20ff7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876715512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3876715512
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3100202042
Short name T107
Test name
Test status
Simulation time 68537374 ps
CPU time 1.42 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203716 kb
Host smart-792647a3-cbe9-4c47-a008-4ab9660cdb7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100202042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3100202042
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.111774824
Short name T109
Test name
Test status
Simulation time 40873861 ps
CPU time 0.82 seconds
Started Apr 18 03:05:52 PM PDT 24
Finished Apr 18 03:05:53 PM PDT 24
Peak memory 221072 kb
Host smart-39fea12c-7dd9-483b-85fe-892172afc80e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111774824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.111774824
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.3954424718
Short name T239
Test name
Test status
Simulation time 13223405575 ps
CPU time 789.01 seconds
Started Apr 18 03:18:35 PM PDT 24
Finished Apr 18 03:31:45 PM PDT 24
Peak memory 1242000 kb
Host smart-950cedb9-56dd-4e68-aaeb-ea41ee2164c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954424718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.3954424718
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1498823185
Short name T28
Test name
Test status
Simulation time 757199821 ps
CPU time 3.72 seconds
Started Apr 18 03:04:28 PM PDT 24
Finished Apr 18 03:04:32 PM PDT 24
Peak memory 212196 kb
Host smart-a8ed386c-865b-498b-ac5e-0ae4ea93649b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498823185 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1498823185
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.4114258540
Short name T69
Test name
Test status
Simulation time 115621530 ps
CPU time 1 seconds
Started Apr 18 03:14:45 PM PDT 24
Finished Apr 18 03:14:46 PM PDT 24
Peak memory 203876 kb
Host smart-8edb7566-d9ef-493c-85c7-bbe93ebef5a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114258540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.4114258540
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4047745036
Short name T152
Test name
Test status
Simulation time 37545367 ps
CPU time 1.17 seconds
Started Apr 18 02:23:49 PM PDT 24
Finished Apr 18 02:23:51 PM PDT 24
Peak memory 203724 kb
Host smart-5b67036c-cc2b-4d22-9acb-5b81b4b51cdd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047745036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.4047745036
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.3573294532
Short name T238
Test name
Test status
Simulation time 97794521564 ps
CPU time 483.19 seconds
Started Apr 18 03:17:11 PM PDT 24
Finished Apr 18 03:25:15 PM PDT 24
Peak memory 838100 kb
Host smart-a9ff9321-2108-433c-aa91-d7a11b7d6d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573294532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3573294532
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2179118893
Short name T44
Test name
Test status
Simulation time 52911477123 ps
CPU time 334.73 seconds
Started Apr 18 03:07:29 PM PDT 24
Finished Apr 18 03:13:04 PM PDT 24
Peak memory 1308052 kb
Host smart-ca598d32-4a49-443c-9d49-ad437a0f9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179118893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2179118893
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.3487321017
Short name T18
Test name
Test status
Simulation time 14442297235 ps
CPU time 22.91 seconds
Started Apr 18 03:16:32 PM PDT 24
Finished Apr 18 03:16:55 PM PDT 24
Peak memory 213544 kb
Host smart-f2a124ac-3839-48b3-8d14-aec88ea8141d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487321017 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.3487321017
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3786917002
Short name T105
Test name
Test status
Simulation time 16238427 ps
CPU time 0.59 seconds
Started Apr 18 03:09:00 PM PDT 24
Finished Apr 18 03:09:01 PM PDT 24
Peak memory 203556 kb
Host smart-b8958dd3-f13b-474b-ab36-0bc6cad01989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786917002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3786917002
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3028816833
Short name T203
Test name
Test status
Simulation time 1398721931 ps
CPU time 2.73 seconds
Started Apr 18 03:09:33 PM PDT 24
Finished Apr 18 03:09:36 PM PDT 24
Peak memory 218864 kb
Host smart-201db59d-d940-4ad1-8e1d-6c5166196b8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028816833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3028816833
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.506740768
Short name T49
Test name
Test status
Simulation time 13413148149 ps
CPU time 132.96 seconds
Started Apr 18 03:18:22 PM PDT 24
Finished Apr 18 03:20:35 PM PDT 24
Peak memory 673376 kb
Host smart-cdb1ba56-829e-46df-a308-6c0926f246a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506740768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.506740768
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3304568413
Short name T411
Test name
Test status
Simulation time 5536782477 ps
CPU time 26.96 seconds
Started Apr 18 03:15:59 PM PDT 24
Finished Apr 18 03:16:26 PM PDT 24
Peak memory 309908 kb
Host smart-0c017167-e1ab-4104-a16d-4f8c29064a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304568413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3304568413
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.4228936317
Short name T52
Test name
Test status
Simulation time 10060241861 ps
CPU time 66.99 seconds
Started Apr 18 03:13:28 PM PDT 24
Finished Apr 18 03:14:36 PM PDT 24
Peak memory 582232 kb
Host smart-aac564ad-bc71-4474-b397-ca850e76a52b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228936317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.4228936317
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3716725755
Short name T162
Test name
Test status
Simulation time 36973975 ps
CPU time 0.66 seconds
Started Apr 18 02:23:53 PM PDT 24
Finished Apr 18 02:23:54 PM PDT 24
Peak memory 203532 kb
Host smart-07964907-c843-4eb4-bd9d-8fed7842a49f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716725755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3716725755
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2133967699
Short name T27
Test name
Test status
Simulation time 945872458 ps
CPU time 2.6 seconds
Started Apr 18 03:15:16 PM PDT 24
Finished Apr 18 03:15:19 PM PDT 24
Peak memory 203972 kb
Host smart-54be313d-eef8-4f91-8b37-b103f9d9c4c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133967699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2133967699
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.4023349148
Short name T217
Test name
Test status
Simulation time 33700443873 ps
CPU time 282.4 seconds
Started Apr 18 03:15:54 PM PDT 24
Finished Apr 18 03:20:37 PM PDT 24
Peak memory 1596376 kb
Host smart-0ba0bed0-7c66-45ff-b350-d03adb1f9494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023349148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.4023349148
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1413296955
Short name T93
Test name
Test status
Simulation time 12604943694 ps
CPU time 171.08 seconds
Started Apr 18 03:17:39 PM PDT 24
Finished Apr 18 03:20:31 PM PDT 24
Peak memory 510672 kb
Host smart-23009445-6c28-45bd-a647-437c728182e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413296955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1413296955
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2343539177
Short name T126
Test name
Test status
Simulation time 83201949 ps
CPU time 2.13 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203724 kb
Host smart-e68aea45-1847-4b76-bd24-fe2792ad6642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343539177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2343539177
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3829356302
Short name T96
Test name
Test status
Simulation time 1379794721 ps
CPU time 77.38 seconds
Started Apr 18 03:03:01 PM PDT 24
Finished Apr 18 03:04:19 PM PDT 24
Peak memory 410592 kb
Host smart-7fd6bd3b-4ea3-4aef-8224-5709d33e0282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829356302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3829356302
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1770112966
Short name T1340
Test name
Test status
Simulation time 10136619254 ps
CPU time 30.49 seconds
Started Apr 18 03:03:39 PM PDT 24
Finished Apr 18 03:04:09 PM PDT 24
Peak memory 375052 kb
Host smart-2f0fbe6d-b25b-46a6-bb74-9effe108b7dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770112966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1770112966
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1374690906
Short name T1083
Test name
Test status
Simulation time 18266197577 ps
CPU time 1024.24 seconds
Started Apr 18 03:15:29 PM PDT 24
Finished Apr 18 03:32:34 PM PDT 24
Peak memory 2224100 kb
Host smart-a6a9cc34-8fad-4e34-a3b1-b6ae946d87e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374690906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1374690906
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2775143804
Short name T234
Test name
Test status
Simulation time 335596788 ps
CPU time 5.12 seconds
Started Apr 18 03:19:22 PM PDT 24
Finished Apr 18 03:19:27 PM PDT 24
Peak memory 203984 kb
Host smart-8e8093ec-ce74-4486-abff-6157b256bbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775143804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2775143804
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.4043905697
Short name T205
Test name
Test status
Simulation time 43958821433 ps
CPU time 1499.6 seconds
Started Apr 18 03:07:05 PM PDT 24
Finished Apr 18 03:32:05 PM PDT 24
Peak memory 2569696 kb
Host smart-9f42ef8c-2834-4ba5-9c16-126a43e08382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043905697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.4043905697
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2300960701
Short name T139
Test name
Test status
Simulation time 1004015244 ps
CPU time 2 seconds
Started Apr 18 02:24:17 PM PDT 24
Finished Apr 18 02:24:20 PM PDT 24
Peak memory 203844 kb
Host smart-5157020c-f4ed-455b-a68f-f9e2fe0844f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300960701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2300960701
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/46.i2c_host_perf.4090637243
Short name T67
Test name
Test status
Simulation time 1349480373 ps
CPU time 6.12 seconds
Started Apr 18 03:19:28 PM PDT 24
Finished Apr 18 03:19:35 PM PDT 24
Peak memory 264628 kb
Host smart-5b66f570-673b-46a1-98c8-a2a0baaad04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090637243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.4090637243
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2738402582
Short name T43
Test name
Test status
Simulation time 1432010702 ps
CPU time 92.92 seconds
Started Apr 18 03:04:00 PM PDT 24
Finished Apr 18 03:05:34 PM PDT 24
Peak memory 531424 kb
Host smart-ae47771e-34ab-473e-96b0-e118e3dae824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738402582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2738402582
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3451935061
Short name T98
Test name
Test status
Simulation time 10320142054 ps
CPU time 13.91 seconds
Started Apr 18 03:12:47 PM PDT 24
Finished Apr 18 03:13:01 PM PDT 24
Peak memory 299700 kb
Host smart-b0cb68ee-d660-47cd-ad42-7e5647af34e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451935061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3451935061
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3615880858
Short name T243
Test name
Test status
Simulation time 20802716 ps
CPU time 0.72 seconds
Started Apr 18 02:23:40 PM PDT 24
Finished Apr 18 02:23:41 PM PDT 24
Peak memory 203492 kb
Host smart-3ce6677c-aacd-4979-a499-537159343e41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615880858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3615880858
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4213161978
Short name T218
Test name
Test status
Simulation time 41618826 ps
CPU time 1.07 seconds
Started Apr 18 02:23:49 PM PDT 24
Finished Apr 18 02:23:51 PM PDT 24
Peak memory 203772 kb
Host smart-586e35d8-6685-4767-ada0-3ebc15b631fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213161978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.4213161978
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3040498063
Short name T1055
Test name
Test status
Simulation time 2175559193 ps
CPU time 24.51 seconds
Started Apr 18 03:08:44 PM PDT 24
Finished Apr 18 03:09:09 PM PDT 24
Peak memory 212244 kb
Host smart-33abc80d-73e3-4fde-8db1-2c55f9cecbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040498063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3040498063
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.3789869643
Short name T176
Test name
Test status
Simulation time 19587519144 ps
CPU time 1155.56 seconds
Started Apr 18 03:09:37 PM PDT 24
Finished Apr 18 03:28:53 PM PDT 24
Peak memory 3922784 kb
Host smart-78ef0f99-1e42-464e-9e5d-57501a0d3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789869643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.3789869643
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1805119010
Short name T727
Test name
Test status
Simulation time 362020545 ps
CPU time 2.18 seconds
Started Apr 18 03:09:43 PM PDT 24
Finished Apr 18 03:09:46 PM PDT 24
Peak memory 203964 kb
Host smart-8fb6698d-e7cd-4d9a-b4a5-463fd75576c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805119010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1805119010
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2293504438
Short name T220
Test name
Test status
Simulation time 10434858455 ps
CPU time 69.14 seconds
Started Apr 18 03:10:20 PM PDT 24
Finished Apr 18 03:11:30 PM PDT 24
Peak memory 790188 kb
Host smart-ee4adc61-7b8c-42f6-9811-3e23d21821a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293504438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2293504438
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2466339741
Short name T134
Test name
Test status
Simulation time 664314304 ps
CPU time 2.04 seconds
Started Apr 18 02:23:49 PM PDT 24
Finished Apr 18 02:23:52 PM PDT 24
Peak memory 203784 kb
Host smart-6d82b2ee-1517-431c-b21c-3aaccaec6350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466339741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2466339741
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3543899666
Short name T55
Test name
Test status
Simulation time 10059773398 ps
CPU time 62.29 seconds
Started Apr 18 03:07:58 PM PDT 24
Finished Apr 18 03:09:01 PM PDT 24
Peak memory 549860 kb
Host smart-5570039f-405e-4b92-bfc8-527529f72d34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543899666 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3543899666
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2786738336
Short name T1405
Test name
Test status
Simulation time 50681704 ps
CPU time 2.45 seconds
Started Apr 18 02:23:43 PM PDT 24
Finished Apr 18 02:23:46 PM PDT 24
Peak memory 203716 kb
Host smart-9fee9a9c-0855-4fc4-8438-3f3a7bffe1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786738336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2786738336
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2981357238
Short name T82
Test name
Test status
Simulation time 10028081687 ps
CPU time 64.53 seconds
Started Apr 18 03:17:57 PM PDT 24
Finished Apr 18 03:19:03 PM PDT 24
Peak memory 533580 kb
Host smart-e744761a-c953-475d-8696-505ba52fd15c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981357238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2981357238
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2543360856
Short name T1373
Test name
Test status
Simulation time 74061303 ps
CPU time 1.65 seconds
Started Apr 18 02:23:47 PM PDT 24
Finished Apr 18 02:23:49 PM PDT 24
Peak memory 203824 kb
Host smart-1690e212-1060-43cb-afff-b890985d423b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543360856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2543360856
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3081021217
Short name T168
Test name
Test status
Simulation time 1004583747 ps
CPU time 3.21 seconds
Started Apr 18 02:23:39 PM PDT 24
Finished Apr 18 02:23:42 PM PDT 24
Peak memory 203748 kb
Host smart-8dca829e-149c-42bb-a908-989dc2c12fe5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081021217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3081021217
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.352730459
Short name T1415
Test name
Test status
Simulation time 57766073 ps
CPU time 0.83 seconds
Started Apr 18 02:23:39 PM PDT 24
Finished Apr 18 02:23:41 PM PDT 24
Peak memory 203648 kb
Host smart-951f248f-f0dc-4b13-a363-478f60de77dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352730459 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.352730459
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3972649771
Short name T164
Test name
Test status
Simulation time 19268807 ps
CPU time 0.75 seconds
Started Apr 18 02:23:42 PM PDT 24
Finished Apr 18 02:23:43 PM PDT 24
Peak memory 203512 kb
Host smart-b801241b-737e-44e8-9b73-ff676e8f3ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972649771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3972649771
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.4267289396
Short name T1425
Test name
Test status
Simulation time 16407332 ps
CPU time 0.65 seconds
Started Apr 18 02:23:38 PM PDT 24
Finished Apr 18 02:23:40 PM PDT 24
Peak memory 203424 kb
Host smart-0cc2496c-274d-4735-9362-a3e838c7d80f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267289396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.4267289396
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.4023119513
Short name T1471
Test name
Test status
Simulation time 29633239 ps
CPU time 1.05 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203784 kb
Host smart-7187ac47-fadf-4114-9aa2-6988f9dbcbcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023119513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.4023119513
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3848678914
Short name T1451
Test name
Test status
Simulation time 40982157 ps
CPU time 1.07 seconds
Started Apr 18 02:23:39 PM PDT 24
Finished Apr 18 02:23:41 PM PDT 24
Peak memory 203460 kb
Host smart-1c29783c-d3d3-460f-ab7f-5b2930df1554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848678914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3848678914
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.343658049
Short name T138
Test name
Test status
Simulation time 82216614 ps
CPU time 1.47 seconds
Started Apr 18 02:23:40 PM PDT 24
Finished Apr 18 02:23:42 PM PDT 24
Peak memory 203804 kb
Host smart-9011d63c-13d2-4410-afdd-a802081facb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343658049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.343658049
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2665346165
Short name T151
Test name
Test status
Simulation time 56883699 ps
CPU time 1.24 seconds
Started Apr 18 02:23:47 PM PDT 24
Finished Apr 18 02:23:49 PM PDT 24
Peak memory 203664 kb
Host smart-185fbd94-3145-462e-8211-62900bd86091
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665346165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2665346165
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.976675619
Short name T1424
Test name
Test status
Simulation time 157517905 ps
CPU time 2.8 seconds
Started Apr 18 02:23:39 PM PDT 24
Finished Apr 18 02:23:42 PM PDT 24
Peak memory 203840 kb
Host smart-a690c898-eb85-423d-bf7b-f54ae6de480f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976675619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.976675619
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3281898552
Short name T1413
Test name
Test status
Simulation time 38970016 ps
CPU time 0.66 seconds
Started Apr 18 02:23:39 PM PDT 24
Finished Apr 18 02:23:40 PM PDT 24
Peak memory 203448 kb
Host smart-ac710edb-a8e4-4e02-afb3-8424ef92703e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281898552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3281898552
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1478624529
Short name T1444
Test name
Test status
Simulation time 24990557 ps
CPU time 1.08 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203580 kb
Host smart-90ea2bab-f1f5-44e8-aca2-8f5d2ad72511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478624529 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1478624529
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.705542886
Short name T156
Test name
Test status
Simulation time 39875166 ps
CPU time 0.74 seconds
Started Apr 18 02:23:47 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203504 kb
Host smart-2c563da0-51e5-4b5e-9ba3-543a3c3ba7f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705542886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.705542886
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.643752690
Short name T1448
Test name
Test status
Simulation time 14779573 ps
CPU time 0.64 seconds
Started Apr 18 02:23:47 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203440 kb
Host smart-e0504dc0-7371-4230-9cd9-78abdfbe5fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643752690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.643752690
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.267461902
Short name T161
Test name
Test status
Simulation time 157229724 ps
CPU time 0.85 seconds
Started Apr 18 02:23:45 PM PDT 24
Finished Apr 18 02:23:47 PM PDT 24
Peak memory 203528 kb
Host smart-268b9dd4-2b28-466d-8a13-b736f215df74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267461902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.267461902
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3583495031
Short name T1382
Test name
Test status
Simulation time 55618212 ps
CPU time 1.27 seconds
Started Apr 18 02:23:42 PM PDT 24
Finished Apr 18 02:23:44 PM PDT 24
Peak memory 203820 kb
Host smart-07de9d72-25ec-4dcb-b565-cd2ee0162c22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583495031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3583495031
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3569318098
Short name T1431
Test name
Test status
Simulation time 44531971 ps
CPU time 0.86 seconds
Started Apr 18 02:24:02 PM PDT 24
Finished Apr 18 02:24:03 PM PDT 24
Peak memory 203536 kb
Host smart-8afd34e1-b7c9-476d-b33c-ea9b9db48c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569318098 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3569318098
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.4037979319
Short name T1376
Test name
Test status
Simulation time 69534161 ps
CPU time 0.7 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:56 PM PDT 24
Peak memory 203556 kb
Host smart-290b8038-a859-4f93-8e26-4f70bec1ad2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037979319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.4037979319
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2380318285
Short name T181
Test name
Test status
Simulation time 22659019 ps
CPU time 0.65 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:56 PM PDT 24
Peak memory 203420 kb
Host smart-bb6e1546-ed71-4dd1-9879-b0e0d4018827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380318285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2380318285
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.839367858
Short name T1434
Test name
Test status
Simulation time 791681794 ps
CPU time 2.74 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:24:00 PM PDT 24
Peak memory 203744 kb
Host smart-1982e3d8-0333-4f2c-8ee9-cbbf2de85b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839367858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.839367858
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.273671348
Short name T136
Test name
Test status
Simulation time 127139480 ps
CPU time 2.01 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:23:59 PM PDT 24
Peak memory 203796 kb
Host smart-c2e91807-d1c6-40f5-8ccf-bb27e162f34b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273671348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.273671348
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4202246445
Short name T1435
Test name
Test status
Simulation time 24589657 ps
CPU time 0.8 seconds
Started Apr 18 02:23:57 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203628 kb
Host smart-676ddcaf-df11-4e8d-8353-cc97ceb5d360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202246445 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.4202246445
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.918715958
Short name T1462
Test name
Test status
Simulation time 16729272 ps
CPU time 0.71 seconds
Started Apr 18 02:23:58 PM PDT 24
Finished Apr 18 02:23:59 PM PDT 24
Peak memory 203576 kb
Host smart-3f1de1e9-3f72-43d9-ae2d-9f8972528572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918715958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.918715958
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1848206062
Short name T1400
Test name
Test status
Simulation time 49572862 ps
CPU time 0.7 seconds
Started Apr 18 02:23:57 PM PDT 24
Finished Apr 18 02:23:59 PM PDT 24
Peak memory 203428 kb
Host smart-b74d89be-1c9a-4c83-8b92-5a14f611dddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848206062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1848206062
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2022056662
Short name T1456
Test name
Test status
Simulation time 61139711 ps
CPU time 0.78 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:56 PM PDT 24
Peak memory 203552 kb
Host smart-ea2f9f9f-0deb-4235-a4c7-a299e8d74300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022056662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2022056662
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2360241585
Short name T1459
Test name
Test status
Simulation time 48616687 ps
CPU time 1.28 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203824 kb
Host smart-6e7ec948-4532-4645-b674-83aca40b77fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360241585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2360241585
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1174243285
Short name T1429
Test name
Test status
Simulation time 194085315 ps
CPU time 0.96 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:02 PM PDT 24
Peak memory 203632 kb
Host smart-ba4f8f54-d200-4496-b1f0-e31eaeecb1f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174243285 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1174243285
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.809112793
Short name T209
Test name
Test status
Simulation time 89580988 ps
CPU time 0.67 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203392 kb
Host smart-1560cd37-2411-4cd6-84b2-fb3cdf3b4a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809112793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.809112793
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1208653718
Short name T1447
Test name
Test status
Simulation time 36686702 ps
CPU time 0.68 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203412 kb
Host smart-102755e2-2da1-4da9-bc29-d0d7bf81e5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208653718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1208653718
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3071604797
Short name T165
Test name
Test status
Simulation time 140502514 ps
CPU time 1.02 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:02 PM PDT 24
Peak memory 203712 kb
Host smart-74a54855-33c8-46a5-96cc-211053b25c44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071604797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3071604797
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.207496913
Short name T129
Test name
Test status
Simulation time 79281752 ps
CPU time 1.29 seconds
Started Apr 18 02:23:57 PM PDT 24
Finished Apr 18 02:23:59 PM PDT 24
Peak memory 203532 kb
Host smart-738c3000-75b6-43aa-8bc1-b650ae89e76f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207496913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.207496913
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.770410709
Short name T214
Test name
Test status
Simulation time 161537614 ps
CPU time 2.08 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:03 PM PDT 24
Peak memory 203748 kb
Host smart-122cf175-b891-4a20-a27a-e25bfce18715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770410709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.770410709
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4134197460
Short name T1418
Test name
Test status
Simulation time 188256826 ps
CPU time 0.94 seconds
Started Apr 18 02:24:02 PM PDT 24
Finished Apr 18 02:24:03 PM PDT 24
Peak memory 203608 kb
Host smart-7168f0ae-6ce6-4c21-b4ee-23dc3af804b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134197460 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.4134197460
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1866848449
Short name T1385
Test name
Test status
Simulation time 68988322 ps
CPU time 0.66 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:03 PM PDT 24
Peak memory 203560 kb
Host smart-229a18b6-afcc-471c-85d0-eae54202cde2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866848449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1866848449
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3301189572
Short name T1394
Test name
Test status
Simulation time 43921470 ps
CPU time 0.63 seconds
Started Apr 18 02:23:59 PM PDT 24
Finished Apr 18 02:24:00 PM PDT 24
Peak memory 203420 kb
Host smart-c34c5843-b4bf-4c7f-8fee-6ce58f0a2709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301189572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3301189572
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1963297822
Short name T1421
Test name
Test status
Simulation time 183797033 ps
CPU time 1.12 seconds
Started Apr 18 02:23:59 PM PDT 24
Finished Apr 18 02:24:01 PM PDT 24
Peak memory 203764 kb
Host smart-ca758cb1-eca6-4c8d-8fa8-3b7ecdceed43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963297822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1963297822
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2962391209
Short name T1439
Test name
Test status
Simulation time 68805157 ps
CPU time 1.4 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:03 PM PDT 24
Peak memory 203772 kb
Host smart-c856a1d6-8825-4fca-aeb3-e251d23eb4bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962391209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2962391209
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.806358194
Short name T140
Test name
Test status
Simulation time 542376924 ps
CPU time 2.45 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:04 PM PDT 24
Peak memory 204000 kb
Host smart-23a0ef33-787b-402a-8437-ea2697445cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806358194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.806358194
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3056185196
Short name T1449
Test name
Test status
Simulation time 41053113 ps
CPU time 0.82 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:02 PM PDT 24
Peak memory 203560 kb
Host smart-04475335-3be9-4135-919b-cea390671945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056185196 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3056185196
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3684990888
Short name T169
Test name
Test status
Simulation time 51271686 ps
CPU time 0.76 seconds
Started Apr 18 02:24:00 PM PDT 24
Finished Apr 18 02:24:02 PM PDT 24
Peak memory 203520 kb
Host smart-e77371d3-f7f2-4879-8198-429fa4c42601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684990888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3684990888
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3875096965
Short name T1458
Test name
Test status
Simulation time 99687819 ps
CPU time 0.66 seconds
Started Apr 18 02:24:04 PM PDT 24
Finished Apr 18 02:24:05 PM PDT 24
Peak memory 203452 kb
Host smart-feb38f05-b40b-49f6-86dc-f84311d78f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875096965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3875096965
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1169442464
Short name T1391
Test name
Test status
Simulation time 143824876 ps
CPU time 0.87 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:03 PM PDT 24
Peak memory 203512 kb
Host smart-d2a3fbdd-5fdd-449f-989c-e5e934ca7f1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169442464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1169442464
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1033019871
Short name T1427
Test name
Test status
Simulation time 160332387 ps
CPU time 2.08 seconds
Started Apr 18 02:24:02 PM PDT 24
Finished Apr 18 02:24:04 PM PDT 24
Peak memory 203720 kb
Host smart-88a1b585-4d61-4c6e-827e-0a3d934f8a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033019871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1033019871
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3944019102
Short name T127
Test name
Test status
Simulation time 81037142 ps
CPU time 1.44 seconds
Started Apr 18 02:24:00 PM PDT 24
Finished Apr 18 02:24:01 PM PDT 24
Peak memory 203860 kb
Host smart-db86abcc-2e2b-4c5c-924e-659b80cff72d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944019102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3944019102
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1139269526
Short name T1390
Test name
Test status
Simulation time 27788514 ps
CPU time 1.12 seconds
Started Apr 18 02:24:06 PM PDT 24
Finished Apr 18 02:24:07 PM PDT 24
Peak memory 203644 kb
Host smart-a83dc5b5-a105-4f7c-a652-3ec37a5afbc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139269526 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1139269526
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1387814838
Short name T1395
Test name
Test status
Simulation time 26747328 ps
CPU time 0.75 seconds
Started Apr 18 02:24:06 PM PDT 24
Finished Apr 18 02:24:07 PM PDT 24
Peak memory 203604 kb
Host smart-e448f38d-9e7d-49f0-85f9-b52e5ff19d83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387814838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1387814838
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1032321738
Short name T1472
Test name
Test status
Simulation time 16816843 ps
CPU time 0.65 seconds
Started Apr 18 02:24:06 PM PDT 24
Finished Apr 18 02:24:07 PM PDT 24
Peak memory 203440 kb
Host smart-16f21e74-dcf2-4aff-8aee-345b5f77aff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032321738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1032321738
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.4263225324
Short name T1466
Test name
Test status
Simulation time 35456220 ps
CPU time 0.84 seconds
Started Apr 18 02:24:07 PM PDT 24
Finished Apr 18 02:24:08 PM PDT 24
Peak memory 203576 kb
Host smart-1ed257ac-3ae4-4e45-9e59-3421f196786e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263225324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.4263225324
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.463878655
Short name T130
Test name
Test status
Simulation time 148816254 ps
CPU time 2.15 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:04 PM PDT 24
Peak memory 203772 kb
Host smart-6ddcf4b3-e06c-4502-950a-0106a53a2657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463878655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.463878655
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3543183085
Short name T198
Test name
Test status
Simulation time 149413600 ps
CPU time 2.35 seconds
Started Apr 18 02:24:01 PM PDT 24
Finished Apr 18 02:24:04 PM PDT 24
Peak memory 203836 kb
Host smart-08a3c398-6a60-48e9-9b7f-e785a582cc7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543183085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3543183085
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1211576735
Short name T1387
Test name
Test status
Simulation time 27352217 ps
CPU time 1.09 seconds
Started Apr 18 02:24:11 PM PDT 24
Finished Apr 18 02:24:13 PM PDT 24
Peak memory 203872 kb
Host smart-4642943e-8a1f-4f5b-8169-77cc561cbb2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211576735 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1211576735
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.341329145
Short name T1384
Test name
Test status
Simulation time 36038956 ps
CPU time 0.75 seconds
Started Apr 18 02:24:11 PM PDT 24
Finished Apr 18 02:24:12 PM PDT 24
Peak memory 203572 kb
Host smart-8d549086-5518-4f86-9a18-35c975e34d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341329145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.341329145
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3993166015
Short name T1422
Test name
Test status
Simulation time 54664639 ps
CPU time 0.69 seconds
Started Apr 18 02:24:12 PM PDT 24
Finished Apr 18 02:24:13 PM PDT 24
Peak memory 203348 kb
Host smart-7bccc082-bd6f-4791-a244-2feb76ae781a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993166015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3993166015
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4031265002
Short name T166
Test name
Test status
Simulation time 38203229 ps
CPU time 0.93 seconds
Started Apr 18 02:24:13 PM PDT 24
Finished Apr 18 02:24:14 PM PDT 24
Peak memory 203512 kb
Host smart-e64615a2-f5fd-4909-a198-1abbab2d9ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031265002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.4031265002
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.661608927
Short name T131
Test name
Test status
Simulation time 44017018 ps
CPU time 1.14 seconds
Started Apr 18 02:24:05 PM PDT 24
Finished Apr 18 02:24:07 PM PDT 24
Peak memory 203776 kb
Host smart-e564330e-d0f4-4ecd-ba24-b8c1b50e44b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661608927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.661608927
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2598127606
Short name T108
Test name
Test status
Simulation time 92671471 ps
CPU time 1.37 seconds
Started Apr 18 02:24:07 PM PDT 24
Finished Apr 18 02:24:09 PM PDT 24
Peak memory 203764 kb
Host smart-bfb6ed68-dca4-43c8-85d1-d87ff71117d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598127606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2598127606
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3678420561
Short name T1409
Test name
Test status
Simulation time 121555006 ps
CPU time 0.97 seconds
Started Apr 18 02:24:17 PM PDT 24
Finished Apr 18 02:24:19 PM PDT 24
Peak memory 203556 kb
Host smart-357087c3-71ed-4e1a-b0af-4cfaddc06ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678420561 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3678420561
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1660500329
Short name T157
Test name
Test status
Simulation time 61631075 ps
CPU time 0.69 seconds
Started Apr 18 02:24:10 PM PDT 24
Finished Apr 18 02:24:11 PM PDT 24
Peak memory 203536 kb
Host smart-097e3499-ad3c-4840-887b-e6e69092c343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660500329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1660500329
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1679471780
Short name T1446
Test name
Test status
Simulation time 35469380 ps
CPU time 0.66 seconds
Started Apr 18 02:24:13 PM PDT 24
Finished Apr 18 02:24:14 PM PDT 24
Peak memory 203128 kb
Host smart-756ab53c-e3b9-4178-a440-fa67634800e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679471780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1679471780
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1140261502
Short name T163
Test name
Test status
Simulation time 59492097 ps
CPU time 0.86 seconds
Started Apr 18 02:24:12 PM PDT 24
Finished Apr 18 02:24:14 PM PDT 24
Peak memory 203532 kb
Host smart-ec29ff77-003b-4c0f-9058-e84bfa9e80f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140261502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1140261502
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3010571093
Short name T1468
Test name
Test status
Simulation time 51377171 ps
CPU time 1.31 seconds
Started Apr 18 02:24:11 PM PDT 24
Finished Apr 18 02:24:13 PM PDT 24
Peak memory 203840 kb
Host smart-86aced8c-477d-4e85-a3de-4ee1a7de797f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010571093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3010571093
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3516185931
Short name T1426
Test name
Test status
Simulation time 295414896 ps
CPU time 1.38 seconds
Started Apr 18 02:24:18 PM PDT 24
Finished Apr 18 02:24:19 PM PDT 24
Peak memory 203804 kb
Host smart-5f9a3fe8-9604-4539-ab2c-33795643a126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516185931 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3516185931
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3973427343
Short name T1388
Test name
Test status
Simulation time 17807227 ps
CPU time 0.68 seconds
Started Apr 18 02:24:14 PM PDT 24
Finished Apr 18 02:24:15 PM PDT 24
Peak memory 203432 kb
Host smart-46b6aec6-a498-426f-a276-710929af8c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973427343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3973427343
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.4237738598
Short name T1401
Test name
Test status
Simulation time 35123826 ps
CPU time 0.65 seconds
Started Apr 18 02:24:19 PM PDT 24
Finished Apr 18 02:24:20 PM PDT 24
Peak memory 203468 kb
Host smart-484ac6aa-a3f3-42be-884e-14bc5375e487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237738598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.4237738598
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1953679179
Short name T76
Test name
Test status
Simulation time 24439154 ps
CPU time 0.89 seconds
Started Apr 18 02:24:16 PM PDT 24
Finished Apr 18 02:24:17 PM PDT 24
Peak memory 203560 kb
Host smart-912807c4-5b2e-43f7-98a4-24ba806b005d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953679179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1953679179
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2669428330
Short name T122
Test name
Test status
Simulation time 32507558 ps
CPU time 1 seconds
Started Apr 18 02:24:17 PM PDT 24
Finished Apr 18 02:24:18 PM PDT 24
Peak memory 203516 kb
Host smart-c3a023eb-ba27-4780-b8e3-8255aa01c9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669428330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2669428330
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2721725269
Short name T1470
Test name
Test status
Simulation time 34346818 ps
CPU time 0.94 seconds
Started Apr 18 02:24:20 PM PDT 24
Finished Apr 18 02:24:22 PM PDT 24
Peak memory 203564 kb
Host smart-327108b2-515b-456e-b16f-92ef27530788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721725269 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2721725269
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1487996616
Short name T146
Test name
Test status
Simulation time 26682659 ps
CPU time 0.77 seconds
Started Apr 18 02:24:19 PM PDT 24
Finished Apr 18 02:24:20 PM PDT 24
Peak memory 203552 kb
Host smart-c6bdff42-e9ae-48f7-a85d-025ff6b3b287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487996616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1487996616
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3185829345
Short name T1443
Test name
Test status
Simulation time 35885096 ps
CPU time 0.65 seconds
Started Apr 18 02:24:16 PM PDT 24
Finished Apr 18 02:24:17 PM PDT 24
Peak memory 203440 kb
Host smart-bd7ef556-ead7-4cfe-9a57-1351a2a9828b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185829345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3185829345
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.315577542
Short name T1379
Test name
Test status
Simulation time 38348519 ps
CPU time 0.85 seconds
Started Apr 18 02:24:16 PM PDT 24
Finished Apr 18 02:24:17 PM PDT 24
Peak memory 203460 kb
Host smart-ba922e5b-8581-4325-b19f-c19d3e5955ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315577542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.315577542
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1905092252
Short name T128
Test name
Test status
Simulation time 118877594 ps
CPU time 1.29 seconds
Started Apr 18 02:24:17 PM PDT 24
Finished Apr 18 02:24:19 PM PDT 24
Peak memory 203740 kb
Host smart-b302f834-4b22-46bb-8673-191a12a9320f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905092252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1905092252
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3437431123
Short name T132
Test name
Test status
Simulation time 253946956 ps
CPU time 2.01 seconds
Started Apr 18 02:24:17 PM PDT 24
Finished Apr 18 02:24:19 PM PDT 24
Peak memory 204052 kb
Host smart-bfd098df-1352-4c74-810c-bb476ccd7371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437431123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3437431123
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3763628914
Short name T154
Test name
Test status
Simulation time 125552241 ps
CPU time 4.93 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:51 PM PDT 24
Peak memory 203812 kb
Host smart-17cbd99a-7b96-41e6-a2aa-df0df8835077
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763628914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3763628914
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1757370408
Short name T144
Test name
Test status
Simulation time 47147927 ps
CPU time 0.64 seconds
Started Apr 18 02:23:48 PM PDT 24
Finished Apr 18 02:23:49 PM PDT 24
Peak memory 203300 kb
Host smart-c5671b0e-6492-4686-8181-3c3019ce71b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757370408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1757370408
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3691428694
Short name T1398
Test name
Test status
Simulation time 82877925 ps
CPU time 1.19 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203784 kb
Host smart-cefd93a2-e139-4e3d-b91b-a43f2797909d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691428694 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3691428694
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1783549382
Short name T1473
Test name
Test status
Simulation time 78360897 ps
CPU time 0.74 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:47 PM PDT 24
Peak memory 203408 kb
Host smart-e690eb7a-70af-48b5-a2f7-5cec9939d10d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783549382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1783549382
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1664539527
Short name T1389
Test name
Test status
Simulation time 52819046 ps
CPU time 0.65 seconds
Started Apr 18 02:23:45 PM PDT 24
Finished Apr 18 02:23:46 PM PDT 24
Peak memory 203432 kb
Host smart-9dcb8841-dc3f-4069-9f0d-baaaf7c397bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664539527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1664539527
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.595595004
Short name T167
Test name
Test status
Simulation time 71418019 ps
CPU time 0.85 seconds
Started Apr 18 02:23:49 PM PDT 24
Finished Apr 18 02:23:50 PM PDT 24
Peak memory 203496 kb
Host smart-482f6655-d17d-49f2-afd4-bcd5fbac28b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595595004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out
standing.595595004
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3319929898
Short name T1442
Test name
Test status
Simulation time 55809794 ps
CPU time 1.43 seconds
Started Apr 18 02:23:45 PM PDT 24
Finished Apr 18 02:23:47 PM PDT 24
Peak memory 203696 kb
Host smart-f46d6c45-c94a-4253-96ec-f2a4f2483442
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319929898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3319929898
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.646631585
Short name T133
Test name
Test status
Simulation time 605861750 ps
CPU time 2.27 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:50 PM PDT 24
Peak memory 203784 kb
Host smart-abbf788c-e765-4986-b2a3-4a858d461e09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646631585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.646631585
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.4127806119
Short name T1419
Test name
Test status
Simulation time 42369101 ps
CPU time 0.66 seconds
Started Apr 18 02:24:16 PM PDT 24
Finished Apr 18 02:24:17 PM PDT 24
Peak memory 203420 kb
Host smart-ac003ecd-e740-4984-bfed-b1ee87ca0e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127806119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.4127806119
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3961137170
Short name T1396
Test name
Test status
Simulation time 19350941 ps
CPU time 0.69 seconds
Started Apr 18 02:24:18 PM PDT 24
Finished Apr 18 02:24:19 PM PDT 24
Peak memory 203404 kb
Host smart-20d51027-b30b-469c-9b5e-aa86f439e563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961137170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3961137170
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.644601903
Short name T1461
Test name
Test status
Simulation time 29052924 ps
CPU time 0.66 seconds
Started Apr 18 02:24:20 PM PDT 24
Finished Apr 18 02:24:22 PM PDT 24
Peak memory 203368 kb
Host smart-80fee7f8-2142-40ad-8fb6-695ef48b1325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644601903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.644601903
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2585396819
Short name T1386
Test name
Test status
Simulation time 47378356 ps
CPU time 0.69 seconds
Started Apr 18 02:24:17 PM PDT 24
Finished Apr 18 02:24:18 PM PDT 24
Peak memory 203388 kb
Host smart-8da79252-65ac-463a-a4d1-fdb06bf3e60d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585396819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2585396819
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.170510532
Short name T1381
Test name
Test status
Simulation time 20955324 ps
CPU time 0.68 seconds
Started Apr 18 02:24:32 PM PDT 24
Finished Apr 18 02:24:33 PM PDT 24
Peak memory 203432 kb
Host smart-5595d66a-cbda-40a4-ba6b-4baed15d47c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170510532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.170510532
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1510815156
Short name T1403
Test name
Test status
Simulation time 34681459 ps
CPU time 0.66 seconds
Started Apr 18 02:24:23 PM PDT 24
Finished Apr 18 02:24:24 PM PDT 24
Peak memory 203040 kb
Host smart-40be941c-e287-4cb6-bc03-fdb507d1ce53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510815156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1510815156
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1452074700
Short name T1465
Test name
Test status
Simulation time 19877885 ps
CPU time 0.64 seconds
Started Apr 18 02:24:22 PM PDT 24
Finished Apr 18 02:24:23 PM PDT 24
Peak memory 203424 kb
Host smart-1484c6d7-a8d7-4c80-90a3-4257d9c43165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452074700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1452074700
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3066379854
Short name T1377
Test name
Test status
Simulation time 35396848 ps
CPU time 0.62 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:24:27 PM PDT 24
Peak memory 203460 kb
Host smart-1239273d-4bd1-4eed-8c48-8ee26297741c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066379854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3066379854
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2331775042
Short name T1416
Test name
Test status
Simulation time 19476937 ps
CPU time 0.62 seconds
Started Apr 18 02:24:24 PM PDT 24
Finished Apr 18 02:24:25 PM PDT 24
Peak memory 203460 kb
Host smart-958e9557-1488-430a-b8c8-cc0cae3de2fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331775042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2331775042
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1832004876
Short name T1475
Test name
Test status
Simulation time 16345172 ps
CPU time 0.67 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:24:26 PM PDT 24
Peak memory 203400 kb
Host smart-a190a5ee-9bee-4aa6-be03-01b1eb634a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832004876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1832004876
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3616132787
Short name T148
Test name
Test status
Simulation time 510707469 ps
CPU time 1.87 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:49 PM PDT 24
Peak memory 203772 kb
Host smart-de519c36-4db6-4548-990f-c8b65f328ec7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616132787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3616132787
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.776261460
Short name T153
Test name
Test status
Simulation time 22042493 ps
CPU time 0.67 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:47 PM PDT 24
Peak memory 203288 kb
Host smart-e5468597-4e2d-41cc-8ba5-ca142dab60d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776261460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.776261460
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3233232322
Short name T1445
Test name
Test status
Simulation time 74630315 ps
CPU time 1.14 seconds
Started Apr 18 02:23:51 PM PDT 24
Finished Apr 18 02:23:52 PM PDT 24
Peak memory 203864 kb
Host smart-4e3c9fad-73c1-454c-aa5b-6a19b46f1f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233232322 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3233232322
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1421472641
Short name T1420
Test name
Test status
Simulation time 22494716 ps
CPU time 0.75 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203560 kb
Host smart-455152e6-fcc0-4b8d-bdb5-9ae66e8adaf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421472641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1421472641
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.476914212
Short name T1411
Test name
Test status
Simulation time 20818967 ps
CPU time 0.62 seconds
Started Apr 18 02:23:44 PM PDT 24
Finished Apr 18 02:23:45 PM PDT 24
Peak memory 203472 kb
Host smart-80f28e05-9cb0-4d9e-8f9a-6d0b218f4a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476914212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.476914212
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.66088786
Short name T74
Test name
Test status
Simulation time 177862903 ps
CPU time 1.09 seconds
Started Apr 18 02:23:47 PM PDT 24
Finished Apr 18 02:23:49 PM PDT 24
Peak memory 203844 kb
Host smart-c762282b-8482-4341-bcf2-5056d72c85ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66088786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outs
tanding.66088786
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2948134678
Short name T1469
Test name
Test status
Simulation time 98385447 ps
CPU time 2.1 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:49 PM PDT 24
Peak memory 203636 kb
Host smart-d3494e32-cd63-4a2b-ba63-53e8679effaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948134678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2948134678
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3136796360
Short name T1417
Test name
Test status
Simulation time 34303161 ps
CPU time 0.67 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:24:27 PM PDT 24
Peak memory 203440 kb
Host smart-0f1275f0-3bb4-4143-ae21-98f7f964d84a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136796360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3136796360
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3610487912
Short name T1440
Test name
Test status
Simulation time 45671893 ps
CPU time 0.68 seconds
Started Apr 18 02:24:20 PM PDT 24
Finished Apr 18 02:24:21 PM PDT 24
Peak memory 203360 kb
Host smart-bda3ce40-6197-4bbc-a881-30254ad17b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610487912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3610487912
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2350907911
Short name T1374
Test name
Test status
Simulation time 129295175 ps
CPU time 0.67 seconds
Started Apr 18 02:24:32 PM PDT 24
Finished Apr 18 02:24:33 PM PDT 24
Peak memory 203436 kb
Host smart-3eba2f68-bf2f-451f-8117-cfaf5ff16ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350907911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2350907911
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2347359710
Short name T1454
Test name
Test status
Simulation time 49821366 ps
CPU time 0.63 seconds
Started Apr 18 02:24:21 PM PDT 24
Finished Apr 18 02:24:22 PM PDT 24
Peak memory 203140 kb
Host smart-90be8368-052f-46eb-bd31-fbb2324eee3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347359710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2347359710
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.4147173692
Short name T1452
Test name
Test status
Simulation time 15479067 ps
CPU time 0.66 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 203440 kb
Host smart-ce6b74ee-31f9-4d4d-9b0f-267681002767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147173692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4147173692
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.686986847
Short name T1414
Test name
Test status
Simulation time 17239479 ps
CPU time 0.63 seconds
Started Apr 18 02:24:22 PM PDT 24
Finished Apr 18 02:24:23 PM PDT 24
Peak memory 203432 kb
Host smart-951d8be7-4bf6-4b3d-8a4f-46fed7bf299a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686986847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.686986847
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1539685011
Short name T1455
Test name
Test status
Simulation time 27534667 ps
CPU time 0.71 seconds
Started Apr 18 02:24:24 PM PDT 24
Finished Apr 18 02:24:25 PM PDT 24
Peak memory 203432 kb
Host smart-543f1da2-19e6-4de9-bff3-7c4e767fbcc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539685011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1539685011
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2754518706
Short name T1378
Test name
Test status
Simulation time 16401114 ps
CPU time 0.69 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:24:26 PM PDT 24
Peak memory 203444 kb
Host smart-cc3a7579-586b-4562-98f6-4c4e3ebe9e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754518706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2754518706
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2828969636
Short name T1404
Test name
Test status
Simulation time 26502951 ps
CPU time 0.63 seconds
Started Apr 18 02:24:20 PM PDT 24
Finished Apr 18 02:24:21 PM PDT 24
Peak memory 203472 kb
Host smart-84baac1c-8838-4197-819e-ec8a6c66761f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828969636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2828969636
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1312925383
Short name T1467
Test name
Test status
Simulation time 24391306 ps
CPU time 0.65 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:34 PM PDT 24
Peak memory 203436 kb
Host smart-41eab364-3b26-4222-885e-c45f83be5cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312925383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1312925383
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2882125691
Short name T150
Test name
Test status
Simulation time 414710310 ps
CPU time 1.81 seconds
Started Apr 18 02:23:50 PM PDT 24
Finished Apr 18 02:23:52 PM PDT 24
Peak memory 203820 kb
Host smart-9a971f1a-7026-49e7-844f-a1033791a7ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882125691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2882125691
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2313398595
Short name T1428
Test name
Test status
Simulation time 1623292847 ps
CPU time 3.11 seconds
Started Apr 18 02:23:50 PM PDT 24
Finished Apr 18 02:23:53 PM PDT 24
Peak memory 203820 kb
Host smart-0a22aaf3-fc1e-47dd-a3ef-234e7536615d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313398595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2313398595
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.122471378
Short name T149
Test name
Test status
Simulation time 87148962 ps
CPU time 0.75 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203572 kb
Host smart-c8ec8975-570d-4252-97b5-8e0c152e9011
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122471378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.122471378
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.234677351
Short name T123
Test name
Test status
Simulation time 35245186 ps
CPU time 0.92 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:56 PM PDT 24
Peak memory 203512 kb
Host smart-17786935-7c37-4f3c-b1a6-678d18574cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234677351 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.234677351
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.4281866787
Short name T145
Test name
Test status
Simulation time 247050162 ps
CPU time 0.75 seconds
Started Apr 18 02:23:46 PM PDT 24
Finished Apr 18 02:23:47 PM PDT 24
Peak memory 203480 kb
Host smart-55bb93c3-7fa6-4241-9b30-b96099e467d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281866787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.4281866787
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.135128485
Short name T1397
Test name
Test status
Simulation time 25705615 ps
CPU time 0.7 seconds
Started Apr 18 02:23:45 PM PDT 24
Finished Apr 18 02:23:47 PM PDT 24
Peak memory 203452 kb
Host smart-3e9f2edd-242f-4ab4-920d-652969df7ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135128485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.135128485
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2057789939
Short name T160
Test name
Test status
Simulation time 31944908 ps
CPU time 0.89 seconds
Started Apr 18 02:23:52 PM PDT 24
Finished Apr 18 02:23:54 PM PDT 24
Peak memory 203628 kb
Host smart-24ffbbb6-53c2-48bd-88db-637abbb4a17d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057789939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2057789939
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1982945051
Short name T1433
Test name
Test status
Simulation time 436474944 ps
CPU time 2.61 seconds
Started Apr 18 02:23:47 PM PDT 24
Finished Apr 18 02:23:50 PM PDT 24
Peak memory 203664 kb
Host smart-2d5672fc-330c-4c8c-8ec3-2a2657b537f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982945051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1982945051
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4255129278
Short name T137
Test name
Test status
Simulation time 290527019 ps
CPU time 2.3 seconds
Started Apr 18 02:23:45 PM PDT 24
Finished Apr 18 02:23:48 PM PDT 24
Peak memory 203764 kb
Host smart-53adfb9d-9b06-4801-a06d-179229747c18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255129278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.4255129278
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3048100697
Short name T1392
Test name
Test status
Simulation time 38133989 ps
CPU time 0.67 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:24:27 PM PDT 24
Peak memory 203444 kb
Host smart-68ab4d23-9d6b-4cee-af17-a3db4d79bf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048100697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3048100697
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3895994403
Short name T1380
Test name
Test status
Simulation time 55612743 ps
CPU time 0.66 seconds
Started Apr 18 02:24:22 PM PDT 24
Finished Apr 18 02:24:23 PM PDT 24
Peak memory 203376 kb
Host smart-fdcf8e47-c21f-4004-8926-532aaf341d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895994403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3895994403
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2261028721
Short name T1476
Test name
Test status
Simulation time 21291103 ps
CPU time 0.65 seconds
Started Apr 18 02:24:21 PM PDT 24
Finished Apr 18 02:24:22 PM PDT 24
Peak memory 203452 kb
Host smart-5830a70a-dad4-40f2-8efa-02e4c8b4bd7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261028721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2261028721
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.871912425
Short name T1410
Test name
Test status
Simulation time 21586698 ps
CPU time 0.64 seconds
Started Apr 18 02:24:20 PM PDT 24
Finished Apr 18 02:24:21 PM PDT 24
Peak memory 203384 kb
Host smart-d3b59a90-8b3f-4c4d-8a1b-5ae65b5114d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871912425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.871912425
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.833715373
Short name T1460
Test name
Test status
Simulation time 16763314 ps
CPU time 0.66 seconds
Started Apr 18 02:24:32 PM PDT 24
Finished Apr 18 02:24:34 PM PDT 24
Peak memory 203436 kb
Host smart-0f3a8182-0f5f-48ff-a6e6-50b9bd971a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833715373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.833715373
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.4213676491
Short name T1383
Test name
Test status
Simulation time 58452820 ps
CPU time 0.67 seconds
Started Apr 18 02:24:23 PM PDT 24
Finished Apr 18 02:24:24 PM PDT 24
Peak memory 203432 kb
Host smart-592d4765-12ab-4f86-913a-13fd41dd4aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213676491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.4213676491
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3358452353
Short name T1402
Test name
Test status
Simulation time 56142849 ps
CPU time 0.63 seconds
Started Apr 18 02:24:31 PM PDT 24
Finished Apr 18 02:24:33 PM PDT 24
Peak memory 203436 kb
Host smart-5ea5813b-8719-41db-aec7-63b15a46b954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358452353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3358452353
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3043697281
Short name T1432
Test name
Test status
Simulation time 35586208 ps
CPU time 0.63 seconds
Started Apr 18 02:24:26 PM PDT 24
Finished Apr 18 02:24:27 PM PDT 24
Peak memory 203424 kb
Host smart-10e5439f-2773-454c-96b5-e6264b9ca44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043697281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3043697281
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.4261895637
Short name T1399
Test name
Test status
Simulation time 40472361 ps
CPU time 0.65 seconds
Started Apr 18 02:24:22 PM PDT 24
Finished Apr 18 02:24:23 PM PDT 24
Peak memory 203380 kb
Host smart-6e2dde07-442b-4a79-81ec-b2e908e7f707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261895637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.4261895637
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2629796781
Short name T1407
Test name
Test status
Simulation time 14899449 ps
CPU time 0.69 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:34 PM PDT 24
Peak memory 203436 kb
Host smart-1e051408-33d3-413b-8ed0-8b9bc3759b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629796781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2629796781
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1502088230
Short name T143
Test name
Test status
Simulation time 28986066 ps
CPU time 0.79 seconds
Started Apr 18 02:23:53 PM PDT 24
Finished Apr 18 02:23:54 PM PDT 24
Peak memory 203548 kb
Host smart-367582ec-b95f-4b35-8535-861fc28d07b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502088230 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1502088230
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1503142818
Short name T1437
Test name
Test status
Simulation time 18223402 ps
CPU time 0.65 seconds
Started Apr 18 02:23:53 PM PDT 24
Finished Apr 18 02:23:54 PM PDT 24
Peak memory 203428 kb
Host smart-91326378-1320-46bf-bc86-6f23477a6612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503142818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1503142818
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2318927575
Short name T159
Test name
Test status
Simulation time 135030396 ps
CPU time 0.87 seconds
Started Apr 18 02:23:49 PM PDT 24
Finished Apr 18 02:23:51 PM PDT 24
Peak memory 203544 kb
Host smart-b89ad8ce-59ea-410c-bad7-1116e8dce91a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318927575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2318927575
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.613784949
Short name T1436
Test name
Test status
Simulation time 105208097 ps
CPU time 2.25 seconds
Started Apr 18 02:23:50 PM PDT 24
Finished Apr 18 02:23:53 PM PDT 24
Peak memory 203744 kb
Host smart-11b4a84a-8844-474d-9354-9a8d954d8777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613784949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.613784949
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3580441416
Short name T124
Test name
Test status
Simulation time 128319752 ps
CPU time 2.21 seconds
Started Apr 18 02:23:54 PM PDT 24
Finished Apr 18 02:23:57 PM PDT 24
Peak memory 203764 kb
Host smart-197e8be6-1288-4ce1-b898-e2eb66936572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580441416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3580441416
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3009121687
Short name T1393
Test name
Test status
Simulation time 33375741 ps
CPU time 0.87 seconds
Started Apr 18 02:23:49 PM PDT 24
Finished Apr 18 02:23:50 PM PDT 24
Peak memory 203652 kb
Host smart-14c1a9ea-7e69-46ec-8dc8-4d184deddce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009121687 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3009121687
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4022946086
Short name T147
Test name
Test status
Simulation time 43424791 ps
CPU time 0.75 seconds
Started Apr 18 02:23:53 PM PDT 24
Finished Apr 18 02:23:55 PM PDT 24
Peak memory 203624 kb
Host smart-901b2a3a-8179-4eb0-babf-5846eeb66c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022946086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.4022946086
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.4270456590
Short name T1375
Test name
Test status
Simulation time 53855020 ps
CPU time 0.68 seconds
Started Apr 18 02:23:51 PM PDT 24
Finished Apr 18 02:23:52 PM PDT 24
Peak memory 203440 kb
Host smart-070f0e3c-d61e-4762-a8f3-664b691a37bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270456590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.4270456590
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1628335579
Short name T1408
Test name
Test status
Simulation time 233596120 ps
CPU time 0.81 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:57 PM PDT 24
Peak memory 203560 kb
Host smart-dc9ea48b-ee83-4351-a605-aad7f0b47eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628335579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1628335579
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4190914487
Short name T1430
Test name
Test status
Simulation time 135498201 ps
CPU time 1.75 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203656 kb
Host smart-79742823-6c2e-4156-9f3c-2ab3524f8693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190914487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.4190914487
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4088529725
Short name T1406
Test name
Test status
Simulation time 126734821 ps
CPU time 1.42 seconds
Started Apr 18 02:23:53 PM PDT 24
Finished Apr 18 02:23:55 PM PDT 24
Peak memory 203868 kb
Host smart-806f4466-007b-4584-9d7b-d2a8cb380973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088529725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4088529725
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2424415951
Short name T1438
Test name
Test status
Simulation time 67491368 ps
CPU time 0.92 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203528 kb
Host smart-78a0e2f6-db5f-44fc-95bd-32b5dae1f65d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424415951 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2424415951
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1448009101
Short name T1441
Test name
Test status
Simulation time 107526922 ps
CPU time 0.77 seconds
Started Apr 18 02:23:54 PM PDT 24
Finished Apr 18 02:23:56 PM PDT 24
Peak memory 203532 kb
Host smart-305556d4-594c-445f-b2cf-516b7b4a2afc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448009101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1448009101
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1972457799
Short name T1412
Test name
Test status
Simulation time 16646047 ps
CPU time 0.65 seconds
Started Apr 18 02:23:50 PM PDT 24
Finished Apr 18 02:23:51 PM PDT 24
Peak memory 203448 kb
Host smart-c37beafa-21ed-4749-af89-79d66686ea58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972457799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1972457799
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1777117809
Short name T75
Test name
Test status
Simulation time 175093350 ps
CPU time 1.1 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:57 PM PDT 24
Peak memory 203784 kb
Host smart-632c2458-8a68-475d-bb01-0839d8cd99bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777117809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1777117809
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3819136314
Short name T106
Test name
Test status
Simulation time 121788347 ps
CPU time 1.57 seconds
Started Apr 18 02:23:50 PM PDT 24
Finished Apr 18 02:23:52 PM PDT 24
Peak memory 203756 kb
Host smart-5a8262df-2d1b-4cf5-ba6d-579aafbd9e16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819136314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3819136314
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2972463692
Short name T1423
Test name
Test status
Simulation time 255901065 ps
CPU time 1.55 seconds
Started Apr 18 02:24:20 PM PDT 24
Finished Apr 18 02:24:23 PM PDT 24
Peak memory 203764 kb
Host smart-66ec877f-b81b-4b4c-a1f3-93a084a22fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972463692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2972463692
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4015013230
Short name T142
Test name
Test status
Simulation time 166261122 ps
CPU time 0.92 seconds
Started Apr 18 02:23:51 PM PDT 24
Finished Apr 18 02:23:53 PM PDT 24
Peak memory 203564 kb
Host smart-8c7ee86c-b3fb-49ce-bdf8-e0dd7f91c284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015013230 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.4015013230
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.983977484
Short name T158
Test name
Test status
Simulation time 37586688 ps
CPU time 0.74 seconds
Started Apr 18 02:23:56 PM PDT 24
Finished Apr 18 02:23:57 PM PDT 24
Peak memory 203452 kb
Host smart-004f9bfa-adb9-4422-9b3f-5dac56a7ce18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983977484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.983977484
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.2581859077
Short name T1450
Test name
Test status
Simulation time 15508916 ps
CPU time 0.7 seconds
Started Apr 18 02:23:51 PM PDT 24
Finished Apr 18 02:23:52 PM PDT 24
Peak memory 203448 kb
Host smart-eeac52f2-c65c-4541-ae5a-52e78b32d308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581859077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2581859077
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3244413688
Short name T1474
Test name
Test status
Simulation time 559963015 ps
CPU time 2.66 seconds
Started Apr 18 02:23:51 PM PDT 24
Finished Apr 18 02:23:54 PM PDT 24
Peak memory 203716 kb
Host smart-b3bae254-96be-4f08-83d1-a5c72705615c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244413688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3244413688
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3763880510
Short name T135
Test name
Test status
Simulation time 119674950 ps
CPU time 1.48 seconds
Started Apr 18 02:23:52 PM PDT 24
Finished Apr 18 02:23:54 PM PDT 24
Peak memory 203768 kb
Host smart-f572d571-723f-4a75-9008-7e987c1d563a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763880510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3763880510
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.592746876
Short name T1464
Test name
Test status
Simulation time 41046754 ps
CPU time 1 seconds
Started Apr 18 02:23:57 PM PDT 24
Finished Apr 18 02:23:58 PM PDT 24
Peak memory 203604 kb
Host smart-0401ed72-b0fa-434c-8bfa-b505148e2c51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592746876 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.592746876
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2835303207
Short name T155
Test name
Test status
Simulation time 15415610 ps
CPU time 0.68 seconds
Started Apr 18 02:23:57 PM PDT 24
Finished Apr 18 02:23:59 PM PDT 24
Peak memory 203580 kb
Host smart-397dc184-8cd1-42fb-809b-3b26505cec5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835303207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2835303207
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.76338946
Short name T1457
Test name
Test status
Simulation time 17179913 ps
CPU time 0.66 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:56 PM PDT 24
Peak memory 203436 kb
Host smart-0db3d316-8203-494a-95a6-b46fe76a7dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76338946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.76338946
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3575765439
Short name T1453
Test name
Test status
Simulation time 154937279 ps
CPU time 0.85 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:56 PM PDT 24
Peak memory 203552 kb
Host smart-306465a6-65bb-4d0b-b426-858d48515dcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575765439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3575765439
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.425492387
Short name T1463
Test name
Test status
Simulation time 130336838 ps
CPU time 1.52 seconds
Started Apr 18 02:23:55 PM PDT 24
Finished Apr 18 02:23:57 PM PDT 24
Peak memory 203640 kb
Host smart-4ada4445-05cd-4f20-8901-4d93cc479bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425492387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.425492387
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3112226293
Short name T1358
Test name
Test status
Simulation time 51877735 ps
CPU time 0.6 seconds
Started Apr 18 03:03:51 PM PDT 24
Finished Apr 18 03:03:52 PM PDT 24
Peak memory 203552 kb
Host smart-d8fb4b13-bdc0-4829-93e8-eac1a6c899a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112226293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3112226293
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2079514626
Short name T514
Test name
Test status
Simulation time 989696479 ps
CPU time 1.75 seconds
Started Apr 18 03:03:14 PM PDT 24
Finished Apr 18 03:03:17 PM PDT 24
Peak memory 212340 kb
Host smart-dbe1a1bf-7d13-4959-a012-ac45f7504241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079514626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2079514626
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.464703615
Short name T1117
Test name
Test status
Simulation time 1569628874 ps
CPU time 4.66 seconds
Started Apr 18 03:02:56 PM PDT 24
Finished Apr 18 03:03:01 PM PDT 24
Peak memory 231680 kb
Host smart-acabe331-4925-43d5-9861-1ca31b3b2573
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464703615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.464703615
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2750312219
Short name T574
Test name
Test status
Simulation time 1960211849 ps
CPU time 66.63 seconds
Started Apr 18 03:02:55 PM PDT 24
Finished Apr 18 03:04:02 PM PDT 24
Peak memory 662496 kb
Host smart-cb4cf343-1747-4640-bc3b-bd095bad6a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750312219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2750312219
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3832643907
Short name T990
Test name
Test status
Simulation time 716962448 ps
CPU time 0.85 seconds
Started Apr 18 03:03:01 PM PDT 24
Finished Apr 18 03:03:02 PM PDT 24
Peak memory 203720 kb
Host smart-e988fe38-50be-44da-8900-727410fca50e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832643907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3832643907
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2695671991
Short name T282
Test name
Test status
Simulation time 189639459 ps
CPU time 9.69 seconds
Started Apr 18 03:03:03 PM PDT 24
Finished Apr 18 03:03:13 PM PDT 24
Peak memory 203952 kb
Host smart-bd312d2c-2721-47b4-a08b-c15e85958b61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695671991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2695671991
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2202090129
Short name T450
Test name
Test status
Simulation time 6774452730 ps
CPU time 271.86 seconds
Started Apr 18 03:02:56 PM PDT 24
Finished Apr 18 03:07:28 PM PDT 24
Peak memory 1056048 kb
Host smart-98985195-3ced-4476-90b6-146e380057fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202090129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2202090129
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.4285061905
Short name T817
Test name
Test status
Simulation time 5865618194 ps
CPU time 8.34 seconds
Started Apr 18 03:03:50 PM PDT 24
Finished Apr 18 03:03:59 PM PDT 24
Peak memory 203996 kb
Host smart-8d57a54a-8690-45fa-9329-c44a8ff5d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285061905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.4285061905
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1349466976
Short name T930
Test name
Test status
Simulation time 6324239722 ps
CPU time 72.04 seconds
Started Apr 18 03:03:52 PM PDT 24
Finished Apr 18 03:05:04 PM PDT 24
Peak memory 292876 kb
Host smart-05934667-c892-4aa4-9eaf-8439a153ea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349466976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1349466976
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3406158692
Short name T188
Test name
Test status
Simulation time 20624056 ps
CPU time 0.66 seconds
Started Apr 18 03:02:52 PM PDT 24
Finished Apr 18 03:02:52 PM PDT 24
Peak memory 203644 kb
Host smart-b31a9600-67fb-4dda-9aad-202f8f21f469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406158692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3406158692
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.532955131
Short name T1140
Test name
Test status
Simulation time 7120137030 ps
CPU time 101.19 seconds
Started Apr 18 03:03:08 PM PDT 24
Finished Apr 18 03:04:49 PM PDT 24
Peak memory 898760 kb
Host smart-907e8aad-782f-4617-be30-fbb2030b4c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532955131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.532955131
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.795925130
Short name T1246
Test name
Test status
Simulation time 3382466662 ps
CPU time 13.61 seconds
Started Apr 18 03:02:46 PM PDT 24
Finished Apr 18 03:03:00 PM PDT 24
Peak memory 284868 kb
Host smart-4f3245c4-ba1f-41ed-9037-b06cfe442332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795925130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.795925130
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2427081890
Short name T740
Test name
Test status
Simulation time 4583644065 ps
CPU time 357.61 seconds
Started Apr 18 03:03:15 PM PDT 24
Finished Apr 18 03:09:13 PM PDT 24
Peak memory 1122904 kb
Host smart-0d5dfebc-8315-476f-bbfc-54aca7edaf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427081890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2427081890
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1024060371
Short name T228
Test name
Test status
Simulation time 3973799144 ps
CPU time 41.88 seconds
Started Apr 18 03:03:08 PM PDT 24
Finished Apr 18 03:03:50 PM PDT 24
Peak memory 215052 kb
Host smart-73dc18d5-d6c4-4005-9e0b-d61f3e1a8d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024060371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1024060371
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1403869801
Short name T113
Test name
Test status
Simulation time 244251461 ps
CPU time 0.93 seconds
Started Apr 18 03:03:49 PM PDT 24
Finished Apr 18 03:03:50 PM PDT 24
Peak memory 222144 kb
Host smart-56b241de-ddd2-4808-b79f-1a08050bb921
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403869801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1403869801
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.33947
Short name T468
Test name
Test status
Simulation time 9412430421 ps
CPU time 3.62 seconds
Started Apr 18 03:03:43 PM PDT 24
Finished Apr 18 03:03:46 PM PDT 24
Peak memory 204072 kb
Host smart-90446eef-b37c-4837-8c20-48b463a96870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33947 -assert nopostproc +UVM_T
ESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.i2c_target_bad_addr.33947
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2303987998
Short name T881
Test name
Test status
Simulation time 10441375583 ps
CPU time 9.72 seconds
Started Apr 18 03:03:35 PM PDT 24
Finished Apr 18 03:03:45 PM PDT 24
Peak memory 260228 kb
Host smart-37e6f922-1279-4593-b9e4-17e714249fed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303987998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2303987998
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2394624631
Short name T22
Test name
Test status
Simulation time 2053223317 ps
CPU time 9.41 seconds
Started Apr 18 03:03:21 PM PDT 24
Finished Apr 18 03:03:31 PM PDT 24
Peak memory 204180 kb
Host smart-41367cc3-8b3c-466a-88fe-ec55b7868bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394624631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2394624631
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.255439604
Short name T1016
Test name
Test status
Simulation time 1847496764 ps
CPU time 2.59 seconds
Started Apr 18 03:03:46 PM PDT 24
Finished Apr 18 03:03:49 PM PDT 24
Peak memory 203984 kb
Host smart-f3a81f83-6961-47a9-b414-f0417db8f5a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255439604 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.255439604
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3494128322
Short name T300
Test name
Test status
Simulation time 1038208709 ps
CPU time 5.45 seconds
Started Apr 18 03:03:30 PM PDT 24
Finished Apr 18 03:03:35 PM PDT 24
Peak memory 211024 kb
Host smart-932f3b90-a3d9-499f-94b5-b5ffbf460dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494128322 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3494128322
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.2646495954
Short name T284
Test name
Test status
Simulation time 19131970345 ps
CPU time 319 seconds
Started Apr 18 03:03:38 PM PDT 24
Finished Apr 18 03:08:57 PM PDT 24
Peak memory 3059052 kb
Host smart-ece27d9d-34e5-420d-b53f-24bfa018768d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646495954 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.2646495954
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.688218677
Short name T483
Test name
Test status
Simulation time 1317608564 ps
CPU time 16.2 seconds
Started Apr 18 03:03:31 PM PDT 24
Finished Apr 18 03:03:48 PM PDT 24
Peak memory 204000 kb
Host smart-7eed7aa9-6d66-4ce7-8d15-aa3ab488c322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688218677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.688218677
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.188735734
Short name T1295
Test name
Test status
Simulation time 740360668 ps
CPU time 11.48 seconds
Started Apr 18 03:03:30 PM PDT 24
Finished Apr 18 03:03:42 PM PDT 24
Peak memory 211104 kb
Host smart-c50d0baa-ea88-4520-be61-c42794f832f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188735734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.188735734
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1566021090
Short name T459
Test name
Test status
Simulation time 28442066076 ps
CPU time 38.35 seconds
Started Apr 18 03:03:30 PM PDT 24
Finished Apr 18 03:04:09 PM PDT 24
Peak memory 740772 kb
Host smart-a0d90f94-e0a8-4cad-acf8-e505502ecee7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566021090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1566021090
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1531125728
Short name T987
Test name
Test status
Simulation time 36710013574 ps
CPU time 336.15 seconds
Started Apr 18 03:03:30 PM PDT 24
Finished Apr 18 03:09:07 PM PDT 24
Peak memory 2175900 kb
Host smart-5c5603b4-466e-4f37-96cc-e0d58be7b3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531125728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1531125728
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2709682549
Short name T522
Test name
Test status
Simulation time 3901418096 ps
CPU time 6.4 seconds
Started Apr 18 03:03:35 PM PDT 24
Finished Apr 18 03:03:42 PM PDT 24
Peak memory 220692 kb
Host smart-346adf96-bc08-47ef-a395-ae8b4c396413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709682549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2709682549
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.356222630
Short name T941
Test name
Test status
Simulation time 40966146 ps
CPU time 0.6 seconds
Started Apr 18 03:04:42 PM PDT 24
Finished Apr 18 03:04:43 PM PDT 24
Peak memory 203548 kb
Host smart-876414d0-c0d0-47b8-a027-8f8b170ed5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356222630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.356222630
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1711431070
Short name T1187
Test name
Test status
Simulation time 148439991 ps
CPU time 1.68 seconds
Started Apr 18 03:04:16 PM PDT 24
Finished Apr 18 03:04:18 PM PDT 24
Peak memory 220436 kb
Host smart-bc01a7c8-c540-46c8-bf97-b90b36325a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711431070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1711431070
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2911274050
Short name T1013
Test name
Test status
Simulation time 1286527609 ps
CPU time 7.56 seconds
Started Apr 18 03:04:02 PM PDT 24
Finished Apr 18 03:04:10 PM PDT 24
Peak memory 273012 kb
Host smart-a084ec62-f9d8-4ebf-9361-ae5e1d93f55f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911274050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2911274050
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.4222468042
Short name T100
Test name
Test status
Simulation time 6051155508 ps
CPU time 87.71 seconds
Started Apr 18 03:04:09 PM PDT 24
Finished Apr 18 03:05:37 PM PDT 24
Peak memory 446956 kb
Host smart-c903e816-2c18-4526-a930-d4f53d1f436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222468042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.4222468042
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.593443022
Short name T208
Test name
Test status
Simulation time 140881970 ps
CPU time 1.05 seconds
Started Apr 18 03:03:55 PM PDT 24
Finished Apr 18 03:03:56 PM PDT 24
Peak memory 203720 kb
Host smart-126507fc-19b4-4624-ae10-8862384e7b85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593443022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt
.593443022
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.937666812
Short name T356
Test name
Test status
Simulation time 1489608418 ps
CPU time 3.79 seconds
Started Apr 18 03:04:07 PM PDT 24
Finished Apr 18 03:04:11 PM PDT 24
Peak memory 203880 kb
Host smart-bcc7758f-7d04-4f04-984c-392ffdeb3189
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937666812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.937666812
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3357661023
Short name T534
Test name
Test status
Simulation time 3502993857 ps
CPU time 223.77 seconds
Started Apr 18 03:03:56 PM PDT 24
Finished Apr 18 03:07:40 PM PDT 24
Peak memory 1029652 kb
Host smart-4eb910c7-28bf-4567-8b83-2cd20347db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357661023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3357661023
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2875920703
Short name T1328
Test name
Test status
Simulation time 936212341 ps
CPU time 18.26 seconds
Started Apr 18 03:04:34 PM PDT 24
Finished Apr 18 03:04:53 PM PDT 24
Peak memory 203900 kb
Host smart-5781fbbc-ad6e-4e59-b1bc-25e6bbf9472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875920703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2875920703
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3471265020
Short name T600
Test name
Test status
Simulation time 2131612355 ps
CPU time 49.37 seconds
Started Apr 18 03:04:34 PM PDT 24
Finished Apr 18 03:05:24 PM PDT 24
Peak memory 311716 kb
Host smart-9e254177-95e5-4f83-84df-89a6e444d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471265020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3471265020
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3296510827
Short name T694
Test name
Test status
Simulation time 18087569 ps
CPU time 0.64 seconds
Started Apr 18 03:04:00 PM PDT 24
Finished Apr 18 03:04:01 PM PDT 24
Peak memory 203692 kb
Host smart-18f970b9-aa47-4941-9c12-a0cfd4468ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296510827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3296510827
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.889885957
Short name T1354
Test name
Test status
Simulation time 7178151609 ps
CPU time 20.36 seconds
Started Apr 18 03:04:15 PM PDT 24
Finished Apr 18 03:04:36 PM PDT 24
Peak memory 248116 kb
Host smart-ad2ee39c-4b5a-489f-9c15-4bed62b3fed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889885957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.889885957
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.4208526546
Short name T451
Test name
Test status
Simulation time 1800858739 ps
CPU time 32.04 seconds
Started Apr 18 03:04:02 PM PDT 24
Finished Apr 18 03:04:34 PM PDT 24
Peak memory 405924 kb
Host smart-d81763ad-e614-44e5-abc5-aca867a8af5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208526546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.4208526546
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.257736685
Short name T1202
Test name
Test status
Simulation time 16515511929 ps
CPU time 432.8 seconds
Started Apr 18 03:04:16 PM PDT 24
Finished Apr 18 03:11:29 PM PDT 24
Peak memory 812036 kb
Host smart-e2fbd984-4a28-413a-82c6-fac6581c4b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257736685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.257736685
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.4096586006
Short name T210
Test name
Test status
Simulation time 997804942 ps
CPU time 9.59 seconds
Started Apr 18 03:04:16 PM PDT 24
Finished Apr 18 03:04:25 PM PDT 24
Peak memory 216564 kb
Host smart-24e3ee13-aa2f-47bb-a3f0-d034eda4d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096586006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.4096586006
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1066881297
Short name T110
Test name
Test status
Simulation time 61520633 ps
CPU time 0.92 seconds
Started Apr 18 03:04:34 PM PDT 24
Finished Apr 18 03:04:35 PM PDT 24
Peak memory 222100 kb
Host smart-2ad56f70-2209-4e77-99c1-68199a14be80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066881297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1066881297
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2584625572
Short name T1299
Test name
Test status
Simulation time 10474256424 ps
CPU time 2.95 seconds
Started Apr 18 03:04:27 PM PDT 24
Finished Apr 18 03:04:31 PM PDT 24
Peak memory 211400 kb
Host smart-e3b37655-06eb-47fe-b700-26e72320ecec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584625572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2584625572
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2257337400
Short name T376
Test name
Test status
Simulation time 10276943391 ps
CPU time 13.2 seconds
Started Apr 18 03:04:28 PM PDT 24
Finished Apr 18 03:04:42 PM PDT 24
Peak memory 308684 kb
Host smart-2b24a919-c9a2-4ee5-abaa-fc8f9c98f921
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257337400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2257337400
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.19472211
Short name T248
Test name
Test status
Simulation time 575027817 ps
CPU time 2.06 seconds
Started Apr 18 03:04:28 PM PDT 24
Finished Apr 18 03:04:31 PM PDT 24
Peak memory 203984 kb
Host smart-5035a17e-20db-4d3d-bd06-fb4458d2ec3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19472211 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.i2c_target_hrst.19472211
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.694375530
Short name T1127
Test name
Test status
Simulation time 682310214 ps
CPU time 3.61 seconds
Started Apr 18 03:04:23 PM PDT 24
Finished Apr 18 03:04:27 PM PDT 24
Peak memory 203928 kb
Host smart-ab8906a2-6cf7-4416-92c6-50b0e56e0394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694375530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.694375530
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2966694402
Short name T920
Test name
Test status
Simulation time 9936160262 ps
CPU time 26.68 seconds
Started Apr 18 03:04:21 PM PDT 24
Finished Apr 18 03:04:48 PM PDT 24
Peak memory 613568 kb
Host smart-38be46e1-a121-47ce-a023-f06c88ba1f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966694402 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2966694402
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1118200094
Short name T432
Test name
Test status
Simulation time 2850481022 ps
CPU time 16.34 seconds
Started Apr 18 03:04:15 PM PDT 24
Finished Apr 18 03:04:32 PM PDT 24
Peak memory 204056 kb
Host smart-fb1694b3-ad89-4f26-9a8a-62fc078775d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118200094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1118200094
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.49164338
Short name T512
Test name
Test status
Simulation time 6859159718 ps
CPU time 53.52 seconds
Started Apr 18 03:04:22 PM PDT 24
Finished Apr 18 03:05:16 PM PDT 24
Peak memory 205480 kb
Host smart-e4cea45d-9b16-4baf-8239-7bb2394749b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49164338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stress_rd.49164338
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1259147289
Short name T322
Test name
Test status
Simulation time 16129413419 ps
CPU time 8.12 seconds
Started Apr 18 03:04:23 PM PDT 24
Finished Apr 18 03:04:32 PM PDT 24
Peak memory 204060 kb
Host smart-e316cb20-cc6d-4c04-a581-cb70facddcb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259147289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1259147289
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3997316411
Short name T685
Test name
Test status
Simulation time 23137786824 ps
CPU time 156.12 seconds
Started Apr 18 03:04:24 PM PDT 24
Finished Apr 18 03:07:01 PM PDT 24
Peak memory 1349716 kb
Host smart-21c0513b-a761-45de-97a0-da3d29dbdd57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997316411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3997316411
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2944306009
Short name T836
Test name
Test status
Simulation time 7788384959 ps
CPU time 6.15 seconds
Started Apr 18 03:04:23 PM PDT 24
Finished Apr 18 03:04:29 PM PDT 24
Peak memory 215008 kb
Host smart-3a023c89-e0b1-431c-b5b9-f7a6195deeac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944306009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2944306009
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.472740164
Short name T1208
Test name
Test status
Simulation time 102063010 ps
CPU time 1.51 seconds
Started Apr 18 03:08:43 PM PDT 24
Finished Apr 18 03:08:45 PM PDT 24
Peak memory 220512 kb
Host smart-7ca3cdb3-0953-4cbe-936e-4be9cefa302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472740164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.472740164
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.575277825
Short name T706
Test name
Test status
Simulation time 950143931 ps
CPU time 10.31 seconds
Started Apr 18 03:08:43 PM PDT 24
Finished Apr 18 03:08:54 PM PDT 24
Peak memory 239780 kb
Host smart-51b15820-015e-4103-9319-947cbe73867e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575277825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.575277825
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1863273282
Short name T724
Test name
Test status
Simulation time 2562431569 ps
CPU time 75.52 seconds
Started Apr 18 03:08:45 PM PDT 24
Finished Apr 18 03:10:01 PM PDT 24
Peak memory 807716 kb
Host smart-a793376a-725c-41aa-985a-d1e827946e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863273282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1863273282
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3357815330
Short name T746
Test name
Test status
Simulation time 4920239971 ps
CPU time 26.26 seconds
Started Apr 18 03:08:39 PM PDT 24
Finished Apr 18 03:09:06 PM PDT 24
Peak memory 423068 kb
Host smart-b21764e3-d125-47e1-89e5-5e4ed3f42532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357815330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3357815330
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2386547397
Short name T642
Test name
Test status
Simulation time 368913237 ps
CPU time 1 seconds
Started Apr 18 03:08:38 PM PDT 24
Finished Apr 18 03:08:39 PM PDT 24
Peak memory 203700 kb
Host smart-aeb89830-f6d0-48d0-b590-c629f24d5089
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386547397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2386547397
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3244533194
Short name T519
Test name
Test status
Simulation time 367926705 ps
CPU time 8.98 seconds
Started Apr 18 03:08:44 PM PDT 24
Finished Apr 18 03:08:53 PM PDT 24
Peak memory 203880 kb
Host smart-f56385da-f400-4bd7-a44b-a388cb5b32c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244533194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3244533194
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3879900540
Short name T835
Test name
Test status
Simulation time 3638201670 ps
CPU time 257.79 seconds
Started Apr 18 03:08:38 PM PDT 24
Finished Apr 18 03:12:56 PM PDT 24
Peak memory 1099616 kb
Host smart-2d85efe7-a37e-4717-8a26-b7ddbd0497d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879900540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3879900540
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2887992545
Short name T1221
Test name
Test status
Simulation time 350678499 ps
CPU time 14.74 seconds
Started Apr 18 03:08:59 PM PDT 24
Finished Apr 18 03:09:14 PM PDT 24
Peak memory 203976 kb
Host smart-6459af66-1b28-4388-93aa-02a62c40ecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887992545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2887992545
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.717389143
Short name T1256
Test name
Test status
Simulation time 1802580870 ps
CPU time 31.63 seconds
Started Apr 18 03:08:53 PM PDT 24
Finished Apr 18 03:09:25 PM PDT 24
Peak memory 334256 kb
Host smart-dec04aee-0333-4a6f-8841-a626b5ef53d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717389143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.717389143
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3174513952
Short name T1099
Test name
Test status
Simulation time 17293001 ps
CPU time 0.63 seconds
Started Apr 18 03:08:38 PM PDT 24
Finished Apr 18 03:08:40 PM PDT 24
Peak memory 203636 kb
Host smart-58c1d077-7ed3-4396-8385-0a20d2bc3f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174513952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3174513952
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3226157177
Short name T85
Test name
Test status
Simulation time 5687296098 ps
CPU time 169.07 seconds
Started Apr 18 03:08:43 PM PDT 24
Finished Apr 18 03:11:32 PM PDT 24
Peak memory 526896 kb
Host smart-de4dfa63-9bb4-46f9-a567-347174f871b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226157177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3226157177
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2839384348
Short name T1027
Test name
Test status
Simulation time 1758127197 ps
CPU time 27.79 seconds
Started Apr 18 03:08:37 PM PDT 24
Finished Apr 18 03:09:06 PM PDT 24
Peak memory 336584 kb
Host smart-aff07960-c12d-477f-bcc3-6b877936d9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839384348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2839384348
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3737735201
Short name T78
Test name
Test status
Simulation time 9818435525 ps
CPU time 265.09 seconds
Started Apr 18 03:08:44 PM PDT 24
Finished Apr 18 03:13:09 PM PDT 24
Peak memory 719928 kb
Host smart-1c6bf975-3482-40b6-a3e0-12ad51a15308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737735201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3737735201
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.633049714
Short name T318
Test name
Test status
Simulation time 3952780677 ps
CPU time 2.56 seconds
Started Apr 18 03:08:54 PM PDT 24
Finished Apr 18 03:08:57 PM PDT 24
Peak memory 204052 kb
Host smart-21f4c042-3d89-4f8c-8798-43dcc39d7feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633049714 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.633049714
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1792593496
Short name T357
Test name
Test status
Simulation time 10505779234 ps
CPU time 12.11 seconds
Started Apr 18 03:08:53 PM PDT 24
Finished Apr 18 03:09:05 PM PDT 24
Peak memory 262404 kb
Host smart-80b01bc8-ca7e-4161-ac6b-e6632459aa10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792593496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1792593496
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1366636517
Short name T332
Test name
Test status
Simulation time 10070513696 ps
CPU time 65.43 seconds
Started Apr 18 03:08:51 PM PDT 24
Finished Apr 18 03:09:56 PM PDT 24
Peak memory 550768 kb
Host smart-d6a13ff2-03e2-4532-be35-c0f18b99035e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366636517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1366636517
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.415652738
Short name T921
Test name
Test status
Simulation time 2125784902 ps
CPU time 2.87 seconds
Started Apr 18 03:08:53 PM PDT 24
Finished Apr 18 03:08:56 PM PDT 24
Peak memory 203976 kb
Host smart-ab024644-738d-43f9-9a6d-83cf26137a7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415652738 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.i2c_target_hrst.415652738
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.3878585577
Short name T708
Test name
Test status
Simulation time 3156966704 ps
CPU time 3.2 seconds
Started Apr 18 03:08:47 PM PDT 24
Finished Apr 18 03:08:50 PM PDT 24
Peak memory 204020 kb
Host smart-30ee202d-575c-44d8-953e-a62a2e463512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878585577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.3878585577
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1068137523
Short name T1210
Test name
Test status
Simulation time 26424221876 ps
CPU time 268.26 seconds
Started Apr 18 03:08:44 PM PDT 24
Finished Apr 18 03:13:13 PM PDT 24
Peak memory 2467108 kb
Host smart-66676e5a-d982-49a5-81c0-b386d01293a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068137523 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1068137523
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2259394893
Short name T1321
Test name
Test status
Simulation time 4525932821 ps
CPU time 44.64 seconds
Started Apr 18 03:08:43 PM PDT 24
Finished Apr 18 03:09:28 PM PDT 24
Peak memory 204028 kb
Host smart-b7719b05-ef96-4b9b-86ce-01db1721497a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259394893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2259394893
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2196712693
Short name T624
Test name
Test status
Simulation time 1960891263 ps
CPU time 17.07 seconds
Started Apr 18 03:08:42 PM PDT 24
Finished Apr 18 03:09:00 PM PDT 24
Peak memory 212252 kb
Host smart-af5a749a-0201-49c4-9b86-c6cd417df3c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196712693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2196712693
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1046606558
Short name T386
Test name
Test status
Simulation time 43307153324 ps
CPU time 99.45 seconds
Started Apr 18 03:08:44 PM PDT 24
Finished Apr 18 03:10:24 PM PDT 24
Peak memory 1526776 kb
Host smart-f6d241d0-7282-4afe-9efc-12b2f645f7a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046606558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1046606558
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3891784613
Short name T1032
Test name
Test status
Simulation time 7258989211 ps
CPU time 79.44 seconds
Started Apr 18 03:08:42 PM PDT 24
Finished Apr 18 03:10:02 PM PDT 24
Peak memory 923152 kb
Host smart-eed0c42d-64c0-4980-a667-5d499980d676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891784613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3891784613
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2963311157
Short name T1287
Test name
Test status
Simulation time 8758712920 ps
CPU time 5.95 seconds
Started Apr 18 03:08:50 PM PDT 24
Finished Apr 18 03:08:56 PM PDT 24
Peak memory 204076 kb
Host smart-d4d99887-029c-4819-ac25-fdeaa29213e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963311157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2963311157
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1883244275
Short name T1161
Test name
Test status
Simulation time 31085357 ps
CPU time 0.59 seconds
Started Apr 18 03:09:24 PM PDT 24
Finished Apr 18 03:09:25 PM PDT 24
Peak memory 203584 kb
Host smart-7efee954-da08-4611-b070-fd1a08dc1ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883244275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1883244275
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.537148506
Short name T1235
Test name
Test status
Simulation time 213511548 ps
CPU time 1.41 seconds
Started Apr 18 03:09:13 PM PDT 24
Finished Apr 18 03:09:15 PM PDT 24
Peak memory 204068 kb
Host smart-1d50893f-6514-45d4-af1f-8e7c39a3bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537148506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.537148506
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1217484015
Short name T1190
Test name
Test status
Simulation time 312714827 ps
CPU time 3.25 seconds
Started Apr 18 03:09:06 PM PDT 24
Finished Apr 18 03:09:10 PM PDT 24
Peak memory 216888 kb
Host smart-789d097a-6446-4d72-bc47-2a8264af7302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217484015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1217484015
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2394848963
Short name T550
Test name
Test status
Simulation time 24215414632 ps
CPU time 142.45 seconds
Started Apr 18 03:09:11 PM PDT 24
Finished Apr 18 03:11:34 PM PDT 24
Peak memory 687824 kb
Host smart-6a9bb7c5-f748-4378-b665-b6fc8adbe2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394848963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2394848963
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.610779281
Short name T872
Test name
Test status
Simulation time 4898193591 ps
CPU time 26.68 seconds
Started Apr 18 03:09:06 PM PDT 24
Finished Apr 18 03:09:33 PM PDT 24
Peak memory 408268 kb
Host smart-3ed6e911-f404-4cae-8912-910379c56beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610779281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.610779281
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1908457193
Short name T1332
Test name
Test status
Simulation time 160180031 ps
CPU time 1.14 seconds
Started Apr 18 03:09:05 PM PDT 24
Finished Apr 18 03:09:06 PM PDT 24
Peak memory 203920 kb
Host smart-c266d44e-c18d-43d3-899e-498607ba0eb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908457193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1908457193
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.590852023
Short name T305
Test name
Test status
Simulation time 1973458455 ps
CPU time 4.18 seconds
Started Apr 18 03:09:10 PM PDT 24
Finished Apr 18 03:09:15 PM PDT 24
Peak memory 203872 kb
Host smart-a381fbb5-db94-48cd-8fee-6285ce831f7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590852023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
590852023
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.221699844
Short name T543
Test name
Test status
Simulation time 2766466038 ps
CPU time 175.93 seconds
Started Apr 18 03:09:05 PM PDT 24
Finished Apr 18 03:12:02 PM PDT 24
Peak memory 863612 kb
Host smart-fc6ee726-1368-40b0-aa1d-2eba8f334f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221699844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.221699844
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.3691796091
Short name T939
Test name
Test status
Simulation time 373448471 ps
CPU time 4.65 seconds
Started Apr 18 03:09:22 PM PDT 24
Finished Apr 18 03:09:27 PM PDT 24
Peak memory 203928 kb
Host smart-7e4b9579-cf4e-4520-9c81-c274f4cc9883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691796091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3691796091
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.2653430870
Short name T1252
Test name
Test status
Simulation time 1761298918 ps
CPU time 29.5 seconds
Started Apr 18 03:09:21 PM PDT 24
Finished Apr 18 03:09:50 PM PDT 24
Peak memory 329388 kb
Host smart-733822aa-c1ae-4b4e-9aa2-8fa233817203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653430870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.2653430870
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2645374711
Short name T38
Test name
Test status
Simulation time 29206377 ps
CPU time 0.72 seconds
Started Apr 18 03:09:00 PM PDT 24
Finished Apr 18 03:09:01 PM PDT 24
Peak memory 203620 kb
Host smart-13dc4f34-f815-4551-bf54-4ba674f9909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645374711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2645374711
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1329718239
Short name T384
Test name
Test status
Simulation time 48010965909 ps
CPU time 903.85 seconds
Started Apr 18 03:09:11 PM PDT 24
Finished Apr 18 03:24:15 PM PDT 24
Peak memory 203804 kb
Host smart-c8232469-e604-40ce-bba5-55e791851085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329718239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1329718239
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3160156052
Short name T752
Test name
Test status
Simulation time 1828786860 ps
CPU time 82.74 seconds
Started Apr 18 03:09:00 PM PDT 24
Finished Apr 18 03:10:24 PM PDT 24
Peak memory 317772 kb
Host smart-fb530f2d-ff3e-4093-9e10-435f85e05d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160156052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3160156052
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.994249141
Short name T46
Test name
Test status
Simulation time 10189120673 ps
CPU time 1163.29 seconds
Started Apr 18 03:09:11 PM PDT 24
Finished Apr 18 03:28:35 PM PDT 24
Peak memory 1816408 kb
Host smart-e51d32a7-87aa-417f-8c56-d611cdea757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994249141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.994249141
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.157443513
Short name T328
Test name
Test status
Simulation time 394824856 ps
CPU time 6.65 seconds
Started Apr 18 03:09:10 PM PDT 24
Finished Apr 18 03:09:17 PM PDT 24
Peak memory 213260 kb
Host smart-53c9c15f-f198-4d52-8a03-e4e2acec03bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157443513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.157443513
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3976613391
Short name T664
Test name
Test status
Simulation time 999055572 ps
CPU time 4.11 seconds
Started Apr 18 03:09:15 PM PDT 24
Finished Apr 18 03:09:20 PM PDT 24
Peak memory 203980 kb
Host smart-04460b98-082a-48b7-b64a-f17a7b6cd1d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976613391 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3976613391
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2800541517
Short name T1296
Test name
Test status
Simulation time 10046953164 ps
CPU time 28.77 seconds
Started Apr 18 03:09:16 PM PDT 24
Finished Apr 18 03:09:45 PM PDT 24
Peak memory 356964 kb
Host smart-321c890f-3824-413e-af51-f554dbbeef6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800541517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2800541517
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2366199628
Short name T590
Test name
Test status
Simulation time 10253143227 ps
CPU time 8.61 seconds
Started Apr 18 03:09:17 PM PDT 24
Finished Apr 18 03:09:25 PM PDT 24
Peak memory 266436 kb
Host smart-8fdc7d60-784d-4e95-8b89-fbaf0067aa39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366199628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2366199628
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.883211625
Short name T1229
Test name
Test status
Simulation time 2266258058 ps
CPU time 2.11 seconds
Started Apr 18 03:09:15 PM PDT 24
Finished Apr 18 03:09:17 PM PDT 24
Peak memory 204076 kb
Host smart-a504faa6-b77a-4456-aa2d-41e34fc1fa53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883211625 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.883211625
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.500998274
Short name T1194
Test name
Test status
Simulation time 919637184 ps
CPU time 4.32 seconds
Started Apr 18 03:09:10 PM PDT 24
Finished Apr 18 03:09:15 PM PDT 24
Peak memory 204028 kb
Host smart-504c5e85-d41f-4756-b40d-f7bb98dc2b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500998274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.500998274
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.926140224
Short name T513
Test name
Test status
Simulation time 15439290127 ps
CPU time 164.62 seconds
Started Apr 18 03:09:15 PM PDT 24
Finished Apr 18 03:12:00 PM PDT 24
Peak memory 2253452 kb
Host smart-bdb070f9-12f7-4375-a4ff-13636e411db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926140224 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.926140224
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3070833465
Short name T35
Test name
Test status
Simulation time 2406985057 ps
CPU time 46.81 seconds
Started Apr 18 03:09:09 PM PDT 24
Finished Apr 18 03:09:57 PM PDT 24
Peak memory 204048 kb
Host smart-97a04085-ab13-409d-bc4f-d122849f208b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070833465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3070833465
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3028657681
Short name T465
Test name
Test status
Simulation time 3734968436 ps
CPU time 14.23 seconds
Started Apr 18 03:09:10 PM PDT 24
Finished Apr 18 03:09:25 PM PDT 24
Peak memory 218596 kb
Host smart-0499c9e4-d306-4af2-86de-81ac87884d3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028657681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3028657681
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.3566571886
Short name T912
Test name
Test status
Simulation time 22815268017 ps
CPU time 25.71 seconds
Started Apr 18 03:09:10 PM PDT 24
Finished Apr 18 03:09:36 PM PDT 24
Peak memory 487740 kb
Host smart-ffbc2e04-b91d-4bee-9ede-28956ab86984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566571886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.3566571886
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1291323747
Short name T1062
Test name
Test status
Simulation time 21340009959 ps
CPU time 636.11 seconds
Started Apr 18 03:09:10 PM PDT 24
Finished Apr 18 03:19:47 PM PDT 24
Peak memory 1786580 kb
Host smart-c99230f2-c814-4d17-8892-a6e622c14462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291323747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1291323747
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.3329499815
Short name T780
Test name
Test status
Simulation time 4712210053 ps
CPU time 5.93 seconds
Started Apr 18 03:09:15 PM PDT 24
Finished Apr 18 03:09:21 PM PDT 24
Peak memory 213584 kb
Host smart-eb53faa9-d699-42fb-878f-3f71a54dbde4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329499815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.3329499815
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.911898889
Short name T993
Test name
Test status
Simulation time 16071490 ps
CPU time 0.63 seconds
Started Apr 18 03:09:45 PM PDT 24
Finished Apr 18 03:09:46 PM PDT 24
Peak memory 203576 kb
Host smart-a7873ba2-0dd3-473e-8cf7-ed1a95203bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911898889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.911898889
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3712925419
Short name T378
Test name
Test status
Simulation time 110723857 ps
CPU time 1.2 seconds
Started Apr 18 03:09:33 PM PDT 24
Finished Apr 18 03:09:35 PM PDT 24
Peak memory 212308 kb
Host smart-49e28cfe-6c42-480c-a50d-2e9a91e631ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712925419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3712925419
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3211195557
Short name T936
Test name
Test status
Simulation time 260081476 ps
CPU time 4.42 seconds
Started Apr 18 03:09:26 PM PDT 24
Finished Apr 18 03:09:31 PM PDT 24
Peak memory 245868 kb
Host smart-f61198c0-50cd-4f8f-a9a9-b88c4ba8baf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211195557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3211195557
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3396584989
Short name T1311
Test name
Test status
Simulation time 2471681397 ps
CPU time 29.82 seconds
Started Apr 18 03:09:34 PM PDT 24
Finished Apr 18 03:10:04 PM PDT 24
Peak memory 213768 kb
Host smart-d689f75c-3d26-4007-8e29-571e6fc4b974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396584989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3396584989
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3459613032
Short name T654
Test name
Test status
Simulation time 2139825867 ps
CPU time 69.69 seconds
Started Apr 18 03:09:25 PM PDT 24
Finished Apr 18 03:10:35 PM PDT 24
Peak memory 438740 kb
Host smart-0323bc0b-c914-4996-9eeb-0cfcf94da113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459613032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3459613032
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2486333648
Short name T697
Test name
Test status
Simulation time 609565351 ps
CPU time 1.17 seconds
Started Apr 18 03:09:26 PM PDT 24
Finished Apr 18 03:09:28 PM PDT 24
Peak memory 203884 kb
Host smart-18e43b2f-7450-450e-8948-8e27b2dab670
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486333648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2486333648
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1841092743
Short name T569
Test name
Test status
Simulation time 3771484812 ps
CPU time 261.87 seconds
Started Apr 18 03:09:25 PM PDT 24
Finished Apr 18 03:13:47 PM PDT 24
Peak memory 1058568 kb
Host smart-d6478461-c39f-4fdf-a652-915720ebdfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841092743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1841092743
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.797499883
Short name T528
Test name
Test status
Simulation time 1106169016 ps
CPU time 10.66 seconds
Started Apr 18 03:09:45 PM PDT 24
Finished Apr 18 03:09:56 PM PDT 24
Peak memory 203960 kb
Host smart-b3c6a915-e9ce-4a77-8168-873a90402e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797499883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.797499883
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1947415905
Short name T448
Test name
Test status
Simulation time 3223660992 ps
CPU time 77.09 seconds
Started Apr 18 03:09:44 PM PDT 24
Finished Apr 18 03:11:01 PM PDT 24
Peak memory 397596 kb
Host smart-ee5b344f-8b87-401b-b95f-5a68af9580be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947415905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1947415905
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.2438458974
Short name T796
Test name
Test status
Simulation time 27944928 ps
CPU time 0.68 seconds
Started Apr 18 03:09:26 PM PDT 24
Finished Apr 18 03:09:26 PM PDT 24
Peak memory 203628 kb
Host smart-9eb58a02-0ec3-48c1-a848-ca2602632ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438458974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2438458974
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2750764431
Short name T1249
Test name
Test status
Simulation time 2796657421 ps
CPU time 13.19 seconds
Started Apr 18 03:09:35 PM PDT 24
Finished Apr 18 03:09:48 PM PDT 24
Peak memory 233364 kb
Host smart-c2e1292a-2f1d-48f0-9ac7-6b286c6f30e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750764431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2750764431
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3626812196
Short name T900
Test name
Test status
Simulation time 2714935835 ps
CPU time 20.63 seconds
Started Apr 18 03:09:25 PM PDT 24
Finished Apr 18 03:09:46 PM PDT 24
Peak memory 309732 kb
Host smart-b0a1299a-2129-4844-980d-81260e488f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626812196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3626812196
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3999408695
Short name T1359
Test name
Test status
Simulation time 2836382672 ps
CPU time 11.26 seconds
Started Apr 18 03:09:33 PM PDT 24
Finished Apr 18 03:09:45 PM PDT 24
Peak memory 220488 kb
Host smart-2d2606e8-2d1c-4005-8020-320021eff274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999408695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3999408695
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1424226258
Short name T731
Test name
Test status
Simulation time 5492234814 ps
CPU time 4.13 seconds
Started Apr 18 03:09:47 PM PDT 24
Finished Apr 18 03:09:52 PM PDT 24
Peak memory 212232 kb
Host smart-34dc2cd0-b0c3-48cd-872f-df012c3c9a98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424226258 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1424226258
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2032566845
Short name T59
Test name
Test status
Simulation time 10101455321 ps
CPU time 72.8 seconds
Started Apr 18 03:09:39 PM PDT 24
Finished Apr 18 03:10:53 PM PDT 24
Peak memory 510716 kb
Host smart-59bd1665-e45f-40d8-aa1e-ea5023683498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032566845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2032566845
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2092002805
Short name T53
Test name
Test status
Simulation time 10075231621 ps
CPU time 30.48 seconds
Started Apr 18 03:09:38 PM PDT 24
Finished Apr 18 03:10:09 PM PDT 24
Peak memory 402416 kb
Host smart-908045b5-4778-4216-b897-9eaa7e991918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092002805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2092002805
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.4198535257
Short name T893
Test name
Test status
Simulation time 3313881847 ps
CPU time 4.18 seconds
Started Apr 18 03:09:39 PM PDT 24
Finished Apr 18 03:09:43 PM PDT 24
Peak memory 204036 kb
Host smart-1acbb53d-00f6-4209-9afc-201617ef5f9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198535257 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.4198535257
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2969527634
Short name T1353
Test name
Test status
Simulation time 22015563843 ps
CPU time 403.21 seconds
Started Apr 18 03:09:40 PM PDT 24
Finished Apr 18 03:16:24 PM PDT 24
Peak memory 3663652 kb
Host smart-cc339977-4bd9-4ccd-9001-98367c2fa092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969527634 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2969527634
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3127809015
Short name T860
Test name
Test status
Simulation time 4189124769 ps
CPU time 14.44 seconds
Started Apr 18 03:09:34 PM PDT 24
Finished Apr 18 03:09:49 PM PDT 24
Peak memory 204060 kb
Host smart-fe7b111f-c084-471d-a39f-9bad56d0b079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127809015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3127809015
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1955979167
Short name T623
Test name
Test status
Simulation time 2102990041 ps
CPU time 43.57 seconds
Started Apr 18 03:09:38 PM PDT 24
Finished Apr 18 03:10:22 PM PDT 24
Peak memory 204352 kb
Host smart-12ff3b5d-d039-40b0-9c73-f72bb29643ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955979167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1955979167
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2608466676
Short name T799
Test name
Test status
Simulation time 49864722731 ps
CPU time 1127.63 seconds
Started Apr 18 03:09:38 PM PDT 24
Finished Apr 18 03:28:26 PM PDT 24
Peak memory 7461416 kb
Host smart-0d8c8715-b51a-4de0-80e5-16ebd5ff7220
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608466676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2608466676
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1067896880
Short name T749
Test name
Test status
Simulation time 15449104445 ps
CPU time 807.81 seconds
Started Apr 18 03:09:38 PM PDT 24
Finished Apr 18 03:23:07 PM PDT 24
Peak memory 3786664 kb
Host smart-45774210-0f8b-4fda-876a-c71d68ef7d81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067896880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1067896880
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2868587059
Short name T498
Test name
Test status
Simulation time 3178480353 ps
CPU time 7.52 seconds
Started Apr 18 03:09:41 PM PDT 24
Finished Apr 18 03:09:49 PM PDT 24
Peak memory 220260 kb
Host smart-5d5efb9d-6c3d-4ebd-a548-c0e818cb0759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868587059 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2868587059
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2724884637
Short name T500
Test name
Test status
Simulation time 57621242 ps
CPU time 0.6 seconds
Started Apr 18 03:10:12 PM PDT 24
Finished Apr 18 03:10:13 PM PDT 24
Peak memory 203532 kb
Host smart-d6aaa408-c952-456f-ac81-d9bd6bdfe381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724884637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2724884637
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1391689717
Short name T968
Test name
Test status
Simulation time 69172297 ps
CPU time 1.21 seconds
Started Apr 18 03:09:55 PM PDT 24
Finished Apr 18 03:09:57 PM PDT 24
Peak memory 212284 kb
Host smart-a1606761-bfd4-48ea-aa60-26c080c0888b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391689717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1391689717
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2189156491
Short name T1259
Test name
Test status
Simulation time 1063497485 ps
CPU time 14.21 seconds
Started Apr 18 03:09:51 PM PDT 24
Finished Apr 18 03:10:06 PM PDT 24
Peak memory 256720 kb
Host smart-ad1703eb-4acd-4df0-99d2-798db445bf2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189156491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2189156491
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.4230287286
Short name T844
Test name
Test status
Simulation time 8358685198 ps
CPU time 81.61 seconds
Started Apr 18 03:09:51 PM PDT 24
Finished Apr 18 03:11:13 PM PDT 24
Peak memory 517520 kb
Host smart-7e0883b0-b726-40ce-99e7-0487eb5abe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230287286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.4230287286
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3104311884
Short name T491
Test name
Test status
Simulation time 4120033777 ps
CPU time 75 seconds
Started Apr 18 03:09:51 PM PDT 24
Finished Apr 18 03:11:06 PM PDT 24
Peak memory 480988 kb
Host smart-4e628425-2f2b-4852-8970-d9820b3dad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104311884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3104311884
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3160597399
Short name T852
Test name
Test status
Simulation time 499552822 ps
CPU time 1 seconds
Started Apr 18 03:09:52 PM PDT 24
Finished Apr 18 03:09:54 PM PDT 24
Peak memory 203896 kb
Host smart-3b003a64-7f2d-499d-8379-6106904418d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160597399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3160597399
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.4056759420
Short name T1003
Test name
Test status
Simulation time 445810023 ps
CPU time 2.97 seconds
Started Apr 18 03:09:55 PM PDT 24
Finished Apr 18 03:09:58 PM PDT 24
Peak memory 203928 kb
Host smart-e248508b-3edb-472f-9203-074dbbd2c5ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056759420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.4056759420
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1897819002
Short name T1273
Test name
Test status
Simulation time 9249324821 ps
CPU time 123.33 seconds
Started Apr 18 03:09:52 PM PDT 24
Finished Apr 18 03:11:56 PM PDT 24
Peak memory 1326980 kb
Host smart-c1bb3186-295a-4a24-9504-10219b0844c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897819002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1897819002
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1668741390
Short name T1313
Test name
Test status
Simulation time 686901467 ps
CPU time 5.32 seconds
Started Apr 18 03:10:10 PM PDT 24
Finished Apr 18 03:10:16 PM PDT 24
Peak memory 203928 kb
Host smart-58082238-af91-451c-9433-3f7069efa4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668741390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1668741390
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.682855186
Short name T1086
Test name
Test status
Simulation time 1715135611 ps
CPU time 80.91 seconds
Started Apr 18 03:10:10 PM PDT 24
Finished Apr 18 03:11:31 PM PDT 24
Peak memory 405956 kb
Host smart-5a2e3be0-b960-4c2a-9fae-1f61c60f0a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682855186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.682855186
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2023985360
Short name T951
Test name
Test status
Simulation time 33797712 ps
CPU time 0.61 seconds
Started Apr 18 03:09:49 PM PDT 24
Finished Apr 18 03:09:50 PM PDT 24
Peak memory 203668 kb
Host smart-1f6148b3-597e-408e-b6c4-74b91fe3669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023985360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2023985360
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2323265849
Short name T1195
Test name
Test status
Simulation time 70399932822 ps
CPU time 248.92 seconds
Started Apr 18 03:09:50 PM PDT 24
Finished Apr 18 03:14:00 PM PDT 24
Peak memory 223144 kb
Host smart-35a3fa34-6c3b-4c7d-ade4-4d391b6ab479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323265849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2323265849
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.4790464
Short name T983
Test name
Test status
Simulation time 1107377220 ps
CPU time 18.96 seconds
Started Apr 18 03:09:52 PM PDT 24
Finished Apr 18 03:10:11 PM PDT 24
Peak memory 316540 kb
Host smart-7b2f21a8-fe02-4d8e-9163-c697c72569e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4790464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.4790464
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.2123715646
Short name T733
Test name
Test status
Simulation time 35249452920 ps
CPU time 872.78 seconds
Started Apr 18 03:09:55 PM PDT 24
Finished Apr 18 03:24:28 PM PDT 24
Peak memory 2294128 kb
Host smart-c11677e8-891a-45e7-a279-d19923da55e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123715646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2123715646
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.4252102634
Short name T1219
Test name
Test status
Simulation time 864227054 ps
CPU time 15.42 seconds
Started Apr 18 03:09:50 PM PDT 24
Finished Apr 18 03:10:06 PM PDT 24
Peak memory 228428 kb
Host smart-5d372901-afbf-4f2b-abc8-81c5d04b6b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252102634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.4252102634
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2690697738
Short name T630
Test name
Test status
Simulation time 4791152877 ps
CPU time 4.66 seconds
Started Apr 18 03:10:11 PM PDT 24
Finished Apr 18 03:10:16 PM PDT 24
Peak memory 212256 kb
Host smart-33ad4433-1832-425f-a648-40e68d050522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690697738 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2690697738
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.717605061
Short name T1305
Test name
Test status
Simulation time 10048237484 ps
CPU time 71.22 seconds
Started Apr 18 03:10:05 PM PDT 24
Finished Apr 18 03:11:16 PM PDT 24
Peak memory 509840 kb
Host smart-2ec4da2c-4fd5-483a-9b2f-c5cdf08e500d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717605061 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.717605061
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3043759163
Short name T342
Test name
Test status
Simulation time 10132940788 ps
CPU time 30.85 seconds
Started Apr 18 03:10:06 PM PDT 24
Finished Apr 18 03:10:37 PM PDT 24
Peak memory 398008 kb
Host smart-61b5369a-93ce-424e-bfd7-38f705b74bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043759163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3043759163
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2490327923
Short name T1129
Test name
Test status
Simulation time 357937904 ps
CPU time 2.02 seconds
Started Apr 18 03:10:13 PM PDT 24
Finished Apr 18 03:10:15 PM PDT 24
Peak memory 203964 kb
Host smart-b3217576-5e4b-44e2-a538-ffa88a066dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490327923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2490327923
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2369372334
Short name T655
Test name
Test status
Simulation time 3067688728 ps
CPU time 4.14 seconds
Started Apr 18 03:10:04 PM PDT 24
Finished Apr 18 03:10:08 PM PDT 24
Peak memory 204068 kb
Host smart-22fab0fb-5029-4cfd-a5cc-6f79b70b6829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369372334 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2369372334
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2590475036
Short name T1031
Test name
Test status
Simulation time 10244956878 ps
CPU time 42.03 seconds
Started Apr 18 03:10:03 PM PDT 24
Finished Apr 18 03:10:46 PM PDT 24
Peak memory 872724 kb
Host smart-57310d78-a009-46ff-a08a-77f57ff1d2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590475036 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2590475036
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2704983246
Short name T355
Test name
Test status
Simulation time 1642203044 ps
CPU time 25.39 seconds
Started Apr 18 03:09:56 PM PDT 24
Finished Apr 18 03:10:22 PM PDT 24
Peak memory 203964 kb
Host smart-604037cd-cb63-4c8d-9116-f5f7362bdcf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704983246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2704983246
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3002000352
Short name T90
Test name
Test status
Simulation time 3693365203 ps
CPU time 35.57 seconds
Started Apr 18 03:10:03 PM PDT 24
Finished Apr 18 03:10:39 PM PDT 24
Peak memory 204068 kb
Host smart-747001fc-f4a6-47c6-9367-043715db9b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002000352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3002000352
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3213008011
Short name T363
Test name
Test status
Simulation time 51210338321 ps
CPU time 1170.83 seconds
Started Apr 18 03:09:55 PM PDT 24
Finished Apr 18 03:29:27 PM PDT 24
Peak memory 7763404 kb
Host smart-08344057-3c3b-46f2-9cb5-40b453daa361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213008011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3213008011
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3330932867
Short name T380
Test name
Test status
Simulation time 39114322592 ps
CPU time 335.78 seconds
Started Apr 18 03:10:06 PM PDT 24
Finished Apr 18 03:15:42 PM PDT 24
Peak memory 2260884 kb
Host smart-66e9596e-d78e-4739-91cc-3448755db25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330932867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3330932867
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2834401533
Short name T671
Test name
Test status
Simulation time 4952083053 ps
CPU time 5.96 seconds
Started Apr 18 03:10:04 PM PDT 24
Finished Apr 18 03:10:10 PM PDT 24
Peak memory 214688 kb
Host smart-d48bb940-11f6-49c7-b22a-97d4ea383e35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834401533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2834401533
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.408748356
Short name T102
Test name
Test status
Simulation time 15211454 ps
CPU time 0.61 seconds
Started Apr 18 03:10:33 PM PDT 24
Finished Apr 18 03:10:35 PM PDT 24
Peak memory 203572 kb
Host smart-b8ad9527-633f-4579-87c1-261f48e4ca7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408748356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.408748356
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2731461242
Short name T1097
Test name
Test status
Simulation time 50504590 ps
CPU time 1.14 seconds
Started Apr 18 03:10:21 PM PDT 24
Finished Apr 18 03:10:22 PM PDT 24
Peak memory 212336 kb
Host smart-fe064656-a0da-47c3-b809-ae1c6f313b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731461242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2731461242
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3232190629
Short name T1310
Test name
Test status
Simulation time 864271182 ps
CPU time 10.97 seconds
Started Apr 18 03:10:18 PM PDT 24
Finished Apr 18 03:10:29 PM PDT 24
Peak memory 246908 kb
Host smart-6022fccd-cb9a-414a-9aa1-0f7dfa4d6e12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232190629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3232190629
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1865714168
Short name T580
Test name
Test status
Simulation time 6904283757 ps
CPU time 41.52 seconds
Started Apr 18 03:10:18 PM PDT 24
Finished Apr 18 03:11:00 PM PDT 24
Peak memory 531752 kb
Host smart-81f44f60-4b27-4a2d-bc6e-45ed00f86716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865714168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1865714168
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.529178554
Short name T1001
Test name
Test status
Simulation time 15541573119 ps
CPU time 75.59 seconds
Started Apr 18 03:10:17 PM PDT 24
Finished Apr 18 03:11:33 PM PDT 24
Peak memory 697156 kb
Host smart-7c18a2a3-027c-42c5-bae7-b477a93aab22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529178554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.529178554
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.58913477
Short name T963
Test name
Test status
Simulation time 422206246 ps
CPU time 0.9 seconds
Started Apr 18 03:10:20 PM PDT 24
Finished Apr 18 03:10:21 PM PDT 24
Peak memory 203724 kb
Host smart-98bd089c-870e-4e63-a63a-f8f88e33b222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58913477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt
.58913477
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3415225979
Short name T505
Test name
Test status
Simulation time 402332538 ps
CPU time 3.71 seconds
Started Apr 18 03:10:17 PM PDT 24
Finished Apr 18 03:10:21 PM PDT 24
Peak memory 203888 kb
Host smart-bcd0adbf-7a12-4fce-8648-4c771d89f1ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415225979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3415225979
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2009419931
Short name T237
Test name
Test status
Simulation time 6193861131 ps
CPU time 114.1 seconds
Started Apr 18 03:10:18 PM PDT 24
Finished Apr 18 03:12:13 PM PDT 24
Peak memory 1273124 kb
Host smart-4232175c-f0bb-4e1c-a1dd-ab0197fec7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009419931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2009419931
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.913579756
Short name T1228
Test name
Test status
Simulation time 1047036601 ps
CPU time 51.24 seconds
Started Apr 18 03:10:27 PM PDT 24
Finished Apr 18 03:11:19 PM PDT 24
Peak memory 336476 kb
Host smart-d7058c51-ba7e-4942-ad6c-dcf010831f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913579756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.913579756
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.4094948799
Short name T189
Test name
Test status
Simulation time 93291328 ps
CPU time 0.71 seconds
Started Apr 18 03:10:17 PM PDT 24
Finished Apr 18 03:10:18 PM PDT 24
Peak memory 203684 kb
Host smart-4828d7cc-f8a2-47e5-810c-c11b8b1aaa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094948799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.4094948799
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3983675155
Short name T737
Test name
Test status
Simulation time 6796451974 ps
CPU time 146.69 seconds
Started Apr 18 03:10:24 PM PDT 24
Finished Apr 18 03:12:52 PM PDT 24
Peak memory 224988 kb
Host smart-661f1a87-2287-413a-bc8d-22a9ee1cf119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983675155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3983675155
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2485678344
Short name T825
Test name
Test status
Simulation time 6117028122 ps
CPU time 58 seconds
Started Apr 18 03:10:18 PM PDT 24
Finished Apr 18 03:11:17 PM PDT 24
Peak memory 315096 kb
Host smart-aa32c7a2-0f1d-4fef-8bf2-a6b5d7686ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485678344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2485678344
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3016256946
Short name T661
Test name
Test status
Simulation time 6841155958 ps
CPU time 543.76 seconds
Started Apr 18 03:10:21 PM PDT 24
Finished Apr 18 03:19:25 PM PDT 24
Peak memory 1274684 kb
Host smart-c6bd9d99-5f6c-4ece-a1b3-16cebce7857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016256946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3016256946
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2661565933
Short name T527
Test name
Test status
Simulation time 3732252930 ps
CPU time 21.12 seconds
Started Apr 18 03:10:20 PM PDT 24
Finished Apr 18 03:10:41 PM PDT 24
Peak memory 212260 kb
Host smart-1419e533-d1da-4fa2-b136-02e1c6cd7d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661565933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2661565933
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1247724669
Short name T462
Test name
Test status
Simulation time 889202203 ps
CPU time 2.47 seconds
Started Apr 18 03:10:26 PM PDT 24
Finished Apr 18 03:10:29 PM PDT 24
Peak memory 204008 kb
Host smart-824b7637-6169-45b9-97ed-731978d1d870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247724669 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1247724669
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.851623608
Short name T57
Test name
Test status
Simulation time 10120873638 ps
CPU time 65.95 seconds
Started Apr 18 03:10:21 PM PDT 24
Finished Apr 18 03:11:28 PM PDT 24
Peak memory 531576 kb
Host smart-b8196f44-aa8b-49e5-aa49-c5195201a9f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851623608 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.851623608
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3092109714
Short name T1336
Test name
Test status
Simulation time 10269352549 ps
CPU time 26.54 seconds
Started Apr 18 03:10:23 PM PDT 24
Finished Apr 18 03:10:50 PM PDT 24
Peak memory 361320 kb
Host smart-51ea23f8-5866-422d-a67b-38f75f7ae42c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092109714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3092109714
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.3137631808
Short name T1037
Test name
Test status
Simulation time 1218466156 ps
CPU time 2.07 seconds
Started Apr 18 03:10:27 PM PDT 24
Finished Apr 18 03:10:30 PM PDT 24
Peak memory 204016 kb
Host smart-c0e4de29-a811-43fb-9ea7-ced61b449eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137631808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.3137631808
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.4063071761
Short name T343
Test name
Test status
Simulation time 2138340329 ps
CPU time 5.41 seconds
Started Apr 18 03:10:21 PM PDT 24
Finished Apr 18 03:10:27 PM PDT 24
Peak memory 212176 kb
Host smart-bfeb1037-b0ec-499d-8e83-0f051efbe0e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063071761 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.4063071761
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2849598321
Short name T340
Test name
Test status
Simulation time 8838692143 ps
CPU time 30.66 seconds
Started Apr 18 03:10:22 PM PDT 24
Finished Apr 18 03:10:53 PM PDT 24
Peak memory 600536 kb
Host smart-6c5736b1-9b53-4992-8a27-d711f082745c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849598321 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2849598321
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3456252669
Short name T421
Test name
Test status
Simulation time 1135275470 ps
CPU time 16.62 seconds
Started Apr 18 03:10:22 PM PDT 24
Finished Apr 18 03:10:39 PM PDT 24
Peak memory 203960 kb
Host smart-51dce159-5fb6-4023-aea8-d948ae6eea6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456252669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3456252669
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1185657335
Short name T857
Test name
Test status
Simulation time 5877685436 ps
CPU time 17.55 seconds
Started Apr 18 03:10:22 PM PDT 24
Finished Apr 18 03:10:39 PM PDT 24
Peak memory 216248 kb
Host smart-20531294-1882-46d8-9c49-3882474179c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185657335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1185657335
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3916207016
Short name T306
Test name
Test status
Simulation time 31253361392 ps
CPU time 271.34 seconds
Started Apr 18 03:10:22 PM PDT 24
Finished Apr 18 03:14:54 PM PDT 24
Peak memory 2958124 kb
Host smart-3c7a5c15-0ff3-4099-b62d-dd287a4a3bf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916207016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3916207016
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3978530572
Short name T1268
Test name
Test status
Simulation time 6150570871 ps
CPU time 6.93 seconds
Started Apr 18 03:10:29 PM PDT 24
Finished Apr 18 03:10:36 PM PDT 24
Peak memory 219632 kb
Host smart-d6ee182c-bb12-438a-9b8a-f6980fc704ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978530572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3978530572
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1042693789
Short name T992
Test name
Test status
Simulation time 18460981 ps
CPU time 0.66 seconds
Started Apr 18 03:11:03 PM PDT 24
Finished Apr 18 03:11:04 PM PDT 24
Peak memory 203560 kb
Host smart-d4380b70-c054-48ee-9365-7b4ef3dd4aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042693789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1042693789
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.126451961
Short name T317
Test name
Test status
Simulation time 183402381 ps
CPU time 1.53 seconds
Started Apr 18 03:10:42 PM PDT 24
Finished Apr 18 03:10:44 PM PDT 24
Peak memory 212332 kb
Host smart-994cb37f-78ba-4138-9132-e2971e2221ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126451961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.126451961
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.511539502
Short name T277
Test name
Test status
Simulation time 346417986 ps
CPU time 17.96 seconds
Started Apr 18 03:10:31 PM PDT 24
Finished Apr 18 03:10:49 PM PDT 24
Peak memory 276768 kb
Host smart-3aab3c63-cee8-4f69-96d8-e86ac0a93cfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511539502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.511539502
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.184860696
Short name T413
Test name
Test status
Simulation time 3247644789 ps
CPU time 49.86 seconds
Started Apr 18 03:10:35 PM PDT 24
Finished Apr 18 03:11:26 PM PDT 24
Peak memory 529980 kb
Host smart-ebec8adf-ae04-4872-8190-b31450b44520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184860696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.184860696
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3976122000
Short name T821
Test name
Test status
Simulation time 4441451960 ps
CPU time 35.8 seconds
Started Apr 18 03:10:32 PM PDT 24
Finished Apr 18 03:11:08 PM PDT 24
Peak memory 447752 kb
Host smart-24f5e3f5-231d-4a6f-9d30-a6d1f45e36c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976122000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3976122000
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.4104885741
Short name T70
Test name
Test status
Simulation time 124904845 ps
CPU time 1.04 seconds
Started Apr 18 03:10:31 PM PDT 24
Finished Apr 18 03:10:32 PM PDT 24
Peak memory 203972 kb
Host smart-c7d86fd3-c45a-4ad3-963b-35f202e6fa09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104885741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.4104885741
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1319601798
Short name T549
Test name
Test status
Simulation time 594520985 ps
CPU time 4.08 seconds
Started Apr 18 03:10:33 PM PDT 24
Finished Apr 18 03:10:37 PM PDT 24
Peak memory 231616 kb
Host smart-fce84ea8-83eb-48c8-97c1-ce222e41370e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319601798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1319601798
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3855451434
Short name T538
Test name
Test status
Simulation time 12617021105 ps
CPU time 63.65 seconds
Started Apr 18 03:10:31 PM PDT 24
Finished Apr 18 03:11:35 PM PDT 24
Peak memory 767856 kb
Host smart-27790f98-d04f-426a-b56d-8c71c991ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855451434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3855451434
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.3078392628
Short name T1106
Test name
Test status
Simulation time 670578984 ps
CPU time 10.5 seconds
Started Apr 18 03:11:02 PM PDT 24
Finished Apr 18 03:11:13 PM PDT 24
Peak memory 203948 kb
Host smart-18a491ca-9c0a-4dd0-b9e2-571a9423d08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078392628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.3078392628
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3501553523
Short name T894
Test name
Test status
Simulation time 4260322496 ps
CPU time 45.58 seconds
Started Apr 18 03:10:54 PM PDT 24
Finished Apr 18 03:11:39 PM PDT 24
Peak memory 263276 kb
Host smart-64bf35c3-eac5-4db5-bd2a-1d3095eaa420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501553523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3501553523
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.226444397
Short name T186
Test name
Test status
Simulation time 30566144 ps
CPU time 0.68 seconds
Started Apr 18 03:10:34 PM PDT 24
Finished Apr 18 03:10:36 PM PDT 24
Peak memory 203656 kb
Host smart-41cd4732-3d11-4294-a7ec-4ebc127eb77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226444397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.226444397
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2404000862
Short name T1047
Test name
Test status
Simulation time 1851961200 ps
CPU time 17.62 seconds
Started Apr 18 03:10:35 PM PDT 24
Finished Apr 18 03:10:54 PM PDT 24
Peak memory 216672 kb
Host smart-9bdd490b-a9ca-42df-9f7c-110a880926c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404000862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2404000862
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3511602143
Short name T272
Test name
Test status
Simulation time 3137380440 ps
CPU time 15.84 seconds
Started Apr 18 03:10:32 PM PDT 24
Finished Apr 18 03:10:48 PM PDT 24
Peak memory 293504 kb
Host smart-dd59f417-8ff5-4129-8786-010fd2ce9aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511602143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3511602143
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.2114745852
Short name T808
Test name
Test status
Simulation time 69611173204 ps
CPU time 2296.69 seconds
Started Apr 18 03:10:42 PM PDT 24
Finished Apr 18 03:49:00 PM PDT 24
Peak memory 1378564 kb
Host smart-88d1a551-8225-4036-9c27-138907ada933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114745852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.2114745852
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3127880227
Short name T650
Test name
Test status
Simulation time 1440107028 ps
CPU time 6.28 seconds
Started Apr 18 03:10:43 PM PDT 24
Finished Apr 18 03:10:50 PM PDT 24
Peak memory 215756 kb
Host smart-e5d681e5-ddda-4c7a-a401-629cf8cd04d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127880227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3127880227
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2940955745
Short name T30
Test name
Test status
Simulation time 7366607405 ps
CPU time 2.91 seconds
Started Apr 18 03:10:51 PM PDT 24
Finished Apr 18 03:10:54 PM PDT 24
Peak memory 212232 kb
Host smart-2b7b9ecb-f578-4967-a252-e9790ec76b04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940955745 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2940955745
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.784568009
Short name T539
Test name
Test status
Simulation time 10046667152 ps
CPU time 65.02 seconds
Started Apr 18 03:10:45 PM PDT 24
Finished Apr 18 03:11:50 PM PDT 24
Peak memory 476280 kb
Host smart-db9caefe-4038-430f-bffe-2bb35e426751
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784568009 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.784568009
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2150408094
Short name T1280
Test name
Test status
Simulation time 11231897287 ps
CPU time 4.71 seconds
Started Apr 18 03:10:45 PM PDT 24
Finished Apr 18 03:10:50 PM PDT 24
Peak memory 246444 kb
Host smart-e0382360-f59f-4570-ba31-a018db8c8c8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150408094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2150408094
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2902433732
Short name T703
Test name
Test status
Simulation time 8614143610 ps
CPU time 2.65 seconds
Started Apr 18 03:10:50 PM PDT 24
Finished Apr 18 03:10:53 PM PDT 24
Peak memory 204032 kb
Host smart-543e9ba8-1d27-47b8-990e-c23095584871
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902433732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2902433732
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.226644915
Short name T956
Test name
Test status
Simulation time 859004238 ps
CPU time 4.24 seconds
Started Apr 18 03:10:43 PM PDT 24
Finished Apr 18 03:10:48 PM PDT 24
Peak memory 205348 kb
Host smart-cf8c78e4-39d1-4b3d-aa41-3136cf253ecc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226644915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.226644915
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3598975310
Short name T665
Test name
Test status
Simulation time 19124188151 ps
CPU time 312.77 seconds
Started Apr 18 03:10:43 PM PDT 24
Finished Apr 18 03:15:56 PM PDT 24
Peak memory 3196200 kb
Host smart-6099e165-ff53-4f22-b289-190f9ef21ca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598975310 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3598975310
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1581098930
Short name T1101
Test name
Test status
Simulation time 6297161375 ps
CPU time 23.54 seconds
Started Apr 18 03:10:41 PM PDT 24
Finished Apr 18 03:11:05 PM PDT 24
Peak memory 204060 kb
Host smart-3a4bb0a3-ebaa-467b-bd41-619d2b0227a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581098930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1581098930
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2607520019
Short name T474
Test name
Test status
Simulation time 8853500397 ps
CPU time 16.32 seconds
Started Apr 18 03:10:40 PM PDT 24
Finished Apr 18 03:10:57 PM PDT 24
Peak memory 219788 kb
Host smart-c780dc01-2eb4-4a5c-a2d8-9896585d08fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607520019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2607520019
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2647673094
Short name T1360
Test name
Test status
Simulation time 12239785501 ps
CPU time 6.67 seconds
Started Apr 18 03:10:41 PM PDT 24
Finished Apr 18 03:10:48 PM PDT 24
Peak memory 204036 kb
Host smart-56341761-d25e-471d-add9-89a8fa7c9f57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647673094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2647673094
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1038289733
Short name T507
Test name
Test status
Simulation time 42619877655 ps
CPU time 209.36 seconds
Started Apr 18 03:10:41 PM PDT 24
Finished Apr 18 03:14:11 PM PDT 24
Peak memory 1833188 kb
Host smart-1b727db9-2056-4510-a18a-0c84dff14e15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038289733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1038289733
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3507154267
Short name T556
Test name
Test status
Simulation time 4586281912 ps
CPU time 5.62 seconds
Started Apr 18 03:10:48 PM PDT 24
Finished Apr 18 03:10:54 PM PDT 24
Peak memory 212280 kb
Host smart-9b5344ed-43c8-44e8-8e87-9fb6449338e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507154267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3507154267
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1427538952
Short name T1324
Test name
Test status
Simulation time 30011558 ps
CPU time 0.6 seconds
Started Apr 18 03:11:16 PM PDT 24
Finished Apr 18 03:11:17 PM PDT 24
Peak memory 203576 kb
Host smart-b4733db4-45bb-4a74-b705-983ab4786251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427538952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1427538952
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2644495489
Short name T385
Test name
Test status
Simulation time 360261036 ps
CPU time 1.47 seconds
Started Apr 18 03:11:05 PM PDT 24
Finished Apr 18 03:11:07 PM PDT 24
Peak memory 212264 kb
Host smart-44f0f357-eb5d-493a-82b9-0db5077e53b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644495489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2644495489
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2515513129
Short name T192
Test name
Test status
Simulation time 498003595 ps
CPU time 7.93 seconds
Started Apr 18 03:11:04 PM PDT 24
Finished Apr 18 03:11:13 PM PDT 24
Peak memory 277272 kb
Host smart-75ec28f3-0e02-4399-8049-00edf9d07864
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515513129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2515513129
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.908970747
Short name T1314
Test name
Test status
Simulation time 1072155539 ps
CPU time 55.81 seconds
Started Apr 18 03:11:14 PM PDT 24
Finished Apr 18 03:12:10 PM PDT 24
Peak memory 212016 kb
Host smart-2d06048f-aa6f-4f80-a295-46a0d1b75e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908970747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.908970747
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3620742588
Short name T430
Test name
Test status
Simulation time 2115771253 ps
CPU time 159.96 seconds
Started Apr 18 03:10:57 PM PDT 24
Finished Apr 18 03:13:38 PM PDT 24
Peak memory 701592 kb
Host smart-304b8d17-043d-40fb-9dc2-2945749ceb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620742588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3620742588
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3539640650
Short name T381
Test name
Test status
Simulation time 183580959 ps
CPU time 0.86 seconds
Started Apr 18 03:10:55 PM PDT 24
Finished Apr 18 03:10:56 PM PDT 24
Peak memory 203756 kb
Host smart-16d844ce-ccf0-4dd3-a008-1a05239c0e7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539640650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3539640650
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.400953603
Short name T678
Test name
Test status
Simulation time 191939481 ps
CPU time 10.2 seconds
Started Apr 18 03:11:04 PM PDT 24
Finished Apr 18 03:11:15 PM PDT 24
Peak memory 239428 kb
Host smart-0ac005d8-4f42-4f51-baee-7d141feca9df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400953603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
400953603
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3397544921
Short name T985
Test name
Test status
Simulation time 14208460801 ps
CPU time 248.99 seconds
Started Apr 18 03:11:04 PM PDT 24
Finished Apr 18 03:15:13 PM PDT 24
Peak memory 1054012 kb
Host smart-fecd70ee-1b52-44e3-b52e-d7b2f7248d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397544921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3397544921
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.4261778469
Short name T802
Test name
Test status
Simulation time 678391486 ps
CPU time 27.01 seconds
Started Apr 18 03:11:16 PM PDT 24
Finished Apr 18 03:11:43 PM PDT 24
Peak memory 203900 kb
Host smart-28181020-f91b-44f5-ab49-4ec950eacabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261778469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.4261778469
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3390462864
Short name T484
Test name
Test status
Simulation time 955008173 ps
CPU time 43.13 seconds
Started Apr 18 03:11:15 PM PDT 24
Finished Apr 18 03:11:58 PM PDT 24
Peak memory 299012 kb
Host smart-22b29fae-5bed-4a67-9ebc-0764deaa49fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390462864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3390462864
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1391890185
Short name T1137
Test name
Test status
Simulation time 73527315 ps
CPU time 0.7 seconds
Started Apr 18 03:11:04 PM PDT 24
Finished Apr 18 03:11:05 PM PDT 24
Peak memory 203660 kb
Host smart-2797e90b-73b2-4233-bd84-e2b85999e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391890185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1391890185
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.317606525
Short name T1150
Test name
Test status
Simulation time 7799388659 ps
CPU time 220.11 seconds
Started Apr 18 03:11:05 PM PDT 24
Finished Apr 18 03:14:46 PM PDT 24
Peak memory 492916 kb
Host smart-f138f6c6-dc0b-4afc-9e06-49d663baddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317606525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.317606525
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3731011144
Short name T492
Test name
Test status
Simulation time 1190051017 ps
CPU time 52.56 seconds
Started Apr 18 03:11:03 PM PDT 24
Finished Apr 18 03:11:56 PM PDT 24
Peak memory 282588 kb
Host smart-83cce38e-3126-44a5-9b3c-eb41002153e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731011144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3731011144
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2783601354
Short name T1162
Test name
Test status
Simulation time 27112933679 ps
CPU time 296.26 seconds
Started Apr 18 03:11:05 PM PDT 24
Finished Apr 18 03:16:02 PM PDT 24
Peak memory 1752364 kb
Host smart-92086b10-1f03-40d5-b604-b0e59ee28ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783601354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2783601354
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1316075667
Short name T728
Test name
Test status
Simulation time 570291568 ps
CPU time 27.36 seconds
Started Apr 18 03:11:03 PM PDT 24
Finished Apr 18 03:11:31 PM PDT 24
Peak memory 212172 kb
Host smart-08c617b6-b954-43e7-95a1-92b48fe58984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316075667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1316075667
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2261112754
Short name T910
Test name
Test status
Simulation time 1403736816 ps
CPU time 3.19 seconds
Started Apr 18 03:11:11 PM PDT 24
Finished Apr 18 03:11:15 PM PDT 24
Peak memory 204028 kb
Host smart-b8b70ffb-f43c-4879-821c-a0c8f0872ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261112754 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2261112754
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3396848158
Short name T516
Test name
Test status
Simulation time 10072637553 ps
CPU time 30.31 seconds
Started Apr 18 03:11:12 PM PDT 24
Finished Apr 18 03:11:43 PM PDT 24
Peak memory 396696 kb
Host smart-7d0caaee-0dcb-415d-a950-44dfc9d4ca1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396848158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3396848158
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1358038673
Short name T611
Test name
Test status
Simulation time 10247119028 ps
CPU time 15.67 seconds
Started Apr 18 03:11:12 PM PDT 24
Finished Apr 18 03:11:28 PM PDT 24
Peak memory 290656 kb
Host smart-cd852a1c-f561-447b-bf08-873a1abc2569
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358038673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1358038673
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2825139604
Short name T1006
Test name
Test status
Simulation time 1866584272 ps
CPU time 1.91 seconds
Started Apr 18 03:11:12 PM PDT 24
Finished Apr 18 03:11:14 PM PDT 24
Peak memory 204012 kb
Host smart-682e4c44-4146-415c-97d4-661da4a6d14b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825139604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2825139604
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3130608566
Short name T264
Test name
Test status
Simulation time 10119791958 ps
CPU time 7.66 seconds
Started Apr 18 03:11:08 PM PDT 24
Finished Apr 18 03:11:16 PM PDT 24
Peak memory 214496 kb
Host smart-0883b678-c85d-45eb-bb36-e9a676a68e9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130608566 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3130608566
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3909063458
Short name T1163
Test name
Test status
Simulation time 17314862710 ps
CPU time 237.96 seconds
Started Apr 18 03:11:06 PM PDT 24
Finished Apr 18 03:15:05 PM PDT 24
Peak memory 2781272 kb
Host smart-85036147-357e-4ab0-a80a-cef66a76b02c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909063458 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3909063458
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.4031123303
Short name T510
Test name
Test status
Simulation time 1126454949 ps
CPU time 15.27 seconds
Started Apr 18 03:11:10 PM PDT 24
Finished Apr 18 03:11:26 PM PDT 24
Peak memory 203984 kb
Host smart-7aede282-646d-4670-a0fc-af00bfed22ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031123303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.4031123303
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.303673076
Short name T1207
Test name
Test status
Simulation time 618995191 ps
CPU time 24.92 seconds
Started Apr 18 03:11:08 PM PDT 24
Finished Apr 18 03:11:33 PM PDT 24
Peak memory 204024 kb
Host smart-74afd2dd-a6be-4148-a699-3cff51b6aa58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303673076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.303673076
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.652435211
Short name T725
Test name
Test status
Simulation time 46623847485 ps
CPU time 115.29 seconds
Started Apr 18 03:18:31 PM PDT 24
Finished Apr 18 03:20:27 PM PDT 24
Peak memory 1524756 kb
Host smart-f836485c-021e-4fa4-9be2-9f2ed65e3d44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652435211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_wr.652435211
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3688791407
Short name T1093
Test name
Test status
Simulation time 35387831307 ps
CPU time 3159.81 seconds
Started Apr 18 03:11:05 PM PDT 24
Finished Apr 18 04:03:47 PM PDT 24
Peak memory 8491164 kb
Host smart-a1bec13d-b54e-4a55-a892-88e4e36a6548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688791407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3688791407
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1299092240
Short name T945
Test name
Test status
Simulation time 12950880927 ps
CPU time 7.4 seconds
Started Apr 18 03:11:08 PM PDT 24
Finished Apr 18 03:11:15 PM PDT 24
Peak memory 211764 kb
Host smart-466353f9-c49a-4033-ac81-19ccdf899a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299092240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1299092240
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.475299494
Short name T610
Test name
Test status
Simulation time 28090466 ps
CPU time 0.62 seconds
Started Apr 18 03:11:41 PM PDT 24
Finished Apr 18 03:11:42 PM PDT 24
Peak memory 203592 kb
Host smart-695a5d88-f5ac-4e86-9f0c-cab5643839e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475299494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.475299494
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3539087119
Short name T1103
Test name
Test status
Simulation time 296552548 ps
CPU time 1.81 seconds
Started Apr 18 03:11:27 PM PDT 24
Finished Apr 18 03:11:29 PM PDT 24
Peak memory 212284 kb
Host smart-bc58c830-e987-4912-a8d4-6efabd066bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539087119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3539087119
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1360725320
Short name T335
Test name
Test status
Simulation time 676989380 ps
CPU time 9.26 seconds
Started Apr 18 03:11:20 PM PDT 24
Finished Apr 18 03:11:30 PM PDT 24
Peak memory 239228 kb
Host smart-2b39b3ae-24cc-4971-a2ee-bedad7c82916
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360725320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1360725320
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.576995668
Short name T452
Test name
Test status
Simulation time 9214496217 ps
CPU time 65 seconds
Started Apr 18 03:11:25 PM PDT 24
Finished Apr 18 03:12:30 PM PDT 24
Peak memory 595600 kb
Host smart-bc3db4d6-7c30-4503-8749-e91e3215b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576995668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.576995668
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3198805043
Short name T1175
Test name
Test status
Simulation time 4499172215 ps
CPU time 67.62 seconds
Started Apr 18 03:11:19 PM PDT 24
Finished Apr 18 03:12:27 PM PDT 24
Peak memory 729908 kb
Host smart-c34dda2a-794f-47a8-8062-c63d5f824c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198805043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3198805043
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1105612620
Short name T883
Test name
Test status
Simulation time 528928921 ps
CPU time 0.89 seconds
Started Apr 18 03:11:20 PM PDT 24
Finished Apr 18 03:11:22 PM PDT 24
Peak memory 203740 kb
Host smart-d2a58f6b-b99d-495b-a62f-7dd199242431
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105612620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1105612620
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2191810106
Short name T638
Test name
Test status
Simulation time 166490796 ps
CPU time 8.77 seconds
Started Apr 18 03:11:19 PM PDT 24
Finished Apr 18 03:11:28 PM PDT 24
Peak memory 233268 kb
Host smart-75dac6a5-737f-49e5-815f-7bdb16f81e04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191810106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2191810106
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.3273942942
Short name T171
Test name
Test status
Simulation time 6085041344 ps
CPU time 69.7 seconds
Started Apr 18 03:11:21 PM PDT 24
Finished Apr 18 03:12:31 PM PDT 24
Peak memory 943852 kb
Host smart-03af77d9-f2e9-46b8-a4d4-d2d44bda28d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273942942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.3273942942
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1813666510
Short name T271
Test name
Test status
Simulation time 643214179 ps
CPU time 6.28 seconds
Started Apr 18 03:11:36 PM PDT 24
Finished Apr 18 03:11:43 PM PDT 24
Peak memory 203976 kb
Host smart-a0be919d-a60c-4625-9e2f-6883593e04a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813666510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1813666510
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3870438457
Short name T1038
Test name
Test status
Simulation time 5184977735 ps
CPU time 57.42 seconds
Started Apr 18 03:11:35 PM PDT 24
Finished Apr 18 03:12:33 PM PDT 24
Peak memory 301620 kb
Host smart-1dcea5d3-65f1-4440-9a17-21ecd6d056d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870438457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3870438457
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.4162625573
Short name T958
Test name
Test status
Simulation time 58878600 ps
CPU time 0.67 seconds
Started Apr 18 03:11:22 PM PDT 24
Finished Apr 18 03:11:23 PM PDT 24
Peak memory 203672 kb
Host smart-940bdf4e-18b6-4b05-9f26-f410eb9eb5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162625573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.4162625573
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2225012780
Short name T885
Test name
Test status
Simulation time 95120444190 ps
CPU time 1693.3 seconds
Started Apr 18 03:11:23 PM PDT 24
Finished Apr 18 03:39:37 PM PDT 24
Peak memory 1589388 kb
Host smart-289b86be-92da-42fb-820a-bf73a552fe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225012780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2225012780
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.2049569556
Short name T297
Test name
Test status
Simulation time 1308905178 ps
CPU time 58.62 seconds
Started Apr 18 03:11:23 PM PDT 24
Finished Apr 18 03:12:21 PM PDT 24
Peak memory 276344 kb
Host smart-ec1d4737-911a-4f30-8fa3-bc00b6218b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049569556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2049569556
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3152342673
Short name T1105
Test name
Test status
Simulation time 78861483875 ps
CPU time 3143.76 seconds
Started Apr 18 03:11:26 PM PDT 24
Finished Apr 18 04:03:50 PM PDT 24
Peak memory 3726272 kb
Host smart-58fb0002-9263-4d3c-99b4-8f03c7394c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152342673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3152342673
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.303873170
Short name T1318
Test name
Test status
Simulation time 2724630817 ps
CPU time 27.35 seconds
Started Apr 18 03:11:26 PM PDT 24
Finished Apr 18 03:11:53 PM PDT 24
Peak memory 220440 kb
Host smart-a8574255-a799-44c9-a264-6fc73b96d852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303873170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.303873170
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1343986475
Short name T1222
Test name
Test status
Simulation time 1446415522 ps
CPU time 3.36 seconds
Started Apr 18 03:11:36 PM PDT 24
Finished Apr 18 03:11:39 PM PDT 24
Peak memory 204040 kb
Host smart-a73b2ebb-d7a8-4935-82a0-91720db5ba9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343986475 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1343986475
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.590692741
Short name T405
Test name
Test status
Simulation time 10138493970 ps
CPU time 26.71 seconds
Started Apr 18 03:11:31 PM PDT 24
Finished Apr 18 03:11:58 PM PDT 24
Peak memory 312932 kb
Host smart-1981c3b0-b7a2-4e07-9740-7a8c928070e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590692741 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.590692741
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3655613138
Short name T567
Test name
Test status
Simulation time 10159302836 ps
CPU time 32.24 seconds
Started Apr 18 03:11:30 PM PDT 24
Finished Apr 18 03:12:03 PM PDT 24
Peak memory 406864 kb
Host smart-b895fe15-54ef-4321-b1d5-73022286ab4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655613138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3655613138
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.4244685228
Short name T577
Test name
Test status
Simulation time 2118233962 ps
CPU time 2.86 seconds
Started Apr 18 03:11:36 PM PDT 24
Finished Apr 18 03:11:39 PM PDT 24
Peak memory 204004 kb
Host smart-a1bf484f-ea52-4de8-ae55-f2e7e686acfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244685228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.4244685228
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2537744114
Short name T829
Test name
Test status
Simulation time 5722895747 ps
CPU time 7.37 seconds
Started Apr 18 03:11:26 PM PDT 24
Finished Apr 18 03:11:33 PM PDT 24
Peak memory 212296 kb
Host smart-f5013f6d-bfd5-4333-b826-809dd6564e40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537744114 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2537744114
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4086115210
Short name T598
Test name
Test status
Simulation time 24809786950 ps
CPU time 9.81 seconds
Started Apr 18 03:11:25 PM PDT 24
Finished Apr 18 03:11:35 PM PDT 24
Peak memory 204072 kb
Host smart-c7da0d0d-8dba-46c2-a9d8-497b08d253e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086115210 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4086115210
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2169954496
Short name T902
Test name
Test status
Simulation time 805139725 ps
CPU time 28.06 seconds
Started Apr 18 03:11:26 PM PDT 24
Finished Apr 18 03:11:54 PM PDT 24
Peak memory 203964 kb
Host smart-db565523-1a89-4316-a731-ccfa16aa32cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169954496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2169954496
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3255181520
Short name T1247
Test name
Test status
Simulation time 4223899602 ps
CPU time 49.77 seconds
Started Apr 18 03:11:25 PM PDT 24
Finished Apr 18 03:12:15 PM PDT 24
Peak memory 204216 kb
Host smart-5f3c9f7e-06a0-47be-87ac-2ecd5c379c04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255181520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3255181520
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3280934404
Short name T283
Test name
Test status
Simulation time 12748575656 ps
CPU time 20.76 seconds
Started Apr 18 03:11:25 PM PDT 24
Finished Apr 18 03:11:46 PM PDT 24
Peak memory 204056 kb
Host smart-d044618f-3bcc-485e-9857-7b4014fa4f03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280934404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3280934404
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2789215576
Short name T1144
Test name
Test status
Simulation time 32890565673 ps
CPU time 352.69 seconds
Started Apr 18 03:11:23 PM PDT 24
Finished Apr 18 03:17:16 PM PDT 24
Peak memory 2270048 kb
Host smart-0407f9f3-a205-4021-a6f5-104e0a3810a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789215576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2789215576
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.733457259
Short name T628
Test name
Test status
Simulation time 1336675939 ps
CPU time 6.4 seconds
Started Apr 18 03:11:24 PM PDT 24
Finished Apr 18 03:11:31 PM PDT 24
Peak memory 217988 kb
Host smart-b7302945-9925-45ec-81f6-3376a3e282f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733457259 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.733457259
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.4048660813
Short name T1255
Test name
Test status
Simulation time 14821363 ps
CPU time 0.6 seconds
Started Apr 18 03:12:01 PM PDT 24
Finished Apr 18 03:12:02 PM PDT 24
Peak memory 203464 kb
Host smart-11c0b81f-3d98-4304-9ee5-3207e71fd105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048660813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.4048660813
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2193985846
Short name T587
Test name
Test status
Simulation time 328879999 ps
CPU time 1.51 seconds
Started Apr 18 03:11:49 PM PDT 24
Finished Apr 18 03:11:51 PM PDT 24
Peak memory 212276 kb
Host smart-471df8c5-8c53-40ba-9416-d2b815cbafb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193985846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2193985846
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3014909868
Short name T732
Test name
Test status
Simulation time 1430620503 ps
CPU time 17.71 seconds
Started Apr 18 03:11:39 PM PDT 24
Finished Apr 18 03:11:57 PM PDT 24
Peak memory 278272 kb
Host smart-303c5f20-6a19-4904-b7b6-0a9b2d906e1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014909868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3014909868
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.4083674618
Short name T480
Test name
Test status
Simulation time 6345757561 ps
CPU time 53.64 seconds
Started Apr 18 03:11:43 PM PDT 24
Finished Apr 18 03:12:37 PM PDT 24
Peak memory 584284 kb
Host smart-ded17efd-0f08-4c3c-bd67-38499111bcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083674618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4083674618
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1883762526
Short name T1278
Test name
Test status
Simulation time 1689541004 ps
CPU time 49.72 seconds
Started Apr 18 03:11:42 PM PDT 24
Finished Apr 18 03:12:32 PM PDT 24
Peak memory 621476 kb
Host smart-b9760f89-f3f3-4c3c-8f7d-d21ae8844677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883762526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1883762526
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.67724413
Short name T1030
Test name
Test status
Simulation time 100008291 ps
CPU time 0.89 seconds
Started Apr 18 03:11:40 PM PDT 24
Finished Apr 18 03:11:42 PM PDT 24
Peak memory 203700 kb
Host smart-654985a9-8237-4071-92b4-c0e1215a213c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67724413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt
.67724413
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3267522921
Short name T896
Test name
Test status
Simulation time 501118611 ps
CPU time 3.07 seconds
Started Apr 18 03:11:41 PM PDT 24
Finished Apr 18 03:11:44 PM PDT 24
Peak memory 203980 kb
Host smart-0fbb036c-9986-4e7e-add6-052b3833cb7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267522921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3267522921
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1833732384
Short name T629
Test name
Test status
Simulation time 60292939684 ps
CPU time 324.68 seconds
Started Apr 18 03:11:40 PM PDT 24
Finished Apr 18 03:17:05 PM PDT 24
Peak memory 1256320 kb
Host smart-718c514c-febb-4255-8d5a-9702dbe6bea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833732384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1833732384
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.3828770370
Short name T482
Test name
Test status
Simulation time 391569723 ps
CPU time 5.73 seconds
Started Apr 18 03:12:05 PM PDT 24
Finished Apr 18 03:12:11 PM PDT 24
Peak memory 203976 kb
Host smart-f32ae1cc-d7a8-497b-bfa7-ce349a9b8161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828770370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3828770370
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2083781529
Short name T294
Test name
Test status
Simulation time 3880525730 ps
CPU time 33.12 seconds
Started Apr 18 03:11:59 PM PDT 24
Finished Apr 18 03:12:33 PM PDT 24
Peak memory 405020 kb
Host smart-a8294870-e00d-49a9-97b5-f128e65437d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083781529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2083781529
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2994245107
Short name T216
Test name
Test status
Simulation time 104949222 ps
CPU time 0.63 seconds
Started Apr 18 03:11:40 PM PDT 24
Finished Apr 18 03:11:41 PM PDT 24
Peak memory 203672 kb
Host smart-c43fe545-b66f-404f-a438-6c2d3577061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994245107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2994245107
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.484973204
Short name T444
Test name
Test status
Simulation time 366243967 ps
CPU time 8.48 seconds
Started Apr 18 03:11:52 PM PDT 24
Finished Apr 18 03:12:01 PM PDT 24
Peak memory 228376 kb
Host smart-bffd6d9c-8ae4-4498-a578-b8c93ea79929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484973204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.484973204
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.4069736160
Short name T395
Test name
Test status
Simulation time 1812904525 ps
CPU time 25.98 seconds
Started Apr 18 03:11:40 PM PDT 24
Finished Apr 18 03:12:06 PM PDT 24
Peak memory 377620 kb
Host smart-90fdfe09-da7e-4a91-9b8a-1fe02c9ae20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069736160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.4069736160
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.966203053
Short name T684
Test name
Test status
Simulation time 15287491143 ps
CPU time 322.02 seconds
Started Apr 18 03:11:48 PM PDT 24
Finished Apr 18 03:17:10 PM PDT 24
Peak memory 1555376 kb
Host smart-59f0a488-979d-4e8a-9aea-03d5b6d54479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966203053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.966203053
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3409262292
Short name T374
Test name
Test status
Simulation time 1866011637 ps
CPU time 8.26 seconds
Started Apr 18 03:11:47 PM PDT 24
Finished Apr 18 03:11:56 PM PDT 24
Peak memory 220092 kb
Host smart-85ffe969-cd65-4823-9a20-ad0d19b1b5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409262292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3409262292
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.804640617
Short name T1091
Test name
Test status
Simulation time 2735306304 ps
CPU time 5.16 seconds
Started Apr 18 03:11:52 PM PDT 24
Finished Apr 18 03:11:57 PM PDT 24
Peak memory 204024 kb
Host smart-cc80a0ba-04d0-447f-819b-a3ab7a4cecc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804640617 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.804640617
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.778123092
Short name T222
Test name
Test status
Simulation time 10198261511 ps
CPU time 8.72 seconds
Started Apr 18 03:11:53 PM PDT 24
Finished Apr 18 03:12:02 PM PDT 24
Peak memory 250484 kb
Host smart-f69cc9e6-9537-4d67-b6e3-15450e7487a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778123092 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.778123092
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3792331764
Short name T1138
Test name
Test status
Simulation time 10126279468 ps
CPU time 62.97 seconds
Started Apr 18 03:11:50 PM PDT 24
Finished Apr 18 03:12:53 PM PDT 24
Peak memory 549296 kb
Host smart-c020f39b-ded1-4ba6-9b4f-8b643bf85e0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792331764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3792331764
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1974954371
Short name T553
Test name
Test status
Simulation time 349874838 ps
CPU time 2.11 seconds
Started Apr 18 03:11:54 PM PDT 24
Finished Apr 18 03:11:56 PM PDT 24
Peak memory 203976 kb
Host smart-afd61ef8-214c-491b-9092-2bc58e85e718
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974954371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1974954371
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.4108567651
Short name T784
Test name
Test status
Simulation time 7194197172 ps
CPU time 4.78 seconds
Started Apr 18 03:11:52 PM PDT 24
Finished Apr 18 03:11:57 PM PDT 24
Peak memory 204080 kb
Host smart-de3f9619-d41d-48c5-8871-016dae276ebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108567651 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.4108567651
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3642966091
Short name T246
Test name
Test status
Simulation time 3392191080 ps
CPU time 1.56 seconds
Started Apr 18 03:11:52 PM PDT 24
Finished Apr 18 03:11:54 PM PDT 24
Peak memory 204024 kb
Host smart-4121fe36-d6e0-43ae-b8a4-8642060b37e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642966091 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3642966091
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2026130892
Short name T619
Test name
Test status
Simulation time 4851202430 ps
CPU time 11.16 seconds
Started Apr 18 03:11:47 PM PDT 24
Finished Apr 18 03:11:58 PM PDT 24
Peak memory 204024 kb
Host smart-03a00f5a-e478-4815-b5e4-f26744a9132c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026130892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2026130892
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.4245798324
Short name T863
Test name
Test status
Simulation time 5541352094 ps
CPU time 28.01 seconds
Started Apr 18 03:11:50 PM PDT 24
Finished Apr 18 03:12:19 PM PDT 24
Peak memory 268592 kb
Host smart-d178d2ef-6ad0-4107-a676-611e24b8bc72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245798324 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.4245798324
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3316322131
Short name T718
Test name
Test status
Simulation time 3311147857 ps
CPU time 14.93 seconds
Started Apr 18 03:11:51 PM PDT 24
Finished Apr 18 03:12:06 PM PDT 24
Peak memory 209072 kb
Host smart-1daac3d7-0d59-4e8a-894b-11bb07f1b5c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316322131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3316322131
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1154648554
Short name T329
Test name
Test status
Simulation time 22064063630 ps
CPU time 3.89 seconds
Started Apr 18 03:11:52 PM PDT 24
Finished Apr 18 03:11:56 PM PDT 24
Peak memory 204052 kb
Host smart-4fc3fead-aa2f-4c9c-bb79-2cda34b90d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154648554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1154648554
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2178812206
Short name T1372
Test name
Test status
Simulation time 36511408068 ps
CPU time 2082.7 seconds
Started Apr 18 03:11:50 PM PDT 24
Finished Apr 18 03:46:34 PM PDT 24
Peak memory 7202516 kb
Host smart-60423fd3-6c13-4e00-bc32-70c4cc53ae0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178812206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2178812206
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3183891047
Short name T1327
Test name
Test status
Simulation time 4862130011 ps
CPU time 6.16 seconds
Started Apr 18 03:11:51 PM PDT 24
Finished Apr 18 03:11:57 PM PDT 24
Peak memory 217356 kb
Host smart-037b68fd-cdf4-4499-b84e-ddeb3c6435ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183891047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3183891047
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1895092714
Short name T476
Test name
Test status
Simulation time 27563259 ps
CPU time 0.6 seconds
Started Apr 18 03:12:15 PM PDT 24
Finished Apr 18 03:12:16 PM PDT 24
Peak memory 203564 kb
Host smart-a3a982f8-c75a-4ff6-a4cc-0665a612d9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895092714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1895092714
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.4182779334
Short name T304
Test name
Test status
Simulation time 94602874 ps
CPU time 1.31 seconds
Started Apr 18 03:12:08 PM PDT 24
Finished Apr 18 03:12:09 PM PDT 24
Peak memory 212312 kb
Host smart-3ec04c55-7cda-43e5-8d46-106baf78d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182779334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4182779334
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3658994528
Short name T524
Test name
Test status
Simulation time 594164127 ps
CPU time 4.15 seconds
Started Apr 18 03:12:04 PM PDT 24
Finished Apr 18 03:12:09 PM PDT 24
Peak memory 236808 kb
Host smart-b49ff9c9-bf33-44ea-b180-044f8b9fa9a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658994528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3658994528
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.231899006
Short name T1206
Test name
Test status
Simulation time 15920129243 ps
CPU time 56.6 seconds
Started Apr 18 03:12:06 PM PDT 24
Finished Apr 18 03:13:03 PM PDT 24
Peak memory 639640 kb
Host smart-df78127b-cdef-43b1-8d84-3f4a6bc4a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231899006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.231899006
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.741155402
Short name T365
Test name
Test status
Simulation time 2242171950 ps
CPU time 65.64 seconds
Started Apr 18 03:12:00 PM PDT 24
Finished Apr 18 03:13:06 PM PDT 24
Peak memory 712068 kb
Host smart-86d549fc-1990-44a3-8208-5b507a1124c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741155402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.741155402
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1631452161
Short name T842
Test name
Test status
Simulation time 363529681 ps
CPU time 0.92 seconds
Started Apr 18 03:12:02 PM PDT 24
Finished Apr 18 03:12:03 PM PDT 24
Peak memory 203720 kb
Host smart-42cea97c-cddb-428e-a22e-19ae6c9aea4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631452161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1631452161
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.156669374
Short name T1158
Test name
Test status
Simulation time 127480891 ps
CPU time 6.51 seconds
Started Apr 18 03:12:03 PM PDT 24
Finished Apr 18 03:12:10 PM PDT 24
Peak memory 222724 kb
Host smart-cc998452-7a8b-40e7-af06-e856a8c368e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156669374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
156669374
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.315352016
Short name T1239
Test name
Test status
Simulation time 15792117223 ps
CPU time 59.49 seconds
Started Apr 18 03:12:01 PM PDT 24
Finished Apr 18 03:13:01 PM PDT 24
Peak memory 831012 kb
Host smart-da280a72-be7d-4b0e-877e-cc1bce949a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315352016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.315352016
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.3569751695
Short name T614
Test name
Test status
Simulation time 3108371399 ps
CPU time 11.97 seconds
Started Apr 18 03:12:15 PM PDT 24
Finished Apr 18 03:12:27 PM PDT 24
Peak memory 203988 kb
Host smart-9314af1a-84dc-46ef-bab7-a7712a65b969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569751695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3569751695
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3479520186
Short name T763
Test name
Test status
Simulation time 6681025042 ps
CPU time 79.09 seconds
Started Apr 18 03:12:17 PM PDT 24
Finished Apr 18 03:13:37 PM PDT 24
Peak memory 341292 kb
Host smart-9fd52f60-ea8c-422b-b7a5-5204c91b0fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479520186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3479520186
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.505790499
Short name T532
Test name
Test status
Simulation time 51288664 ps
CPU time 0.62 seconds
Started Apr 18 03:12:03 PM PDT 24
Finished Apr 18 03:12:04 PM PDT 24
Peak memory 203656 kb
Host smart-8e892d19-8fde-406c-9db5-e553b7c16bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505790499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.505790499
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1391738804
Short name T72
Test name
Test status
Simulation time 49813532359 ps
CPU time 1962.22 seconds
Started Apr 18 03:12:08 PM PDT 24
Finished Apr 18 03:44:50 PM PDT 24
Peak memory 212204 kb
Host smart-a8b17fcc-b631-4c11-a38e-c533f451bc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391738804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1391738804
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1733937610
Short name T1041
Test name
Test status
Simulation time 3717578564 ps
CPU time 99.84 seconds
Started Apr 18 03:12:02 PM PDT 24
Finished Apr 18 03:13:42 PM PDT 24
Peak memory 495812 kb
Host smart-e9465990-5a52-4ac0-87d9-78346bd0ed89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733937610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1733937610
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.448358709
Short name T1298
Test name
Test status
Simulation time 64681080796 ps
CPU time 3347.61 seconds
Started Apr 18 03:12:04 PM PDT 24
Finished Apr 18 04:07:52 PM PDT 24
Peak memory 3670968 kb
Host smart-013b8ff0-e81b-4246-9773-9a5b59160229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448358709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.448358709
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2279772240
Short name T60
Test name
Test status
Simulation time 2887576274 ps
CPU time 11.04 seconds
Started Apr 18 03:12:05 PM PDT 24
Finished Apr 18 03:12:16 PM PDT 24
Peak memory 220452 kb
Host smart-063f6f13-96e6-41eb-84c6-ae32854c035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279772240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2279772240
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.4141354358
Short name T372
Test name
Test status
Simulation time 3286998845 ps
CPU time 3.56 seconds
Started Apr 18 03:12:15 PM PDT 24
Finished Apr 18 03:12:19 PM PDT 24
Peak memory 204056 kb
Host smart-b3354311-0edc-4134-a596-5bfefc5b6696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141354358 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.4141354358
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2320401906
Short name T202
Test name
Test status
Simulation time 10103555502 ps
CPU time 15.3 seconds
Started Apr 18 03:12:17 PM PDT 24
Finished Apr 18 03:12:32 PM PDT 24
Peak memory 279312 kb
Host smart-4d99dfc6-644d-4617-bf2e-9914b3d2ec0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320401906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2320401906
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1842936950
Short name T874
Test name
Test status
Simulation time 10685289241 ps
CPU time 9.56 seconds
Started Apr 18 03:12:17 PM PDT 24
Finished Apr 18 03:12:27 PM PDT 24
Peak memory 261636 kb
Host smart-2b10e4db-96fb-4293-8c09-4d78d8fc3531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842936950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1842936950
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3375858844
Short name T13
Test name
Test status
Simulation time 488484085 ps
CPU time 2.85 seconds
Started Apr 18 03:12:14 PM PDT 24
Finished Apr 18 03:12:17 PM PDT 24
Peak memory 203968 kb
Host smart-b6e4f4e2-19e4-4f08-8a63-d507b542f5bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375858844 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3375858844
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.274540050
Short name T1020
Test name
Test status
Simulation time 813652649 ps
CPU time 4.33 seconds
Started Apr 18 03:12:08 PM PDT 24
Finished Apr 18 03:12:13 PM PDT 24
Peak memory 204208 kb
Host smart-86294156-1243-4765-9775-94c4549e163c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274540050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.274540050
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.33244284
Short name T440
Test name
Test status
Simulation time 3613000893 ps
CPU time 2.75 seconds
Started Apr 18 03:12:07 PM PDT 24
Finished Apr 18 03:12:11 PM PDT 24
Peak memory 204052 kb
Host smart-5c99ae6e-ffb1-4c23-be5b-cf56f38c99cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33244284 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.33244284
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1697998032
Short name T1348
Test name
Test status
Simulation time 837325032 ps
CPU time 20.57 seconds
Started Apr 18 03:12:09 PM PDT 24
Finished Apr 18 03:12:29 PM PDT 24
Peak memory 203960 kb
Host smart-f0a23f24-4398-41e4-bf4d-2678a8dac37b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697998032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1697998032
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1868930050
Short name T1113
Test name
Test status
Simulation time 12723006862 ps
CPU time 20.59 seconds
Started Apr 18 03:12:05 PM PDT 24
Finished Apr 18 03:12:26 PM PDT 24
Peak memory 228756 kb
Host smart-aa21ee3b-c577-459c-9054-5a68ba0e5a47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868930050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1868930050
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.4184193384
Short name T1240
Test name
Test status
Simulation time 8603883204 ps
CPU time 131.56 seconds
Started Apr 18 03:12:06 PM PDT 24
Finished Apr 18 03:14:18 PM PDT 24
Peak memory 1279424 kb
Host smart-08e45a11-32ec-4b56-9142-889e626ab423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184193384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.4184193384
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1169094067
Short name T1114
Test name
Test status
Simulation time 1273614817 ps
CPU time 6.49 seconds
Started Apr 18 03:12:10 PM PDT 24
Finished Apr 18 03:12:17 PM PDT 24
Peak memory 220236 kb
Host smart-e72bd06f-7073-43c6-aed1-72d4d599fb2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169094067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1169094067
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.4044663891
Short name T652
Test name
Test status
Simulation time 53399504 ps
CPU time 0.63 seconds
Started Apr 18 03:05:16 PM PDT 24
Finished Apr 18 03:05:17 PM PDT 24
Peak memory 203600 kb
Host smart-8220f7ff-548f-4041-8150-2ffa5da40077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044663891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.4044663891
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1806751440
Short name T1168
Test name
Test status
Simulation time 114550645 ps
CPU time 1.6 seconds
Started Apr 18 03:04:52 PM PDT 24
Finished Apr 18 03:04:54 PM PDT 24
Peak memory 220492 kb
Host smart-f1090892-0277-4e8c-b8ca-e0578f45a21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806751440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1806751440
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.3490560220
Short name T1165
Test name
Test status
Simulation time 200741565 ps
CPU time 10.48 seconds
Started Apr 18 03:04:47 PM PDT 24
Finished Apr 18 03:04:58 PM PDT 24
Peak memory 243512 kb
Host smart-76bbdff8-ddde-477f-9a44-30a3a3375a95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490560220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.3490560220
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1625478753
Short name T441
Test name
Test status
Simulation time 15037752280 ps
CPU time 59.47 seconds
Started Apr 18 03:04:47 PM PDT 24
Finished Apr 18 03:05:46 PM PDT 24
Peak memory 572564 kb
Host smart-3f49364b-0270-4832-88ab-358637865db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625478753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1625478753
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1895857677
Short name T1277
Test name
Test status
Simulation time 5405496714 ps
CPU time 86.4 seconds
Started Apr 18 03:04:46 PM PDT 24
Finished Apr 18 03:06:13 PM PDT 24
Peak memory 489040 kb
Host smart-118eaafc-b14b-413c-a763-111e30c153c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895857677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1895857677
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3055235345
Short name T291
Test name
Test status
Simulation time 77501730 ps
CPU time 0.93 seconds
Started Apr 18 03:04:46 PM PDT 24
Finished Apr 18 03:04:47 PM PDT 24
Peak memory 203728 kb
Host smart-492167c7-16a2-4f8d-b21c-7dbaeae98c53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055235345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3055235345
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.196009102
Short name T668
Test name
Test status
Simulation time 511502507 ps
CPU time 7.08 seconds
Started Apr 18 03:04:48 PM PDT 24
Finished Apr 18 03:04:55 PM PDT 24
Peak memory 203944 kb
Host smart-3d367932-0b56-44bd-b7d5-596088175a2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196009102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.196009102
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.971306824
Short name T541
Test name
Test status
Simulation time 3853342098 ps
CPU time 116.6 seconds
Started Apr 18 03:04:40 PM PDT 24
Finished Apr 18 03:06:37 PM PDT 24
Peak memory 1152884 kb
Host smart-9f72bb9c-2ff8-45d8-ac01-2fa39c417773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971306824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.971306824
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1342238926
Short name T798
Test name
Test status
Simulation time 767095365 ps
CPU time 5.42 seconds
Started Apr 18 03:05:10 PM PDT 24
Finished Apr 18 03:05:16 PM PDT 24
Peak memory 203916 kb
Host smart-0a389822-65dc-4465-85a8-5589a45691ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342238926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1342238926
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1524481228
Short name T947
Test name
Test status
Simulation time 5579434836 ps
CPU time 28.08 seconds
Started Apr 18 03:05:17 PM PDT 24
Finished Apr 18 03:05:45 PM PDT 24
Peak memory 295280 kb
Host smart-2fcdbe9a-b60c-430b-a7e8-2c7795d1512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524481228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1524481228
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.152344771
Short name T416
Test name
Test status
Simulation time 103535507 ps
CPU time 0.63 seconds
Started Apr 18 03:04:42 PM PDT 24
Finished Apr 18 03:04:43 PM PDT 24
Peak memory 203692 kb
Host smart-a99b4b63-cc73-48a1-bcbd-bd1aca03a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152344771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.152344771
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1484842351
Short name T586
Test name
Test status
Simulation time 25661218826 ps
CPU time 99.69 seconds
Started Apr 18 03:04:45 PM PDT 24
Finished Apr 18 03:06:25 PM PDT 24
Peak memory 282704 kb
Host smart-20a17d7f-c013-4810-8293-c87c55be641d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484842351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1484842351
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2270695335
Short name T1304
Test name
Test status
Simulation time 1016405203 ps
CPU time 43.18 seconds
Started Apr 18 03:04:39 PM PDT 24
Finished Apr 18 03:05:23 PM PDT 24
Peak memory 263772 kb
Host smart-a9c7ec0d-4b1d-4eae-8d00-20a2ef2c48cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270695335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2270695335
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3828828216
Short name T331
Test name
Test status
Simulation time 7742731094 ps
CPU time 282.94 seconds
Started Apr 18 03:04:53 PM PDT 24
Finished Apr 18 03:09:36 PM PDT 24
Peak memory 876528 kb
Host smart-8486b0e4-3096-48f7-b600-c19aacd153c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828828216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3828828216
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.690138500
Short name T375
Test name
Test status
Simulation time 1451582352 ps
CPU time 36.3 seconds
Started Apr 18 03:04:47 PM PDT 24
Finished Apr 18 03:05:24 PM PDT 24
Peak memory 220384 kb
Host smart-2fdd6c41-2c5d-415d-8862-e92bbf9e31d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690138500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.690138500
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.4063182991
Short name T112
Test name
Test status
Simulation time 475740346 ps
CPU time 0.92 seconds
Started Apr 18 03:05:10 PM PDT 24
Finished Apr 18 03:05:11 PM PDT 24
Peak memory 222088 kb
Host smart-49ca3d0d-22d3-4b62-8b97-5cd2aa8f3e0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063182991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.4063182991
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.858497186
Short name T537
Test name
Test status
Simulation time 2278206702 ps
CPU time 2.71 seconds
Started Apr 18 03:05:10 PM PDT 24
Finished Apr 18 03:05:13 PM PDT 24
Peak memory 204048 kb
Host smart-085870b2-d9a3-4842-9549-87f60358ed1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858497186 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.858497186
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3962009758
Short name T227
Test name
Test status
Simulation time 10203978639 ps
CPU time 6.92 seconds
Started Apr 18 03:05:04 PM PDT 24
Finished Apr 18 03:05:11 PM PDT 24
Peak memory 243304 kb
Host smart-51017073-c90d-4096-8ce4-8a60be86d314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962009758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3962009758
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.266377297
Short name T1357
Test name
Test status
Simulation time 10224466853 ps
CPU time 28.6 seconds
Started Apr 18 03:05:05 PM PDT 24
Finished Apr 18 03:05:33 PM PDT 24
Peak memory 357444 kb
Host smart-7755f923-c14a-41e6-961d-6259a674e136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266377297 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_tx.266377297
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3813610963
Short name T412
Test name
Test status
Simulation time 407725295 ps
CPU time 2.31 seconds
Started Apr 18 03:05:11 PM PDT 24
Finished Apr 18 03:05:14 PM PDT 24
Peak memory 204016 kb
Host smart-764d98f2-db6b-47c1-8213-c50d0f791134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813610963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3813610963
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.548954029
Short name T950
Test name
Test status
Simulation time 920687241 ps
CPU time 4.41 seconds
Started Apr 18 03:05:06 PM PDT 24
Finished Apr 18 03:05:11 PM PDT 24
Peak memory 203944 kb
Host smart-6e3a823d-625f-4223-b04f-df09a6ef473f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548954029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.548954029
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.1320774515
Short name T561
Test name
Test status
Simulation time 9168519574 ps
CPU time 3.39 seconds
Started Apr 18 03:05:04 PM PDT 24
Finished Apr 18 03:05:08 PM PDT 24
Peak memory 204052 kb
Host smart-744c7603-f922-4110-8fe5-d367f4e8ba6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320774515 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1320774515
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2385815174
Short name T496
Test name
Test status
Simulation time 9894694190 ps
CPU time 28.8 seconds
Started Apr 18 03:04:52 PM PDT 24
Finished Apr 18 03:05:21 PM PDT 24
Peak memory 204064 kb
Host smart-49b7fbab-1566-45f4-8fc9-4be5308ef2fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385815174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2385815174
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.2072786788
Short name T555
Test name
Test status
Simulation time 606176177 ps
CPU time 8.84 seconds
Started Apr 18 03:04:58 PM PDT 24
Finished Apr 18 03:05:07 PM PDT 24
Peak memory 207716 kb
Host smart-9659fa60-2be5-429b-b1c5-84b145a77ace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072786788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.2072786788
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.4158447825
Short name T564
Test name
Test status
Simulation time 10691989414 ps
CPU time 18.7 seconds
Started Apr 18 03:04:59 PM PDT 24
Finished Apr 18 03:05:18 PM PDT 24
Peak memory 203980 kb
Host smart-38566602-4d37-4986-aaa6-ec1cedbdd1ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158447825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.4158447825
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.2355338613
Short name T316
Test name
Test status
Simulation time 36710711689 ps
CPU time 26.83 seconds
Started Apr 18 03:05:05 PM PDT 24
Finished Apr 18 03:05:32 PM PDT 24
Peak memory 374572 kb
Host smart-ef39be11-d498-40ce-959a-0a64c83da247
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355338613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.2355338613
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.245880447
Short name T1199
Test name
Test status
Simulation time 9610633131 ps
CPU time 6.02 seconds
Started Apr 18 03:05:05 PM PDT 24
Finished Apr 18 03:05:11 PM PDT 24
Peak memory 209772 kb
Host smart-e2d636b2-2a8d-4be6-88a1-754b058c3474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245880447 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.245880447
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3479684435
Short name T689
Test name
Test status
Simulation time 35635212 ps
CPU time 0.61 seconds
Started Apr 18 03:12:35 PM PDT 24
Finished Apr 18 03:12:36 PM PDT 24
Peak memory 203596 kb
Host smart-4129853b-7bf0-489e-bf58-bec006cfd8af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479684435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3479684435
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.390094072
Short name T1218
Test name
Test status
Simulation time 1331708976 ps
CPU time 1.83 seconds
Started Apr 18 03:12:27 PM PDT 24
Finished Apr 18 03:12:30 PM PDT 24
Peak memory 212308 kb
Host smart-e106d9f4-4710-42c3-a370-ca3dc2306535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390094072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.390094072
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1096883299
Short name T292
Test name
Test status
Simulation time 519499630 ps
CPU time 4.84 seconds
Started Apr 18 03:12:20 PM PDT 24
Finished Apr 18 03:12:26 PM PDT 24
Peak memory 256520 kb
Host smart-a7790b9b-4bd4-4c7e-961b-b1209542976e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096883299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1096883299
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.310031146
Short name T926
Test name
Test status
Simulation time 5388889698 ps
CPU time 45.7 seconds
Started Apr 18 03:12:26 PM PDT 24
Finished Apr 18 03:13:12 PM PDT 24
Peak memory 540360 kb
Host smart-1fd58780-8e8c-4a6e-bc45-0da3de793f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310031146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.310031146
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.4154268760
Short name T663
Test name
Test status
Simulation time 6152493511 ps
CPU time 36.8 seconds
Started Apr 18 03:12:15 PM PDT 24
Finished Apr 18 03:12:53 PM PDT 24
Peak memory 515272 kb
Host smart-707d70a7-651d-484d-9619-5668815ecc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154268760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.4154268760
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3155982463
Short name T506
Test name
Test status
Simulation time 84594062 ps
CPU time 0.84 seconds
Started Apr 18 03:12:22 PM PDT 24
Finished Apr 18 03:12:23 PM PDT 24
Peak memory 203724 kb
Host smart-47336d1f-1961-409d-bc7c-2c252a2e53b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155982463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3155982463
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1165496308
Short name T795
Test name
Test status
Simulation time 493553725 ps
CPU time 2.61 seconds
Started Apr 18 03:12:24 PM PDT 24
Finished Apr 18 03:12:27 PM PDT 24
Peak memory 203892 kb
Host smart-b868ccac-1f24-43ea-8e35-8f045526ebd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165496308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1165496308
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.4014802991
Short name T1164
Test name
Test status
Simulation time 10650254104 ps
CPU time 140.83 seconds
Started Apr 18 03:12:15 PM PDT 24
Finished Apr 18 03:14:37 PM PDT 24
Peak memory 1342748 kb
Host smart-a2dc6309-47a9-4da1-bdd6-fd28819fe233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014802991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.4014802991
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.629132876
Short name T759
Test name
Test status
Simulation time 994252342 ps
CPU time 6.19 seconds
Started Apr 18 03:12:33 PM PDT 24
Finished Apr 18 03:12:40 PM PDT 24
Peak memory 203936 kb
Host smart-502ffce9-06ba-45af-862e-4edb33e49e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629132876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.629132876
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2613897781
Short name T632
Test name
Test status
Simulation time 7322766639 ps
CPU time 20.69 seconds
Started Apr 18 03:12:34 PM PDT 24
Finished Apr 18 03:12:55 PM PDT 24
Peak memory 326008 kb
Host smart-9dad604e-86d2-4e30-9c4c-f7a570aaa5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613897781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2613897781
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3866502327
Short name T347
Test name
Test status
Simulation time 2876472149 ps
CPU time 53.47 seconds
Started Apr 18 03:12:24 PM PDT 24
Finished Apr 18 03:13:18 PM PDT 24
Peak memory 212220 kb
Host smart-b339ea4e-0691-4355-a436-dd4091fdcc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866502327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3866502327
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1259985054
Short name T1197
Test name
Test status
Simulation time 4793760999 ps
CPU time 22.36 seconds
Started Apr 18 03:12:16 PM PDT 24
Finished Apr 18 03:12:39 PM PDT 24
Peak memory 301204 kb
Host smart-b2b9c158-f451-4bed-8309-e7bc79d626c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259985054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1259985054
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1298383277
Short name T231
Test name
Test status
Simulation time 15088441907 ps
CPU time 525.17 seconds
Started Apr 18 03:12:31 PM PDT 24
Finished Apr 18 03:21:17 PM PDT 24
Peak memory 1948860 kb
Host smart-12b62f42-1b8f-4470-bb7a-b6f704bbe668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298383277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1298383277
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3520284926
Short name T831
Test name
Test status
Simulation time 2253815103 ps
CPU time 16.51 seconds
Started Apr 18 03:12:24 PM PDT 24
Finished Apr 18 03:12:41 PM PDT 24
Peak memory 212272 kb
Host smart-f4a9a135-f43f-465b-8e60-590fe2c25f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520284926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3520284926
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2913412520
Short name T1024
Test name
Test status
Simulation time 429210670 ps
CPU time 2.25 seconds
Started Apr 18 03:12:30 PM PDT 24
Finished Apr 18 03:12:33 PM PDT 24
Peak memory 203968 kb
Host smart-b0e82fe6-e21b-43f1-a89a-56af60748022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913412520 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2913412520
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.853905575
Short name T1169
Test name
Test status
Simulation time 10142951488 ps
CPU time 12.6 seconds
Started Apr 18 03:12:31 PM PDT 24
Finished Apr 18 03:12:44 PM PDT 24
Peak memory 255980 kb
Host smart-7998daa8-8027-49eb-839f-758fd4c5fb89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853905575 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.853905575
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.41961371
Short name T719
Test name
Test status
Simulation time 10547931171 ps
CPU time 15.72 seconds
Started Apr 18 03:12:28 PM PDT 24
Finished Apr 18 03:12:44 PM PDT 24
Peak memory 335204 kb
Host smart-ee598d96-6e60-439e-860e-3bc0332fa0aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41961371 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_fifo_reset_tx.41961371
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1004468941
Short name T994
Test name
Test status
Simulation time 712324120 ps
CPU time 2.3 seconds
Started Apr 18 03:12:30 PM PDT 24
Finished Apr 18 03:12:33 PM PDT 24
Peak memory 204004 kb
Host smart-31b068c8-5aec-4b2b-ab75-e1d7eea3d6e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004468941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1004468941
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1332728788
Short name T810
Test name
Test status
Simulation time 4327481321 ps
CPU time 5.25 seconds
Started Apr 18 03:12:28 PM PDT 24
Finished Apr 18 03:12:34 PM PDT 24
Peak memory 219500 kb
Host smart-7b4cfb6d-e26a-417d-bb9d-1f30d9fba4bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332728788 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1332728788
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.19781566
Short name T518
Test name
Test status
Simulation time 8214713822 ps
CPU time 4.63 seconds
Started Apr 18 03:12:29 PM PDT 24
Finished Apr 18 03:12:34 PM PDT 24
Peak memory 204004 kb
Host smart-77175f68-e40a-4184-b1ad-8386ad74d3d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19781566 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.19781566
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2994257472
Short name T1035
Test name
Test status
Simulation time 4543632870 ps
CPU time 43.2 seconds
Started Apr 18 03:12:32 PM PDT 24
Finished Apr 18 03:13:16 PM PDT 24
Peak memory 204092 kb
Host smart-430b2d24-5b02-4572-ae9b-0e80d69b6cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994257472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2994257472
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3345118791
Short name T944
Test name
Test status
Simulation time 5494752077 ps
CPU time 25.34 seconds
Started Apr 18 03:12:31 PM PDT 24
Finished Apr 18 03:12:57 PM PDT 24
Peak memory 222008 kb
Host smart-05628272-abf9-4208-a273-807ecf8f0de6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345118791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3345118791
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2218053377
Short name T560
Test name
Test status
Simulation time 25754393570 ps
CPU time 12.67 seconds
Started Apr 18 03:12:30 PM PDT 24
Finished Apr 18 03:12:43 PM PDT 24
Peak memory 273292 kb
Host smart-aa3e63ed-e8c7-41c5-9e32-66094a34a24c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218053377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2218053377
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3918782749
Short name T401
Test name
Test status
Simulation time 27067947656 ps
CPU time 2135.98 seconds
Started Apr 18 03:12:30 PM PDT 24
Finished Apr 18 03:48:07 PM PDT 24
Peak memory 6566216 kb
Host smart-7a4b452c-bca7-4f4c-84d2-a3d316f611c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918782749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3918782749
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1265316361
Short name T701
Test name
Test status
Simulation time 1339827034 ps
CPU time 5.38 seconds
Started Apr 18 03:12:32 PM PDT 24
Finished Apr 18 03:12:37 PM PDT 24
Peak memory 207852 kb
Host smart-bdd1adc7-2b0c-48a6-a00c-608cd10e2edf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265316361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1265316361
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.773702069
Short name T873
Test name
Test status
Simulation time 66011036 ps
CPU time 0.61 seconds
Started Apr 18 03:12:56 PM PDT 24
Finished Apr 18 03:12:58 PM PDT 24
Peak memory 203564 kb
Host smart-99e9b3e8-e2b9-4c9f-a1b8-a061d7827f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773702069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.773702069
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1057207346
Short name T542
Test name
Test status
Simulation time 112367490 ps
CPU time 1.7 seconds
Started Apr 18 03:12:40 PM PDT 24
Finished Apr 18 03:12:42 PM PDT 24
Peak memory 204068 kb
Host smart-12fb3f65-184d-43b6-8b54-cb00073e1b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057207346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1057207346
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.261307722
Short name T755
Test name
Test status
Simulation time 517834888 ps
CPU time 5.51 seconds
Started Apr 18 03:12:35 PM PDT 24
Finished Apr 18 03:12:41 PM PDT 24
Peak memory 260512 kb
Host smart-607c6741-b1b9-4de0-9f94-d61d862e584a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261307722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.261307722
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3202113714
Short name T882
Test name
Test status
Simulation time 4776836160 ps
CPU time 38.13 seconds
Started Apr 18 03:12:34 PM PDT 24
Finished Apr 18 03:13:12 PM PDT 24
Peak memory 502688 kb
Host smart-7b9dba98-8b63-4f88-a29b-8176cacf71f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202113714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3202113714
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2926273370
Short name T273
Test name
Test status
Simulation time 2155670008 ps
CPU time 62.78 seconds
Started Apr 18 03:12:34 PM PDT 24
Finished Apr 18 03:13:37 PM PDT 24
Peak memory 732280 kb
Host smart-56d1af44-20fc-47af-aec8-ca110cd7c658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926273370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2926273370
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.4212772775
Short name T946
Test name
Test status
Simulation time 215187876 ps
CPU time 0.99 seconds
Started Apr 18 03:12:33 PM PDT 24
Finished Apr 18 03:12:35 PM PDT 24
Peak memory 203732 kb
Host smart-cdbbaaa0-8612-40cc-bdb1-97633029ae5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212772775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.4212772775
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1752311507
Short name T929
Test name
Test status
Simulation time 224938071 ps
CPU time 6.94 seconds
Started Apr 18 03:12:35 PM PDT 24
Finished Apr 18 03:12:43 PM PDT 24
Peak memory 222648 kb
Host smart-33dc00ec-d020-4b95-9b73-1776310fbc66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752311507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1752311507
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2062114939
Short name T175
Test name
Test status
Simulation time 7533420682 ps
CPU time 74.71 seconds
Started Apr 18 03:12:33 PM PDT 24
Finished Apr 18 03:13:49 PM PDT 24
Peak memory 1008168 kb
Host smart-830da621-8204-4f61-8eff-32367727efa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062114939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2062114939
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2343911190
Short name T313
Test name
Test status
Simulation time 1360146995 ps
CPU time 13.82 seconds
Started Apr 18 03:12:52 PM PDT 24
Finished Apr 18 03:13:08 PM PDT 24
Peak memory 203972 kb
Host smart-cdcf25b2-3ae2-403e-92e6-05417f25f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343911190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2343911190
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3618262091
Short name T955
Test name
Test status
Simulation time 1671201962 ps
CPU time 31.08 seconds
Started Apr 18 03:12:49 PM PDT 24
Finished Apr 18 03:13:21 PM PDT 24
Peak memory 430472 kb
Host smart-79e4ad61-cb03-4082-9cd9-b7b2760cbb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618262091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3618262091
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2286951594
Short name T1349
Test name
Test status
Simulation time 17314534 ps
CPU time 0.61 seconds
Started Apr 18 03:12:36 PM PDT 24
Finished Apr 18 03:12:37 PM PDT 24
Peak memory 203672 kb
Host smart-16894842-106f-4c65-b795-2234bcba01da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286951594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2286951594
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.892322987
Short name T791
Test name
Test status
Simulation time 26731261958 ps
CPU time 1513.94 seconds
Started Apr 18 03:12:39 PM PDT 24
Finished Apr 18 03:37:54 PM PDT 24
Peak memory 905256 kb
Host smart-99a2a0d8-6746-4f3f-b0d2-cc63b24260d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892322987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.892322987
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.571550737
Short name T472
Test name
Test status
Simulation time 1404569027 ps
CPU time 24.62 seconds
Started Apr 18 03:12:33 PM PDT 24
Finished Apr 18 03:12:58 PM PDT 24
Peak memory 305656 kb
Host smart-3be7d35f-8e90-453d-a489-09678431a295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571550737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.571550737
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1805835490
Short name T1157
Test name
Test status
Simulation time 27736510229 ps
CPU time 409.28 seconds
Started Apr 18 03:12:43 PM PDT 24
Finished Apr 18 03:19:33 PM PDT 24
Peak memory 1631032 kb
Host smart-b2e8ac27-9d01-45ea-abfe-a78da2e5e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805835490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1805835490
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.237653796
Short name T420
Test name
Test status
Simulation time 489990642 ps
CPU time 7.88 seconds
Started Apr 18 03:12:40 PM PDT 24
Finished Apr 18 03:12:48 PM PDT 24
Peak memory 212780 kb
Host smart-15e548f7-a650-4902-8102-9c6f360a5b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237653796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.237653796
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3740199373
Short name T1367
Test name
Test status
Simulation time 560889885 ps
CPU time 1.8 seconds
Started Apr 18 03:12:50 PM PDT 24
Finished Apr 18 03:12:53 PM PDT 24
Peak memory 204028 kb
Host smart-a24495c4-0a69-4697-b411-3515fd7ff925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740199373 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3740199373
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.64310152
Short name T1118
Test name
Test status
Simulation time 10155396615 ps
CPU time 19.85 seconds
Started Apr 18 03:12:53 PM PDT 24
Finished Apr 18 03:13:14 PM PDT 24
Peak memory 297480 kb
Host smart-1f7c9b7c-03fc-4ca9-b692-9aecae25a07c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64310152 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_acq.64310152
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.592056515
Short name T1366
Test name
Test status
Simulation time 789318971 ps
CPU time 2.26 seconds
Started Apr 18 03:12:53 PM PDT 24
Finished Apr 18 03:12:56 PM PDT 24
Peak memory 203908 kb
Host smart-6da1ce01-a6d9-492b-b10a-3bc642dc08a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592056515 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.592056515
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3379960560
Short name T934
Test name
Test status
Simulation time 2082372641 ps
CPU time 5.14 seconds
Started Apr 18 03:12:47 PM PDT 24
Finished Apr 18 03:12:52 PM PDT 24
Peak memory 213796 kb
Host smart-bad9924a-d824-4c7f-aa83-2018d8426e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379960560 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3379960560
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3104637959
Short name T998
Test name
Test status
Simulation time 5332996705 ps
CPU time 5.8 seconds
Started Apr 18 03:12:43 PM PDT 24
Finished Apr 18 03:12:50 PM PDT 24
Peak memory 204060 kb
Host smart-37f48bd2-8c50-44c0-a182-5be27a8c33d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104637959 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3104637959
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.4160218063
Short name T414
Test name
Test status
Simulation time 4145389665 ps
CPU time 32.85 seconds
Started Apr 18 03:12:46 PM PDT 24
Finished Apr 18 03:13:19 PM PDT 24
Peak memory 204020 kb
Host smart-48ac4ab2-b0e4-48c5-b297-a6655fb43d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160218063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.4160218063
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.305368773
Short name T1213
Test name
Test status
Simulation time 5560182010 ps
CPU time 57.12 seconds
Started Apr 18 03:12:45 PM PDT 24
Finished Apr 18 03:13:42 PM PDT 24
Peak memory 206000 kb
Host smart-a2580c7b-8834-43b9-ae82-a525a3e6fb83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305368773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.305368773
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.240096051
Short name T1350
Test name
Test status
Simulation time 49318928274 ps
CPU time 95.02 seconds
Started Apr 18 03:12:43 PM PDT 24
Finished Apr 18 03:14:19 PM PDT 24
Peak memory 1361328 kb
Host smart-124d50fb-d645-4674-873b-df97e28d3c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240096051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.240096051
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3926258099
Short name T1152
Test name
Test status
Simulation time 33514586713 ps
CPU time 230.01 seconds
Started Apr 18 03:12:45 PM PDT 24
Finished Apr 18 03:16:36 PM PDT 24
Peak memory 1803036 kb
Host smart-904ad020-9680-48a2-af9b-355760c09ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926258099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3926258099
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3293902346
Short name T344
Test name
Test status
Simulation time 1125682183 ps
CPU time 6.42 seconds
Started Apr 18 03:12:48 PM PDT 24
Finished Apr 18 03:12:55 PM PDT 24
Peak memory 220208 kb
Host smart-b3202d01-6ac1-4f7f-9bfa-99a26855ead7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293902346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3293902346
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.4145188918
Short name T1191
Test name
Test status
Simulation time 147750016 ps
CPU time 0.6 seconds
Started Apr 18 03:13:09 PM PDT 24
Finished Apr 18 03:13:10 PM PDT 24
Peak memory 203572 kb
Host smart-c0c8ccca-4175-48a6-9692-6dc67329846c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145188918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.4145188918
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2944888354
Short name T470
Test name
Test status
Simulation time 119854718 ps
CPU time 1.71 seconds
Started Apr 18 03:12:59 PM PDT 24
Finished Apr 18 03:13:01 PM PDT 24
Peak memory 212264 kb
Host smart-dc3bdbde-4cbc-4508-9243-2719f29e0ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944888354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2944888354
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3406715706
Short name T1230
Test name
Test status
Simulation time 475485819 ps
CPU time 9.96 seconds
Started Apr 18 03:12:58 PM PDT 24
Finished Apr 18 03:13:09 PM PDT 24
Peak memory 308516 kb
Host smart-26924f1d-2f3d-4e5a-ab47-5c78dbf7be4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406715706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3406715706
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2220528756
Short name T868
Test name
Test status
Simulation time 6257940626 ps
CPU time 94.23 seconds
Started Apr 18 03:12:57 PM PDT 24
Finished Apr 18 03:14:32 PM PDT 24
Peak memory 545716 kb
Host smart-c17165f1-3111-476a-b267-f5a66630b63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220528756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2220528756
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1098583555
Short name T366
Test name
Test status
Simulation time 1244764665 ps
CPU time 38.94 seconds
Started Apr 18 03:12:54 PM PDT 24
Finished Apr 18 03:13:34 PM PDT 24
Peak memory 509880 kb
Host smart-63c0f431-7e63-4442-a5d2-104cd77f013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098583555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1098583555
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.207725343
Short name T915
Test name
Test status
Simulation time 1563058182 ps
CPU time 1.06 seconds
Started Apr 18 03:13:00 PM PDT 24
Finished Apr 18 03:13:01 PM PDT 24
Peak memory 203832 kb
Host smart-94e46c53-d898-4a65-b2ff-b021fb5548ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207725343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.207725343
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2296924738
Short name T1074
Test name
Test status
Simulation time 376071946 ps
CPU time 5.57 seconds
Started Apr 18 03:13:00 PM PDT 24
Finished Apr 18 03:13:06 PM PDT 24
Peak memory 217928 kb
Host smart-4a0f5b37-6a0e-4dd9-9624-8dcaabeda1f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296924738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2296924738
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.921940042
Short name T1253
Test name
Test status
Simulation time 3643095746 ps
CPU time 57.21 seconds
Started Apr 18 03:12:54 PM PDT 24
Finished Apr 18 03:13:52 PM PDT 24
Peak memory 745940 kb
Host smart-dd917ea9-e0f6-4c52-b100-a9bea600637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921940042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.921940042
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3855163075
Short name T793
Test name
Test status
Simulation time 978376094 ps
CPU time 19.49 seconds
Started Apr 18 03:13:09 PM PDT 24
Finished Apr 18 03:13:28 PM PDT 24
Peak memory 203952 kb
Host smart-9776d3a2-c469-477c-9076-ced6fce8dba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855163075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3855163075
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.1288285628
Short name T584
Test name
Test status
Simulation time 1529408617 ps
CPU time 29.76 seconds
Started Apr 18 03:13:09 PM PDT 24
Finished Apr 18 03:13:39 PM PDT 24
Peak memory 335024 kb
Host smart-9af55bae-b071-4b89-b748-ba6c52f6b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288285628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.1288285628
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2205658839
Short name T190
Test name
Test status
Simulation time 26558624 ps
CPU time 0.62 seconds
Started Apr 18 03:12:53 PM PDT 24
Finished Apr 18 03:12:55 PM PDT 24
Peak memory 203652 kb
Host smart-7b29c7d2-283b-492a-8de5-0e5703ad93b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205658839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2205658839
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3131221878
Short name T1053
Test name
Test status
Simulation time 5526825944 ps
CPU time 164.4 seconds
Started Apr 18 03:12:58 PM PDT 24
Finished Apr 18 03:15:43 PM PDT 24
Peak memory 834020 kb
Host smart-c4cdbf7d-3e98-4f5d-8c83-d6b2468714bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131221878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3131221878
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.137371756
Short name T878
Test name
Test status
Simulation time 1431890680 ps
CPU time 22.36 seconds
Started Apr 18 03:12:54 PM PDT 24
Finished Apr 18 03:13:17 PM PDT 24
Peak memory 329476 kb
Host smart-01f902b1-ef9d-4a73-b3ff-9fdb93384a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137371756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.137371756
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3280430726
Short name T230
Test name
Test status
Simulation time 43259111027 ps
CPU time 1375.82 seconds
Started Apr 18 03:12:58 PM PDT 24
Finished Apr 18 03:35:54 PM PDT 24
Peak memory 1775512 kb
Host smart-910be4bb-845b-4c1f-b856-ee8d0c6ee9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280430726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3280430726
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2073925675
Short name T1049
Test name
Test status
Simulation time 1603620331 ps
CPU time 12.32 seconds
Started Apr 18 03:13:00 PM PDT 24
Finished Apr 18 03:13:12 PM PDT 24
Peak memory 228476 kb
Host smart-83c1a4c4-150b-4de0-b902-c4931cf4884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073925675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2073925675
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.904123775
Short name T263
Test name
Test status
Simulation time 4276587645 ps
CPU time 5.62 seconds
Started Apr 18 03:13:11 PM PDT 24
Finished Apr 18 03:13:17 PM PDT 24
Peak memory 207408 kb
Host smart-ca8a8b78-f294-4009-950c-8bb990fcaed5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904123775 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.904123775
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3200913867
Short name T409
Test name
Test status
Simulation time 10210325268 ps
CPU time 13.13 seconds
Started Apr 18 03:13:12 PM PDT 24
Finished Apr 18 03:13:26 PM PDT 24
Peak memory 259016 kb
Host smart-6302927b-7166-425d-9298-df67dc5131a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200913867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3200913867
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.543046305
Short name T741
Test name
Test status
Simulation time 10276832450 ps
CPU time 13 seconds
Started Apr 18 03:13:09 PM PDT 24
Finished Apr 18 03:13:23 PM PDT 24
Peak memory 309100 kb
Host smart-b2056496-4569-4fa6-b4ac-634112d71ab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543046305 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.543046305
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.598955721
Short name T1245
Test name
Test status
Simulation time 1461533419 ps
CPU time 2.29 seconds
Started Apr 18 03:13:09 PM PDT 24
Finished Apr 18 03:13:11 PM PDT 24
Peak memory 203928 kb
Host smart-7c2449d7-f7c3-4b1f-9abb-f1a6a27aae5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598955721 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.598955721
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3700730987
Short name T681
Test name
Test status
Simulation time 18916395210 ps
CPU time 4.65 seconds
Started Apr 18 03:13:04 PM PDT 24
Finished Apr 18 03:13:09 PM PDT 24
Peak memory 212272 kb
Host smart-18f73401-c1ae-40d9-8f30-ba5b8871a6e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700730987 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3700730987
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2910646288
Short name T801
Test name
Test status
Simulation time 12266681807 ps
CPU time 10.7 seconds
Started Apr 18 03:13:02 PM PDT 24
Finished Apr 18 03:13:13 PM PDT 24
Peak memory 317876 kb
Host smart-d1e80219-14ba-42bc-b9e9-4bd8cf83e042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910646288 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2910646288
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.682278793
Short name T418
Test name
Test status
Simulation time 1531447106 ps
CPU time 14.3 seconds
Started Apr 18 03:13:04 PM PDT 24
Finished Apr 18 03:13:18 PM PDT 24
Peak memory 203996 kb
Host smart-6a3327ac-a34c-40e2-ab65-44a812a559a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682278793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.682278793
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2234348909
Short name T1193
Test name
Test status
Simulation time 5867106942 ps
CPU time 32.63 seconds
Started Apr 18 03:13:05 PM PDT 24
Finished Apr 18 03:13:38 PM PDT 24
Peak memory 204040 kb
Host smart-3885082d-afa4-4010-b544-70c89b599c68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234348909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2234348909
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2838107853
Short name T387
Test name
Test status
Simulation time 50065970611 ps
CPU time 1144.44 seconds
Started Apr 18 03:13:04 PM PDT 24
Finished Apr 18 03:32:09 PM PDT 24
Peak memory 7724188 kb
Host smart-e3a4ac91-ff9b-462a-a8f4-bab39c5ed2ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838107853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2838107853
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3457293782
Short name T348
Test name
Test status
Simulation time 13265999101 ps
CPU time 172.68 seconds
Started Apr 18 03:13:04 PM PDT 24
Finished Apr 18 03:15:57 PM PDT 24
Peak memory 1365364 kb
Host smart-8f87c27c-5169-42e6-bc37-31e6846985cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457293782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3457293782
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1152592391
Short name T4
Test name
Test status
Simulation time 5864021450 ps
CPU time 6.77 seconds
Started Apr 18 03:13:10 PM PDT 24
Finished Apr 18 03:13:18 PM PDT 24
Peak memory 220052 kb
Host smart-c949b876-9ef0-410a-9fcb-537b6c2d6bef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152592391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1152592391
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1884470959
Short name T1072
Test name
Test status
Simulation time 22790317 ps
CPU time 0.61 seconds
Started Apr 18 03:13:30 PM PDT 24
Finished Apr 18 03:13:31 PM PDT 24
Peak memory 203572 kb
Host smart-0e8e8524-4ea4-4415-b307-66d4428d8120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884470959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1884470959
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2572108801
Short name T669
Test name
Test status
Simulation time 662722415 ps
CPU time 1.38 seconds
Started Apr 18 03:13:20 PM PDT 24
Finished Apr 18 03:13:22 PM PDT 24
Peak memory 220428 kb
Host smart-887d2065-6e8c-4213-a1b7-97c8cd6cb3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572108801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2572108801
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.511298168
Short name T280
Test name
Test status
Simulation time 500925652 ps
CPU time 13.41 seconds
Started Apr 18 03:13:16 PM PDT 24
Finished Apr 18 03:13:30 PM PDT 24
Peak memory 256224 kb
Host smart-dcf6317e-318a-444f-a547-c76b6d15d46b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511298168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.511298168
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2439299239
Short name T525
Test name
Test status
Simulation time 9298326684 ps
CPU time 142.63 seconds
Started Apr 18 03:13:16 PM PDT 24
Finished Apr 18 03:15:39 PM PDT 24
Peak memory 688964 kb
Host smart-2a87f0d5-b737-456f-b37c-28f5429d04ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439299239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2439299239
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2624448568
Short name T775
Test name
Test status
Simulation time 3529900929 ps
CPU time 118.76 seconds
Started Apr 18 03:13:13 PM PDT 24
Finished Apr 18 03:15:13 PM PDT 24
Peak memory 597352 kb
Host smart-6d12c80d-5cbb-4e75-b30b-4e478cb3deaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624448568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2624448568
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2308827296
Short name T1076
Test name
Test status
Simulation time 1565238414 ps
CPU time 0.86 seconds
Started Apr 18 03:13:15 PM PDT 24
Finished Apr 18 03:13:16 PM PDT 24
Peak memory 203728 kb
Host smart-ffff699b-3717-41ec-bf05-ed83bd876126
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308827296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2308827296
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.249233632
Short name T497
Test name
Test status
Simulation time 584934925 ps
CPU time 4.39 seconds
Started Apr 18 03:13:16 PM PDT 24
Finished Apr 18 03:13:21 PM PDT 24
Peak memory 231308 kb
Host smart-13171271-2a45-4095-b1dd-1af488f4899a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249233632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
249233632
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2005749567
Short name T788
Test name
Test status
Simulation time 13563082502 ps
CPU time 86.18 seconds
Started Apr 18 03:13:13 PM PDT 24
Finished Apr 18 03:14:39 PM PDT 24
Peak memory 1082624 kb
Host smart-7aed07af-e856-4f43-aea2-3e6b485f92b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005749567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2005749567
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1469776034
Short name T219
Test name
Test status
Simulation time 537237961 ps
CPU time 4.19 seconds
Started Apr 18 03:13:28 PM PDT 24
Finished Apr 18 03:13:33 PM PDT 24
Peak memory 203984 kb
Host smart-9603395d-01dc-49e4-b5d1-158b3befd61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469776034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1469776034
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2022473731
Short name T508
Test name
Test status
Simulation time 20696045350 ps
CPU time 18.76 seconds
Started Apr 18 03:13:30 PM PDT 24
Finished Apr 18 03:13:49 PM PDT 24
Peak memory 341572 kb
Host smart-9070245e-2b79-4094-8153-35a14a6aa476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022473731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2022473731
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.3200919770
Short name T1342
Test name
Test status
Simulation time 23231592 ps
CPU time 0.61 seconds
Started Apr 18 03:13:09 PM PDT 24
Finished Apr 18 03:13:10 PM PDT 24
Peak memory 203664 kb
Host smart-db65422e-c600-4797-aa9e-71703a277133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200919770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3200919770
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1293765827
Short name T609
Test name
Test status
Simulation time 6539104650 ps
CPU time 23.58 seconds
Started Apr 18 03:13:17 PM PDT 24
Finished Apr 18 03:13:41 PM PDT 24
Peak memory 213004 kb
Host smart-8c33484d-ec3f-43b7-b612-d8487ca9fe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293765827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1293765827
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1538428079
Short name T1104
Test name
Test status
Simulation time 1466485827 ps
CPU time 21.18 seconds
Started Apr 18 03:13:09 PM PDT 24
Finished Apr 18 03:13:31 PM PDT 24
Peak memory 301324 kb
Host smart-91072fbd-2634-4484-96bb-66c338fe5e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538428079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1538428079
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1891869201
Short name T180
Test name
Test status
Simulation time 131107071873 ps
CPU time 267.07 seconds
Started Apr 18 03:13:20 PM PDT 24
Finished Apr 18 03:17:47 PM PDT 24
Peak memory 1361140 kb
Host smart-d3ff1d84-ee50-4287-ac99-a5f01e3cdd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891869201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1891869201
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2943333634
Short name T377
Test name
Test status
Simulation time 1001730550 ps
CPU time 22.86 seconds
Started Apr 18 03:13:19 PM PDT 24
Finished Apr 18 03:13:42 PM PDT 24
Peak memory 212228 kb
Host smart-0eadf555-eb34-425c-9615-6623bb66186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943333634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2943333634
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2611427137
Short name T278
Test name
Test status
Simulation time 3841577549 ps
CPU time 4.25 seconds
Started Apr 18 03:13:35 PM PDT 24
Finished Apr 18 03:13:40 PM PDT 24
Peak memory 212220 kb
Host smart-43a48dd9-0039-4961-b7ad-a6624f632a55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611427137 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2611427137
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2425712221
Short name T200
Test name
Test status
Simulation time 10118905099 ps
CPU time 43.31 seconds
Started Apr 18 03:13:29 PM PDT 24
Finished Apr 18 03:14:13 PM PDT 24
Peak memory 420452 kb
Host smart-357d9985-11ae-4144-a9f8-5466fb33a5f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425712221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2425712221
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2825209209
Short name T33
Test name
Test status
Simulation time 3197327205 ps
CPU time 2.48 seconds
Started Apr 18 03:13:30 PM PDT 24
Finished Apr 18 03:13:33 PM PDT 24
Peak memory 204012 kb
Host smart-36d34d62-d615-4723-800d-398572d21efd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825209209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2825209209
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.511807260
Short name T923
Test name
Test status
Simulation time 1196658101 ps
CPU time 3.33 seconds
Started Apr 18 03:13:24 PM PDT 24
Finished Apr 18 03:13:28 PM PDT 24
Peak memory 204580 kb
Host smart-2a58a7d4-c8fb-45f3-af10-ddd98af2f777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511807260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.511807260
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1239829626
Short name T995
Test name
Test status
Simulation time 17977960845 ps
CPU time 121.81 seconds
Started Apr 18 03:13:26 PM PDT 24
Finished Apr 18 03:15:28 PM PDT 24
Peak memory 1536768 kb
Host smart-dbdcb42c-88a3-463b-af25-0b22a11c5d82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239829626 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1239829626
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.4067354076
Short name T309
Test name
Test status
Simulation time 865300942 ps
CPU time 10.83 seconds
Started Apr 18 03:13:19 PM PDT 24
Finished Apr 18 03:13:30 PM PDT 24
Peak memory 203932 kb
Host smart-0c3f9f2d-e524-4f8a-87ad-df3a75373aae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067354076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.4067354076
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3563294792
Short name T1250
Test name
Test status
Simulation time 1960555055 ps
CPU time 17.74 seconds
Started Apr 18 03:13:18 PM PDT 24
Finished Apr 18 03:13:37 PM PDT 24
Peak memory 211728 kb
Host smart-e97679c0-fbff-4656-a336-f80f8218cdce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563294792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3563294792
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1261889916
Short name T1244
Test name
Test status
Simulation time 61163368146 ps
CPU time 274.79 seconds
Started Apr 18 03:13:20 PM PDT 24
Finished Apr 18 03:17:55 PM PDT 24
Peak memory 2830972 kb
Host smart-812ce9a6-37e7-4fa1-a070-afd643249eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261889916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1261889916
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.4183385265
Short name T1196
Test name
Test status
Simulation time 4230575182 ps
CPU time 6.22 seconds
Started Apr 18 03:13:24 PM PDT 24
Finished Apr 18 03:13:31 PM PDT 24
Peak memory 204020 kb
Host smart-409cca76-e50f-4ee0-bace-385370f74394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183385265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.4183385265
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.1944103711
Short name T1335
Test name
Test status
Simulation time 896407671 ps
CPU time 4.57 seconds
Started Apr 18 03:13:24 PM PDT 24
Finished Apr 18 03:13:29 PM PDT 24
Peak memory 207444 kb
Host smart-a698b05c-fab4-4b0e-b61e-1b90bca64cfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944103711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.1944103711
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1603096074
Short name T1192
Test name
Test status
Simulation time 22511568 ps
CPU time 0.59 seconds
Started Apr 18 03:13:44 PM PDT 24
Finished Apr 18 03:13:45 PM PDT 24
Peak memory 203600 kb
Host smart-8189c77b-095a-4af0-8945-cdef60cd044a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603096074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1603096074
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3005464511
Short name T299
Test name
Test status
Simulation time 1211407707 ps
CPU time 1.77 seconds
Started Apr 18 03:13:33 PM PDT 24
Finished Apr 18 03:13:35 PM PDT 24
Peak memory 212260 kb
Host smart-da8fe404-a6cd-460b-8cb5-4494405d8cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005464511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3005464511
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.4291229620
Short name T714
Test name
Test status
Simulation time 120116285 ps
CPU time 5.81 seconds
Started Apr 18 03:13:37 PM PDT 24
Finished Apr 18 03:13:43 PM PDT 24
Peak memory 218684 kb
Host smart-e18b9292-b82b-467e-9fdc-8059e29f7845
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291229620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.4291229620
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1155811574
Short name T51
Test name
Test status
Simulation time 8127164762 ps
CPU time 128.9 seconds
Started Apr 18 03:13:33 PM PDT 24
Finished Apr 18 03:15:43 PM PDT 24
Peak memory 650656 kb
Host smart-ed977d27-b087-46f6-8309-d7dfb048594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155811574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1155811574
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3653140622
Short name T1264
Test name
Test status
Simulation time 12635781768 ps
CPU time 38.73 seconds
Started Apr 18 03:13:35 PM PDT 24
Finished Apr 18 03:14:14 PM PDT 24
Peak memory 499988 kb
Host smart-62016b70-606a-4058-94f0-cef75d419ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653140622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3653140622
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3433153633
Short name T854
Test name
Test status
Simulation time 98910826 ps
CPU time 0.93 seconds
Started Apr 18 03:13:35 PM PDT 24
Finished Apr 18 03:13:36 PM PDT 24
Peak memory 203680 kb
Host smart-b61982e2-9aab-4ca8-8eff-629e87578b66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433153633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3433153633
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3311368595
Short name T84
Test name
Test status
Simulation time 321820597 ps
CPU time 7.61 seconds
Started Apr 18 03:13:33 PM PDT 24
Finished Apr 18 03:13:42 PM PDT 24
Peak memory 203892 kb
Host smart-625127af-d54c-4d57-87a6-84b9d571360f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311368595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3311368595
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1207881522
Short name T460
Test name
Test status
Simulation time 10602868549 ps
CPU time 150.8 seconds
Started Apr 18 03:13:34 PM PDT 24
Finished Apr 18 03:16:06 PM PDT 24
Peak memory 712120 kb
Host smart-4ef4c543-e2aa-491f-9586-9e429b0ca6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207881522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1207881522
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1076377584
Short name T932
Test name
Test status
Simulation time 223220400 ps
CPU time 3.82 seconds
Started Apr 18 03:13:44 PM PDT 24
Finished Apr 18 03:13:48 PM PDT 24
Peak memory 203972 kb
Host smart-5d974bd7-6ac1-4a5d-9a46-f67c2460ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076377584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1076377584
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2495587040
Short name T94
Test name
Test status
Simulation time 12161514842 ps
CPU time 28.32 seconds
Started Apr 18 03:13:46 PM PDT 24
Finished Apr 18 03:14:14 PM PDT 24
Peak memory 313272 kb
Host smart-2c20e093-a71d-4b32-891a-dff446ee4604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495587040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2495587040
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1406162426
Short name T400
Test name
Test status
Simulation time 15077960 ps
CPU time 0.62 seconds
Started Apr 18 03:13:36 PM PDT 24
Finished Apr 18 03:13:37 PM PDT 24
Peak memory 203648 kb
Host smart-b26af2d0-a29b-4b1e-a056-1c2e9d629faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406162426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1406162426
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2072104315
Short name T1232
Test name
Test status
Simulation time 2582853138 ps
CPU time 103.49 seconds
Started Apr 18 03:13:38 PM PDT 24
Finished Apr 18 03:15:21 PM PDT 24
Peak memory 220848 kb
Host smart-6fa66065-d35b-4881-85d7-600d1533b05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072104315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2072104315
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2395121837
Short name T310
Test name
Test status
Simulation time 3607201658 ps
CPU time 16.29 seconds
Started Apr 18 03:13:30 PM PDT 24
Finished Apr 18 03:13:47 PM PDT 24
Peak memory 280672 kb
Host smart-c3a57cbd-031c-4099-8e9c-a76f0e496c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395121837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2395121837
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2365271553
Short name T199
Test name
Test status
Simulation time 77577073239 ps
CPU time 979.83 seconds
Started Apr 18 03:13:35 PM PDT 24
Finished Apr 18 03:29:55 PM PDT 24
Peak memory 1509656 kb
Host smart-63ad23ed-2f92-4c89-8640-70e0b4111c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365271553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2365271553
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3525233393
Short name T1131
Test name
Test status
Simulation time 2264657393 ps
CPU time 8.62 seconds
Started Apr 18 03:13:36 PM PDT 24
Finished Apr 18 03:13:45 PM PDT 24
Peak memory 217284 kb
Host smart-47ab3f3e-78bd-466e-b8ed-1ad2f438f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525233393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3525233393
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3953502862
Short name T511
Test name
Test status
Simulation time 1367311280 ps
CPU time 3.62 seconds
Started Apr 18 03:13:44 PM PDT 24
Finished Apr 18 03:13:48 PM PDT 24
Peak memory 204048 kb
Host smart-52139362-1cea-425f-a3c5-8a33046c6036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953502862 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3953502862
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.2630593782
Short name T931
Test name
Test status
Simulation time 10093534361 ps
CPU time 10.8 seconds
Started Apr 18 03:13:44 PM PDT 24
Finished Apr 18 03:13:55 PM PDT 24
Peak memory 267700 kb
Host smart-5f419f33-cc3e-42ee-9f25-07f1eb8d036a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630593782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.2630593782
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.27812836
Short name T466
Test name
Test status
Simulation time 10075838318 ps
CPU time 85.99 seconds
Started Apr 18 03:13:45 PM PDT 24
Finished Apr 18 03:15:11 PM PDT 24
Peak memory 553052 kb
Host smart-c208a2fd-5805-4891-8b0a-b6037940cdbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27812836 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_fifo_reset_tx.27812836
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2104375797
Short name T957
Test name
Test status
Simulation time 438057508 ps
CPU time 2.56 seconds
Started Apr 18 03:13:46 PM PDT 24
Finished Apr 18 03:13:49 PM PDT 24
Peak memory 204008 kb
Host smart-e6c802f0-96b8-4615-a86d-d49e61e8632d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104375797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2104375797
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1515320766
Short name T726
Test name
Test status
Simulation time 2622649379 ps
CPU time 7.73 seconds
Started Apr 18 03:13:40 PM PDT 24
Finished Apr 18 03:13:48 PM PDT 24
Peak memory 220272 kb
Host smart-504a30e6-66d6-4432-84fe-8088b2d0c7da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515320766 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1515320766
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1472782648
Short name T371
Test name
Test status
Simulation time 14731673532 ps
CPU time 58.92 seconds
Started Apr 18 03:13:50 PM PDT 24
Finished Apr 18 03:14:49 PM PDT 24
Peak memory 1008848 kb
Host smart-ab19f8f1-a42b-4eca-a718-0f41c4e49a17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472782648 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1472782648
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2099990258
Short name T1075
Test name
Test status
Simulation time 645793031 ps
CPU time 7.08 seconds
Started Apr 18 03:13:41 PM PDT 24
Finished Apr 18 03:13:49 PM PDT 24
Peak memory 203988 kb
Host smart-75cbdec9-c04d-4fe0-a986-0e10e3172c01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099990258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2099990258
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2028519643
Short name T489
Test name
Test status
Simulation time 229322861 ps
CPU time 9.97 seconds
Started Apr 18 03:13:38 PM PDT 24
Finished Apr 18 03:13:49 PM PDT 24
Peak memory 203948 kb
Host smart-4d8a97ea-8ebc-47ef-a93c-a082a0992830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028519643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2028519643
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.594592496
Short name T649
Test name
Test status
Simulation time 54208638507 ps
CPU time 1527.5 seconds
Started Apr 18 03:13:40 PM PDT 24
Finished Apr 18 03:39:09 PM PDT 24
Peak memory 8748316 kb
Host smart-e3de5d92-83be-4fb0-aafc-f605539173dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594592496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.594592496
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2762635079
Short name T742
Test name
Test status
Simulation time 28448730563 ps
CPU time 1722.99 seconds
Started Apr 18 03:13:40 PM PDT 24
Finished Apr 18 03:42:24 PM PDT 24
Peak memory 7031248 kb
Host smart-b48494ef-7be4-4909-9cea-0e5556f8e76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762635079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2762635079
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.998305841
Short name T818
Test name
Test status
Simulation time 2628201554 ps
CPU time 5.99 seconds
Started Apr 18 03:13:43 PM PDT 24
Finished Apr 18 03:13:50 PM PDT 24
Peak memory 210940 kb
Host smart-8f2f2615-d7a9-4cd7-bb8c-2647e60b5d87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998305841 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.998305841
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.1853302506
Short name T1238
Test name
Test status
Simulation time 2558381254 ps
CPU time 3.65 seconds
Started Apr 18 03:13:45 PM PDT 24
Finished Apr 18 03:13:49 PM PDT 24
Peak memory 204096 kb
Host smart-c4685d50-a049-4b8b-9df0-4a6ee0a7a6c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853302506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.i2c_target_unexp_stop.1853302506
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1127889742
Short name T1059
Test name
Test status
Simulation time 25245314 ps
CPU time 0.66 seconds
Started Apr 18 03:14:04 PM PDT 24
Finished Apr 18 03:14:05 PM PDT 24
Peak memory 203560 kb
Host smart-4b0a8d0a-9878-4edf-9351-40ac6c966b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127889742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1127889742
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.721767926
Short name T858
Test name
Test status
Simulation time 43400962 ps
CPU time 1.11 seconds
Started Apr 18 03:13:56 PM PDT 24
Finished Apr 18 03:13:57 PM PDT 24
Peak memory 204088 kb
Host smart-9d298c1e-fb9d-404c-93b9-8068e8cd77db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721767926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.721767926
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.510724507
Short name T899
Test name
Test status
Simulation time 383365843 ps
CPU time 6.46 seconds
Started Apr 18 03:13:53 PM PDT 24
Finished Apr 18 03:14:00 PM PDT 24
Peak memory 262696 kb
Host smart-fc7c950a-5f9f-47d3-928a-68a51871b29d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510724507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.510724507
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1148152257
Short name T301
Test name
Test status
Simulation time 7537117086 ps
CPU time 56.13 seconds
Started Apr 18 03:13:53 PM PDT 24
Finished Apr 18 03:14:49 PM PDT 24
Peak memory 641384 kb
Host smart-cdbff6f3-eb3a-4e69-a55a-421341218932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148152257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1148152257
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.520439065
Short name T1141
Test name
Test status
Simulation time 2137324157 ps
CPU time 55.43 seconds
Started Apr 18 03:13:50 PM PDT 24
Finished Apr 18 03:14:45 PM PDT 24
Peak memory 641120 kb
Host smart-96a789ee-fac0-479e-b8dc-fb46992febc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520439065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.520439065
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.928507298
Short name T206
Test name
Test status
Simulation time 97600635 ps
CPU time 0.96 seconds
Started Apr 18 03:13:49 PM PDT 24
Finished Apr 18 03:13:51 PM PDT 24
Peak memory 203676 kb
Host smart-bdee72da-73ec-4618-af5b-2e27170d89f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928507298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fm
t.928507298
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2882171452
Short name T422
Test name
Test status
Simulation time 149849508 ps
CPU time 7.89 seconds
Started Apr 18 03:13:49 PM PDT 24
Finished Apr 18 03:13:57 PM PDT 24
Peak memory 203920 kb
Host smart-5df6285b-4985-41b9-a288-600f0370195e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882171452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2882171452
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2860485510
Short name T895
Test name
Test status
Simulation time 13418684974 ps
CPU time 240.36 seconds
Started Apr 18 03:13:53 PM PDT 24
Finished Apr 18 03:17:53 PM PDT 24
Peak memory 1016112 kb
Host smart-7aa45ce0-d67e-4d74-847e-93bed5c9bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860485510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2860485510
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3998966546
Short name T211
Test name
Test status
Simulation time 1340602218 ps
CPU time 4.33 seconds
Started Apr 18 03:14:06 PM PDT 24
Finished Apr 18 03:14:11 PM PDT 24
Peak memory 203996 kb
Host smart-71a82edf-3960-4cae-b34f-f803cd63e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998966546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3998966546
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.4072531791
Short name T819
Test name
Test status
Simulation time 2474362057 ps
CPU time 56.09 seconds
Started Apr 18 03:14:05 PM PDT 24
Finished Apr 18 03:15:02 PM PDT 24
Peak memory 301460 kb
Host smart-5186d0ef-b7c1-4381-bbf0-4eae754ab296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072531791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.4072531791
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.4123085514
Short name T39
Test name
Test status
Simulation time 25612994 ps
CPU time 0.71 seconds
Started Apr 18 03:13:51 PM PDT 24
Finished Apr 18 03:13:52 PM PDT 24
Peak memory 203680 kb
Host smart-6024c002-4f05-4c3c-b071-8bfe00676b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123085514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.4123085514
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.4215657025
Short name T323
Test name
Test status
Simulation time 13222775631 ps
CPU time 123.92 seconds
Started Apr 18 03:13:55 PM PDT 24
Finished Apr 18 03:16:00 PM PDT 24
Peak memory 919000 kb
Host smart-bd85ca1e-cfd2-4759-81e2-81c2a708ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215657025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.4215657025
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.691054648
Short name T1257
Test name
Test status
Simulation time 5121158241 ps
CPU time 13.36 seconds
Started Apr 18 03:13:43 PM PDT 24
Finished Apr 18 03:13:57 PM PDT 24
Peak memory 265132 kb
Host smart-4c7fd040-5269-47d5-9cfc-34e0adcdc383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691054648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.691054648
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.3784106195
Short name T77
Test name
Test status
Simulation time 16984382687 ps
CPU time 2583.39 seconds
Started Apr 18 03:13:56 PM PDT 24
Finished Apr 18 03:57:00 PM PDT 24
Peak memory 3133080 kb
Host smart-2f82e920-f287-4304-b4bb-a6de754784d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784106195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.3784106195
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2741594215
Short name T867
Test name
Test status
Simulation time 3079834490 ps
CPU time 13.77 seconds
Started Apr 18 03:13:54 PM PDT 24
Finished Apr 18 03:14:08 PM PDT 24
Peak memory 220356 kb
Host smart-74cf1968-0edd-4123-ab65-7c89f39336d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741594215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2741594215
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.656201652
Short name T439
Test name
Test status
Simulation time 11218182088 ps
CPU time 3.62 seconds
Started Apr 18 03:14:06 PM PDT 24
Finished Apr 18 03:14:10 PM PDT 24
Peak memory 204064 kb
Host smart-d5b96169-c2ac-4dee-9d1f-5bf0a93bb0b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656201652 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.656201652
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3800333632
Short name T977
Test name
Test status
Simulation time 10195304968 ps
CPU time 58.68 seconds
Started Apr 18 03:14:01 PM PDT 24
Finished Apr 18 03:15:00 PM PDT 24
Peak memory 487544 kb
Host smart-2f700ade-3813-477b-9d7a-66b6cd0e59ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800333632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3800333632
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.140379208
Short name T463
Test name
Test status
Simulation time 10487337108 ps
CPU time 13.48 seconds
Started Apr 18 03:14:01 PM PDT 24
Finished Apr 18 03:14:14 PM PDT 24
Peak memory 296392 kb
Host smart-5cd2af8c-c027-4c76-bc31-ccdcb47786a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140379208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_tx.140379208
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.658151626
Short name T504
Test name
Test status
Simulation time 775014546 ps
CPU time 2.53 seconds
Started Apr 18 03:14:06 PM PDT 24
Finished Apr 18 03:14:09 PM PDT 24
Peak memory 203940 kb
Host smart-b48d6b44-bd9a-4858-8774-7fb78053bb9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658151626 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.658151626
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3516831477
Short name T1291
Test name
Test status
Simulation time 9424537968 ps
CPU time 2.73 seconds
Started Apr 18 03:14:00 PM PDT 24
Finished Apr 18 03:14:03 PM PDT 24
Peak memory 204076 kb
Host smart-1bcc20d5-0a2c-4db6-a684-f86ae9a040c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516831477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3516831477
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3542395215
Short name T647
Test name
Test status
Simulation time 23441828493 ps
CPU time 80.58 seconds
Started Apr 18 03:14:02 PM PDT 24
Finished Apr 18 03:15:23 PM PDT 24
Peak memory 1144588 kb
Host smart-4b09a8a3-13b0-4751-886c-af46a02d70ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542395215 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3542395215
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.8331807
Short name T889
Test name
Test status
Simulation time 3321161513 ps
CPU time 30.42 seconds
Started Apr 18 03:13:57 PM PDT 24
Finished Apr 18 03:14:27 PM PDT 24
Peak memory 204068 kb
Host smart-98578ac9-1dab-4aca-a38a-87d57bfa41d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8331807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_targe
t_smoke.8331807
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3034638789
Short name T536
Test name
Test status
Simulation time 5033305171 ps
CPU time 13.56 seconds
Started Apr 18 03:13:54 PM PDT 24
Finished Apr 18 03:14:08 PM PDT 24
Peak memory 204036 kb
Host smart-441a7cd1-8e01-491e-8c09-164b31e8bc7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034638789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3034638789
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.884844279
Short name T627
Test name
Test status
Simulation time 40357294939 ps
CPU time 567.84 seconds
Started Apr 18 03:13:54 PM PDT 24
Finished Apr 18 03:23:22 PM PDT 24
Peak memory 4810852 kb
Host smart-a3dc2391-3ec5-4ca6-8b72-8c2a457cf2bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884844279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.884844279
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1118390407
Short name T772
Test name
Test status
Simulation time 16877034654 ps
CPU time 32.96 seconds
Started Apr 18 03:13:58 PM PDT 24
Finished Apr 18 03:14:32 PM PDT 24
Peak memory 465012 kb
Host smart-6634408b-eedc-4d8d-8b1e-b6a73a168f56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118390407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1118390407
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.530953605
Short name T383
Test name
Test status
Simulation time 4114193965 ps
CPU time 5.47 seconds
Started Apr 18 03:14:00 PM PDT 24
Finished Apr 18 03:14:06 PM PDT 24
Peak memory 212284 kb
Host smart-36b16148-04de-4cb7-b4be-ca0e1baf63cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530953605 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.530953605
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.3703864380
Short name T17
Test name
Test status
Simulation time 3712693763 ps
CPU time 5.01 seconds
Started Apr 18 03:13:58 PM PDT 24
Finished Apr 18 03:14:04 PM PDT 24
Peak memory 206008 kb
Host smart-481e2ea1-44ca-47b0-af05-75462a2c1802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703864380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.3703864380
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2701122464
Short name T104
Test name
Test status
Simulation time 17479052 ps
CPU time 0.65 seconds
Started Apr 18 03:14:27 PM PDT 24
Finished Apr 18 03:14:28 PM PDT 24
Peak memory 203556 kb
Host smart-b911567d-7464-44e1-81d3-41b5ca20bcba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701122464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2701122464
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1602746165
Short name T540
Test name
Test status
Simulation time 171615245 ps
CPU time 1.07 seconds
Started Apr 18 03:14:13 PM PDT 24
Finished Apr 18 03:14:14 PM PDT 24
Peak memory 212324 kb
Host smart-0ff4a586-b6f5-4215-b626-dd203e9e3613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602746165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1602746165
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2669033734
Short name T324
Test name
Test status
Simulation time 466969589 ps
CPU time 4.88 seconds
Started Apr 18 03:14:11 PM PDT 24
Finished Apr 18 03:14:16 PM PDT 24
Peak memory 245696 kb
Host smart-66700c8d-db9d-4bd0-8647-d6d0b1ecf2c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669033734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2669033734
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.341797761
Short name T97
Test name
Test status
Simulation time 2439580900 ps
CPU time 160.76 seconds
Started Apr 18 03:14:13 PM PDT 24
Finished Apr 18 03:16:54 PM PDT 24
Peak memory 701404 kb
Host smart-a0e7125c-0f98-4975-85ea-e13de1b0e244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341797761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.341797761
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3531061211
Short name T427
Test name
Test status
Simulation time 3049175362 ps
CPU time 108.51 seconds
Started Apr 18 03:14:14 PM PDT 24
Finished Apr 18 03:16:03 PM PDT 24
Peak memory 583672 kb
Host smart-5ca708fe-ba30-4c58-a9be-335223f5c569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531061211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3531061211
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.17471919
Short name T473
Test name
Test status
Simulation time 614393559 ps
CPU time 1 seconds
Started Apr 18 03:14:10 PM PDT 24
Finished Apr 18 03:14:11 PM PDT 24
Peak memory 203728 kb
Host smart-dcac150b-bc85-4a4e-8ecb-6763da078c6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17471919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt
.17471919
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2093048157
Short name T901
Test name
Test status
Simulation time 118206777 ps
CPU time 2.63 seconds
Started Apr 18 03:14:09 PM PDT 24
Finished Apr 18 03:14:12 PM PDT 24
Peak memory 203936 kb
Host smart-fc96caee-ddd3-4e1d-8b17-da6fba57e902
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093048157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2093048157
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1652472993
Short name T173
Test name
Test status
Simulation time 2720137655 ps
CPU time 47.93 seconds
Started Apr 18 03:14:05 PM PDT 24
Finished Apr 18 03:14:53 PM PDT 24
Peak memory 703796 kb
Host smart-86b29625-5bd2-460d-a5cd-cff16ea22ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652472993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1652472993
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.684714894
Short name T353
Test name
Test status
Simulation time 2642419958 ps
CPU time 9.75 seconds
Started Apr 18 03:14:19 PM PDT 24
Finished Apr 18 03:14:29 PM PDT 24
Peak memory 204032 kb
Host smart-8465cad2-e03c-4aa0-94d0-ae8480aa6af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684714894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.684714894
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1910923359
Short name T9
Test name
Test status
Simulation time 2366650854 ps
CPU time 105.84 seconds
Started Apr 18 03:14:21 PM PDT 24
Finished Apr 18 03:16:07 PM PDT 24
Peak memory 359204 kb
Host smart-0ed1af88-cb54-4189-b2c0-0c116681078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910923359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1910923359
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.75282861
Short name T730
Test name
Test status
Simulation time 19524855 ps
CPU time 0.66 seconds
Started Apr 18 03:14:05 PM PDT 24
Finished Apr 18 03:14:06 PM PDT 24
Peak memory 203616 kb
Host smart-6c03a11b-bfd8-48a7-a464-a28c40eb8b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75282861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.75282861
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2687768936
Short name T1120
Test name
Test status
Simulation time 2812567944 ps
CPU time 44.19 seconds
Started Apr 18 03:14:11 PM PDT 24
Finished Apr 18 03:14:56 PM PDT 24
Peak memory 225436 kb
Host smart-8f7c0d79-e68a-43d8-8617-46300016f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687768936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2687768936
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.2979510623
Short name T916
Test name
Test status
Simulation time 4588797963 ps
CPU time 22.2 seconds
Started Apr 18 03:14:05 PM PDT 24
Finished Apr 18 03:14:28 PM PDT 24
Peak memory 316528 kb
Host smart-d8eff514-75a9-4f4d-8c3e-eb25e654ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979510623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2979510623
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3304645231
Short name T235
Test name
Test status
Simulation time 15637982790 ps
CPU time 1663.97 seconds
Started Apr 18 03:14:13 PM PDT 24
Finished Apr 18 03:41:58 PM PDT 24
Peak memory 2512640 kb
Host smart-130ddd5e-3d55-4cc7-b2ac-0942ff4cd51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304645231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3304645231
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2250612064
Short name T604
Test name
Test status
Simulation time 371348044 ps
CPU time 18.08 seconds
Started Apr 18 03:14:11 PM PDT 24
Finished Apr 18 03:14:29 PM PDT 24
Peak memory 212236 kb
Host smart-36cd458a-6f9d-4004-8729-9369f667c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250612064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2250612064
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.1027083190
Short name T196
Test name
Test status
Simulation time 465615652 ps
CPU time 2.36 seconds
Started Apr 18 03:14:18 PM PDT 24
Finished Apr 18 03:14:21 PM PDT 24
Peak memory 204028 kb
Host smart-4c239211-9984-45cb-ab1e-f66fa63350e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027083190 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.1027083190
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1329861136
Short name T247
Test name
Test status
Simulation time 10075569061 ps
CPU time 21.97 seconds
Started Apr 18 03:14:14 PM PDT 24
Finished Apr 18 03:14:36 PM PDT 24
Peak memory 314788 kb
Host smart-f2f15b61-b3ea-4626-8b2d-bee908b1a551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329861136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1329861136
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.501263475
Short name T660
Test name
Test status
Simulation time 10087239939 ps
CPU time 13.14 seconds
Started Apr 18 03:14:14 PM PDT 24
Finished Apr 18 03:14:27 PM PDT 24
Peak memory 281292 kb
Host smart-0f3a8257-382e-452f-8c96-90eda48dfd6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501263475 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.501263475
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3677531792
Short name T1271
Test name
Test status
Simulation time 542737979 ps
CPU time 2.84 seconds
Started Apr 18 03:14:21 PM PDT 24
Finished Apr 18 03:14:25 PM PDT 24
Peak memory 203900 kb
Host smart-44bf3abf-7bad-4647-bb27-2efd8597f356
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677531792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3677531792
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3316275234
Short name T388
Test name
Test status
Simulation time 6234829313 ps
CPU time 6.03 seconds
Started Apr 18 03:14:17 PM PDT 24
Finished Apr 18 03:14:23 PM PDT 24
Peak memory 212272 kb
Host smart-c06b4957-8392-43ec-9865-2dc5bca6d609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316275234 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3316275234
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2705037150
Short name T1263
Test name
Test status
Simulation time 9276140455 ps
CPU time 5.8 seconds
Started Apr 18 03:14:15 PM PDT 24
Finished Apr 18 03:14:21 PM PDT 24
Peak memory 204036 kb
Host smart-dc56183e-6cb4-46a0-9912-8134605f78c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705037150 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2705037150
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3819776483
Short name T639
Test name
Test status
Simulation time 675778811 ps
CPU time 23.55 seconds
Started Apr 18 03:14:16 PM PDT 24
Finished Apr 18 03:14:40 PM PDT 24
Peak memory 203972 kb
Host smart-20e891f7-0c1f-420d-b3be-52586aec561b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819776483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3819776483
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.3701006407
Short name T1119
Test name
Test status
Simulation time 20858189372 ps
CPU time 27.33 seconds
Started Apr 18 03:14:25 PM PDT 24
Finished Apr 18 03:14:53 PM PDT 24
Peak memory 222196 kb
Host smart-739ab003-50aa-44b7-b597-932fdc3df731
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701006407 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.3701006407
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1821413341
Short name T943
Test name
Test status
Simulation time 702612838 ps
CPU time 29.43 seconds
Started Apr 18 03:14:14 PM PDT 24
Finished Apr 18 03:14:44 PM PDT 24
Peak memory 203976 kb
Host smart-aad6cf5b-5fd0-4d0c-b4aa-1be92f849894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821413341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1821413341
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1015303884
Short name T392
Test name
Test status
Simulation time 10673267238 ps
CPU time 18.83 seconds
Started Apr 18 03:14:15 PM PDT 24
Finished Apr 18 03:14:34 PM PDT 24
Peak memory 204028 kb
Host smart-262ae2a1-acde-4062-b44a-6f897faf1d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015303884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1015303884
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3678952637
Short name T197
Test name
Test status
Simulation time 29899743996 ps
CPU time 1720.6 seconds
Started Apr 18 03:14:16 PM PDT 24
Finished Apr 18 03:42:57 PM PDT 24
Peak memory 3472980 kb
Host smart-d7c7c528-3e7d-4824-8ffe-ffa2ef7d31ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678952637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3678952637
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.875093232
Short name T1300
Test name
Test status
Simulation time 4768158537 ps
CPU time 5.75 seconds
Started Apr 18 03:14:16 PM PDT 24
Finished Apr 18 03:14:23 PM PDT 24
Peak memory 204080 kb
Host smart-62dff7a4-cff2-46b5-bbca-1ce2e1336337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875093232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.875093232
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3364885022
Short name T1019
Test name
Test status
Simulation time 42999195 ps
CPU time 0.58 seconds
Started Apr 18 03:14:40 PM PDT 24
Finished Apr 18 03:14:42 PM PDT 24
Peak memory 203576 kb
Host smart-0b9edd43-5ac0-4d11-aab4-ca8edf5ddd3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364885022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3364885022
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2155719254
Short name T1064
Test name
Test status
Simulation time 126088666 ps
CPU time 2.12 seconds
Started Apr 18 03:14:30 PM PDT 24
Finished Apr 18 03:14:33 PM PDT 24
Peak memory 212244 kb
Host smart-9448239b-53df-4a4e-9ccd-06f4f674dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155719254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2155719254
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.55466617
Short name T1078
Test name
Test status
Simulation time 533174496 ps
CPU time 10.7 seconds
Started Apr 18 03:14:25 PM PDT 24
Finished Apr 18 03:14:37 PM PDT 24
Peak memory 292164 kb
Host smart-53db90aa-7961-4573-acaf-b68b622ad41c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55466617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty
.55466617
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3832668626
Short name T581
Test name
Test status
Simulation time 4263530688 ps
CPU time 142.36 seconds
Started Apr 18 03:14:25 PM PDT 24
Finished Apr 18 03:16:48 PM PDT 24
Peak memory 691236 kb
Host smart-f86bdf09-2363-46d9-94b9-4573b94dfd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832668626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3832668626
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3503786205
Short name T1057
Test name
Test status
Simulation time 1911429364 ps
CPU time 146.09 seconds
Started Apr 18 03:14:27 PM PDT 24
Finished Apr 18 03:16:54 PM PDT 24
Peak memory 676440 kb
Host smart-91d6ef1b-9f43-45aa-ad3a-c25cc18c9461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503786205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3503786205
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2861834453
Short name T207
Test name
Test status
Simulation time 475414296 ps
CPU time 1.06 seconds
Started Apr 18 03:14:25 PM PDT 24
Finished Apr 18 03:14:27 PM PDT 24
Peak memory 203896 kb
Host smart-de403ad4-384b-4b39-a53f-2c9f62758822
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861834453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2861834453
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.281636436
Short name T608
Test name
Test status
Simulation time 527010940 ps
CPU time 3.25 seconds
Started Apr 18 03:14:27 PM PDT 24
Finished Apr 18 03:14:31 PM PDT 24
Peak memory 224036 kb
Host smart-554d807a-0302-4e86-9a23-084afed11d90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281636436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
281636436
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.724615970
Short name T1343
Test name
Test status
Simulation time 2808478910 ps
CPU time 59.44 seconds
Started Apr 18 03:14:26 PM PDT 24
Finished Apr 18 03:15:26 PM PDT 24
Peak memory 874004 kb
Host smart-7905e2b8-31a1-410c-b36f-ffdb76d45553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724615970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.724615970
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3883818657
Short name T1136
Test name
Test status
Simulation time 1880486554 ps
CPU time 6.28 seconds
Started Apr 18 03:14:43 PM PDT 24
Finished Apr 18 03:14:49 PM PDT 24
Peak memory 203976 kb
Host smart-cc140f0e-5530-4fe3-9797-6e7cf7bed60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883818657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3883818657
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2504724064
Short name T1085
Test name
Test status
Simulation time 1801109661 ps
CPU time 17.15 seconds
Started Apr 18 03:14:41 PM PDT 24
Finished Apr 18 03:14:59 PM PDT 24
Peak memory 278208 kb
Host smart-734fe029-8d36-4782-a457-3fbc0901bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504724064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2504724064
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.859516058
Short name T406
Test name
Test status
Simulation time 26057518 ps
CPU time 0.67 seconds
Started Apr 18 03:14:22 PM PDT 24
Finished Apr 18 03:14:22 PM PDT 24
Peak memory 203572 kb
Host smart-0c262b25-e695-4c8f-87cb-8e248530edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859516058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.859516058
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3241391564
Short name T841
Test name
Test status
Simulation time 25413707532 ps
CPU time 280.36 seconds
Started Apr 18 03:14:24 PM PDT 24
Finished Apr 18 03:19:05 PM PDT 24
Peak memory 212156 kb
Host smart-2228915e-8cf6-49cb-98bf-83943059c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241391564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3241391564
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2862865904
Short name T721
Test name
Test status
Simulation time 1208838103 ps
CPU time 56.82 seconds
Started Apr 18 03:14:27 PM PDT 24
Finished Apr 18 03:15:24 PM PDT 24
Peak memory 334708 kb
Host smart-4f964e42-161c-443b-a169-408e57af4a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862865904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2862865904
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3043577027
Short name T812
Test name
Test status
Simulation time 20401029167 ps
CPU time 1592.64 seconds
Started Apr 18 03:14:31 PM PDT 24
Finished Apr 18 03:41:04 PM PDT 24
Peak memory 1816048 kb
Host smart-fea30c79-c35f-474e-905e-e01af52bc148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043577027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3043577027
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.541286747
Short name T1110
Test name
Test status
Simulation time 1687440982 ps
CPU time 37.06 seconds
Started Apr 18 03:14:26 PM PDT 24
Finished Apr 18 03:15:04 PM PDT 24
Peak memory 213632 kb
Host smart-72164a68-4fed-4c3c-8207-867ca191b143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541286747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.541286747
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2516541585
Short name T1145
Test name
Test status
Simulation time 1280559781 ps
CPU time 3.12 seconds
Started Apr 18 03:14:41 PM PDT 24
Finished Apr 18 03:14:45 PM PDT 24
Peak memory 203976 kb
Host smart-e91f5e68-7696-42c5-987a-1613ce6b1f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516541585 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2516541585
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2903153702
Short name T833
Test name
Test status
Simulation time 10109580242 ps
CPU time 11.9 seconds
Started Apr 18 03:14:36 PM PDT 24
Finished Apr 18 03:14:48 PM PDT 24
Peak memory 274060 kb
Host smart-425807e3-beb8-4133-87b6-3685a162222e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903153702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2903153702
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2124283155
Short name T973
Test name
Test status
Simulation time 10909333169 ps
CPU time 6.54 seconds
Started Apr 18 03:14:36 PM PDT 24
Finished Apr 18 03:14:43 PM PDT 24
Peak memory 263180 kb
Host smart-4f9abe1f-b6bd-468b-a068-7200615a6531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124283155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2124283155
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2238528653
Short name T461
Test name
Test status
Simulation time 1949942148 ps
CPU time 2.3 seconds
Started Apr 18 03:14:42 PM PDT 24
Finished Apr 18 03:14:45 PM PDT 24
Peak memory 203964 kb
Host smart-91f6c7ed-f1ba-44f9-be3e-c7533dc1b314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238528653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2238528653
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.946892279
Short name T686
Test name
Test status
Simulation time 1077785115 ps
CPU time 5.28 seconds
Started Apr 18 03:14:35 PM PDT 24
Finished Apr 18 03:14:41 PM PDT 24
Peak memory 204024 kb
Host smart-31c542d3-700b-46cb-8703-dac2d40ed227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946892279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.946892279
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.2794434049
Short name T635
Test name
Test status
Simulation time 17501627362 ps
CPU time 92.05 seconds
Started Apr 18 03:14:37 PM PDT 24
Finished Apr 18 03:16:10 PM PDT 24
Peak memory 1367192 kb
Host smart-7863d14f-3e71-4e9e-b64c-df6ba0675ef8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794434049 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2794434049
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3242703794
Short name T99
Test name
Test status
Simulation time 1430938137 ps
CPU time 9.36 seconds
Started Apr 18 03:14:31 PM PDT 24
Finished Apr 18 03:14:41 PM PDT 24
Peak memory 203948 kb
Host smart-90c0c412-2199-42a3-94a3-20e6b22ed74b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242703794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3242703794
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.662904519
Short name T1107
Test name
Test status
Simulation time 1593055310 ps
CPU time 18.2 seconds
Started Apr 18 03:14:32 PM PDT 24
Finished Apr 18 03:14:50 PM PDT 24
Peak memory 214684 kb
Host smart-29d8e8c4-bfef-4bb6-8dac-a709329a1160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662904519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.662904519
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2050640399
Short name T1282
Test name
Test status
Simulation time 11637496133 ps
CPU time 11 seconds
Started Apr 18 03:14:37 PM PDT 24
Finished Apr 18 03:14:48 PM PDT 24
Peak memory 204080 kb
Host smart-2466a589-f4ec-46c2-ad7b-1cdeed8ebc18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050640399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2050640399
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2013788234
Short name T1225
Test name
Test status
Simulation time 20289331134 ps
CPU time 115.41 seconds
Started Apr 18 03:14:36 PM PDT 24
Finished Apr 18 03:16:32 PM PDT 24
Peak memory 1194708 kb
Host smart-340c7653-9429-420e-beeb-0e79d9965439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013788234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2013788234
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3054646090
Short name T673
Test name
Test status
Simulation time 2696657115 ps
CPU time 6.42 seconds
Started Apr 18 03:14:41 PM PDT 24
Finished Apr 18 03:14:48 PM PDT 24
Peak memory 219816 kb
Host smart-a25491f3-7a36-4186-a10f-654d58523d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054646090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3054646090
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3315271979
Short name T325
Test name
Test status
Simulation time 49628429 ps
CPU time 0.64 seconds
Started Apr 18 03:15:00 PM PDT 24
Finished Apr 18 03:15:02 PM PDT 24
Peak memory 203612 kb
Host smart-2b6d974e-a760-4f9d-8bc0-b42a1536bf4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315271979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3315271979
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1986957208
Short name T675
Test name
Test status
Simulation time 344421157 ps
CPU time 1.46 seconds
Started Apr 18 03:14:45 PM PDT 24
Finished Apr 18 03:14:47 PM PDT 24
Peak memory 212336 kb
Host smart-1685f341-6ec7-4d27-8d08-7104ee48ff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986957208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1986957208
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3988209494
Short name T290
Test name
Test status
Simulation time 372500152 ps
CPU time 18.93 seconds
Started Apr 18 03:14:45 PM PDT 24
Finished Apr 18 03:15:04 PM PDT 24
Peak memory 265320 kb
Host smart-1abdff9d-0662-4650-a858-6e5a93850de6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988209494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3988209494
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.444975662
Short name T48
Test name
Test status
Simulation time 3510740125 ps
CPU time 157.61 seconds
Started Apr 18 03:14:46 PM PDT 24
Finished Apr 18 03:17:24 PM PDT 24
Peak memory 729516 kb
Host smart-91bf85f3-4c2b-44b2-99e3-a83d18b4ef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444975662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.444975662
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.2610677773
Short name T443
Test name
Test status
Simulation time 4139993101 ps
CPU time 62.15 seconds
Started Apr 18 03:14:41 PM PDT 24
Finished Apr 18 03:15:43 PM PDT 24
Peak memory 720972 kb
Host smart-496f7e3c-8c10-4690-8339-0b4643233e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610677773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2610677773
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.21304194
Short name T1033
Test name
Test status
Simulation time 2217850040 ps
CPU time 8.46 seconds
Started Apr 18 03:14:44 PM PDT 24
Finished Apr 18 03:14:53 PM PDT 24
Peak memory 203996 kb
Host smart-03df2a9f-bb04-4465-9803-ccbe6ef05f25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.21304194
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3502020688
Short name T1178
Test name
Test status
Simulation time 94422026201 ps
CPU time 124.91 seconds
Started Apr 18 03:14:40 PM PDT 24
Finished Apr 18 03:16:45 PM PDT 24
Peak memory 1380884 kb
Host smart-2afe380b-92b0-4d38-9772-71d788d775ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502020688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3502020688
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2103259888
Short name T750
Test name
Test status
Simulation time 653997850 ps
CPU time 19.09 seconds
Started Apr 18 03:14:55 PM PDT 24
Finished Apr 18 03:15:15 PM PDT 24
Peak memory 203944 kb
Host smart-6aa4dcf3-f701-4641-9809-4da2f590048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103259888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2103259888
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.3994004323
Short name T529
Test name
Test status
Simulation time 8635490923 ps
CPU time 26.11 seconds
Started Apr 18 03:14:54 PM PDT 24
Finished Apr 18 03:15:21 PM PDT 24
Peak memory 388892 kb
Host smart-253f403c-2d8a-4ebc-bc59-abc46a7c3410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994004323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3994004323
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.615121882
Short name T816
Test name
Test status
Simulation time 33971122 ps
CPU time 0.62 seconds
Started Apr 18 03:14:41 PM PDT 24
Finished Apr 18 03:14:42 PM PDT 24
Peak memory 203652 kb
Host smart-522ebcc7-bfb6-49c7-935c-1c57732fc807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615121882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.615121882
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3463963000
Short name T1312
Test name
Test status
Simulation time 47362544510 ps
CPU time 442.2 seconds
Started Apr 18 03:14:44 PM PDT 24
Finished Apr 18 03:22:06 PM PDT 24
Peak memory 203932 kb
Host smart-bd99d505-2899-4a4f-b347-884f6ee3745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463963000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3463963000
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.296324010
Short name T1044
Test name
Test status
Simulation time 1833132745 ps
CPU time 14.13 seconds
Started Apr 18 03:14:40 PM PDT 24
Finished Apr 18 03:14:54 PM PDT 24
Peak memory 267948 kb
Host smart-b444f12b-6113-4fdb-b136-77f9ec91a763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296324010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.296324010
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.736349108
Short name T1315
Test name
Test status
Simulation time 81173000782 ps
CPU time 708.49 seconds
Started Apr 18 03:14:44 PM PDT 24
Finished Apr 18 03:26:33 PM PDT 24
Peak memory 1643380 kb
Host smart-e6bc7e38-abef-4974-a415-1edfcd22270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736349108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.736349108
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.4126108074
Short name T905
Test name
Test status
Simulation time 3275701846 ps
CPU time 12.07 seconds
Started Apr 18 03:14:46 PM PDT 24
Finished Apr 18 03:14:58 PM PDT 24
Peak memory 228432 kb
Host smart-059c649b-dbaf-4a97-9079-db29c7471b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126108074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.4126108074
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3498034954
Short name T1185
Test name
Test status
Simulation time 982483899 ps
CPU time 4.02 seconds
Started Apr 18 03:14:55 PM PDT 24
Finished Apr 18 03:14:59 PM PDT 24
Peak memory 212228 kb
Host smart-8d58fdc5-46de-4123-891d-cb938b4e9f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498034954 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3498034954
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3789236257
Short name T778
Test name
Test status
Simulation time 10076443466 ps
CPU time 61.12 seconds
Started Apr 18 03:14:50 PM PDT 24
Finished Apr 18 03:15:52 PM PDT 24
Peak memory 503948 kb
Host smart-e94a1ee3-f770-4ac9-b200-eb8a4e7e3dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789236257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3789236257
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3115242229
Short name T1344
Test name
Test status
Simulation time 10360665591 ps
CPU time 3.01 seconds
Started Apr 18 03:14:50 PM PDT 24
Finished Apr 18 03:14:54 PM PDT 24
Peak memory 220296 kb
Host smart-00f2ee57-634c-4bc7-86aa-90599b522176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115242229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3115242229
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1535052111
Short name T622
Test name
Test status
Simulation time 420327337 ps
CPU time 2.39 seconds
Started Apr 18 03:14:56 PM PDT 24
Finished Apr 18 03:14:59 PM PDT 24
Peak memory 204012 kb
Host smart-de434240-bbf4-447b-85e2-2799c0aed00e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535052111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1535052111
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2177511878
Short name T1135
Test name
Test status
Simulation time 953972178 ps
CPU time 4.14 seconds
Started Apr 18 03:14:53 PM PDT 24
Finished Apr 18 03:14:57 PM PDT 24
Peak memory 204048 kb
Host smart-be659cc6-40b9-4f6b-a17a-f6b1d3fa65b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177511878 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2177511878
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.4200626274
Short name T887
Test name
Test status
Simulation time 16286482475 ps
CPU time 235.82 seconds
Started Apr 18 03:14:50 PM PDT 24
Finished Apr 18 03:18:46 PM PDT 24
Peak memory 2369988 kb
Host smart-6e0a753e-fe40-44b7-97c7-c18352ce53bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200626274 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.4200626274
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.171200818
Short name T846
Test name
Test status
Simulation time 787632091 ps
CPU time 10.89 seconds
Started Apr 18 03:14:47 PM PDT 24
Finished Apr 18 03:14:58 PM PDT 24
Peak memory 203944 kb
Host smart-7ba61215-2bcd-444d-a15b-88086bba5f3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171200818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.171200818
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.414419325
Short name T1186
Test name
Test status
Simulation time 2241549075 ps
CPU time 20.42 seconds
Started Apr 18 03:14:53 PM PDT 24
Finished Apr 18 03:15:14 PM PDT 24
Peak memory 204024 kb
Host smart-084336fe-836d-4402-9697-f4f72bea3bfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414419325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.414419325
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.590256272
Short name T653
Test name
Test status
Simulation time 26183930082 ps
CPU time 10.77 seconds
Started Apr 18 03:14:45 PM PDT 24
Finished Apr 18 03:14:56 PM PDT 24
Peak memory 296184 kb
Host smart-2cc190bc-6a43-4450-b872-29cc907af015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590256272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_wr.590256272
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2491747721
Short name T953
Test name
Test status
Simulation time 15489730610 ps
CPU time 510.27 seconds
Started Apr 18 03:14:45 PM PDT 24
Finished Apr 18 03:23:16 PM PDT 24
Peak memory 1486000 kb
Host smart-7be44a2e-84d4-47b2-93b9-6534d587c889
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491747721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2491747721
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.812130646
Short name T341
Test name
Test status
Simulation time 6258998644 ps
CPU time 6.4 seconds
Started Apr 18 03:14:48 PM PDT 24
Finished Apr 18 03:14:55 PM PDT 24
Peak memory 210072 kb
Host smart-325a34d5-e2a6-4eec-98cb-1e9f6e14b354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812130646 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.812130646
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3979243063
Short name T715
Test name
Test status
Simulation time 17791507 ps
CPU time 0.64 seconds
Started Apr 18 03:15:15 PM PDT 24
Finished Apr 18 03:15:16 PM PDT 24
Peak memory 203516 kb
Host smart-c8308945-8783-499c-a344-5d93c8ed815b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979243063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3979243063
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3654807165
Short name T712
Test name
Test status
Simulation time 214844343 ps
CPU time 1.69 seconds
Started Apr 18 03:15:08 PM PDT 24
Finished Apr 18 03:15:10 PM PDT 24
Peak memory 211660 kb
Host smart-a9f07161-5d08-4819-bb12-d273809df30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654807165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3654807165
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2310455250
Short name T2
Test name
Test status
Simulation time 227561364 ps
CPU time 3.68 seconds
Started Apr 18 03:15:01 PM PDT 24
Finished Apr 18 03:15:05 PM PDT 24
Peak memory 212632 kb
Host smart-dc98173a-df1c-45de-a555-04e8e55797eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310455250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2310455250
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1091935531
Short name T1214
Test name
Test status
Simulation time 7360070308 ps
CPU time 52.99 seconds
Started Apr 18 03:15:00 PM PDT 24
Finished Apr 18 03:15:53 PM PDT 24
Peak memory 619188 kb
Host smart-bb5dbf2b-d21b-4822-b1cc-849be8136235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091935531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1091935531
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.4009696514
Short name T345
Test name
Test status
Simulation time 4604435201 ps
CPU time 83.51 seconds
Started Apr 18 03:15:02 PM PDT 24
Finished Apr 18 03:16:26 PM PDT 24
Peak memory 767360 kb
Host smart-2a9f916e-6ec7-49c0-9091-9ff82a80e784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009696514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.4009696514
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.345808209
Short name T756
Test name
Test status
Simulation time 150180348 ps
CPU time 1.01 seconds
Started Apr 18 03:15:00 PM PDT 24
Finished Apr 18 03:15:01 PM PDT 24
Peak memory 203728 kb
Host smart-6d7559ce-b3c8-4c32-8cd5-66395ecdf2bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345808209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.345808209
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3213330931
Short name T1209
Test name
Test status
Simulation time 106695797 ps
CPU time 2.53 seconds
Started Apr 18 03:15:02 PM PDT 24
Finished Apr 18 03:15:05 PM PDT 24
Peak memory 203928 kb
Host smart-b0e57a8b-e729-43bf-81a1-84b6d60fbc23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213330931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3213330931
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.56369893
Short name T729
Test name
Test status
Simulation time 7545808020 ps
CPU time 105.3 seconds
Started Apr 18 03:15:00 PM PDT 24
Finished Apr 18 03:16:46 PM PDT 24
Peak memory 1084480 kb
Host smart-e675a89d-9602-4b23-b8f2-55e106252250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56369893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.56369893
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.853287707
Short name T65
Test name
Test status
Simulation time 1337314494 ps
CPU time 4.04 seconds
Started Apr 18 03:15:15 PM PDT 24
Finished Apr 18 03:15:19 PM PDT 24
Peak memory 203872 kb
Host smart-519bc7d4-28c0-48a3-91d5-7dcddadc0e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853287707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.853287707
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1058993135
Short name T972
Test name
Test status
Simulation time 5617196764 ps
CPU time 23.26 seconds
Started Apr 18 03:15:13 PM PDT 24
Finished Apr 18 03:15:37 PM PDT 24
Peak memory 344168 kb
Host smart-32224de2-19ba-4210-9e4f-2b81ff96decb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058993135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1058993135
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.4014417676
Short name T1368
Test name
Test status
Simulation time 18008926 ps
CPU time 0.64 seconds
Started Apr 18 03:15:02 PM PDT 24
Finished Apr 18 03:15:03 PM PDT 24
Peak memory 203628 kb
Host smart-e78d0d7a-e5ec-4a1d-ae3f-e84516f57102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014417676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4014417676
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2998987503
Short name T557
Test name
Test status
Simulation time 29245411394 ps
CPU time 42.96 seconds
Started Apr 18 03:15:00 PM PDT 24
Finished Apr 18 03:15:44 PM PDT 24
Peak memory 592092 kb
Host smart-552494bb-247f-483f-b345-b442c80fefb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998987503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2998987503
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.914244803
Short name T839
Test name
Test status
Simulation time 3318040125 ps
CPU time 31.97 seconds
Started Apr 18 03:15:05 PM PDT 24
Finished Apr 18 03:15:37 PM PDT 24
Peak memory 333668 kb
Host smart-e7ac9e5f-5193-47d3-b948-3df0c812e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914244803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.914244803
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.52853212
Short name T478
Test name
Test status
Simulation time 35245886226 ps
CPU time 2679.13 seconds
Started Apr 18 03:15:05 PM PDT 24
Finished Apr 18 03:59:44 PM PDT 24
Peak memory 1077380 kb
Host smart-0a28d3fe-80d7-4c1d-a7b0-6f235729bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52853212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.52853212
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2841056719
Short name T559
Test name
Test status
Simulation time 3003487424 ps
CPU time 23.33 seconds
Started Apr 18 03:15:08 PM PDT 24
Finished Apr 18 03:15:32 PM PDT 24
Peak memory 211624 kb
Host smart-0b956582-689e-4502-a45b-335afac54acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841056719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2841056719
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2520500268
Short name T908
Test name
Test status
Simulation time 2390442167 ps
CPU time 4.75 seconds
Started Apr 18 03:15:15 PM PDT 24
Finished Apr 18 03:15:20 PM PDT 24
Peak memory 204032 kb
Host smart-58c80c46-139c-4c88-b46e-d8294f66a6b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520500268 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2520500268
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1653499516
Short name T975
Test name
Test status
Simulation time 10243458333 ps
CPU time 11.74 seconds
Started Apr 18 03:15:11 PM PDT 24
Finished Apr 18 03:15:23 PM PDT 24
Peak memory 269812 kb
Host smart-4a878979-7aef-4397-982d-8029ee9624da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653499516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1653499516
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3923721904
Short name T262
Test name
Test status
Simulation time 10407316288 ps
CPU time 5.61 seconds
Started Apr 18 03:15:12 PM PDT 24
Finished Apr 18 03:15:18 PM PDT 24
Peak memory 235400 kb
Host smart-f3f97baa-ef5c-4629-b4c9-2ad32954b25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923721904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3923721904
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2006767367
Short name T615
Test name
Test status
Simulation time 1105907525 ps
CPU time 5.19 seconds
Started Apr 18 03:15:14 PM PDT 24
Finished Apr 18 03:15:19 PM PDT 24
Peak memory 211040 kb
Host smart-0d87016f-709a-458f-93a7-8d0f52832e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006767367 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2006767367
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.159177486
Short name T699
Test name
Test status
Simulation time 3605937852 ps
CPU time 3.19 seconds
Started Apr 18 03:15:10 PM PDT 24
Finished Apr 18 03:15:14 PM PDT 24
Peak memory 204000 kb
Host smart-38dc888d-8b21-46a5-8298-bb9128edfc99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159177486 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.159177486
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1247341717
Short name T754
Test name
Test status
Simulation time 3934477182 ps
CPU time 49.93 seconds
Started Apr 18 03:15:04 PM PDT 24
Finished Apr 18 03:15:54 PM PDT 24
Peak memory 204060 kb
Host smart-b94a9032-41ed-4bf2-9deb-9420767bd39d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247341717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1247341717
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3035661176
Short name T351
Test name
Test status
Simulation time 3060639405 ps
CPU time 27.02 seconds
Started Apr 18 03:15:04 PM PDT 24
Finished Apr 18 03:15:32 PM PDT 24
Peak memory 219548 kb
Host smart-e67a7c08-4209-47e4-a48a-3af5d9e3d4ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035661176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3035661176
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2018047917
Short name T114
Test name
Test status
Simulation time 34327892106 ps
CPU time 139.26 seconds
Started Apr 18 03:15:04 PM PDT 24
Finished Apr 18 03:17:24 PM PDT 24
Peak memory 1904052 kb
Host smart-82007ee6-97eb-4350-b6d4-06ac44d0d049
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018047917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2018047917
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1639319775
Short name T396
Test name
Test status
Simulation time 14389010675 ps
CPU time 63.13 seconds
Started Apr 18 03:15:03 PM PDT 24
Finished Apr 18 03:16:07 PM PDT 24
Peak memory 808648 kb
Host smart-dbf7f394-8405-4b91-b491-be24ab5bb1cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639319775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1639319775
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2498166676
Short name T11
Test name
Test status
Simulation time 1098562885 ps
CPU time 5.72 seconds
Started Apr 18 03:15:09 PM PDT 24
Finished Apr 18 03:15:15 PM PDT 24
Peak memory 212228 kb
Host smart-b10a9ac5-d306-4372-8dc7-19af5f2092c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498166676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2498166676
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2702391944
Short name T785
Test name
Test status
Simulation time 47682035 ps
CPU time 0.6 seconds
Started Apr 18 03:05:51 PM PDT 24
Finished Apr 18 03:05:52 PM PDT 24
Peak memory 203620 kb
Host smart-0afdb614-c013-4d34-8f9c-511aff01e1e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702391944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2702391944
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.753802161
Short name T565
Test name
Test status
Simulation time 397894767 ps
CPU time 1.47 seconds
Started Apr 18 03:05:31 PM PDT 24
Finished Apr 18 03:05:33 PM PDT 24
Peak memory 204072 kb
Host smart-f3d2c818-8fe5-4ec3-90f9-becf6383d2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753802161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.753802161
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2501099552
Short name T193
Test name
Test status
Simulation time 796370534 ps
CPU time 2.72 seconds
Started Apr 18 03:05:24 PM PDT 24
Finished Apr 18 03:05:27 PM PDT 24
Peak memory 223560 kb
Host smart-c67577cf-5df5-452a-9318-97920cb6cbcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501099552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2501099552
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2509446764
Short name T768
Test name
Test status
Simulation time 1694673539 ps
CPU time 48.24 seconds
Started Apr 18 03:05:24 PM PDT 24
Finished Apr 18 03:06:13 PM PDT 24
Peak memory 612340 kb
Host smart-bcbd0b68-a612-47a1-aaa3-a62a545d5972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509446764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2509446764
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1788653197
Short name T904
Test name
Test status
Simulation time 8794862284 ps
CPU time 44.55 seconds
Started Apr 18 03:05:17 PM PDT 24
Finished Apr 18 03:06:02 PM PDT 24
Peak memory 574856 kb
Host smart-049eb020-777b-47a3-91dc-3e00debb17c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788653197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1788653197
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3894921144
Short name T911
Test name
Test status
Simulation time 279465250 ps
CPU time 0.96 seconds
Started Apr 18 03:05:17 PM PDT 24
Finished Apr 18 03:05:18 PM PDT 24
Peak memory 203684 kb
Host smart-e9be5a24-7304-4290-bac9-639c4a3dbb7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894921144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3894921144
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2238067376
Short name T404
Test name
Test status
Simulation time 842663081 ps
CPU time 3.06 seconds
Started Apr 18 03:05:25 PM PDT 24
Finished Apr 18 03:05:29 PM PDT 24
Peak memory 203940 kb
Host smart-cff1e34f-7eaf-4fa2-b246-be801fb0cb31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238067376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2238067376
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2931932355
Short name T170
Test name
Test status
Simulation time 2548486288 ps
CPU time 49.52 seconds
Started Apr 18 03:05:17 PM PDT 24
Finished Apr 18 03:06:07 PM PDT 24
Peak memory 785964 kb
Host smart-d5208d72-1fce-4429-89f7-164fc72f9866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931932355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2931932355
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.1335896222
Short name T212
Test name
Test status
Simulation time 855704945 ps
CPU time 12.2 seconds
Started Apr 18 03:05:51 PM PDT 24
Finished Apr 18 03:06:04 PM PDT 24
Peak memory 203952 kb
Host smart-985a5488-afa1-478e-86ff-db9aaa5e7817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335896222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1335896222
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.1091466462
Short name T1293
Test name
Test status
Simulation time 1948852294 ps
CPU time 64.75 seconds
Started Apr 18 03:05:50 PM PDT 24
Finished Apr 18 03:06:55 PM PDT 24
Peak memory 313232 kb
Host smart-ebe960cf-4b08-4961-b4b1-6d0fddb0fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091466462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.1091466462
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2263773674
Short name T265
Test name
Test status
Simulation time 27016424 ps
CPU time 0.65 seconds
Started Apr 18 03:05:16 PM PDT 24
Finished Apr 18 03:05:17 PM PDT 24
Peak memory 203700 kb
Host smart-dd73b446-b3ad-4cc4-8857-364a2f95ba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263773674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2263773674
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3951011235
Short name T786
Test name
Test status
Simulation time 5522985215 ps
CPU time 127.5 seconds
Started Apr 18 03:05:31 PM PDT 24
Finished Apr 18 03:07:38 PM PDT 24
Peak memory 277184 kb
Host smart-f5a05b1e-7772-4fb6-b780-bb080838567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951011235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3951011235
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1780078162
Short name T562
Test name
Test status
Simulation time 3507501755 ps
CPU time 15.55 seconds
Started Apr 18 03:05:17 PM PDT 24
Finished Apr 18 03:05:33 PM PDT 24
Peak memory 320348 kb
Host smart-d7fafe81-f042-427a-ad1b-1582c5ca0ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780078162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1780078162
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3930170548
Short name T1302
Test name
Test status
Simulation time 67585158157 ps
CPU time 1081.98 seconds
Started Apr 18 03:05:33 PM PDT 24
Finished Apr 18 03:23:35 PM PDT 24
Peak memory 3642452 kb
Host smart-0bac8f5c-30f6-46f4-9f2d-818bbb49b84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930170548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3930170548
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.355895686
Short name T637
Test name
Test status
Simulation time 2186307884 ps
CPU time 25.1 seconds
Started Apr 18 03:05:32 PM PDT 24
Finished Apr 18 03:05:58 PM PDT 24
Peak memory 212316 kb
Host smart-cc6e8a71-428e-423f-a00b-b00f4628391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355895686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.355895686
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3996301615
Short name T403
Test name
Test status
Simulation time 5413042309 ps
CPU time 3.02 seconds
Started Apr 18 03:05:51 PM PDT 24
Finished Apr 18 03:05:55 PM PDT 24
Peak memory 204136 kb
Host smart-e0fd2bb3-816e-4e42-b316-114e536cb37e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996301615 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3996301615
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2262459696
Short name T898
Test name
Test status
Simulation time 10112614356 ps
CPU time 64.02 seconds
Started Apr 18 03:05:50 PM PDT 24
Finished Apr 18 03:06:54 PM PDT 24
Peak memory 470480 kb
Host smart-b406d369-afbc-41fd-a58d-0c8dd1df0d00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262459696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2262459696
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.925817467
Short name T566
Test name
Test status
Simulation time 10045628205 ps
CPU time 73.82 seconds
Started Apr 18 03:05:50 PM PDT 24
Finished Apr 18 03:07:04 PM PDT 24
Peak memory 562156 kb
Host smart-52f1468a-7fef-494e-a778-c5453fd5f8fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925817467 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.925817467
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3913328623
Short name T848
Test name
Test status
Simulation time 568315069 ps
CPU time 2.99 seconds
Started Apr 18 03:05:50 PM PDT 24
Finished Apr 18 03:05:53 PM PDT 24
Peak memory 203976 kb
Host smart-28ce4487-17ea-4294-89c6-115d3d705288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913328623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3913328623
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.59068143
Short name T487
Test name
Test status
Simulation time 615869910 ps
CPU time 3.38 seconds
Started Apr 18 03:05:38 PM PDT 24
Finished Apr 18 03:05:42 PM PDT 24
Peak memory 203992 kb
Host smart-1e2676d4-1ca3-4abd-9ba6-e522a19a2617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59068143 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.59068143
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2705196520
Short name T244
Test name
Test status
Simulation time 7229365226 ps
CPU time 7.86 seconds
Started Apr 18 03:05:45 PM PDT 24
Finished Apr 18 03:05:53 PM PDT 24
Peak memory 204016 kb
Host smart-d65ea225-9616-4a48-8aa7-2e7c60d0ec86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705196520 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2705196520
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.42924269
Short name T36
Test name
Test status
Simulation time 10842677184 ps
CPU time 38.21 seconds
Started Apr 18 03:05:33 PM PDT 24
Finished Apr 18 03:06:12 PM PDT 24
Peak memory 204008 kb
Host smart-da7a9b67-7c8f-42fe-b401-41c0632c14c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42924269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targe
t_smoke.42924269
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1758405446
Short name T91
Test name
Test status
Simulation time 2915713085 ps
CPU time 31.04 seconds
Started Apr 18 03:05:38 PM PDT 24
Finished Apr 18 03:06:10 PM PDT 24
Peak memory 204060 kb
Host smart-7781d0a0-2dd5-453e-9c18-db080bc5a618
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758405446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1758405446
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.4075236494
Short name T631
Test name
Test status
Simulation time 12911836178 ps
CPU time 13.02 seconds
Started Apr 18 03:05:32 PM PDT 24
Finished Apr 18 03:05:45 PM PDT 24
Peak memory 204064 kb
Host smart-3e1f1a39-1595-450a-95cd-567c0daeeb5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075236494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.4075236494
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3850119646
Short name T924
Test name
Test status
Simulation time 9566697294 ps
CPU time 259.57 seconds
Started Apr 18 03:05:38 PM PDT 24
Finished Apr 18 03:09:58 PM PDT 24
Peak memory 1096468 kb
Host smart-8b4bb00d-be7a-4a4d-8d50-1265acfa6cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850119646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3850119646
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.238585863
Short name T1167
Test name
Test status
Simulation time 8431078244 ps
CPU time 7.23 seconds
Started Apr 18 03:05:45 PM PDT 24
Finished Apr 18 03:05:53 PM PDT 24
Peak memory 219112 kb
Host smart-89188ab9-5346-41aa-bb99-ab803135934d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238585863 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.238585863
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3134053984
Short name T308
Test name
Test status
Simulation time 53427528 ps
CPU time 0.61 seconds
Started Apr 18 03:15:36 PM PDT 24
Finished Apr 18 03:15:37 PM PDT 24
Peak memory 203500 kb
Host smart-a7c61ea7-6d9b-4972-9050-393689419868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134053984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3134053984
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.402194100
Short name T658
Test name
Test status
Simulation time 165729088 ps
CPU time 1.61 seconds
Started Apr 18 03:15:21 PM PDT 24
Finished Apr 18 03:15:23 PM PDT 24
Peak memory 212320 kb
Host smart-5d06d95d-eea5-4ae6-8765-7ce3c0821bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402194100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.402194100
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.244191929
Short name T1303
Test name
Test status
Simulation time 330371519 ps
CPU time 5.18 seconds
Started Apr 18 03:15:21 PM PDT 24
Finished Apr 18 03:15:27 PM PDT 24
Peak memory 256064 kb
Host smart-75404cd7-92d9-49de-b133-d6fa07e40b12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244191929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empt
y.244191929
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2790173503
Short name T588
Test name
Test status
Simulation time 6926845495 ps
CPU time 104.42 seconds
Started Apr 18 03:15:23 PM PDT 24
Finished Apr 18 03:17:08 PM PDT 24
Peak memory 584756 kb
Host smart-639769d1-fedf-47cb-b2c0-5a8240134c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790173503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2790173503
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1108541996
Short name T925
Test name
Test status
Simulation time 20980580651 ps
CPU time 38.65 seconds
Started Apr 18 03:15:21 PM PDT 24
Finished Apr 18 03:16:00 PM PDT 24
Peak memory 515508 kb
Host smart-7714c21d-4334-4cdc-b111-6b48d68546e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108541996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1108541996
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3366780070
Short name T256
Test name
Test status
Simulation time 93624684 ps
CPU time 1.03 seconds
Started Apr 18 03:15:21 PM PDT 24
Finished Apr 18 03:15:23 PM PDT 24
Peak memory 203948 kb
Host smart-50747100-1594-4598-836d-84563a2d2ed1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366780070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3366780070
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1989321670
Short name T869
Test name
Test status
Simulation time 155133335 ps
CPU time 8.18 seconds
Started Apr 18 03:15:20 PM PDT 24
Finished Apr 18 03:15:29 PM PDT 24
Peak memory 231084 kb
Host smart-4e43eaa8-a541-47f4-ace8-7b49232a9303
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989321670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1989321670
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.268100199
Short name T270
Test name
Test status
Simulation time 8090570265 ps
CPU time 274.95 seconds
Started Apr 18 03:15:15 PM PDT 24
Finished Apr 18 03:19:50 PM PDT 24
Peak memory 1117284 kb
Host smart-4852435b-643b-4240-9a97-f9039144aefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268100199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.268100199
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1338095837
Short name T961
Test name
Test status
Simulation time 553902625 ps
CPU time 22.49 seconds
Started Apr 18 03:15:32 PM PDT 24
Finished Apr 18 03:15:54 PM PDT 24
Peak memory 203980 kb
Host smart-9c38bb1b-a653-4ffb-b78c-36c9701b5981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338095837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1338095837
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1878492809
Short name T1224
Test name
Test status
Simulation time 9975085776 ps
CPU time 31.13 seconds
Started Apr 18 03:15:31 PM PDT 24
Finished Apr 18 03:16:02 PM PDT 24
Peak memory 359340 kb
Host smart-512711b7-2752-42e5-950c-e52148040948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878492809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1878492809
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3275151428
Short name T40
Test name
Test status
Simulation time 40871780 ps
CPU time 0.61 seconds
Started Apr 18 03:15:15 PM PDT 24
Finished Apr 18 03:15:16 PM PDT 24
Peak memory 203640 kb
Host smart-983a6afa-9f05-4ce4-864c-c9d44f199d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275151428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3275151428
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.875661098
Short name T257
Test name
Test status
Simulation time 1015328471 ps
CPU time 42.72 seconds
Started Apr 18 03:15:20 PM PDT 24
Finished Apr 18 03:16:03 PM PDT 24
Peak memory 276440 kb
Host smart-6cb47ebd-24a1-47d4-9e49-d26cf376378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875661098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.875661098
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2867262881
Short name T563
Test name
Test status
Simulation time 1585929094 ps
CPU time 19.59 seconds
Started Apr 18 03:15:15 PM PDT 24
Finished Apr 18 03:15:35 PM PDT 24
Peak memory 315928 kb
Host smart-5784b271-a592-4141-9172-bf1c46b798a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867262881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2867262881
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3330534315
Short name T177
Test name
Test status
Simulation time 9611112902 ps
CPU time 80.77 seconds
Started Apr 18 03:15:20 PM PDT 24
Finished Apr 18 03:16:41 PM PDT 24
Peak memory 672420 kb
Host smart-8af13984-a6cd-4b57-93a3-3364a8f3fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330534315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3330534315
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2930112799
Short name T321
Test name
Test status
Simulation time 880655011 ps
CPU time 7.88 seconds
Started Apr 18 03:15:21 PM PDT 24
Finished Apr 18 03:15:29 PM PDT 24
Peak memory 217508 kb
Host smart-ad813054-28c8-4c93-829b-3f73327f952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930112799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2930112799
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2471315129
Short name T442
Test name
Test status
Simulation time 1015973572 ps
CPU time 4.52 seconds
Started Apr 18 03:15:25 PM PDT 24
Finished Apr 18 03:15:29 PM PDT 24
Peak memory 203936 kb
Host smart-97b45615-5fba-481c-8148-35b717586b27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471315129 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2471315129
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2583835592
Short name T576
Test name
Test status
Simulation time 10103126468 ps
CPU time 14.24 seconds
Started Apr 18 03:15:28 PM PDT 24
Finished Apr 18 03:15:42 PM PDT 24
Peak memory 286436 kb
Host smart-7161c244-82ff-4812-8a1e-fc7aef662fee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583835592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2583835592
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2968614687
Short name T268
Test name
Test status
Simulation time 10084220982 ps
CPU time 56.08 seconds
Started Apr 18 03:15:25 PM PDT 24
Finished Apr 18 03:16:21 PM PDT 24
Peak memory 502912 kb
Host smart-6d2ceccc-e7bb-49a3-b8ad-b1a26851e3a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968614687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2968614687
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.4053426536
Short name T651
Test name
Test status
Simulation time 310286176 ps
CPU time 2.07 seconds
Started Apr 18 03:15:30 PM PDT 24
Finished Apr 18 03:15:32 PM PDT 24
Peak memory 203960 kb
Host smart-3f314761-fe57-418e-92f7-4063d62139c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053426536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.4053426536
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1889418752
Short name T410
Test name
Test status
Simulation time 6654737989 ps
CPU time 6.72 seconds
Started Apr 18 03:15:29 PM PDT 24
Finished Apr 18 03:15:36 PM PDT 24
Peak memory 218776 kb
Host smart-65b654fc-7170-4a1e-9df1-ca6da0f2d51a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889418752 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1889418752
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3638469678
Short name T626
Test name
Test status
Simulation time 13333068283 ps
CPU time 113.58 seconds
Started Apr 18 03:15:27 PM PDT 24
Finished Apr 18 03:17:21 PM PDT 24
Peak memory 1681144 kb
Host smart-9221bf88-6173-4378-ae64-b64ead3012c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638469678 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3638469678
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.3756186797
Short name T940
Test name
Test status
Simulation time 3216611263 ps
CPU time 9.96 seconds
Started Apr 18 03:15:22 PM PDT 24
Finished Apr 18 03:15:32 PM PDT 24
Peak memory 204064 kb
Host smart-87892b0a-3dd5-443a-8139-9299887e3990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756186797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.3756186797
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1039188326
Short name T1337
Test name
Test status
Simulation time 1635385847 ps
CPU time 11.58 seconds
Started Apr 18 03:15:26 PM PDT 24
Finished Apr 18 03:15:38 PM PDT 24
Peak memory 209424 kb
Host smart-8ccb183a-da3f-46e3-b127-f4b63f8e7ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039188326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1039188326
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.562322928
Short name T805
Test name
Test status
Simulation time 7420182869 ps
CPU time 11.51 seconds
Started Apr 18 03:15:27 PM PDT 24
Finished Apr 18 03:15:38 PM PDT 24
Peak memory 204012 kb
Host smart-aaac2749-846a-4a32-bcf8-ad40975ffa82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562322928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.562322928
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2341377593
Short name T445
Test name
Test status
Simulation time 3377136300 ps
CPU time 7.02 seconds
Started Apr 18 03:15:27 PM PDT 24
Finished Apr 18 03:15:34 PM PDT 24
Peak memory 220280 kb
Host smart-4a4156ee-4135-48be-9c97-9fc6ea1b8507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341377593 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2341377593
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2614079715
Short name T1204
Test name
Test status
Simulation time 44907458 ps
CPU time 0.56 seconds
Started Apr 18 03:15:49 PM PDT 24
Finished Apr 18 03:15:50 PM PDT 24
Peak memory 203580 kb
Host smart-742eee4d-824a-428a-ada8-65684f73d538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614079715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2614079715
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.557964829
Short name T670
Test name
Test status
Simulation time 398223565 ps
CPU time 1.69 seconds
Started Apr 18 03:15:38 PM PDT 24
Finished Apr 18 03:15:40 PM PDT 24
Peak memory 212312 kb
Host smart-7d568fd6-a90d-44b5-8cce-de8e75b38a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557964829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.557964829
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.870695068
Short name T253
Test name
Test status
Simulation time 548944249 ps
CPU time 13.1 seconds
Started Apr 18 03:15:36 PM PDT 24
Finished Apr 18 03:15:50 PM PDT 24
Peak memory 257432 kb
Host smart-b6ea536d-915e-4573-b161-2e243399f561
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870695068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.870695068
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.32813127
Short name T303
Test name
Test status
Simulation time 5071645683 ps
CPU time 138.46 seconds
Started Apr 18 03:15:36 PM PDT 24
Finished Apr 18 03:17:55 PM PDT 24
Peak memory 551364 kb
Host smart-404ee362-7a40-49a5-9b34-59f7559fa1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32813127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.32813127
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2526248059
Short name T42
Test name
Test status
Simulation time 12285334616 ps
CPU time 27.65 seconds
Started Apr 18 03:15:29 PM PDT 24
Finished Apr 18 03:15:58 PM PDT 24
Peak memory 454928 kb
Host smart-03e4034b-53a0-4127-b3c7-121bd777428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526248059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2526248059
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3040437459
Short name T1369
Test name
Test status
Simulation time 217330931 ps
CPU time 0.94 seconds
Started Apr 18 03:15:37 PM PDT 24
Finished Apr 18 03:15:38 PM PDT 24
Peak memory 203728 kb
Host smart-37135178-9bdc-48c0-a433-5d07821b3a0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040437459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3040437459
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2865975541
Short name T766
Test name
Test status
Simulation time 276094191 ps
CPU time 2.79 seconds
Started Apr 18 03:15:36 PM PDT 24
Finished Apr 18 03:15:40 PM PDT 24
Peak memory 203960 kb
Host smart-ba9f8128-2f59-4708-816e-beb4c9e76dcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865975541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2865975541
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1297118830
Short name T370
Test name
Test status
Simulation time 17120329040 ps
CPU time 146.34 seconds
Started Apr 18 03:15:31 PM PDT 24
Finished Apr 18 03:17:58 PM PDT 24
Peak memory 1313224 kb
Host smart-a274dc32-953d-4c13-938e-98396b4d62e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297118830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1297118830
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3885182130
Short name T1109
Test name
Test status
Simulation time 568883353 ps
CPU time 13.23 seconds
Started Apr 18 03:15:49 PM PDT 24
Finished Apr 18 03:16:02 PM PDT 24
Peak memory 203880 kb
Host smart-b538798d-11cf-429c-9bb6-9dc8dd9b6dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885182130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3885182130
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2639991678
Short name T716
Test name
Test status
Simulation time 2939196489 ps
CPU time 22.13 seconds
Started Apr 18 03:15:55 PM PDT 24
Finished Apr 18 03:16:17 PM PDT 24
Peak memory 287696 kb
Host smart-6d9f22ba-ebfe-4ba8-9eda-6b2e500658d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639991678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2639991678
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1514675286
Short name T267
Test name
Test status
Simulation time 17840158 ps
CPU time 0.67 seconds
Started Apr 18 03:15:36 PM PDT 24
Finished Apr 18 03:15:37 PM PDT 24
Peak memory 203648 kb
Host smart-00457ff8-681c-4e51-b1fc-c3805bfd4ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514675286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1514675286
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3965125460
Short name T1309
Test name
Test status
Simulation time 6339787019 ps
CPU time 584.28 seconds
Started Apr 18 03:15:36 PM PDT 24
Finished Apr 18 03:25:21 PM PDT 24
Peak memory 1577420 kb
Host smart-d5604df2-9d90-4007-8a28-496e3fbc183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965125460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3965125460
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.4029071217
Short name T1130
Test name
Test status
Simulation time 11621149797 ps
CPU time 87.63 seconds
Started Apr 18 03:15:34 PM PDT 24
Finished Apr 18 03:17:02 PM PDT 24
Peak memory 327420 kb
Host smart-9472e065-fbd3-4f8f-b61a-8f74fdf1b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029071217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.4029071217
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3324022718
Short name T688
Test name
Test status
Simulation time 39597895582 ps
CPU time 2816.52 seconds
Started Apr 18 03:15:34 PM PDT 24
Finished Apr 18 04:02:32 PM PDT 24
Peak memory 2659332 kb
Host smart-ad952cc9-ff57-4812-8816-f38db4779826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324022718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3324022718
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.906271294
Short name T1098
Test name
Test status
Simulation time 1199530223 ps
CPU time 6.25 seconds
Started Apr 18 03:15:36 PM PDT 24
Finished Apr 18 03:15:43 PM PDT 24
Peak memory 212164 kb
Host smart-a6b1bceb-c091-4a94-849a-e5cb2dbe86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906271294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.906271294
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1665517584
Short name T666
Test name
Test status
Simulation time 2760977004 ps
CPU time 3.43 seconds
Started Apr 18 03:15:43 PM PDT 24
Finished Apr 18 03:15:47 PM PDT 24
Peak memory 204032 kb
Host smart-d9f8fd7e-ba76-4050-85e4-a3bf225df9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665517584 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1665517584
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1632714727
Short name T781
Test name
Test status
Simulation time 10214518866 ps
CPU time 19.16 seconds
Started Apr 18 03:15:43 PM PDT 24
Finished Apr 18 03:16:02 PM PDT 24
Peak memory 309160 kb
Host smart-669cede1-b6f4-4c05-b985-ab612d66e1e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632714727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1632714727
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.618647085
Short name T758
Test name
Test status
Simulation time 10518888676 ps
CPU time 13.05 seconds
Started Apr 18 03:15:50 PM PDT 24
Finished Apr 18 03:16:03 PM PDT 24
Peak memory 289404 kb
Host smart-94067cef-8815-49c1-8cb2-8862b0b91cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618647085 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.618647085
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3380056258
Short name T1082
Test name
Test status
Simulation time 379749237 ps
CPU time 2.29 seconds
Started Apr 18 03:15:50 PM PDT 24
Finished Apr 18 03:15:53 PM PDT 24
Peak memory 203988 kb
Host smart-a4a3bab7-4e7a-48a2-bfa7-4239af618100
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380056258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3380056258
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3138321544
Short name T1122
Test name
Test status
Simulation time 1018742585 ps
CPU time 4.07 seconds
Started Apr 18 03:15:41 PM PDT 24
Finished Apr 18 03:15:45 PM PDT 24
Peak memory 204048 kb
Host smart-0c1ba28e-817f-43e5-93d7-7979fc4a2242
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138321544 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3138321544
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1172825156
Short name T330
Test name
Test status
Simulation time 2994437515 ps
CPU time 2.36 seconds
Started Apr 18 03:15:39 PM PDT 24
Finished Apr 18 03:15:41 PM PDT 24
Peak memory 204012 kb
Host smart-dda6af0f-359b-47ef-a08a-c7fffceb66b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172825156 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1172825156
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3420903330
Short name T948
Test name
Test status
Simulation time 641226921 ps
CPU time 8.93 seconds
Started Apr 18 03:15:37 PM PDT 24
Finished Apr 18 03:15:46 PM PDT 24
Peak memory 203944 kb
Host smart-12902ea1-6597-4199-b931-f7e90f639243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420903330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3420903330
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.152391442
Short name T570
Test name
Test status
Simulation time 7550801784 ps
CPU time 22.89 seconds
Started Apr 18 03:15:40 PM PDT 24
Finished Apr 18 03:16:03 PM PDT 24
Peak memory 231028 kb
Host smart-240f608c-7571-472b-8555-47ad3db22963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152391442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.152391442
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.631120476
Short name T1227
Test name
Test status
Simulation time 16727914028 ps
CPU time 9.25 seconds
Started Apr 18 03:15:41 PM PDT 24
Finished Apr 18 03:15:50 PM PDT 24
Peak memory 204056 kb
Host smart-206e1695-d255-4343-a743-6877c7586c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631120476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_wr.631120476
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1885963951
Short name T1371
Test name
Test status
Simulation time 8874424517 ps
CPU time 45.92 seconds
Started Apr 18 03:15:42 PM PDT 24
Finished Apr 18 03:16:28 PM PDT 24
Peak memory 645204 kb
Host smart-04bfe0af-5f0c-4919-99ba-a99cb860b387
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885963951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1885963951
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3757295439
Short name T12
Test name
Test status
Simulation time 2458965472 ps
CPU time 5.9 seconds
Started Apr 18 03:15:41 PM PDT 24
Finished Apr 18 03:15:47 PM PDT 24
Peak memory 212240 kb
Host smart-efe06e1b-b111-400d-90ec-18fdcdff3896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757295439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3757295439
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1388484694
Short name T1048
Test name
Test status
Simulation time 19427872 ps
CPU time 0.59 seconds
Started Apr 18 03:16:05 PM PDT 24
Finished Apr 18 03:16:06 PM PDT 24
Peak memory 203560 kb
Host smart-8efd687e-626a-425c-8476-287e3e65a4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388484694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1388484694
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.394618367
Short name T866
Test name
Test status
Simulation time 316919649 ps
CPU time 1.3 seconds
Started Apr 18 03:15:55 PM PDT 24
Finished Apr 18 03:15:57 PM PDT 24
Peak memory 212328 kb
Host smart-5d87867f-29ef-4752-9c98-12bb0c5d1f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394618367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.394618367
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2631661158
Short name T692
Test name
Test status
Simulation time 231788635 ps
CPU time 4.17 seconds
Started Apr 18 03:15:51 PM PDT 24
Finished Apr 18 03:15:56 PM PDT 24
Peak memory 226288 kb
Host smart-de7c4d65-cd62-4701-91fd-16ce1ef76370
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631661158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2631661158
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3235525828
Short name T1290
Test name
Test status
Simulation time 1887734676 ps
CPU time 105.07 seconds
Started Apr 18 03:15:50 PM PDT 24
Finished Apr 18 03:17:35 PM PDT 24
Peak memory 463432 kb
Host smart-4a497c20-161a-42a8-9c2b-865ba9ef3545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235525828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3235525828
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.4096703290
Short name T1352
Test name
Test status
Simulation time 8671483395 ps
CPU time 41.52 seconds
Started Apr 18 03:15:51 PM PDT 24
Finished Apr 18 03:16:33 PM PDT 24
Peak memory 572140 kb
Host smart-3cb02e2c-143f-4f00-b3da-bf556236fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096703290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.4096703290
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.563777305
Short name T495
Test name
Test status
Simulation time 349737342 ps
CPU time 0.92 seconds
Started Apr 18 03:15:50 PM PDT 24
Finished Apr 18 03:15:51 PM PDT 24
Peak memory 203728 kb
Host smart-f8e03482-acde-4820-8bc2-fbc110d27258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563777305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.563777305
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.819057466
Short name T1005
Test name
Test status
Simulation time 732885822 ps
CPU time 9.16 seconds
Started Apr 18 03:15:50 PM PDT 24
Finished Apr 18 03:15:59 PM PDT 24
Peak memory 235252 kb
Host smart-f02eb2fb-70f2-4a7a-9dee-a652368dce89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819057466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
819057466
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3951851290
Short name T415
Test name
Test status
Simulation time 2467230190 ps
CPU time 60.28 seconds
Started Apr 18 03:15:49 PM PDT 24
Finished Apr 18 03:16:50 PM PDT 24
Peak memory 764600 kb
Host smart-4d2948f8-c284-458d-95a3-be1e09a2b1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951851290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3951851290
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1446112128
Short name T1301
Test name
Test status
Simulation time 1103794705 ps
CPU time 3.48 seconds
Started Apr 18 03:16:03 PM PDT 24
Finished Apr 18 03:16:07 PM PDT 24
Peak memory 203920 kb
Host smart-88fd9ca4-3aa1-458f-acde-d3de7ffa6c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446112128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1446112128
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.549972645
Short name T847
Test name
Test status
Simulation time 152827793 ps
CPU time 0.65 seconds
Started Apr 18 03:15:49 PM PDT 24
Finished Apr 18 03:15:50 PM PDT 24
Peak memory 203648 kb
Host smart-82a379ad-23be-458c-b8b6-1f0c2245e789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549972645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.549972645
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3990987566
Short name T687
Test name
Test status
Simulation time 7717878177 ps
CPU time 14.05 seconds
Started Apr 18 03:15:58 PM PDT 24
Finished Apr 18 03:16:12 PM PDT 24
Peak memory 204008 kb
Host smart-3673b775-9266-4b61-9f72-3e42ea5f3239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990987566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3990987566
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3106583236
Short name T806
Test name
Test status
Simulation time 7510864372 ps
CPU time 24.88 seconds
Started Apr 18 03:15:51 PM PDT 24
Finished Apr 18 03:16:16 PM PDT 24
Peak memory 313784 kb
Host smart-95338871-8ac9-4149-a085-699e5fc522a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106583236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3106583236
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1240083748
Short name T354
Test name
Test status
Simulation time 616771128 ps
CPU time 26.57 seconds
Started Apr 18 03:15:55 PM PDT 24
Finished Apr 18 03:16:22 PM PDT 24
Peak memory 212196 kb
Host smart-749dc396-98bd-44d1-8cf6-58f97bd26626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240083748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1240083748
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3648364934
Short name T568
Test name
Test status
Simulation time 2373294993 ps
CPU time 3.26 seconds
Started Apr 18 03:15:58 PM PDT 24
Finished Apr 18 03:16:02 PM PDT 24
Peak memory 204000 kb
Host smart-17ce2e33-3c05-497d-b65c-e7517178374a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648364934 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3648364934
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2511752123
Short name T913
Test name
Test status
Simulation time 10063207299 ps
CPU time 67.13 seconds
Started Apr 18 03:16:01 PM PDT 24
Finished Apr 18 03:17:09 PM PDT 24
Peak memory 497132 kb
Host smart-811f7913-b43a-4c9d-8834-0c187abd6ac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511752123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2511752123
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3273574648
Short name T880
Test name
Test status
Simulation time 10466411363 ps
CPU time 14.72 seconds
Started Apr 18 03:16:01 PM PDT 24
Finished Apr 18 03:16:16 PM PDT 24
Peak memory 297632 kb
Host smart-56c2dcff-70c3-4189-a443-4e5b03ddbd18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273574648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3273574648
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.224753559
Short name T1102
Test name
Test status
Simulation time 5602136675 ps
CPU time 2.83 seconds
Started Apr 18 03:16:00 PM PDT 24
Finished Apr 18 03:16:03 PM PDT 24
Peak memory 204076 kb
Host smart-e6da4918-2a73-49f7-ade1-3efd1fbabc1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224753559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.224753559
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3881464521
Short name T594
Test name
Test status
Simulation time 594541420 ps
CPU time 3.05 seconds
Started Apr 18 03:15:56 PM PDT 24
Finished Apr 18 03:16:00 PM PDT 24
Peak memory 203976 kb
Host smart-3a4cc654-ced0-484a-80ee-8a4fdccf66bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881464521 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3881464521
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1684212148
Short name T959
Test name
Test status
Simulation time 12117905880 ps
CPU time 3.59 seconds
Started Apr 18 03:15:56 PM PDT 24
Finished Apr 18 03:16:00 PM PDT 24
Peak memory 204028 kb
Host smart-769dc684-a9f3-463d-b2a3-30110f9eb241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684212148 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1684212148
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3586897998
Short name T1134
Test name
Test status
Simulation time 2568623710 ps
CPU time 17.47 seconds
Started Apr 18 03:15:58 PM PDT 24
Finished Apr 18 03:16:15 PM PDT 24
Peak memory 204020 kb
Host smart-5dae6b37-9042-4994-842e-28e1d9a1c7d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586897998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3586897998
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3147172223
Short name T285
Test name
Test status
Simulation time 343609183 ps
CPU time 5.34 seconds
Started Apr 18 03:15:55 PM PDT 24
Finished Apr 18 03:16:01 PM PDT 24
Peak memory 203996 kb
Host smart-df15c64e-ea48-45a8-83e1-d36cb7f86cef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147172223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3147172223
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1009867766
Short name T591
Test name
Test status
Simulation time 28676319391 ps
CPU time 23.27 seconds
Started Apr 18 03:16:02 PM PDT 24
Finished Apr 18 03:16:26 PM PDT 24
Peak memory 573224 kb
Host smart-734887ad-b8a4-4526-ba99-7ee3044df563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009867766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1009867766
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1383591983
Short name T1258
Test name
Test status
Simulation time 13002871969 ps
CPU time 211.56 seconds
Started Apr 18 03:15:56 PM PDT 24
Finished Apr 18 03:19:28 PM PDT 24
Peak memory 942384 kb
Host smart-2c4e7973-db4f-4f9b-b387-2bbfe28db6b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383591983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1383591983
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3759707737
Short name T954
Test name
Test status
Simulation time 1246644711 ps
CPU time 6.4 seconds
Started Apr 18 03:15:55 PM PDT 24
Finished Apr 18 03:16:01 PM PDT 24
Peak memory 220200 kb
Host smart-4926199b-6cf0-45f0-abe8-38c85a24af21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759707737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3759707737
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1293980829
Short name T988
Test name
Test status
Simulation time 46770440 ps
CPU time 0.61 seconds
Started Apr 18 03:16:21 PM PDT 24
Finished Apr 18 03:16:22 PM PDT 24
Peak memory 203580 kb
Host smart-9cf5bd09-5fd2-49cd-9eb0-194dcce51b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293980829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1293980829
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.599959006
Short name T762
Test name
Test status
Simulation time 49099345 ps
CPU time 1.35 seconds
Started Apr 18 03:16:12 PM PDT 24
Finished Apr 18 03:16:14 PM PDT 24
Peak memory 212260 kb
Host smart-40abeb15-9967-4865-bb8d-42df8407609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599959006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.599959006
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.4262663470
Short name T1189
Test name
Test status
Simulation time 2518199149 ps
CPU time 3.73 seconds
Started Apr 18 03:16:07 PM PDT 24
Finished Apr 18 03:16:11 PM PDT 24
Peak memory 242620 kb
Host smart-02ebfe9d-7e83-4093-acb1-2586b2a77404
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262663470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.4262663470
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3712231507
Short name T47
Test name
Test status
Simulation time 2962498964 ps
CPU time 40.02 seconds
Started Apr 18 03:16:06 PM PDT 24
Finished Apr 18 03:16:47 PM PDT 24
Peak memory 570580 kb
Host smart-f320cbe5-1eb1-452f-9ec5-39006bc6f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712231507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3712231507
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.4118784616
Short name T918
Test name
Test status
Simulation time 1230832853 ps
CPU time 84.86 seconds
Started Apr 18 03:16:08 PM PDT 24
Finished Apr 18 03:17:33 PM PDT 24
Peak memory 494160 kb
Host smart-d0493ca6-18b7-43ff-9980-c81753109f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118784616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.4118784616
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1848579632
Short name T1142
Test name
Test status
Simulation time 278307416 ps
CPU time 0.88 seconds
Started Apr 18 03:16:07 PM PDT 24
Finished Apr 18 03:16:08 PM PDT 24
Peak memory 203688 kb
Host smart-567ddf9f-8ab7-4df1-ab39-8254cae6ae86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848579632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1848579632
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1868153582
Short name T475
Test name
Test status
Simulation time 481727162 ps
CPU time 3.27 seconds
Started Apr 18 03:16:07 PM PDT 24
Finished Apr 18 03:16:11 PM PDT 24
Peak memory 203920 kb
Host smart-c09102a1-1971-408e-83c0-44eece72a482
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868153582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1868153582
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2680515820
Short name T602
Test name
Test status
Simulation time 2858149860 ps
CPU time 64.64 seconds
Started Apr 18 03:16:07 PM PDT 24
Finished Apr 18 03:17:12 PM PDT 24
Peak memory 911668 kb
Host smart-af88c9a7-d851-4ed3-a6e0-6fbe79fc091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680515820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2680515820
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.746247436
Short name T1111
Test name
Test status
Simulation time 502200963 ps
CPU time 6.32 seconds
Started Apr 18 03:16:16 PM PDT 24
Finished Apr 18 03:16:23 PM PDT 24
Peak memory 203864 kb
Host smart-078e5c6a-9da5-485e-9581-90ec35795d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746247436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.746247436
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1259296326
Short name T379
Test name
Test status
Simulation time 814953128 ps
CPU time 33.14 seconds
Started Apr 18 03:16:17 PM PDT 24
Finished Apr 18 03:16:51 PM PDT 24
Peak memory 266052 kb
Host smart-37c671b0-650d-4df8-82ca-9bd7410ffa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259296326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1259296326
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3429968648
Short name T1341
Test name
Test status
Simulation time 240094137 ps
CPU time 0.63 seconds
Started Apr 18 03:16:07 PM PDT 24
Finished Apr 18 03:16:08 PM PDT 24
Peak memory 203568 kb
Host smart-655f3a40-b070-470b-8b35-cc6871ac507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429968648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3429968648
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1241567644
Short name T1153
Test name
Test status
Simulation time 27336177065 ps
CPU time 220.54 seconds
Started Apr 18 03:16:18 PM PDT 24
Finished Apr 18 03:19:59 PM PDT 24
Peak memory 1228864 kb
Host smart-f7b5ae85-c7dd-4b55-b699-5689c4e444fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241567644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1241567644
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.1590444061
Short name T744
Test name
Test status
Simulation time 6449764030 ps
CPU time 57.26 seconds
Started Apr 18 03:16:06 PM PDT 24
Finished Apr 18 03:17:04 PM PDT 24
Peak memory 315748 kb
Host smart-569fd395-b467-4401-87b0-48f9ed055b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590444061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1590444061
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.2678850453
Short name T811
Test name
Test status
Simulation time 42855376054 ps
CPU time 1197.43 seconds
Started Apr 18 03:16:11 PM PDT 24
Finished Apr 18 03:36:09 PM PDT 24
Peak memory 2142040 kb
Host smart-fbe499ab-2c24-4064-989a-700b8c7a9a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678850453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.2678850453
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2916654914
Short name T1011
Test name
Test status
Simulation time 469361060 ps
CPU time 7.74 seconds
Started Apr 18 03:16:11 PM PDT 24
Finished Apr 18 03:16:20 PM PDT 24
Peak memory 212244 kb
Host smart-663cff85-57ea-4681-af12-de5c5e196d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916654914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2916654914
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.862964410
Short name T29
Test name
Test status
Simulation time 2761421699 ps
CPU time 3.26 seconds
Started Apr 18 03:16:17 PM PDT 24
Finished Apr 18 03:16:20 PM PDT 24
Peak memory 204076 kb
Host smart-429976d4-a8a2-4b3a-b066-67e34baf22cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862964410 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.862964410
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.539770179
Short name T897
Test name
Test status
Simulation time 10310505222 ps
CPU time 11.47 seconds
Started Apr 18 03:16:11 PM PDT 24
Finished Apr 18 03:16:22 PM PDT 24
Peak memory 276976 kb
Host smart-bfa4f6af-2229-4857-b4a2-5c8177a5dbd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539770179 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.539770179
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.4070061672
Short name T980
Test name
Test status
Simulation time 10053148901 ps
CPU time 83.31 seconds
Started Apr 18 03:16:17 PM PDT 24
Finished Apr 18 03:17:41 PM PDT 24
Peak memory 551212 kb
Host smart-7764bf16-6d69-486d-bca0-ba569f2aa85d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070061672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.4070061672
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3524481032
Short name T927
Test name
Test status
Simulation time 2250238217 ps
CPU time 2.49 seconds
Started Apr 18 03:16:17 PM PDT 24
Finished Apr 18 03:16:20 PM PDT 24
Peak memory 204076 kb
Host smart-148ba93a-d784-4fec-83c6-a53de0e427c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524481032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3524481032
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.1099468251
Short name T676
Test name
Test status
Simulation time 1089584676 ps
CPU time 2.95 seconds
Started Apr 18 03:16:09 PM PDT 24
Finished Apr 18 03:16:12 PM PDT 24
Peak memory 203988 kb
Host smart-71c4eda7-97c7-4695-9cc9-b84b9ea95e8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099468251 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.1099468251
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3350555032
Short name T368
Test name
Test status
Simulation time 3459357135 ps
CPU time 2.52 seconds
Started Apr 18 03:16:10 PM PDT 24
Finished Apr 18 03:16:13 PM PDT 24
Peak memory 204068 kb
Host smart-0b7f4552-661c-4a6c-a265-9b6969cec467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350555032 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3350555032
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1124565170
Short name T643
Test name
Test status
Simulation time 2272802066 ps
CPU time 13.69 seconds
Started Apr 18 03:16:18 PM PDT 24
Finished Apr 18 03:16:32 PM PDT 24
Peak memory 204068 kb
Host smart-fc4915be-a1d8-41b7-858c-dd1c42e5e637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124565170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1124565170
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.4008268741
Short name T1241
Test name
Test status
Simulation time 5688800072 ps
CPU time 22.16 seconds
Started Apr 18 03:16:11 PM PDT 24
Finished Apr 18 03:16:33 PM PDT 24
Peak memory 232440 kb
Host smart-34540660-e96a-45ee-bf04-1b2a6d312554
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008268741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.4008268741
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.4265496757
Short name T1355
Test name
Test status
Simulation time 47087630997 ps
CPU time 488.53 seconds
Started Apr 18 03:16:12 PM PDT 24
Finished Apr 18 03:24:21 PM PDT 24
Peak memory 4145800 kb
Host smart-abcd0c4a-9696-4865-8393-1d15609f42d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265496757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.4265496757
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3593152549
Short name T293
Test name
Test status
Simulation time 24606304284 ps
CPU time 1731.15 seconds
Started Apr 18 03:16:17 PM PDT 24
Finished Apr 18 03:45:09 PM PDT 24
Peak memory 2962616 kb
Host smart-5e79d51f-3244-4d59-b192-f793b83eb707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593152549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3593152549
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2504060651
Short name T1203
Test name
Test status
Simulation time 1160454985 ps
CPU time 5.72 seconds
Started Apr 18 03:16:10 PM PDT 24
Finished Apr 18 03:16:16 PM PDT 24
Peak memory 203896 kb
Host smart-b2611029-34e5-4cf4-a1e3-0eaeb616ed34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504060651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2504060651
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.452926207
Short name T449
Test name
Test status
Simulation time 109141262 ps
CPU time 0.6 seconds
Started Apr 18 03:16:37 PM PDT 24
Finished Apr 18 03:16:38 PM PDT 24
Peak memory 203588 kb
Host smart-0a05ef28-cf52-496f-b9ad-3966dcab7af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452926207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.452926207
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3622067209
Short name T1067
Test name
Test status
Simulation time 329957766 ps
CPU time 1.46 seconds
Started Apr 18 03:16:25 PM PDT 24
Finished Apr 18 03:16:27 PM PDT 24
Peak memory 212320 kb
Host smart-011bbe40-3153-43e0-b787-fedfa008cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622067209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3622067209
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.348674105
Short name T698
Test name
Test status
Simulation time 267147703 ps
CPU time 5.12 seconds
Started Apr 18 03:16:24 PM PDT 24
Finished Apr 18 03:16:30 PM PDT 24
Peak memory 255256 kb
Host smart-421b6a5e-4adb-4962-83d6-fe28097c936f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348674105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.348674105
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.759170308
Short name T996
Test name
Test status
Simulation time 5584337029 ps
CPU time 97.79 seconds
Started Apr 18 03:16:20 PM PDT 24
Finished Apr 18 03:17:59 PM PDT 24
Peak memory 552832 kb
Host smart-7584701a-03ad-48e8-b048-0fe74bd616bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759170308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.759170308
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2216739958
Short name T369
Test name
Test status
Simulation time 14083464477 ps
CPU time 73.74 seconds
Started Apr 18 03:16:21 PM PDT 24
Finished Apr 18 03:17:35 PM PDT 24
Peak memory 802712 kb
Host smart-0b317000-f5d3-4522-913e-94ffc0a691fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216739958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2216739958
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1809443539
Short name T914
Test name
Test status
Simulation time 652727816 ps
CPU time 0.84 seconds
Started Apr 18 03:16:21 PM PDT 24
Finished Apr 18 03:16:22 PM PDT 24
Peak memory 203688 kb
Host smart-153f1bb2-3b1f-40ec-b49b-b720be6240de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809443539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1809443539
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1363310180
Short name T1089
Test name
Test status
Simulation time 213506850 ps
CPU time 2.73 seconds
Started Apr 18 03:16:22 PM PDT 24
Finished Apr 18 03:16:25 PM PDT 24
Peak memory 219664 kb
Host smart-20546179-d899-4224-a482-b9ed46822e9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363310180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1363310180
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.439605059
Short name T312
Test name
Test status
Simulation time 21024840878 ps
CPU time 280.12 seconds
Started Apr 18 03:16:17 PM PDT 24
Finished Apr 18 03:20:57 PM PDT 24
Peak memory 1143668 kb
Host smart-829350cb-bf62-4355-a4fc-460d83c0f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439605059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.439605059
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1039579666
Short name T191
Test name
Test status
Simulation time 709494445 ps
CPU time 5.81 seconds
Started Apr 18 03:16:38 PM PDT 24
Finished Apr 18 03:16:44 PM PDT 24
Peak memory 203992 kb
Host smart-d2fd665e-f695-4d91-8d28-8ab7d085fec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039579666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1039579666
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.316574195
Short name T599
Test name
Test status
Simulation time 4305890805 ps
CPU time 31.43 seconds
Started Apr 18 03:16:34 PM PDT 24
Finished Apr 18 03:17:06 PM PDT 24
Peak memory 317612 kb
Host smart-90fbd04e-480e-4f49-bd87-acb5947845fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316574195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.316574195
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3174544445
Short name T184
Test name
Test status
Simulation time 253231259 ps
CPU time 0.69 seconds
Started Apr 18 03:16:16 PM PDT 24
Finished Apr 18 03:16:18 PM PDT 24
Peak memory 203672 kb
Host smart-e4db6a9c-22fa-473a-b310-3ffceecc5e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174544445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3174544445
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1040614027
Short name T337
Test name
Test status
Simulation time 2817109541 ps
CPU time 158.67 seconds
Started Apr 18 03:16:21 PM PDT 24
Finished Apr 18 03:19:00 PM PDT 24
Peak memory 667320 kb
Host smart-b845ba05-0408-44fe-bebb-5fb729983e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040614027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1040614027
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.437742898
Short name T258
Test name
Test status
Simulation time 1670034038 ps
CPU time 86.37 seconds
Started Apr 18 03:16:17 PM PDT 24
Finished Apr 18 03:17:44 PM PDT 24
Peak memory 372640 kb
Host smart-5e58de9d-8a25-4dc0-b322-4c77920ab3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437742898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.437742898
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.54997521
Short name T232
Test name
Test status
Simulation time 35077140245 ps
CPU time 337.6 seconds
Started Apr 18 03:16:20 PM PDT 24
Finished Apr 18 03:21:58 PM PDT 24
Peak memory 1562052 kb
Host smart-ac248cfe-5d77-4999-a515-438c93f21409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54997521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.54997521
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.944883356
Short name T625
Test name
Test status
Simulation time 4661087466 ps
CPU time 7.48 seconds
Started Apr 18 03:16:24 PM PDT 24
Finished Apr 18 03:16:32 PM PDT 24
Peak memory 212288 kb
Host smart-d0609418-d8e3-49e7-bbfd-d6cfd8b83746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944883356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.944883356
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.343273925
Short name T1081
Test name
Test status
Simulation time 4595000449 ps
CPU time 3.45 seconds
Started Apr 18 03:16:32 PM PDT 24
Finished Apr 18 03:16:36 PM PDT 24
Peak memory 203992 kb
Host smart-9082bb57-c84e-48fb-969a-6292be6eecc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343273925 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.343273925
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.107795591
Short name T832
Test name
Test status
Simulation time 10378568516 ps
CPU time 12.86 seconds
Started Apr 18 03:16:26 PM PDT 24
Finished Apr 18 03:16:39 PM PDT 24
Peak memory 262920 kb
Host smart-86497a61-3f32-4d10-a87d-9612e1014c66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107795591 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.107795591
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1046370556
Short name T1073
Test name
Test status
Simulation time 10122674524 ps
CPU time 14.03 seconds
Started Apr 18 03:16:33 PM PDT 24
Finished Apr 18 03:16:47 PM PDT 24
Peak memory 290180 kb
Host smart-17d338f2-7dc2-4a75-b607-fe9bfd5f712b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046370556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1046370556
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1098254384
Short name T596
Test name
Test status
Simulation time 1812102333 ps
CPU time 2.55 seconds
Started Apr 18 03:16:32 PM PDT 24
Finished Apr 18 03:16:35 PM PDT 24
Peak memory 204004 kb
Host smart-4df20063-efed-4bd5-8e0a-ec588e389d5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098254384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1098254384
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1519859652
Short name T710
Test name
Test status
Simulation time 4067328331 ps
CPU time 4.67 seconds
Started Apr 18 03:16:25 PM PDT 24
Finished Apr 18 03:16:30 PM PDT 24
Peak memory 212236 kb
Host smart-b6e76056-c913-4fb2-bc37-632bdfed7232
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519859652 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1519859652
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.758464175
Short name T657
Test name
Test status
Simulation time 23535104823 ps
CPU time 20.56 seconds
Started Apr 18 03:16:25 PM PDT 24
Finished Apr 18 03:16:46 PM PDT 24
Peak memory 424960 kb
Host smart-d8abbd38-1b4c-41bc-b48d-27ca8fa94194
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758464175 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.758464175
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.471562827
Short name T1188
Test name
Test status
Simulation time 8735848022 ps
CPU time 14.79 seconds
Started Apr 18 03:16:26 PM PDT 24
Finished Apr 18 03:16:41 PM PDT 24
Peak memory 203992 kb
Host smart-3f9a9c91-cd55-4128-a579-fbcd7dcc0366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471562827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.471562827
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3185352895
Short name T408
Test name
Test status
Simulation time 2807441853 ps
CPU time 60.6 seconds
Started Apr 18 03:16:25 PM PDT 24
Finished Apr 18 03:17:26 PM PDT 24
Peak memory 205256 kb
Host smart-ec0f9830-94fd-4244-8bdf-26466b85660d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185352895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3185352895
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2420388470
Short name T437
Test name
Test status
Simulation time 42410743641 ps
CPU time 715.03 seconds
Started Apr 18 03:16:26 PM PDT 24
Finished Apr 18 03:28:22 PM PDT 24
Peak memory 5756044 kb
Host smart-76b93f2a-af80-4843-993b-d92b335d0088
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420388470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2420388470
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.49870441
Short name T1090
Test name
Test status
Simulation time 16924996294 ps
CPU time 331.24 seconds
Started Apr 18 03:16:27 PM PDT 24
Finished Apr 18 03:21:59 PM PDT 24
Peak memory 2168312 kb
Host smart-b9f560dd-7b96-4bb5-90ee-8941ce677975
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49870441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_stretch.49870441
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2148254502
Short name T1345
Test name
Test status
Simulation time 4630756246 ps
CPU time 6.4 seconds
Started Apr 18 03:16:27 PM PDT 24
Finished Apr 18 03:16:34 PM PDT 24
Peak memory 210292 kb
Host smart-690f4ebe-cf7f-49ec-97a4-2e06a720f717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148254502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2148254502
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.49635371
Short name T682
Test name
Test status
Simulation time 17563371 ps
CPU time 0.66 seconds
Started Apr 18 03:16:46 PM PDT 24
Finished Apr 18 03:16:48 PM PDT 24
Peak memory 203556 kb
Host smart-6722b941-e942-4a42-9175-f061c5bfa0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49635371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.49635371
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3647908752
Short name T618
Test name
Test status
Simulation time 549020451 ps
CPU time 1.03 seconds
Started Apr 18 03:16:36 PM PDT 24
Finished Apr 18 03:16:37 PM PDT 24
Peak memory 212284 kb
Host smart-d9e0275b-3b72-44ad-a66a-36985fbcc573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647908752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3647908752
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1611486606
Short name T390
Test name
Test status
Simulation time 255968079 ps
CPU time 14.12 seconds
Started Apr 18 03:16:37 PM PDT 24
Finished Apr 18 03:16:52 PM PDT 24
Peak memory 255744 kb
Host smart-ef7ffcb7-ecba-42d8-97c6-6e5caf63dcbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611486606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1611486606
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.663514904
Short name T620
Test name
Test status
Simulation time 5721519542 ps
CPU time 95.05 seconds
Started Apr 18 03:16:35 PM PDT 24
Finished Apr 18 03:18:11 PM PDT 24
Peak memory 559044 kb
Host smart-84127be1-29fe-4323-981b-33418ac58ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663514904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.663514904
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3869074220
Short name T1254
Test name
Test status
Simulation time 1903197803 ps
CPU time 141.85 seconds
Started Apr 18 03:16:36 PM PDT 24
Finished Apr 18 03:18:58 PM PDT 24
Peak memory 655256 kb
Host smart-ae8f9a7f-6902-4ae7-ba1d-9399075b95e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869074220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3869074220
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1409213907
Short name T1347
Test name
Test status
Simulation time 404556469 ps
CPU time 0.99 seconds
Started Apr 18 03:16:36 PM PDT 24
Finished Apr 18 03:16:37 PM PDT 24
Peak memory 203960 kb
Host smart-fd4d2d34-8b5e-42be-b8b7-cebf525080cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409213907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1409213907
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3744143477
Short name T204
Test name
Test status
Simulation time 512921589 ps
CPU time 8.16 seconds
Started Apr 18 03:16:39 PM PDT 24
Finished Apr 18 03:16:48 PM PDT 24
Peak memory 228852 kb
Host smart-9abdff8f-f53f-4fae-a5eb-26245c26f443
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744143477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3744143477
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3391674151
Short name T236
Test name
Test status
Simulation time 2553378754 ps
CPU time 49.7 seconds
Started Apr 18 03:16:35 PM PDT 24
Finished Apr 18 03:17:25 PM PDT 24
Peak memory 738612 kb
Host smart-d7e1e089-b611-4bf4-b424-606e4286dc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391674151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3391674151
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.3686053679
Short name T970
Test name
Test status
Simulation time 1584047573 ps
CPU time 10.45 seconds
Started Apr 18 03:16:46 PM PDT 24
Finished Apr 18 03:16:58 PM PDT 24
Peak memory 203896 kb
Host smart-1060f67c-147d-4344-ba4d-5f8cb0bc0f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686053679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3686053679
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1463009294
Short name T782
Test name
Test status
Simulation time 5773469324 ps
CPU time 30.79 seconds
Started Apr 18 03:16:46 PM PDT 24
Finished Apr 18 03:17:17 PM PDT 24
Peak memory 410644 kb
Host smart-82b0e133-9a2f-4846-861d-af7be550e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463009294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1463009294
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3703581716
Short name T499
Test name
Test status
Simulation time 50995799 ps
CPU time 0.65 seconds
Started Apr 18 03:16:35 PM PDT 24
Finished Apr 18 03:16:36 PM PDT 24
Peak memory 203660 kb
Host smart-cf0049f2-7dae-4404-b3d6-e2b2a4238074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703581716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3703581716
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.333901887
Short name T417
Test name
Test status
Simulation time 5303999326 ps
CPU time 21 seconds
Started Apr 18 03:16:35 PM PDT 24
Finished Apr 18 03:16:57 PM PDT 24
Peak memory 220720 kb
Host smart-4252481f-00ea-4842-a5be-e2c764742a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333901887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.333901887
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2443114834
Short name T269
Test name
Test status
Simulation time 3100657209 ps
CPU time 44.5 seconds
Started Apr 18 03:16:37 PM PDT 24
Finished Apr 18 03:17:21 PM PDT 24
Peak memory 301392 kb
Host smart-5b6ce701-b944-4b87-8eee-666f5eed56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443114834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2443114834
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.3736439160
Short name T1087
Test name
Test status
Simulation time 114233893118 ps
CPU time 1487.88 seconds
Started Apr 18 03:16:38 PM PDT 24
Finished Apr 18 03:41:27 PM PDT 24
Peak memory 4135772 kb
Host smart-5e439967-fb9a-4619-9da4-fe5bf47307f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736439160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.3736439160
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1328826989
Short name T350
Test name
Test status
Simulation time 1015988680 ps
CPU time 11.44 seconds
Started Apr 18 03:16:37 PM PDT 24
Finished Apr 18 03:16:49 PM PDT 24
Peak memory 213940 kb
Host smart-b880fb15-c196-4df5-b4a0-dbda959bd722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328826989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1328826989
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2831401362
Short name T644
Test name
Test status
Simulation time 533441143 ps
CPU time 2.6 seconds
Started Apr 18 03:16:42 PM PDT 24
Finished Apr 18 03:16:45 PM PDT 24
Peak memory 204036 kb
Host smart-3ec7704c-7ffb-4046-b5bb-5a0d5657ae7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831401362 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2831401362
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1223538165
Short name T1068
Test name
Test status
Simulation time 10051179923 ps
CPU time 65.85 seconds
Started Apr 18 03:16:40 PM PDT 24
Finished Apr 18 03:17:46 PM PDT 24
Peak memory 508264 kb
Host smart-26cc69a9-8f43-476b-bd4f-1c20d263da68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223538165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1223538165
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.979887026
Short name T194
Test name
Test status
Simulation time 10152666512 ps
CPU time 12.56 seconds
Started Apr 18 03:16:44 PM PDT 24
Finished Apr 18 03:16:57 PM PDT 24
Peak memory 294620 kb
Host smart-94a05298-1fdb-4dfb-b556-553117b0311c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979887026 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.979887026
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2160398894
Short name T672
Test name
Test status
Simulation time 4780949407 ps
CPU time 2.04 seconds
Started Apr 18 03:16:44 PM PDT 24
Finished Apr 18 03:16:47 PM PDT 24
Peak memory 204024 kb
Host smart-53d18f8c-c3a3-43f2-a276-0f12bfb7645b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160398894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2160398894
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.84816658
Short name T962
Test name
Test status
Simulation time 1408919823 ps
CPU time 3.59 seconds
Started Apr 18 03:16:40 PM PDT 24
Finished Apr 18 03:16:44 PM PDT 24
Peak memory 203944 kb
Host smart-1793719f-6a30-4cea-bf27-112e918c1f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84816658 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.84816658
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2639911871
Short name T1306
Test name
Test status
Simulation time 8033041905 ps
CPU time 15.45 seconds
Started Apr 18 03:16:41 PM PDT 24
Finished Apr 18 03:16:57 PM PDT 24
Peak memory 326560 kb
Host smart-79c3a2c3-d662-45c9-843d-1ee5d79c7f46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639911871 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2639911871
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2838728394
Short name T751
Test name
Test status
Simulation time 1023703613 ps
CPU time 8.1 seconds
Started Apr 18 03:16:36 PM PDT 24
Finished Apr 18 03:16:45 PM PDT 24
Peak memory 204008 kb
Host smart-798460de-86b4-4050-a0fe-e542b2cb46f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838728394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2838728394
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1482159166
Short name T1198
Test name
Test status
Simulation time 2348972393 ps
CPU time 11.35 seconds
Started Apr 18 03:16:39 PM PDT 24
Finished Apr 18 03:16:50 PM PDT 24
Peak memory 208624 kb
Host smart-02329909-e21b-482f-a919-d29a0561f884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482159166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1482159166
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3156290039
Short name T1216
Test name
Test status
Simulation time 48470667507 ps
CPU time 974.19 seconds
Started Apr 18 03:16:38 PM PDT 24
Finished Apr 18 03:32:52 PM PDT 24
Peak memory 7062796 kb
Host smart-751ab2d8-36d8-4785-82e9-618327d1738c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156290039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3156290039
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.1421641741
Short name T1080
Test name
Test status
Simulation time 8509935225 ps
CPU time 247.25 seconds
Started Apr 18 03:16:45 PM PDT 24
Finished Apr 18 03:20:52 PM PDT 24
Peak memory 2115392 kb
Host smart-059c258a-66db-42b5-a889-06a5f570972d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421641741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.1421641741
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.914150134
Short name T991
Test name
Test status
Simulation time 4992076595 ps
CPU time 6.28 seconds
Started Apr 18 03:16:43 PM PDT 24
Finished Apr 18 03:16:49 PM PDT 24
Peak memory 212260 kb
Host smart-cff410d3-9afd-4016-aaf3-8940c42ff2a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914150134 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.914150134
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1472217508
Short name T843
Test name
Test status
Simulation time 45260052 ps
CPU time 0.61 seconds
Started Apr 18 03:17:07 PM PDT 24
Finished Apr 18 03:17:08 PM PDT 24
Peak memory 203580 kb
Host smart-72939daf-de0f-4c06-bdcb-7752d36cdfb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472217508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1472217508
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.224565080
Short name T523
Test name
Test status
Simulation time 207465148 ps
CPU time 1.25 seconds
Started Apr 18 03:16:54 PM PDT 24
Finished Apr 18 03:16:56 PM PDT 24
Peak memory 204100 kb
Host smart-1f81e258-affd-4bd8-b9ce-2db4b66db50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224565080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.224565080
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2037707017
Short name T1156
Test name
Test status
Simulation time 1350126025 ps
CPU time 17.8 seconds
Started Apr 18 03:16:53 PM PDT 24
Finished Apr 18 03:17:11 PM PDT 24
Peak memory 280436 kb
Host smart-551c5bf7-ae3d-40db-8f67-991f39fd32fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037707017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2037707017
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2435306527
Short name T765
Test name
Test status
Simulation time 8065396351 ps
CPU time 61.79 seconds
Started Apr 18 03:16:53 PM PDT 24
Finished Apr 18 03:17:55 PM PDT 24
Peak memory 667540 kb
Host smart-3bc9f40a-6c7a-4a5f-a4fb-f66e86b507df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435306527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2435306527
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1729852896
Short name T1281
Test name
Test status
Simulation time 2346247760 ps
CPU time 70.05 seconds
Started Apr 18 03:16:45 PM PDT 24
Finished Apr 18 03:17:56 PM PDT 24
Peak memory 771460 kb
Host smart-8ad8d68f-7be7-425b-b1b9-0792fe6cde07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729852896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1729852896
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1432661998
Short name T774
Test name
Test status
Simulation time 465866222 ps
CPU time 1 seconds
Started Apr 18 03:16:53 PM PDT 24
Finished Apr 18 03:16:55 PM PDT 24
Peak memory 203792 kb
Host smart-0d06db99-1f1f-4f04-ae95-31b8a1f5166a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432661998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1432661998
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2187927340
Short name T1323
Test name
Test status
Simulation time 173592229 ps
CPU time 3.12 seconds
Started Apr 18 03:16:53 PM PDT 24
Finished Apr 18 03:16:57 PM PDT 24
Peak memory 223740 kb
Host smart-a8fa982f-6be3-481a-b255-93eaf08514fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187927340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2187927340
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.591943517
Short name T1286
Test name
Test status
Simulation time 14074571210 ps
CPU time 254.8 seconds
Started Apr 18 03:16:46 PM PDT 24
Finished Apr 18 03:21:02 PM PDT 24
Peak memory 1078164 kb
Host smart-99f87856-f2c4-4d52-80b3-36c8dbc02d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591943517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.591943517
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1584501715
Short name T886
Test name
Test status
Simulation time 1330854614 ps
CPU time 5.51 seconds
Started Apr 18 03:17:02 PM PDT 24
Finished Apr 18 03:17:08 PM PDT 24
Peak memory 203948 kb
Host smart-fa097d03-81ea-4f0b-8960-b2e7d4891fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584501715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1584501715
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.733149127
Short name T783
Test name
Test status
Simulation time 1313481545 ps
CPU time 19.03 seconds
Started Apr 18 03:17:00 PM PDT 24
Finished Apr 18 03:17:20 PM PDT 24
Peak memory 332816 kb
Host smart-88dade2f-93cf-4c3f-8673-dc86f24db7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733149127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.733149127
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3435191308
Short name T674
Test name
Test status
Simulation time 89255017 ps
CPU time 0.67 seconds
Started Apr 18 03:16:47 PM PDT 24
Finished Apr 18 03:16:49 PM PDT 24
Peak memory 203668 kb
Host smart-030964ef-24a5-405b-b3d4-e2ca86b99f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435191308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3435191308
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1072773114
Short name T302
Test name
Test status
Simulation time 12847741999 ps
CPU time 157.25 seconds
Started Apr 18 03:16:53 PM PDT 24
Finished Apr 18 03:19:31 PM PDT 24
Peak memory 520264 kb
Host smart-757ad442-eda7-4400-873c-1f8f04ef5767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072773114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1072773114
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.4243344190
Short name T634
Test name
Test status
Simulation time 1238852446 ps
CPU time 24.53 seconds
Started Apr 18 03:16:45 PM PDT 24
Finished Apr 18 03:17:10 PM PDT 24
Peak memory 317744 kb
Host smart-e4406449-475e-4563-9a90-f9f3a7748e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243344190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.4243344190
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.3579322870
Short name T1176
Test name
Test status
Simulation time 81058259288 ps
CPU time 3372.58 seconds
Started Apr 18 03:16:52 PM PDT 24
Finished Apr 18 04:13:06 PM PDT 24
Peak memory 1323968 kb
Host smart-fe9801fc-34c1-4262-8d84-8a8bcc78b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579322870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.3579322870
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.553251752
Short name T976
Test name
Test status
Simulation time 441396074 ps
CPU time 7.47 seconds
Started Apr 18 03:16:54 PM PDT 24
Finished Apr 18 03:17:02 PM PDT 24
Peak memory 220356 kb
Host smart-08028a69-fa59-4ed5-a698-b4991b6b415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553251752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.553251752
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2357446302
Short name T592
Test name
Test status
Simulation time 691357035 ps
CPU time 3.15 seconds
Started Apr 18 03:16:59 PM PDT 24
Finished Apr 18 03:17:03 PM PDT 24
Peak memory 203992 kb
Host smart-d36b83f4-e6a0-41f1-a9c1-d9f412e0ef80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357446302 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2357446302
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1552279044
Short name T1009
Test name
Test status
Simulation time 10487495014 ps
CPU time 8.13 seconds
Started Apr 18 03:16:55 PM PDT 24
Finished Apr 18 03:17:03 PM PDT 24
Peak memory 254100 kb
Host smart-dd40c00e-833d-471a-8648-f857be697f0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552279044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1552279044
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.3998644226
Short name T1215
Test name
Test status
Simulation time 10138692730 ps
CPU time 25.3 seconds
Started Apr 18 03:16:56 PM PDT 24
Finished Apr 18 03:17:22 PM PDT 24
Peak memory 339524 kb
Host smart-ffa68058-61f1-4c87-a7ee-e81737720fe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998644226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.3998644226
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3337199110
Short name T23
Test name
Test status
Simulation time 1574523550 ps
CPU time 2.4 seconds
Started Apr 18 03:17:02 PM PDT 24
Finished Apr 18 03:17:05 PM PDT 24
Peak memory 203888 kb
Host smart-0c96d7cc-56e8-4981-b255-4008825507a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337199110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3337199110
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2053749224
Short name T645
Test name
Test status
Simulation time 5673813203 ps
CPU time 6.62 seconds
Started Apr 18 03:16:56 PM PDT 24
Finished Apr 18 03:17:03 PM PDT 24
Peak memory 218664 kb
Host smart-c4710220-5bf9-43ef-92fd-543fc470ffdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053749224 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2053749224
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.4046023286
Short name T1051
Test name
Test status
Simulation time 22283369396 ps
CPU time 386.4 seconds
Started Apr 18 03:16:57 PM PDT 24
Finished Apr 18 03:23:24 PM PDT 24
Peak memory 3704188 kb
Host smart-772c2504-b29c-4305-9d43-318a199267c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046023286 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.4046023286
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.178833262
Short name T399
Test name
Test status
Simulation time 1633944320 ps
CPU time 13.01 seconds
Started Apr 18 03:16:59 PM PDT 24
Finished Apr 18 03:17:12 PM PDT 24
Peak memory 204016 kb
Host smart-33a37c82-37e4-41da-ba57-af50877d3cca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178833262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.178833262
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1823146981
Short name T1322
Test name
Test status
Simulation time 7670064279 ps
CPU time 15.92 seconds
Started Apr 18 03:16:57 PM PDT 24
Finished Apr 18 03:17:13 PM PDT 24
Peak memory 216740 kb
Host smart-0ba313b9-7b6b-4f50-9afd-512865a2a007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823146981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1823146981
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.373829403
Short name T245
Test name
Test status
Simulation time 13639291264 ps
CPU time 15.12 seconds
Started Apr 18 03:16:58 PM PDT 24
Finished Apr 18 03:17:13 PM PDT 24
Peak memory 204016 kb
Host smart-0fbca18c-4663-47fe-9578-c52bacd20260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373829403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.373829403
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1245615207
Short name T1365
Test name
Test status
Simulation time 6265751807 ps
CPU time 13.86 seconds
Started Apr 18 03:16:58 PM PDT 24
Finished Apr 18 03:17:12 PM PDT 24
Peak memory 326756 kb
Host smart-1a3bd7a9-cf12-40b8-bf13-0be9e2346791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245615207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1245615207
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.169206068
Short name T1123
Test name
Test status
Simulation time 8053647350 ps
CPU time 6.31 seconds
Started Apr 18 03:16:56 PM PDT 24
Finished Apr 18 03:17:03 PM PDT 24
Peak memory 220268 kb
Host smart-99271a18-e1d4-4ce2-bcee-aa052d6e930c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169206068 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_timeout.169206068
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2652920597
Short name T477
Test name
Test status
Simulation time 18350056 ps
CPU time 0.66 seconds
Started Apr 18 03:17:25 PM PDT 24
Finished Apr 18 03:17:26 PM PDT 24
Peak memory 203588 kb
Host smart-75b1bb76-f5c7-416a-b206-d00fe3435dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652920597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2652920597
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2538269646
Short name T515
Test name
Test status
Simulation time 87425252 ps
CPU time 1.55 seconds
Started Apr 18 03:17:06 PM PDT 24
Finished Apr 18 03:17:08 PM PDT 24
Peak memory 212248 kb
Host smart-694abc95-0263-4efa-a6ba-bd330d2e6f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538269646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2538269646
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3384317738
Short name T1183
Test name
Test status
Simulation time 373688746 ps
CPU time 6.16 seconds
Started Apr 18 03:17:07 PM PDT 24
Finished Apr 18 03:17:14 PM PDT 24
Peak memory 256136 kb
Host smart-cfb99fb6-2652-4d0e-8ce7-162f4e4ddcf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384317738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3384317738
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.484289122
Short name T118
Test name
Test status
Simulation time 9299751823 ps
CPU time 140.6 seconds
Started Apr 18 03:17:08 PM PDT 24
Finished Apr 18 03:19:29 PM PDT 24
Peak memory 551732 kb
Host smart-914be62e-9023-4566-8af7-ce17b428b1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484289122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.484289122
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1409852293
Short name T989
Test name
Test status
Simulation time 1250068740 ps
CPU time 30.32 seconds
Started Apr 18 03:17:07 PM PDT 24
Finished Apr 18 03:17:38 PM PDT 24
Peak memory 478752 kb
Host smart-014fc97f-72f1-4192-beb5-895eafbafbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409852293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1409852293
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2977299093
Short name T1095
Test name
Test status
Simulation time 241903516 ps
CPU time 0.88 seconds
Started Apr 18 03:17:07 PM PDT 24
Finished Apr 18 03:17:09 PM PDT 24
Peak memory 203744 kb
Host smart-307493e7-b3f5-4593-be33-09b07c9ef873
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977299093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2977299093
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.287687435
Short name T521
Test name
Test status
Simulation time 165712803 ps
CPU time 4.24 seconds
Started Apr 18 03:17:08 PM PDT 24
Finished Apr 18 03:17:13 PM PDT 24
Peak memory 203892 kb
Host smart-5be954d2-fd93-44b2-95e3-d28b5b07e0f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287687435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
287687435
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1279407043
Short name T952
Test name
Test status
Simulation time 8207363614 ps
CPU time 145.71 seconds
Started Apr 18 03:17:05 PM PDT 24
Finished Apr 18 03:19:31 PM PDT 24
Peak memory 714708 kb
Host smart-b386e6f1-d5b7-4110-bdd3-a8c63694fff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279407043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1279407043
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.812317185
Short name T969
Test name
Test status
Simulation time 443865685 ps
CPU time 17.5 seconds
Started Apr 18 03:17:23 PM PDT 24
Finished Apr 18 03:17:40 PM PDT 24
Peak memory 203920 kb
Host smart-f06ea173-e3b9-45e8-adb8-773e3e0b2ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812317185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.812317185
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1138253716
Short name T1143
Test name
Test status
Simulation time 6967031076 ps
CPU time 31.09 seconds
Started Apr 18 03:17:21 PM PDT 24
Finished Apr 18 03:17:53 PM PDT 24
Peak memory 341980 kb
Host smart-a57f72e6-a56c-434e-ad8f-807ca7a242a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138253716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1138253716
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3993891738
Short name T182
Test name
Test status
Simulation time 28325509 ps
CPU time 0.66 seconds
Started Apr 18 03:17:05 PM PDT 24
Finished Apr 18 03:17:06 PM PDT 24
Peak memory 203664 kb
Host smart-66b0ae47-c405-4f80-9a06-55ec86d33100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993891738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3993891738
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.312294194
Short name T824
Test name
Test status
Simulation time 551410988 ps
CPU time 7.04 seconds
Started Apr 18 03:17:06 PM PDT 24
Finished Apr 18 03:17:13 PM PDT 24
Peak memory 262944 kb
Host smart-2c16e2de-7577-4f8d-ba65-af1e29be6959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312294194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.312294194
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3769537701
Short name T1331
Test name
Test status
Simulation time 3564592074 ps
CPU time 30.03 seconds
Started Apr 18 03:17:04 PM PDT 24
Finished Apr 18 03:17:35 PM PDT 24
Peak memory 414212 kb
Host smart-78673d48-a713-4aea-8449-2f1d9807aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769537701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3769537701
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3542608165
Short name T1128
Test name
Test status
Simulation time 999705325 ps
CPU time 9.21 seconds
Started Apr 18 03:17:09 PM PDT 24
Finished Apr 18 03:17:18 PM PDT 24
Peak memory 220132 kb
Host smart-8a406206-38f8-4225-a3d6-b9dc5c62a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542608165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3542608165
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1001811362
Short name T855
Test name
Test status
Simulation time 740993697 ps
CPU time 3.11 seconds
Started Apr 18 03:17:16 PM PDT 24
Finished Apr 18 03:17:19 PM PDT 24
Peak memory 203980 kb
Host smart-e57b4697-f949-417e-8f0a-9d685222525c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001811362 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1001811362
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2355535386
Short name T1248
Test name
Test status
Simulation time 10136986975 ps
CPU time 9.43 seconds
Started Apr 18 03:17:15 PM PDT 24
Finished Apr 18 03:17:25 PM PDT 24
Peak memory 239272 kb
Host smart-5b3da85e-1ad3-4da4-9e4d-6da0d850a40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355535386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2355535386
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.446848640
Short name T373
Test name
Test status
Simulation time 10512408081 ps
CPU time 8.41 seconds
Started Apr 18 03:17:14 PM PDT 24
Finished Apr 18 03:17:23 PM PDT 24
Peak memory 258228 kb
Host smart-e6ab6fa0-1819-47e5-8c39-39002a036a98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446848640 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_fifo_reset_tx.446848640
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.46863281
Short name T606
Test name
Test status
Simulation time 438273852 ps
CPU time 2.78 seconds
Started Apr 18 03:17:14 PM PDT 24
Finished Apr 18 03:17:18 PM PDT 24
Peak memory 204008 kb
Host smart-b0e64162-e571-439f-a32a-aab70791527d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46863281 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.i2c_target_hrst.46863281
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3083330162
Short name T251
Test name
Test status
Simulation time 7206298964 ps
CPU time 5.63 seconds
Started Apr 18 03:17:15 PM PDT 24
Finished Apr 18 03:17:21 PM PDT 24
Peak memory 205024 kb
Host smart-3f8ce705-0245-4001-bae7-723a32838a55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083330162 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3083330162
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1291249726
Short name T454
Test name
Test status
Simulation time 19882109146 ps
CPU time 272.4 seconds
Started Apr 18 03:17:11 PM PDT 24
Finished Apr 18 03:21:44 PM PDT 24
Peak memory 2896948 kb
Host smart-d6a5c8e5-1a1b-4152-85da-7eea5d699522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291249726 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1291249726
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1754142011
Short name T709
Test name
Test status
Simulation time 1076727255 ps
CPU time 37.42 seconds
Started Apr 18 03:17:15 PM PDT 24
Finished Apr 18 03:17:53 PM PDT 24
Peak memory 203960 kb
Host smart-85129bc1-ac75-49e5-ab7c-0d160fea961d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754142011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1754142011
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3637600261
Short name T1002
Test name
Test status
Simulation time 6852220207 ps
CPU time 62.05 seconds
Started Apr 18 03:17:11 PM PDT 24
Finished Apr 18 03:18:13 PM PDT 24
Peak memory 205748 kb
Host smart-b721ebf1-7066-4970-ba23-b706fd4f045b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637600261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3637600261
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.545600254
Short name T1065
Test name
Test status
Simulation time 7121319025 ps
CPU time 4.01 seconds
Started Apr 18 03:17:11 PM PDT 24
Finished Apr 18 03:17:16 PM PDT 24
Peak memory 203980 kb
Host smart-aa296218-2a9d-4a12-9f32-e2d510aa0074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545600254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.545600254
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.520676031
Short name T286
Test name
Test status
Simulation time 28000073710 ps
CPU time 87.57 seconds
Started Apr 18 03:17:10 PM PDT 24
Finished Apr 18 03:18:38 PM PDT 24
Peak memory 437644 kb
Host smart-f5818de4-96bc-4540-8ec9-d73ac9b4b708
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520676031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.520676031
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.521278254
Short name T636
Test name
Test status
Simulation time 5353742513 ps
CPU time 6.1 seconds
Started Apr 18 03:17:11 PM PDT 24
Finished Apr 18 03:17:18 PM PDT 24
Peak memory 204080 kb
Host smart-44446544-6825-42e4-9422-9b4fbd317624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521278254 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.521278254
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1814621583
Short name T960
Test name
Test status
Simulation time 16789686 ps
CPU time 0.62 seconds
Started Apr 18 03:17:33 PM PDT 24
Finished Apr 18 03:17:34 PM PDT 24
Peak memory 203500 kb
Host smart-bc66a868-fc71-453d-bb05-310d9878b197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814621583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1814621583
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.279862111
Short name T949
Test name
Test status
Simulation time 59038056 ps
CPU time 1.87 seconds
Started Apr 18 03:17:21 PM PDT 24
Finished Apr 18 03:17:23 PM PDT 24
Peak memory 212292 kb
Host smart-02f4d916-9524-4613-9a80-4f2b2fc26147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279862111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.279862111
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1308304547
Short name T117
Test name
Test status
Simulation time 326450912 ps
CPU time 6.89 seconds
Started Apr 18 03:17:25 PM PDT 24
Finished Apr 18 03:17:33 PM PDT 24
Peak memory 271104 kb
Host smart-db19321c-2ff1-4075-8fbf-9f34af693c7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308304547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1308304547
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.687434496
Short name T1180
Test name
Test status
Simulation time 9639566028 ps
CPU time 168.05 seconds
Started Apr 18 03:17:20 PM PDT 24
Finished Apr 18 03:20:09 PM PDT 24
Peak memory 779128 kb
Host smart-76c021bd-6fbf-4438-8b0b-02deb9a70573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687434496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.687434496
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.900390096
Short name T481
Test name
Test status
Simulation time 2175875676 ps
CPU time 58.03 seconds
Started Apr 18 03:17:21 PM PDT 24
Finished Apr 18 03:18:20 PM PDT 24
Peak memory 695040 kb
Host smart-732a193f-9066-4473-b392-a98d0abf2d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900390096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.900390096
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2623773165
Short name T809
Test name
Test status
Simulation time 222420084 ps
CPU time 0.94 seconds
Started Apr 18 03:17:22 PM PDT 24
Finished Apr 18 03:17:24 PM PDT 24
Peak memory 203724 kb
Host smart-b0d17779-6f5d-405a-8f79-5c0ea10e4d40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623773165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2623773165
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4202922679
Short name T83
Test name
Test status
Simulation time 195947204 ps
CPU time 9.73 seconds
Started Apr 18 03:17:23 PM PDT 24
Finished Apr 18 03:17:33 PM PDT 24
Peak memory 238076 kb
Host smart-87d8657e-13ff-4d7b-85b8-bf464092b8af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202922679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4202922679
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1624994370
Short name T767
Test name
Test status
Simulation time 17832966959 ps
CPU time 128.47 seconds
Started Apr 18 03:17:20 PM PDT 24
Finished Apr 18 03:19:29 PM PDT 24
Peak memory 1268436 kb
Host smart-5ddf8711-67d4-433d-b691-0cb3ab7164e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624994370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1624994370
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.1959767552
Short name T659
Test name
Test status
Simulation time 788654673 ps
CPU time 15.53 seconds
Started Apr 18 03:17:30 PM PDT 24
Finished Apr 18 03:17:45 PM PDT 24
Peak memory 203928 kb
Host smart-8448545c-1357-4215-8ccf-3686cfb70a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959767552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1959767552
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2476149105
Short name T62
Test name
Test status
Simulation time 1376853068 ps
CPU time 66.18 seconds
Started Apr 18 03:17:32 PM PDT 24
Finished Apr 18 03:18:39 PM PDT 24
Peak memory 306188 kb
Host smart-ed75b452-b070-478f-93fe-08b0b338e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476149105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2476149105
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1996062596
Short name T546
Test name
Test status
Simulation time 99308319 ps
CPU time 0.6 seconds
Started Apr 18 03:17:20 PM PDT 24
Finished Apr 18 03:17:21 PM PDT 24
Peak memory 203664 kb
Host smart-1136901f-ab09-4c90-b27c-af994fe4471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996062596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1996062596
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3853979726
Short name T544
Test name
Test status
Simulation time 18422867261 ps
CPU time 85 seconds
Started Apr 18 03:17:23 PM PDT 24
Finished Apr 18 03:18:49 PM PDT 24
Peak memory 562796 kb
Host smart-62e07537-36c0-4c39-9078-a3ec520b7739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853979726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3853979726
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1561525674
Short name T770
Test name
Test status
Simulation time 4208231165 ps
CPU time 21.57 seconds
Started Apr 18 03:17:21 PM PDT 24
Finished Apr 18 03:17:43 PM PDT 24
Peak memory 300660 kb
Host smart-a3f6869a-16db-4832-9fe6-f894a2ff65ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561525674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1561525674
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1955569181
Short name T45
Test name
Test status
Simulation time 12502661406 ps
CPU time 1356.03 seconds
Started Apr 18 03:17:20 PM PDT 24
Finished Apr 18 03:39:57 PM PDT 24
Peak memory 2682128 kb
Host smart-6b5fc43e-a618-484f-8eaf-86f95b46af4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955569181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1955569181
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3373329608
Short name T289
Test name
Test status
Simulation time 610107809 ps
CPU time 11.18 seconds
Started Apr 18 03:17:23 PM PDT 24
Finished Apr 18 03:17:34 PM PDT 24
Peak memory 215788 kb
Host smart-e581a82a-b464-4a00-a55e-d1249a83f767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373329608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3373329608
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2700230980
Short name T613
Test name
Test status
Simulation time 544602336 ps
CPU time 2.69 seconds
Started Apr 18 03:17:33 PM PDT 24
Finished Apr 18 03:17:36 PM PDT 24
Peak memory 203968 kb
Host smart-fa8a65dc-82fd-4ae7-8917-3fa0b8be97b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700230980 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2700230980
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3727900245
Short name T1028
Test name
Test status
Simulation time 10295556539 ps
CPU time 5.94 seconds
Started Apr 18 03:17:31 PM PDT 24
Finished Apr 18 03:17:37 PM PDT 24
Peak memory 228940 kb
Host smart-44f844e6-eb34-430d-910b-716a2d359b15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727900245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3727900245
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.391436062
Short name T34
Test name
Test status
Simulation time 10134802099 ps
CPU time 15.13 seconds
Started Apr 18 03:17:29 PM PDT 24
Finished Apr 18 03:17:44 PM PDT 24
Peak memory 295824 kb
Host smart-4691f64f-42ff-418f-96e1-070b07a8a3a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391436062 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.391436062
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1440607406
Short name T1288
Test name
Test status
Simulation time 856937980 ps
CPU time 1.95 seconds
Started Apr 18 03:17:32 PM PDT 24
Finished Apr 18 03:17:34 PM PDT 24
Peak memory 203932 kb
Host smart-0b7b3a11-fed8-4cac-821e-99a814cc14f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440607406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1440607406
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3066034115
Short name T1034
Test name
Test status
Simulation time 16520502312 ps
CPU time 6.1 seconds
Started Apr 18 03:17:25 PM PDT 24
Finished Apr 18 03:17:32 PM PDT 24
Peak memory 214480 kb
Host smart-062b16a2-2b30-4ab0-9af2-af702be861fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066034115 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3066034115
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1285676579
Short name T1058
Test name
Test status
Simulation time 21817420807 ps
CPU time 412.42 seconds
Started Apr 18 03:17:25 PM PDT 24
Finished Apr 18 03:24:18 PM PDT 24
Peak memory 3755976 kb
Host smart-2871fd4a-ccd0-4d9c-8017-445f93e4afe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285676579 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1285676579
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3093224520
Short name T424
Test name
Test status
Simulation time 5770502355 ps
CPU time 23.14 seconds
Started Apr 18 03:17:27 PM PDT 24
Finished Apr 18 03:17:50 PM PDT 24
Peak memory 204064 kb
Host smart-dc20f1e6-3034-4084-b315-4739570a0929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093224520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3093224520
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1350923535
Short name T779
Test name
Test status
Simulation time 4151872485 ps
CPU time 18.19 seconds
Started Apr 18 03:17:25 PM PDT 24
Finished Apr 18 03:17:44 PM PDT 24
Peak memory 217028 kb
Host smart-2a4de8d7-59af-418c-81f2-11bb2ecf1cce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350923535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1350923535
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2181531681
Short name T1040
Test name
Test status
Simulation time 48221412480 ps
CPU time 101.43 seconds
Started Apr 18 03:17:27 PM PDT 24
Finished Apr 18 03:19:09 PM PDT 24
Peak memory 1399576 kb
Host smart-098a8920-4a58-435f-bc1e-866ca47213df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181531681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2181531681
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3879886511
Short name T1112
Test name
Test status
Simulation time 2380003097 ps
CPU time 6.27 seconds
Started Apr 18 03:17:28 PM PDT 24
Finished Apr 18 03:17:34 PM PDT 24
Peak memory 216904 kb
Host smart-26743af9-b4aa-4b99-9af2-8e6cfe713d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879886511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3879886511
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1440679561
Short name T607
Test name
Test status
Simulation time 23524754 ps
CPU time 0.62 seconds
Started Apr 18 03:17:50 PM PDT 24
Finished Apr 18 03:17:51 PM PDT 24
Peak memory 203520 kb
Host smart-929296bf-d0eb-4e73-9bce-644f891c08d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440679561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1440679561
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2075158858
Short name T1325
Test name
Test status
Simulation time 192733744 ps
CPU time 1.33 seconds
Started Apr 18 03:17:40 PM PDT 24
Finished Apr 18 03:17:42 PM PDT 24
Peak memory 212228 kb
Host smart-4b5d631b-f01d-46cc-90d3-d46385d79985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075158858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2075158858
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3148579852
Short name T195
Test name
Test status
Simulation time 230679734 ps
CPU time 4.46 seconds
Started Apr 18 03:17:37 PM PDT 24
Finished Apr 18 03:17:42 PM PDT 24
Peak memory 247324 kb
Host smart-53aa4da5-6944-4e64-bcd3-37674564d620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148579852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.3148579852
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.1876826912
Short name T713
Test name
Test status
Simulation time 1478403319 ps
CPU time 38.46 seconds
Started Apr 18 03:17:41 PM PDT 24
Finished Apr 18 03:18:20 PM PDT 24
Peak memory 525424 kb
Host smart-949e2ce3-8d4f-44ec-8258-8dab7de746be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876826912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1876826912
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.36287162
Short name T436
Test name
Test status
Simulation time 3577233207 ps
CPU time 57.33 seconds
Started Apr 18 03:17:36 PM PDT 24
Finished Apr 18 03:18:33 PM PDT 24
Peak memory 574288 kb
Host smart-e0453f23-31a3-4665-8ffb-76431e344dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36287162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.36287162
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3613388100
Short name T1124
Test name
Test status
Simulation time 231073902 ps
CPU time 1 seconds
Started Apr 18 03:17:35 PM PDT 24
Finished Apr 18 03:17:36 PM PDT 24
Peak memory 203692 kb
Host smart-d205877c-9112-41ca-856a-e91c2ca1cd1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613388100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3613388100
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.4267019581
Short name T807
Test name
Test status
Simulation time 209209382 ps
CPU time 2.73 seconds
Started Apr 18 03:17:39 PM PDT 24
Finished Apr 18 03:17:42 PM PDT 24
Peak memory 203924 kb
Host smart-d8b431c2-99cd-495a-9c8a-9e890f654f7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267019581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.4267019581
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3583898720
Short name T792
Test name
Test status
Simulation time 13224870328 ps
CPU time 215.42 seconds
Started Apr 18 03:17:35 PM PDT 24
Finished Apr 18 03:21:11 PM PDT 24
Peak memory 909400 kb
Host smart-ee614e27-c4a6-4ec3-a0c1-bdf0a40cdd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583898720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3583898720
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.4055628185
Short name T1242
Test name
Test status
Simulation time 497286970 ps
CPU time 6.36 seconds
Started Apr 18 03:17:43 PM PDT 24
Finished Apr 18 03:17:50 PM PDT 24
Peak memory 203916 kb
Host smart-d8466aff-e96c-4c25-acdb-ddb0c76bfd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055628185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.4055628185
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2294802847
Short name T938
Test name
Test status
Simulation time 3175098876 ps
CPU time 35.78 seconds
Started Apr 18 03:17:45 PM PDT 24
Finished Apr 18 03:18:21 PM PDT 24
Peak memory 430668 kb
Host smart-96f3be93-f3f1-47d4-a5cd-687ad7e9c02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294802847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2294802847
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.516144753
Short name T531
Test name
Test status
Simulation time 26426883 ps
CPU time 0.64 seconds
Started Apr 18 03:17:36 PM PDT 24
Finished Apr 18 03:17:37 PM PDT 24
Peak memory 203572 kb
Host smart-491b7819-6586-4c8c-ac59-fb8996a01d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516144753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.516144753
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1428113858
Short name T407
Test name
Test status
Simulation time 7066993007 ps
CPU time 50.45 seconds
Started Apr 18 03:17:41 PM PDT 24
Finished Apr 18 03:18:32 PM PDT 24
Peak memory 203964 kb
Host smart-bf73ada6-89e3-479a-a1a4-0feb6128008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428113858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1428113858
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1180913878
Short name T526
Test name
Test status
Simulation time 809910021 ps
CPU time 10.99 seconds
Started Apr 18 03:17:36 PM PDT 24
Finished Apr 18 03:17:48 PM PDT 24
Peak memory 258264 kb
Host smart-5f74e41e-3aa9-451c-a73a-dc2e49606258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180913878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1180913878
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.908784267
Short name T612
Test name
Test status
Simulation time 2788580059 ps
CPU time 10.84 seconds
Started Apr 18 03:17:39 PM PDT 24
Finished Apr 18 03:17:51 PM PDT 24
Peak memory 228344 kb
Host smart-bd60b862-8739-47a9-90ca-b977c60f18d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908784267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.908784267
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2358267176
Short name T362
Test name
Test status
Simulation time 489028780 ps
CPU time 2.95 seconds
Started Apr 18 03:17:46 PM PDT 24
Finished Apr 18 03:17:49 PM PDT 24
Peak memory 204008 kb
Host smart-44df82f4-2923-41a2-a6e6-f2fae12ecfdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358267176 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2358267176
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2555622439
Short name T393
Test name
Test status
Simulation time 10067820968 ps
CPU time 73.22 seconds
Started Apr 18 03:17:46 PM PDT 24
Finished Apr 18 03:19:00 PM PDT 24
Peak memory 480924 kb
Host smart-b871cae0-2ffe-4ab5-9392-9f319fb5fed6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555622439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2555622439
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1261410272
Short name T907
Test name
Test status
Simulation time 10077993664 ps
CPU time 78.85 seconds
Started Apr 18 03:17:45 PM PDT 24
Finished Apr 18 03:19:04 PM PDT 24
Peak memory 577644 kb
Host smart-4b25801b-9ea6-4e65-8c8a-d24003e093fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261410272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1261410272
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.3424987528
Short name T997
Test name
Test status
Simulation time 420457004 ps
CPU time 2.33 seconds
Started Apr 18 03:17:53 PM PDT 24
Finished Apr 18 03:17:56 PM PDT 24
Peak memory 203988 kb
Host smart-8713c867-9f83-4b6f-a447-aa5943f1646b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424987528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.3424987528
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.36198414
Short name T429
Test name
Test status
Simulation time 2410486595 ps
CPU time 6.02 seconds
Started Apr 18 03:17:42 PM PDT 24
Finished Apr 18 03:17:49 PM PDT 24
Peak memory 211720 kb
Host smart-87a27afb-8a68-45c8-bc43-7c7e7e85c46a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36198414 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.36198414
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2169115952
Short name T530
Test name
Test status
Simulation time 17643875818 ps
CPU time 211.37 seconds
Started Apr 18 03:17:46 PM PDT 24
Finished Apr 18 03:21:18 PM PDT 24
Peak memory 2786316 kb
Host smart-74964128-af97-432a-bfc1-c0846fc95f7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169115952 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2169115952
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3521052372
Short name T1132
Test name
Test status
Simulation time 4030680599 ps
CPU time 13.27 seconds
Started Apr 18 03:17:40 PM PDT 24
Finished Apr 18 03:17:54 PM PDT 24
Peak memory 204096 kb
Host smart-fadb9449-73af-4f3e-9f15-0e60b3fab333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521052372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3521052372
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1095429923
Short name T287
Test name
Test status
Simulation time 9802642035 ps
CPU time 16.87 seconds
Started Apr 18 03:17:39 PM PDT 24
Finished Apr 18 03:17:57 PM PDT 24
Peak memory 212468 kb
Host smart-08060ead-7971-411d-a3cd-34a299ee0f71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095429923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1095429923
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1610434004
Short name T31
Test name
Test status
Simulation time 37668052851 ps
CPU time 509.47 seconds
Started Apr 18 03:17:41 PM PDT 24
Finished Apr 18 03:26:11 PM PDT 24
Peak memory 4592248 kb
Host smart-d3a7b718-8aed-4aa7-930a-67e8554f28d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610434004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1610434004
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3692373774
Short name T1316
Test name
Test status
Simulation time 22387889144 ps
CPU time 660.12 seconds
Started Apr 18 03:17:41 PM PDT 24
Finished Apr 18 03:28:41 PM PDT 24
Peak memory 3333796 kb
Host smart-e96a4bfb-a731-42a4-9d81-e4343b5b763a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692373774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3692373774
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1017825668
Short name T978
Test name
Test status
Simulation time 5861450569 ps
CPU time 6.86 seconds
Started Apr 18 03:17:54 PM PDT 24
Finished Apr 18 03:18:01 PM PDT 24
Peak memory 212252 kb
Host smart-bad43090-be67-4850-8c55-99acfbb07f7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017825668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1017825668
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3603759639
Short name T865
Test name
Test status
Simulation time 19688869 ps
CPU time 0.62 seconds
Started Apr 18 03:06:27 PM PDT 24
Finished Apr 18 03:06:28 PM PDT 24
Peak memory 203588 kb
Host smart-e2de00c8-2981-4a76-93f6-cc6fe7411381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603759639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3603759639
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.4131200769
Short name T533
Test name
Test status
Simulation time 281252545 ps
CPU time 1.42 seconds
Started Apr 18 03:06:02 PM PDT 24
Finished Apr 18 03:06:03 PM PDT 24
Peak memory 212276 kb
Host smart-0890ed42-6014-4e0a-90ce-9408aa99179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131200769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.4131200769
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3867204936
Short name T967
Test name
Test status
Simulation time 1449966443 ps
CPU time 7.61 seconds
Started Apr 18 03:05:55 PM PDT 24
Finished Apr 18 03:06:03 PM PDT 24
Peak memory 276512 kb
Host smart-7f5fb4ce-f2fd-4f93-8f51-b1c5ec884008
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867204936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3867204936
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.110369465
Short name T760
Test name
Test status
Simulation time 2021892794 ps
CPU time 66.53 seconds
Started Apr 18 03:05:55 PM PDT 24
Finished Apr 18 03:07:02 PM PDT 24
Peak memory 682220 kb
Host smart-fd766eb4-4acc-4abc-9fbf-63dfd8ffb72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110369465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.110369465
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1976502119
Short name T695
Test name
Test status
Simulation time 22796916308 ps
CPU time 39.03 seconds
Started Apr 18 03:05:54 PM PDT 24
Finished Apr 18 03:06:34 PM PDT 24
Peak memory 489272 kb
Host smart-7df91d3d-87ab-46ec-8744-ac1f0816ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976502119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1976502119
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.3766625133
Short name T589
Test name
Test status
Simulation time 75208577 ps
CPU time 0.8 seconds
Started Apr 18 03:05:57 PM PDT 24
Finished Apr 18 03:05:58 PM PDT 24
Peak memory 203604 kb
Host smart-604cbfc4-0669-4bdc-9d4a-ffbdebe92f80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766625133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.3766625133
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2511449807
Short name T814
Test name
Test status
Simulation time 112106617 ps
CPU time 2.49 seconds
Started Apr 18 03:05:56 PM PDT 24
Finished Apr 18 03:05:58 PM PDT 24
Peak memory 203980 kb
Host smart-4255c4ff-27fe-4082-b417-8f96a367a92f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511449807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2511449807
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.422995334
Short name T101
Test name
Test status
Simulation time 3301303658 ps
CPU time 223.91 seconds
Started Apr 18 03:05:55 PM PDT 24
Finished Apr 18 03:09:40 PM PDT 24
Peak memory 984308 kb
Host smart-15254260-fe64-48af-be9c-1303f64f9171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422995334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.422995334
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3699560037
Short name T667
Test name
Test status
Simulation time 410499403 ps
CPU time 16.5 seconds
Started Apr 18 03:06:24 PM PDT 24
Finished Apr 18 03:06:41 PM PDT 24
Peak memory 203972 kb
Host smart-fbf0b93f-5d85-44fc-a93e-d71eb562060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699560037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3699560037
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.301486890
Short name T61
Test name
Test status
Simulation time 5594754396 ps
CPU time 65.67 seconds
Started Apr 18 03:06:22 PM PDT 24
Finished Apr 18 03:07:29 PM PDT 24
Peak memory 343620 kb
Host smart-70774471-c147-4f16-a0db-fe8d82a7d3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301486890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.301486890
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2419241089
Short name T382
Test name
Test status
Simulation time 28253557 ps
CPU time 0.67 seconds
Started Apr 18 03:05:58 PM PDT 24
Finished Apr 18 03:05:59 PM PDT 24
Peak memory 203700 kb
Host smart-ddb8ec0e-5830-4db2-9641-17f8cb0964d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419241089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2419241089
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.67260154
Short name T1088
Test name
Test status
Simulation time 94810014523 ps
CPU time 529.25 seconds
Started Apr 18 03:05:57 PM PDT 24
Finished Apr 18 03:14:46 PM PDT 24
Peak memory 203924 kb
Host smart-e804ae49-79cb-4444-a99f-a55e2477fafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67260154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.67260154
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.4113200349
Short name T1045
Test name
Test status
Simulation time 4543101809 ps
CPU time 20.85 seconds
Started Apr 18 03:05:49 PM PDT 24
Finished Apr 18 03:06:10 PM PDT 24
Peak memory 310516 kb
Host smart-2df18351-26d6-4e99-9e51-30c9a2ad90af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113200349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.4113200349
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3076458800
Short name T1071
Test name
Test status
Simulation time 1383748964 ps
CPU time 31.69 seconds
Started Apr 18 03:06:01 PM PDT 24
Finished Apr 18 03:06:33 PM PDT 24
Peak memory 213240 kb
Host smart-119c964c-2ab3-4dde-a1f4-78a1a231216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076458800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3076458800
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.4159090368
Short name T111
Test name
Test status
Simulation time 193699380 ps
CPU time 0.92 seconds
Started Apr 18 03:06:23 PM PDT 24
Finished Apr 18 03:06:24 PM PDT 24
Peak memory 221084 kb
Host smart-6f8a5213-d6ff-448d-9c53-9a9edfb1781c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159090368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.4159090368
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2786394882
Short name T1351
Test name
Test status
Simulation time 710711875 ps
CPU time 3.3 seconds
Started Apr 18 03:06:14 PM PDT 24
Finished Apr 18 03:06:18 PM PDT 24
Peak memory 203984 kb
Host smart-30bd218d-acba-4f4e-8d63-da83d20d21ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786394882 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2786394882
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1797801437
Short name T769
Test name
Test status
Simulation time 10100987219 ps
CPU time 66.58 seconds
Started Apr 18 03:06:08 PM PDT 24
Finished Apr 18 03:07:15 PM PDT 24
Peak memory 496400 kb
Host smart-24b359b2-b4b0-4940-835f-6f62a799e35f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797801437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1797801437
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.404262921
Short name T547
Test name
Test status
Simulation time 10056241790 ps
CPU time 63.63 seconds
Started Apr 18 03:06:07 PM PDT 24
Finished Apr 18 03:07:11 PM PDT 24
Peak memory 517064 kb
Host smart-aa952da6-7660-4333-9576-12c31f8f2d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404262921 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.404262921
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.632934951
Short name T24
Test name
Test status
Simulation time 764934132 ps
CPU time 2.19 seconds
Started Apr 18 03:06:14 PM PDT 24
Finished Apr 18 03:06:16 PM PDT 24
Peak memory 203968 kb
Host smart-6a0dc690-0a66-404f-b896-9eda3e03983f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632934951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.632934951
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2772664438
Short name T1267
Test name
Test status
Simulation time 2068917853 ps
CPU time 2.68 seconds
Started Apr 18 03:07:21 PM PDT 24
Finished Apr 18 03:07:24 PM PDT 24
Peak memory 204028 kb
Host smart-61463e66-857c-4184-9d4f-31c9cf53eb60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772664438 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2772664438
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3197588789
Short name T696
Test name
Test status
Simulation time 14395393279 ps
CPU time 117.57 seconds
Started Apr 18 03:06:08 PM PDT 24
Finished Apr 18 03:08:05 PM PDT 24
Peak memory 1800172 kb
Host smart-40702e2f-8847-4d06-8774-0329e17a2a37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197588789 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3197588789
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3155330006
Short name T223
Test name
Test status
Simulation time 1038995711 ps
CPU time 13.31 seconds
Started Apr 18 03:06:02 PM PDT 24
Finished Apr 18 03:06:15 PM PDT 24
Peak memory 203976 kb
Host smart-4fb92bf3-2842-4f8a-824e-d08a6c425653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155330006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3155330006
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.336529354
Short name T1146
Test name
Test status
Simulation time 1384056780 ps
CPU time 29.93 seconds
Started Apr 18 03:06:03 PM PDT 24
Finished Apr 18 03:06:33 PM PDT 24
Peak memory 203980 kb
Host smart-629a8774-e71a-40f1-adc8-a4f5a0b71c94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336529354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.336529354
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2754561140
Short name T850
Test name
Test status
Simulation time 10826551184 ps
CPU time 20.33 seconds
Started Apr 18 03:06:03 PM PDT 24
Finished Apr 18 03:06:23 PM PDT 24
Peak memory 204060 kb
Host smart-1848eba9-ab2c-4c83-a1d0-5757273ba9b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754561140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2754561140
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.453241159
Short name T690
Test name
Test status
Simulation time 15438681111 ps
CPU time 88.09 seconds
Started Apr 18 03:06:06 PM PDT 24
Finished Apr 18 03:07:34 PM PDT 24
Peak memory 951800 kb
Host smart-658c679e-bc1a-49c8-9509-c171eae6ffd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453241159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.453241159
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1374158039
Short name T743
Test name
Test status
Simulation time 4672822035 ps
CPU time 6.14 seconds
Started Apr 18 03:06:07 PM PDT 24
Finished Apr 18 03:06:14 PM PDT 24
Peak memory 219036 kb
Host smart-ae9c3302-66ba-4100-8499-07a675543193
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374158039 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1374158039
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3907639931
Short name T717
Test name
Test status
Simulation time 25439489 ps
CPU time 0.58 seconds
Started Apr 18 03:17:58 PM PDT 24
Finished Apr 18 03:17:59 PM PDT 24
Peak memory 203576 kb
Host smart-eefc5af0-6cbe-4bd5-a798-aeb09ed09b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907639931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3907639931
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1303839018
Short name T490
Test name
Test status
Simulation time 445945055 ps
CPU time 1.34 seconds
Started Apr 18 03:17:57 PM PDT 24
Finished Apr 18 03:17:59 PM PDT 24
Peak memory 212316 kb
Host smart-8d5398f8-6969-447e-be59-b6ef8de050f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303839018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1303839018
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.65268580
Short name T426
Test name
Test status
Simulation time 2989388114 ps
CPU time 13.74 seconds
Started Apr 18 03:17:50 PM PDT 24
Finished Apr 18 03:18:04 PM PDT 24
Peak memory 255120 kb
Host smart-6504072f-c452-4e32-93a8-ee2023950fbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65268580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty
.65268580
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.194644846
Short name T1069
Test name
Test status
Simulation time 3270084922 ps
CPU time 80.48 seconds
Started Apr 18 03:17:51 PM PDT 24
Finished Apr 18 03:19:12 PM PDT 24
Peak memory 212200 kb
Host smart-0e6183f1-f33c-4839-8d93-eacd5ce5210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194644846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.194644846
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.278178611
Short name T352
Test name
Test status
Simulation time 6547781715 ps
CPU time 107.26 seconds
Started Apr 18 03:17:50 PM PDT 24
Finished Apr 18 03:19:38 PM PDT 24
Peak memory 577712 kb
Host smart-5177de9f-e1af-4ada-9caf-6351a622c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278178611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.278178611
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1167078181
Short name T764
Test name
Test status
Simulation time 68865055 ps
CPU time 0.79 seconds
Started Apr 18 03:17:54 PM PDT 24
Finished Apr 18 03:17:55 PM PDT 24
Peak memory 203072 kb
Host smart-5697479f-3bbc-4709-81fd-e5963bf0630c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167078181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1167078181
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.551728939
Short name T1269
Test name
Test status
Simulation time 154774098 ps
CPU time 3.81 seconds
Started Apr 18 03:17:50 PM PDT 24
Finished Apr 18 03:17:54 PM PDT 24
Peak memory 226756 kb
Host smart-2ed31076-bd39-4cbd-bec4-2b5505ffee12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551728939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
551728939
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2018706713
Short name T862
Test name
Test status
Simulation time 33978468689 ps
CPU time 133.36 seconds
Started Apr 18 03:17:53 PM PDT 24
Finished Apr 18 03:20:07 PM PDT 24
Peak memory 709864 kb
Host smart-3f6f6538-c92e-4fe1-9e5e-4596eff866bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018706713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2018706713
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1252970352
Short name T1205
Test name
Test status
Simulation time 358183020 ps
CPU time 3.85 seconds
Started Apr 18 03:18:01 PM PDT 24
Finished Apr 18 03:18:05 PM PDT 24
Peak memory 203952 kb
Host smart-e6250d53-3fb1-4405-a92b-3ee01f20c71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252970352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1252970352
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.2062927703
Short name T64
Test name
Test status
Simulation time 1237860212 ps
CPU time 24.8 seconds
Started Apr 18 03:18:00 PM PDT 24
Finished Apr 18 03:18:25 PM PDT 24
Peak memory 279268 kb
Host smart-9888a2d8-9138-4db6-99a7-3cad9e5a0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062927703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.2062927703
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2841295500
Short name T1171
Test name
Test status
Simulation time 202770168 ps
CPU time 0.67 seconds
Started Apr 18 03:17:50 PM PDT 24
Finished Apr 18 03:17:51 PM PDT 24
Peak memory 203668 kb
Host smart-05c737b0-7543-4d45-b6f7-99e6e38060b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841295500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2841295500
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3791575534
Short name T1155
Test name
Test status
Simulation time 2717315807 ps
CPU time 26.61 seconds
Started Apr 18 03:17:52 PM PDT 24
Finished Apr 18 03:18:18 PM PDT 24
Peak memory 212192 kb
Host smart-fc7ad1a8-1ebe-4a6f-8d33-4ef2bb913554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791575534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3791575534
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2302567338
Short name T877
Test name
Test status
Simulation time 6580156736 ps
CPU time 16.55 seconds
Started Apr 18 03:17:50 PM PDT 24
Finished Apr 18 03:18:07 PM PDT 24
Peak memory 299368 kb
Host smart-c241e215-658f-41be-b192-5f454667c7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302567338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2302567338
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2661265949
Short name T241
Test name
Test status
Simulation time 32750260451 ps
CPU time 719.86 seconds
Started Apr 18 03:17:54 PM PDT 24
Finished Apr 18 03:29:54 PM PDT 24
Peak memory 1820652 kb
Host smart-c8a936ae-13df-48ae-9ef2-e1c23c2e736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661265949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2661265949
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3960597671
Short name T554
Test name
Test status
Simulation time 1738259765 ps
CPU time 21.4 seconds
Started Apr 18 03:17:51 PM PDT 24
Finished Apr 18 03:18:13 PM PDT 24
Peak memory 212208 kb
Host smart-ddde79eb-5677-4292-a6a8-ba395b22f164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960597671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3960597671
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2680531033
Short name T705
Test name
Test status
Simulation time 3397943277 ps
CPU time 3.13 seconds
Started Apr 18 03:17:54 PM PDT 24
Finished Apr 18 03:17:57 PM PDT 24
Peak memory 204072 kb
Host smart-abc45473-0653-4b86-831b-88e5a394e28e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680531033 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2680531033
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.3566798684
Short name T1036
Test name
Test status
Simulation time 10048487352 ps
CPU time 91.63 seconds
Started Apr 18 03:17:58 PM PDT 24
Finished Apr 18 03:19:30 PM PDT 24
Peak memory 546768 kb
Host smart-3de84f06-ef26-4deb-88c7-fe6f9b518747
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566798684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.3566798684
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1414742692
Short name T906
Test name
Test status
Simulation time 411298366 ps
CPU time 2.39 seconds
Started Apr 18 03:18:00 PM PDT 24
Finished Apr 18 03:18:03 PM PDT 24
Peak memory 203896 kb
Host smart-645270e1-b48f-4683-8d17-779b2962051e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414742692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1414742692
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3046228131
Short name T119
Test name
Test status
Simulation time 1172184335 ps
CPU time 5.2 seconds
Started Apr 18 03:17:58 PM PDT 24
Finished Apr 18 03:18:04 PM PDT 24
Peak memory 206376 kb
Host smart-1f08894c-6d7f-4660-a37e-fc740f971fde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046228131 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3046228131
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2427207231
Short name T1346
Test name
Test status
Simulation time 21968240846 ps
CPU time 298.8 seconds
Started Apr 18 03:17:56 PM PDT 24
Finished Apr 18 03:22:55 PM PDT 24
Peak memory 3262528 kb
Host smart-991131d6-9498-41ba-b3f4-5e9921a236ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427207231 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2427207231
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3661927272
Short name T640
Test name
Test status
Simulation time 6690176995 ps
CPU time 21.01 seconds
Started Apr 18 03:17:56 PM PDT 24
Finished Apr 18 03:18:17 PM PDT 24
Peak memory 204100 kb
Host smart-7e82e5d4-d539-4a01-bf4e-81533888bc89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661927272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3661927272
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3240606224
Short name T573
Test name
Test status
Simulation time 1727354409 ps
CPU time 13.89 seconds
Started Apr 18 03:17:56 PM PDT 24
Finished Apr 18 03:18:11 PM PDT 24
Peak memory 204032 kb
Host smart-4f3b53cc-5021-49c7-97b2-e6656959daf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240606224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3240606224
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3402092016
Short name T1063
Test name
Test status
Simulation time 30091937369 ps
CPU time 205.06 seconds
Started Apr 18 03:17:56 PM PDT 24
Finished Apr 18 03:21:22 PM PDT 24
Peak memory 2510896 kb
Host smart-d6352746-499d-477e-b9ca-e2850d02b15f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402092016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3402092016
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1800158996
Short name T254
Test name
Test status
Simulation time 13656237098 ps
CPU time 1614.54 seconds
Started Apr 18 03:17:55 PM PDT 24
Finished Apr 18 03:44:50 PM PDT 24
Peak memory 3359572 kb
Host smart-7e176bd0-ed9e-470e-b297-a88d39a48094
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800158996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1800158996
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3104245184
Short name T700
Test name
Test status
Simulation time 1417781674 ps
CPU time 6.97 seconds
Started Apr 18 03:17:56 PM PDT 24
Finished Apr 18 03:18:04 PM PDT 24
Peak memory 220172 kb
Host smart-ebe546d4-6ec5-463c-98b6-c77c0b48043a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104245184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3104245184
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.785699535
Short name T745
Test name
Test status
Simulation time 2255231784 ps
CPU time 7.08 seconds
Started Apr 18 03:17:58 PM PDT 24
Finished Apr 18 03:18:06 PM PDT 24
Peak memory 204044 kb
Host smart-d45d1615-b0d7-4e33-9918-e9c34f6f205f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785699535 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_unexp_stop.785699535
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3955703045
Short name T748
Test name
Test status
Simulation time 27777837 ps
CPU time 0.61 seconds
Started Apr 18 03:18:17 PM PDT 24
Finished Apr 18 03:18:18 PM PDT 24
Peak memory 203500 kb
Host smart-3ff7d470-2c27-47fb-8cb8-7477d7378f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955703045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3955703045
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.4074009596
Short name T1211
Test name
Test status
Simulation time 326185736 ps
CPU time 1.5 seconds
Started Apr 18 03:18:12 PM PDT 24
Finished Apr 18 03:18:14 PM PDT 24
Peak memory 215780 kb
Host smart-43a40224-d0fa-43cd-a243-218d50e3e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074009596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.4074009596
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2260619448
Short name T1004
Test name
Test status
Simulation time 393414939 ps
CPU time 8.73 seconds
Started Apr 18 03:18:05 PM PDT 24
Finished Apr 18 03:18:14 PM PDT 24
Peak memory 288052 kb
Host smart-cca11095-d920-46fd-aa24-f8ad8dbc59fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260619448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.2260619448
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.208982436
Short name T747
Test name
Test status
Simulation time 6725480254 ps
CPU time 92.38 seconds
Started Apr 18 03:18:08 PM PDT 24
Finished Apr 18 03:19:40 PM PDT 24
Peak memory 409860 kb
Host smart-d24b51d0-043e-433c-b19a-8613575477ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208982436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.208982436
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3060610199
Short name T1084
Test name
Test status
Simulation time 11925152767 ps
CPU time 52.24 seconds
Started Apr 18 03:18:07 PM PDT 24
Finished Apr 18 03:19:00 PM PDT 24
Peak memory 591628 kb
Host smart-06fa42c6-8ada-4c15-b7b5-abfbc6a328ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060610199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3060610199
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1987138705
Short name T1270
Test name
Test status
Simulation time 1056146231 ps
CPU time 0.9 seconds
Started Apr 18 03:18:05 PM PDT 24
Finished Apr 18 03:18:06 PM PDT 24
Peak memory 203688 kb
Host smart-c7ba3696-eb40-4564-bb9e-67b2f2e4af4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987138705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1987138705
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.283870112
Short name T346
Test name
Test status
Simulation time 424842445 ps
CPU time 2.77 seconds
Started Apr 18 03:18:07 PM PDT 24
Finished Apr 18 03:18:10 PM PDT 24
Peak memory 203940 kb
Host smart-e913baed-ba0a-4a20-9df9-eddca742c8c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283870112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
283870112
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2552272600
Short name T680
Test name
Test status
Simulation time 16999033774 ps
CPU time 115.74 seconds
Started Apr 18 03:18:04 PM PDT 24
Finished Apr 18 03:20:00 PM PDT 24
Peak memory 1218600 kb
Host smart-7eef2197-ce9e-4077-b7e9-1adaed066b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552272600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2552272600
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.131144598
Short name T1226
Test name
Test status
Simulation time 610782456 ps
CPU time 23.45 seconds
Started Apr 18 03:18:16 PM PDT 24
Finished Apr 18 03:18:39 PM PDT 24
Peak memory 203892 kb
Host smart-6926f266-51c3-438e-8cfc-8ad6b19ba65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131144598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.131144598
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2810588561
Short name T794
Test name
Test status
Simulation time 3129807577 ps
CPU time 27.14 seconds
Started Apr 18 03:18:18 PM PDT 24
Finished Apr 18 03:18:46 PM PDT 24
Peak memory 368056 kb
Host smart-10222195-f7c0-4133-a7fe-13a3a166e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810588561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2810588561
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3551850486
Short name T467
Test name
Test status
Simulation time 18230077 ps
CPU time 0.66 seconds
Started Apr 18 03:18:08 PM PDT 24
Finished Apr 18 03:18:09 PM PDT 24
Peak memory 203680 kb
Host smart-06f3cc30-92be-4b1f-b928-1e7a6cb4f2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551850486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3551850486
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3717010206
Short name T391
Test name
Test status
Simulation time 12322384589 ps
CPU time 266.18 seconds
Started Apr 18 03:18:05 PM PDT 24
Finished Apr 18 03:22:32 PM PDT 24
Peak memory 1752292 kb
Host smart-5257eda5-e2f1-4df9-a798-58b1e4221ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717010206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3717010206
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2473975780
Short name T1154
Test name
Test status
Simulation time 1579233351 ps
CPU time 68.64 seconds
Started Apr 18 03:18:01 PM PDT 24
Finished Apr 18 03:19:10 PM PDT 24
Peak memory 266640 kb
Host smart-a62916f7-2427-410a-85a2-f0aaff21ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473975780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2473975780
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.1588362447
Short name T121
Test name
Test status
Simulation time 9838499573 ps
CPU time 430.64 seconds
Started Apr 18 03:18:12 PM PDT 24
Finished Apr 18 03:25:23 PM PDT 24
Peak memory 2136328 kb
Host smart-7fdcfd82-a001-4bc0-ab49-856ffa804c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588362447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.1588362447
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2134106110
Short name T80
Test name
Test status
Simulation time 6004607910 ps
CPU time 10.1 seconds
Started Apr 18 03:18:12 PM PDT 24
Finished Apr 18 03:18:22 PM PDT 24
Peak memory 213676 kb
Host smart-bb867a25-6d38-4d52-8af8-4ac9cbdfe229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134106110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2134106110
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1917203987
Short name T693
Test name
Test status
Simulation time 684375041 ps
CPU time 3.24 seconds
Started Apr 18 03:18:17 PM PDT 24
Finished Apr 18 03:18:21 PM PDT 24
Peak memory 204028 kb
Host smart-69479ea9-7793-4f56-94be-7bbb5afecca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917203987 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1917203987
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.131973957
Short name T402
Test name
Test status
Simulation time 10069658109 ps
CPU time 65.87 seconds
Started Apr 18 03:18:11 PM PDT 24
Finished Apr 18 03:19:17 PM PDT 24
Peak memory 496512 kb
Host smart-539380c5-fafc-430e-9e43-050aea3b1e72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131973957 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.131973957
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2123569183
Short name T711
Test name
Test status
Simulation time 10241171639 ps
CPU time 13.98 seconds
Started Apr 18 03:18:15 PM PDT 24
Finished Apr 18 03:18:30 PM PDT 24
Peak memory 279400 kb
Host smart-24dc0a1a-6249-44e0-9bf5-163ad4921264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123569183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2123569183
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2224638185
Short name T15
Test name
Test status
Simulation time 3194381995 ps
CPU time 2.55 seconds
Started Apr 18 03:18:16 PM PDT 24
Finished Apr 18 03:18:19 PM PDT 24
Peak memory 204092 kb
Host smart-d83105b3-4e08-4055-9e06-3c5b73e08769
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224638185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2224638185
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1089070037
Short name T1148
Test name
Test status
Simulation time 5148113242 ps
CPU time 6.29 seconds
Started Apr 18 03:18:13 PM PDT 24
Finished Apr 18 03:18:20 PM PDT 24
Peak memory 220260 kb
Host smart-dc7bdf8c-a6f3-4383-8073-e1b7baa56a63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089070037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1089070037
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3714206150
Short name T20
Test name
Test status
Simulation time 15920976247 ps
CPU time 28.91 seconds
Started Apr 18 03:18:11 PM PDT 24
Finished Apr 18 03:18:40 PM PDT 24
Peak memory 602884 kb
Host smart-21375d45-3924-4824-bef8-2f5e4326db07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714206150 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3714206150
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3438080457
Short name T397
Test name
Test status
Simulation time 2559857592 ps
CPU time 21.38 seconds
Started Apr 18 03:18:11 PM PDT 24
Finished Apr 18 03:18:32 PM PDT 24
Peak memory 204108 kb
Host smart-93e68a74-0199-4914-8de8-db87f33886d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438080457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3438080457
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.4060687568
Short name T261
Test name
Test status
Simulation time 4287614458 ps
CPU time 80.72 seconds
Started Apr 18 03:18:12 PM PDT 24
Finished Apr 18 03:19:33 PM PDT 24
Peak memory 207944 kb
Host smart-ef6b707a-953f-4504-b3cd-917f65cd00f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060687568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.4060687568
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3170709456
Short name T1333
Test name
Test status
Simulation time 65056743388 ps
CPU time 222.24 seconds
Started Apr 18 03:18:11 PM PDT 24
Finished Apr 18 03:21:54 PM PDT 24
Peak memory 2544600 kb
Host smart-2df26d5d-df94-465f-b29a-c3871167f5dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170709456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3170709456
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3024846026
Short name T823
Test name
Test status
Simulation time 15977465781 ps
CPU time 165.57 seconds
Started Apr 18 03:18:11 PM PDT 24
Finished Apr 18 03:20:57 PM PDT 24
Peak memory 738884 kb
Host smart-7a930381-3a5c-41f4-9001-99ea2cded2d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024846026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3024846026
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1250520196
Short name T1108
Test name
Test status
Simulation time 8055086366 ps
CPU time 7 seconds
Started Apr 18 03:18:13 PM PDT 24
Finished Apr 18 03:18:20 PM PDT 24
Peak memory 220252 kb
Host smart-0cefcd8b-c0a7-40b3-845a-de336293133e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250520196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1250520196
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.159310730
Short name T1015
Test name
Test status
Simulation time 49640150 ps
CPU time 0.6 seconds
Started Apr 18 03:18:31 PM PDT 24
Finished Apr 18 03:18:32 PM PDT 24
Peak memory 203564 kb
Host smart-793b067a-bc4b-4757-a4c0-a54af4886f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159310730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.159310730
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1852619279
Short name T571
Test name
Test status
Simulation time 191770136 ps
CPU time 1.38 seconds
Started Apr 18 03:18:20 PM PDT 24
Finished Apr 18 03:18:22 PM PDT 24
Peak memory 212296 kb
Host smart-4866a55d-5703-4630-aac1-cdb1720c9a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852619279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1852619279
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.626003311
Short name T453
Test name
Test status
Simulation time 338403266 ps
CPU time 17.04 seconds
Started Apr 18 03:18:24 PM PDT 24
Finished Apr 18 03:18:41 PM PDT 24
Peak memory 271872 kb
Host smart-3365ec1c-4eda-4cb3-96a6-1e78a455886f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626003311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.626003311
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.219689180
Short name T92
Test name
Test status
Simulation time 3469132972 ps
CPU time 39.6 seconds
Started Apr 18 03:18:22 PM PDT 24
Finished Apr 18 03:19:02 PM PDT 24
Peak memory 488280 kb
Host smart-2f98f86c-999e-4a6a-9477-a879bdeb671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219689180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.219689180
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.933954217
Short name T1320
Test name
Test status
Simulation time 267539064 ps
CPU time 0.75 seconds
Started Apr 18 03:18:25 PM PDT 24
Finished Apr 18 03:18:26 PM PDT 24
Peak memory 203632 kb
Host smart-524da1fb-967b-4e40-bc33-801968e77ca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933954217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.933954217
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1548444623
Short name T1092
Test name
Test status
Simulation time 269544400 ps
CPU time 7 seconds
Started Apr 18 03:18:21 PM PDT 24
Finished Apr 18 03:18:28 PM PDT 24
Peak memory 203828 kb
Host smart-5d3f9317-a99d-44c8-8a27-ca15a9819738
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548444623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1548444623
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.4079353678
Short name T856
Test name
Test status
Simulation time 17726303132 ps
CPU time 105.66 seconds
Started Apr 18 03:18:16 PM PDT 24
Finished Apr 18 03:20:02 PM PDT 24
Peak memory 1238272 kb
Host smart-c7079848-e37f-4422-9f85-cbbce04b7567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079353678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.4079353678
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.1663085784
Short name T1170
Test name
Test status
Simulation time 357743909 ps
CPU time 13.54 seconds
Started Apr 18 03:18:31 PM PDT 24
Finished Apr 18 03:18:46 PM PDT 24
Peak memory 203980 kb
Host smart-0b282694-6997-4f04-b995-82e410ca2f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663085784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1663085784
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3563493641
Short name T679
Test name
Test status
Simulation time 848831823 ps
CPU time 35.09 seconds
Started Apr 18 03:18:32 PM PDT 24
Finished Apr 18 03:19:08 PM PDT 24
Peak memory 253760 kb
Host smart-283379ae-6e4a-4143-973e-cbadfcdec24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563493641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3563493641
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1952178769
Short name T279
Test name
Test status
Simulation time 24458181 ps
CPU time 0.65 seconds
Started Apr 18 03:18:17 PM PDT 24
Finished Apr 18 03:18:18 PM PDT 24
Peak memory 203672 kb
Host smart-7bd5588e-d1e5-42f7-a3c5-ba2898bb83cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952178769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1952178769
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.778534615
Short name T428
Test name
Test status
Simulation time 5437757678 ps
CPU time 64.06 seconds
Started Apr 18 03:18:17 PM PDT 24
Finished Apr 18 03:19:21 PM PDT 24
Peak memory 344528 kb
Host smart-30a23b6b-3476-4470-9a5e-970323d775d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778534615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.778534615
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3154232774
Short name T179
Test name
Test status
Simulation time 15076861635 ps
CPU time 91.29 seconds
Started Apr 18 03:18:20 PM PDT 24
Finished Apr 18 03:19:52 PM PDT 24
Peak memory 499124 kb
Host smart-87ea299e-ce80-4c39-bb9c-d9572fd3b921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154232774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3154232774
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2255833985
Short name T1330
Test name
Test status
Simulation time 2023348600 ps
CPU time 24.19 seconds
Started Apr 18 03:18:23 PM PDT 24
Finished Apr 18 03:18:48 PM PDT 24
Peak memory 212196 kb
Host smart-88e63c0b-96bd-456d-bb1f-a3e7760f43f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255833985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2255833985
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3035529198
Short name T493
Test name
Test status
Simulation time 950368393 ps
CPU time 3.91 seconds
Started Apr 18 03:18:27 PM PDT 24
Finished Apr 18 03:18:31 PM PDT 24
Peak memory 204012 kb
Host smart-807388bc-33c9-4222-83f1-8f45c2a89eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035529198 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3035529198
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1593178101
Short name T1173
Test name
Test status
Simulation time 10111793731 ps
CPU time 27.46 seconds
Started Apr 18 03:18:29 PM PDT 24
Finished Apr 18 03:18:56 PM PDT 24
Peak memory 372040 kb
Host smart-71b4ee00-7516-45db-8bd9-e82556ab0d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593178101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1593178101
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.539405158
Short name T37
Test name
Test status
Simulation time 10099050707 ps
CPU time 39.28 seconds
Started Apr 18 03:18:27 PM PDT 24
Finished Apr 18 03:19:07 PM PDT 24
Peak memory 435812 kb
Host smart-2e662601-53e2-4ed9-9d71-58e01aa34fc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539405158 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.539405158
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3783506726
Short name T776
Test name
Test status
Simulation time 1513602786 ps
CPU time 2.49 seconds
Started Apr 18 03:18:32 PM PDT 24
Finished Apr 18 03:18:35 PM PDT 24
Peak memory 204072 kb
Host smart-755ec90f-e31d-4afb-9933-2cca50a71d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783506726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3783506726
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.485113564
Short name T761
Test name
Test status
Simulation time 7250531042 ps
CPU time 8.19 seconds
Started Apr 18 03:18:29 PM PDT 24
Finished Apr 18 03:18:37 PM PDT 24
Peak memory 214848 kb
Host smart-d712b2d4-945e-4efb-be86-8f808b413bcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485113564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.485113564
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.780719306
Short name T1052
Test name
Test status
Simulation time 4412016482 ps
CPU time 8.85 seconds
Started Apr 18 03:18:26 PM PDT 24
Finished Apr 18 03:18:36 PM PDT 24
Peak memory 204056 kb
Host smart-7e53afa3-f55f-4c6b-844a-248293cdae3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780719306 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.780719306
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3538905387
Short name T1294
Test name
Test status
Simulation time 1426509198 ps
CPU time 18.66 seconds
Started Apr 18 03:18:29 PM PDT 24
Finished Apr 18 03:18:48 PM PDT 24
Peak memory 203972 kb
Host smart-fe508c37-d62d-4296-9547-6aa84d0692c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538905387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3538905387
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2917311236
Short name T677
Test name
Test status
Simulation time 290450411 ps
CPU time 5.37 seconds
Started Apr 18 03:18:26 PM PDT 24
Finished Apr 18 03:18:32 PM PDT 24
Peak memory 204020 kb
Host smart-53ea2e8a-38de-4029-ab58-f9a8946eded4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917311236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2917311236
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.149254696
Short name T753
Test name
Test status
Simulation time 62659884128 ps
CPU time 671.91 seconds
Started Apr 18 03:18:26 PM PDT 24
Finished Apr 18 03:29:38 PM PDT 24
Peak memory 5395288 kb
Host smart-f641a6cb-8c4a-45c8-95a5-c2cea0cd9b87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149254696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.149254696
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.359849709
Short name T338
Test name
Test status
Simulation time 9340150691 ps
CPU time 32.61 seconds
Started Apr 18 03:18:27 PM PDT 24
Finished Apr 18 03:19:00 PM PDT 24
Peak memory 538336 kb
Host smart-37df9f22-1496-40d3-997d-6f42164bc762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359849709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.359849709
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1065588684
Short name T458
Test name
Test status
Simulation time 1248927792 ps
CPU time 6.71 seconds
Started Apr 18 03:18:28 PM PDT 24
Finished Apr 18 03:18:35 PM PDT 24
Peak memory 214640 kb
Host smart-f6ae6fce-ac8c-40c8-9b77-ec245ee4b337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065588684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1065588684
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1178111971
Short name T116
Test name
Test status
Simulation time 40133723 ps
CPU time 0.58 seconds
Started Apr 18 03:18:51 PM PDT 24
Finished Apr 18 03:18:52 PM PDT 24
Peak memory 203584 kb
Host smart-fac8b255-60b1-468a-9774-0524f28c1334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178111971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1178111971
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.3723460372
Short name T861
Test name
Test status
Simulation time 287572510 ps
CPU time 1.38 seconds
Started Apr 18 03:18:36 PM PDT 24
Finished Apr 18 03:18:38 PM PDT 24
Peak memory 212296 kb
Host smart-5e0dc2be-8878-4633-b9d1-9cb4103ff3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723460372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3723460372
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2788823100
Short name T438
Test name
Test status
Simulation time 1001273085 ps
CPU time 14.27 seconds
Started Apr 18 03:18:39 PM PDT 24
Finished Apr 18 03:18:54 PM PDT 24
Peak memory 262716 kb
Host smart-06fd2e46-2390-4bab-bcdf-82c0934102de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788823100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2788823100
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3747956063
Short name T79
Test name
Test status
Simulation time 1772515023 ps
CPU time 46.32 seconds
Started Apr 18 03:18:37 PM PDT 24
Finished Apr 18 03:19:24 PM PDT 24
Peak memory 522956 kb
Host smart-21ab93ad-5ccf-40f1-a2e7-de2bd53a9523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747956063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3747956063
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.119864701
Short name T734
Test name
Test status
Simulation time 4919400142 ps
CPU time 34.74 seconds
Started Apr 18 03:18:35 PM PDT 24
Finished Apr 18 03:19:10 PM PDT 24
Peak memory 440188 kb
Host smart-3de11943-a0ef-4615-aba2-5cbde2edeab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119864701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.119864701
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.1130879217
Short name T1060
Test name
Test status
Simulation time 603220780 ps
CPU time 1.09 seconds
Started Apr 18 03:18:35 PM PDT 24
Finished Apr 18 03:18:37 PM PDT 24
Peak memory 203920 kb
Host smart-5c6e76d6-e20d-425b-b8d7-86fa61ad35e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130879217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.1130879217
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3839423874
Short name T1026
Test name
Test status
Simulation time 642762620 ps
CPU time 4.25 seconds
Started Apr 18 03:18:31 PM PDT 24
Finished Apr 18 03:18:36 PM PDT 24
Peak memory 232288 kb
Host smart-852021e4-62ed-4fee-b7c9-13c538343dab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839423874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3839423874
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1151931716
Short name T174
Test name
Test status
Simulation time 3161031800 ps
CPU time 65.62 seconds
Started Apr 18 03:18:32 PM PDT 24
Finished Apr 18 03:19:39 PM PDT 24
Peak memory 930028 kb
Host smart-9daa9085-a648-4404-b073-f397d117944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151931716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1151931716
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2487216282
Short name T66
Test name
Test status
Simulation time 1698592655 ps
CPU time 18.38 seconds
Started Apr 18 03:18:47 PM PDT 24
Finished Apr 18 03:19:06 PM PDT 24
Peak memory 203888 kb
Host smart-686e4d48-3b38-45b8-9b53-0e01e23e323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487216282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2487216282
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3530635135
Short name T1018
Test name
Test status
Simulation time 2548041519 ps
CPU time 55.65 seconds
Started Apr 18 03:18:46 PM PDT 24
Finished Apr 18 03:19:43 PM PDT 24
Peak memory 252856 kb
Host smart-a1a33089-1329-48e4-8862-3e09a847295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530635135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3530635135
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3400798762
Short name T431
Test name
Test status
Simulation time 75310278 ps
CPU time 0.71 seconds
Started Apr 18 03:18:33 PM PDT 24
Finished Apr 18 03:18:34 PM PDT 24
Peak memory 203620 kb
Host smart-f511b5b6-70b6-4567-97ce-96b5e869b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400798762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3400798762
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1225741186
Short name T71
Test name
Test status
Simulation time 25061661633 ps
CPU time 1952.24 seconds
Started Apr 18 03:18:40 PM PDT 24
Finished Apr 18 03:51:13 PM PDT 24
Peak memory 4014640 kb
Host smart-7ea01d34-02df-44b2-84cf-2bc19d96d317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225741186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1225741186
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.4063087142
Short name T603
Test name
Test status
Simulation time 11489700259 ps
CPU time 24.91 seconds
Started Apr 18 03:18:33 PM PDT 24
Finished Apr 18 03:18:59 PM PDT 24
Peak memory 317676 kb
Host smart-083fa58b-fb0b-4288-9178-73c7b8bb0fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063087142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.4063087142
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1302492433
Short name T616
Test name
Test status
Simulation time 1521791868 ps
CPU time 16.96 seconds
Started Apr 18 03:18:37 PM PDT 24
Finished Apr 18 03:18:55 PM PDT 24
Peak memory 212260 kb
Host smart-1646d49f-fb4b-4ece-a7ca-2e11e61ca112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302492433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1302492433
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1004545148
Short name T360
Test name
Test status
Simulation time 4378771894 ps
CPU time 4.77 seconds
Started Apr 18 03:18:46 PM PDT 24
Finished Apr 18 03:18:51 PM PDT 24
Peak memory 212268 kb
Host smart-679d97cb-fd65-46fe-91cc-0ed74181f150
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004545148 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1004545148
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.801004506
Short name T503
Test name
Test status
Simulation time 10125619787 ps
CPU time 12.42 seconds
Started Apr 18 03:18:42 PM PDT 24
Finished Apr 18 03:18:55 PM PDT 24
Peak memory 284848 kb
Host smart-6032e5f9-64b0-4469-a439-6bde35d83170
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801004506 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.801004506
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1388042853
Short name T32
Test name
Test status
Simulation time 10282726576 ps
CPU time 13.49 seconds
Started Apr 18 03:18:42 PM PDT 24
Finished Apr 18 03:18:56 PM PDT 24
Peak memory 291308 kb
Host smart-afa2c86e-a353-4ab7-9015-31759d83de08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388042853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1388042853
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1455848993
Short name T1262
Test name
Test status
Simulation time 286114304 ps
CPU time 1.83 seconds
Started Apr 18 03:18:46 PM PDT 24
Finished Apr 18 03:18:48 PM PDT 24
Peak memory 203984 kb
Host smart-af2b8ed5-91d6-4723-bb4c-29f24574f0e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455848993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1455848993
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3724513848
Short name T95
Test name
Test status
Simulation time 7159221037 ps
CPU time 5.47 seconds
Started Apr 18 03:18:37 PM PDT 24
Finished Apr 18 03:18:43 PM PDT 24
Peak memory 210812 kb
Host smart-372eb1af-f335-4dae-bed0-212a46482271
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724513848 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3724513848
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2958497857
Short name T1251
Test name
Test status
Simulation time 25666670041 ps
CPU time 95.5 seconds
Started Apr 18 03:18:40 PM PDT 24
Finished Apr 18 03:20:17 PM PDT 24
Peak memory 1158912 kb
Host smart-395ef97a-4246-4755-9edb-6f6100d3028f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958497857 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2958497857
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1332496666
Short name T1231
Test name
Test status
Simulation time 2528074554 ps
CPU time 50.1 seconds
Started Apr 18 03:18:38 PM PDT 24
Finished Apr 18 03:19:29 PM PDT 24
Peak memory 204080 kb
Host smart-435d0a9f-cfa8-45ad-8e3a-cb0c50652d06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332496666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1332496666
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3419713137
Short name T1260
Test name
Test status
Simulation time 886558697 ps
CPU time 28.06 seconds
Started Apr 18 03:18:37 PM PDT 24
Finished Apr 18 03:19:06 PM PDT 24
Peak memory 203988 kb
Host smart-a3807809-ff75-48db-93b4-a962be9eef90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419713137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3419713137
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3035193559
Short name T339
Test name
Test status
Simulation time 29395519013 ps
CPU time 147.06 seconds
Started Apr 18 03:18:36 PM PDT 24
Finished Apr 18 03:21:03 PM PDT 24
Peak memory 2056768 kb
Host smart-d3a4a522-2187-45d8-b129-a0f8644e0c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035193559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3035193559
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1063131266
Short name T582
Test name
Test status
Simulation time 3988105800 ps
CPU time 37.86 seconds
Started Apr 18 03:18:35 PM PDT 24
Finished Apr 18 03:19:14 PM PDT 24
Peak memory 643272 kb
Host smart-5f9f5821-aa6f-4738-94ab-5b8fa2a15485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063131266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1063131266
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1105728258
Short name T1147
Test name
Test status
Simulation time 1429562203 ps
CPU time 6.86 seconds
Started Apr 18 03:18:41 PM PDT 24
Finished Apr 18 03:18:48 PM PDT 24
Peak memory 220164 kb
Host smart-de7d3cb5-d7c8-435b-81bf-52231c530c24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105728258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1105728258
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3401481501
Short name T1056
Test name
Test status
Simulation time 77099408 ps
CPU time 0.62 seconds
Started Apr 18 03:19:08 PM PDT 24
Finished Apr 18 03:19:09 PM PDT 24
Peak memory 203564 kb
Host smart-0b46db3b-90f7-4047-ac51-8ec529914a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401481501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3401481501
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1444019065
Short name T942
Test name
Test status
Simulation time 188144963 ps
CPU time 1.49 seconds
Started Apr 18 03:18:57 PM PDT 24
Finished Apr 18 03:18:59 PM PDT 24
Peak memory 220380 kb
Host smart-fadef080-ce6b-4a48-96af-6c5391601097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444019065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1444019065
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1459778773
Short name T820
Test name
Test status
Simulation time 460694595 ps
CPU time 7.62 seconds
Started Apr 18 03:18:53 PM PDT 24
Finished Apr 18 03:19:01 PM PDT 24
Peak memory 287740 kb
Host smart-28b081b4-39a7-4729-b15f-1292b6be297b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459778773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1459778773
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1354802468
Short name T707
Test name
Test status
Simulation time 4487370528 ps
CPU time 35.84 seconds
Started Apr 18 03:18:55 PM PDT 24
Finished Apr 18 03:19:31 PM PDT 24
Peak memory 481980 kb
Host smart-6790dd35-9ea4-49e9-84e4-9da5f2377937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354802468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1354802468
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2513902576
Short name T485
Test name
Test status
Simulation time 1222488176 ps
CPU time 73.42 seconds
Started Apr 18 03:18:52 PM PDT 24
Finished Apr 18 03:20:06 PM PDT 24
Peak memory 491804 kb
Host smart-3f68aac7-1939-4c0b-aac5-e4997f79f5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513902576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2513902576
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3156537189
Short name T1220
Test name
Test status
Simulation time 407680267 ps
CPU time 1.09 seconds
Started Apr 18 03:18:55 PM PDT 24
Finished Apr 18 03:18:56 PM PDT 24
Peak memory 203952 kb
Host smart-7f4ffc54-f274-48ed-8f96-aaaf049580f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156537189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3156537189
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.321613717
Short name T662
Test name
Test status
Simulation time 395488141 ps
CPU time 5.53 seconds
Started Apr 18 03:18:53 PM PDT 24
Finished Apr 18 03:18:59 PM PDT 24
Peak memory 242496 kb
Host smart-d9e75bf4-6d50-4d17-b581-0ed375751613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321613717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
321613717
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.507322569
Short name T917
Test name
Test status
Simulation time 10255823575 ps
CPU time 159.52 seconds
Started Apr 18 03:18:51 PM PDT 24
Finished Apr 18 03:21:31 PM PDT 24
Peak memory 788100 kb
Host smart-61f1dba1-553b-4995-9853-0219b06d9eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507322569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.507322569
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1632663398
Short name T595
Test name
Test status
Simulation time 2383744018 ps
CPU time 23.92 seconds
Started Apr 18 03:19:06 PM PDT 24
Finished Apr 18 03:19:30 PM PDT 24
Peak memory 204004 kb
Host smart-fa358dd8-eec7-4f2d-826a-c88c1edeb36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632663398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1632663398
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1364511235
Short name T1339
Test name
Test status
Simulation time 6173407099 ps
CPU time 14.95 seconds
Started Apr 18 03:19:06 PM PDT 24
Finished Apr 18 03:19:22 PM PDT 24
Peak memory 282836 kb
Host smart-14d58c3d-7eab-431b-9936-109f027c1759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364511235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1364511235
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2381587884
Short name T364
Test name
Test status
Simulation time 128797023 ps
CPU time 0.66 seconds
Started Apr 18 03:18:53 PM PDT 24
Finished Apr 18 03:18:54 PM PDT 24
Peak memory 203688 kb
Host smart-0cce88f5-264c-46f9-ba18-c60a357f161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381587884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2381587884
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2910804316
Short name T892
Test name
Test status
Simulation time 51244756392 ps
CPU time 289.01 seconds
Started Apr 18 03:18:52 PM PDT 24
Finished Apr 18 03:23:41 PM PDT 24
Peak memory 1646296 kb
Host smart-76bca900-45da-4631-a24c-77298ba8abab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910804316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2910804316
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1635244264
Short name T1212
Test name
Test status
Simulation time 14577212347 ps
CPU time 29.78 seconds
Started Apr 18 03:18:55 PM PDT 24
Finished Apr 18 03:19:25 PM PDT 24
Peak memory 401504 kb
Host smart-98820182-a7f4-47af-9195-885d97e3a473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635244264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1635244264
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.3106682385
Short name T1338
Test name
Test status
Simulation time 3934376584 ps
CPU time 80.25 seconds
Started Apr 18 03:18:58 PM PDT 24
Finished Apr 18 03:20:18 PM PDT 24
Peak memory 567488 kb
Host smart-7d06a9d9-7a7f-46d9-83d2-ad7ebb9125af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106682385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.3106682385
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.3795496961
Short name T722
Test name
Test status
Simulation time 1009040618 ps
CPU time 22.13 seconds
Started Apr 18 03:18:55 PM PDT 24
Finished Apr 18 03:19:17 PM PDT 24
Peak memory 212228 kb
Host smart-413a4ad0-c239-444d-ab68-526c107f9fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795496961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3795496961
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3492086968
Short name T935
Test name
Test status
Simulation time 977080424 ps
CPU time 4.27 seconds
Started Apr 18 03:19:07 PM PDT 24
Finished Apr 18 03:19:12 PM PDT 24
Peak memory 212688 kb
Host smart-692b2aca-e222-4c2f-beff-a5431c81db41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492086968 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3492086968
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2865318405
Short name T1319
Test name
Test status
Simulation time 10041013084 ps
CPU time 61.6 seconds
Started Apr 18 03:19:03 PM PDT 24
Finished Apr 18 03:20:04 PM PDT 24
Peak memory 482732 kb
Host smart-7198fe07-caa8-40a4-b2b2-dcc833d4fd4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865318405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2865318405
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1295862192
Short name T787
Test name
Test status
Simulation time 10053782615 ps
CPU time 77.32 seconds
Started Apr 18 03:19:04 PM PDT 24
Finished Apr 18 03:20:21 PM PDT 24
Peak memory 615992 kb
Host smart-a48eb89a-eabb-4af2-8bcc-bb7ff0712922
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295862192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1295862192
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2556584490
Short name T25
Test name
Test status
Simulation time 4278177541 ps
CPU time 2.38 seconds
Started Apr 18 03:19:07 PM PDT 24
Finished Apr 18 03:19:10 PM PDT 24
Peak memory 203944 kb
Host smart-8ddfe78f-1306-4a1c-b7ff-33a17e56b4e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556584490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2556584490
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.994459408
Short name T1201
Test name
Test status
Simulation time 9951621265 ps
CPU time 2.8 seconds
Started Apr 18 03:18:57 PM PDT 24
Finished Apr 18 03:19:00 PM PDT 24
Peak memory 204084 kb
Host smart-ad62b1e2-b526-45ad-8851-d0ca16d841bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994459408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.994459408
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.2933098830
Short name T1234
Test name
Test status
Simulation time 5361252365 ps
CPU time 3.46 seconds
Started Apr 18 03:18:56 PM PDT 24
Finished Apr 18 03:19:01 PM PDT 24
Peak memory 203976 kb
Host smart-cb85ea81-4cbc-40d6-a32c-e6250d0ab67b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933098830 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.2933098830
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.114373893
Short name T1177
Test name
Test status
Simulation time 779392088 ps
CPU time 11.94 seconds
Started Apr 18 03:18:58 PM PDT 24
Finished Apr 18 03:19:10 PM PDT 24
Peak memory 203988 kb
Host smart-14f3d19d-2ef3-46ca-b15c-b5335f8759f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114373893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_tar
get_smoke.114373893
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2574645183
Short name T250
Test name
Test status
Simulation time 5505684434 ps
CPU time 13.28 seconds
Started Apr 18 03:18:57 PM PDT 24
Finished Apr 18 03:19:10 PM PDT 24
Peak memory 216792 kb
Host smart-f378edae-28e1-4f25-81d3-7503972633d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574645183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2574645183
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2845457182
Short name T259
Test name
Test status
Simulation time 13753024266 ps
CPU time 24.38 seconds
Started Apr 18 03:18:56 PM PDT 24
Finished Apr 18 03:19:21 PM PDT 24
Peak memory 204016 kb
Host smart-07ff28bc-3d71-4e77-88d7-7c642d4b0ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845457182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2845457182
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.680628298
Short name T486
Test name
Test status
Simulation time 25639533557 ps
CPU time 1048.45 seconds
Started Apr 18 03:18:58 PM PDT 24
Finished Apr 18 03:36:27 PM PDT 24
Peak memory 2414272 kb
Host smart-206d232d-534f-4466-b82d-4bfc176df3d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680628298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.680628298
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1531733974
Short name T1070
Test name
Test status
Simulation time 12547384822 ps
CPU time 6.53 seconds
Started Apr 18 03:19:03 PM PDT 24
Finished Apr 18 03:19:10 PM PDT 24
Peak memory 204080 kb
Host smart-5ae5c7f7-9ea1-44b8-a79b-870fa9bd7a81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531733974 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1531733974
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1179960830
Short name T771
Test name
Test status
Simulation time 29508530 ps
CPU time 0.6 seconds
Started Apr 18 03:19:26 PM PDT 24
Finished Apr 18 03:19:27 PM PDT 24
Peak memory 203568 kb
Host smart-2601e8d1-4014-46b3-adee-124ee14653c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179960830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1179960830
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1730128174
Short name T648
Test name
Test status
Simulation time 114622292 ps
CPU time 1.48 seconds
Started Apr 18 03:19:12 PM PDT 24
Finished Apr 18 03:19:14 PM PDT 24
Peak memory 212292 kb
Host smart-05fe26f8-9fde-49a1-8282-6f5b1d0cc1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730128174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1730128174
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.17582078
Short name T1179
Test name
Test status
Simulation time 1586657495 ps
CPU time 7.13 seconds
Started Apr 18 03:19:14 PM PDT 24
Finished Apr 18 03:19:22 PM PDT 24
Peak memory 287120 kb
Host smart-59382fa8-517e-4305-94d7-b2c0584a7bbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17582078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty
.17582078
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.4294770025
Short name T837
Test name
Test status
Simulation time 2230961464 ps
CPU time 63.24 seconds
Started Apr 18 03:19:14 PM PDT 24
Finished Apr 18 03:20:18 PM PDT 24
Peak memory 737208 kb
Host smart-255bf7ae-77ed-4889-9357-33f5f3b5adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294770025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.4294770025
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2144886995
Short name T275
Test name
Test status
Simulation time 1417133283 ps
CPU time 88.32 seconds
Started Apr 18 03:19:07 PM PDT 24
Finished Apr 18 03:20:36 PM PDT 24
Peak memory 463620 kb
Host smart-0220a883-7ad5-4042-8240-af746a3a7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144886995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2144886995
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1832360824
Short name T1121
Test name
Test status
Simulation time 127776841 ps
CPU time 1.01 seconds
Started Apr 18 03:19:10 PM PDT 24
Finished Apr 18 03:19:12 PM PDT 24
Peak memory 203868 kb
Host smart-5e5c0c00-69f7-4a5d-8b36-0fb5ba5aec19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832360824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1832360824
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.286214031
Short name T1022
Test name
Test status
Simulation time 736522432 ps
CPU time 4.4 seconds
Started Apr 18 03:19:11 PM PDT 24
Finished Apr 18 03:19:16 PM PDT 24
Peak memory 235560 kb
Host smart-19233c20-e96d-4b8a-a612-0d783bcefb5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286214031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
286214031
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.4140071593
Short name T633
Test name
Test status
Simulation time 13338839811 ps
CPU time 192.5 seconds
Started Apr 18 03:19:07 PM PDT 24
Finished Apr 18 03:22:20 PM PDT 24
Peak memory 872092 kb
Host smart-756afb67-6586-4f23-8254-fbe5ed07c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140071593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.4140071593
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.746571347
Short name T1329
Test name
Test status
Simulation time 5551887906 ps
CPU time 60.36 seconds
Started Apr 18 03:19:22 PM PDT 24
Finished Apr 18 03:20:23 PM PDT 24
Peak memory 295208 kb
Host smart-9711ac1b-24c0-4f5a-b0e8-294af540032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746571347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.746571347
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3767566115
Short name T903
Test name
Test status
Simulation time 94999879 ps
CPU time 0.67 seconds
Started Apr 18 03:19:10 PM PDT 24
Finished Apr 18 03:19:11 PM PDT 24
Peak memory 203672 kb
Host smart-eb3c9b6e-c61c-4bca-9bce-5f83c428ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767566115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3767566115
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3703099853
Short name T838
Test name
Test status
Simulation time 12930358432 ps
CPU time 803.29 seconds
Started Apr 18 03:19:12 PM PDT 24
Finished Apr 18 03:32:36 PM PDT 24
Peak memory 2989176 kb
Host smart-ff341b7f-cb30-45af-89cd-87eba955d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703099853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3703099853
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.676334372
Short name T965
Test name
Test status
Simulation time 983215070 ps
CPU time 18 seconds
Started Apr 18 03:19:06 PM PDT 24
Finished Apr 18 03:19:25 PM PDT 24
Peak memory 284876 kb
Host smart-67f959a1-d0d4-46aa-945c-4df6540d3aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676334372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.676334372
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.3190528862
Short name T178
Test name
Test status
Simulation time 10160138609 ps
CPU time 156.52 seconds
Started Apr 18 03:19:14 PM PDT 24
Finished Apr 18 03:21:51 PM PDT 24
Peak memory 792380 kb
Host smart-b53f1747-0b4c-469e-82fb-04f6cb6bcf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190528862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3190528862
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.4210269545
Short name T1243
Test name
Test status
Simulation time 810803075 ps
CPU time 12.17 seconds
Started Apr 18 03:19:15 PM PDT 24
Finished Apr 18 03:19:28 PM PDT 24
Peak memory 228424 kb
Host smart-a8d7fdec-9a9e-4ed0-8bf2-8005b6412f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210269545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.4210269545
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.719597354
Short name T225
Test name
Test status
Simulation time 3293884390 ps
CPU time 3.51 seconds
Started Apr 18 03:19:22 PM PDT 24
Finished Apr 18 03:19:26 PM PDT 24
Peak memory 212176 kb
Host smart-5e0c1d96-bd6a-4045-ae8c-98a4b9ce0ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719597354 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.719597354
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.589938295
Short name T789
Test name
Test status
Simulation time 10095546494 ps
CPU time 69.43 seconds
Started Apr 18 03:19:18 PM PDT 24
Finished Apr 18 03:20:27 PM PDT 24
Peak memory 495756 kb
Host smart-6054a808-cd4b-4be7-89a8-36a40288b249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589938295 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.589938295
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.4209802385
Short name T870
Test name
Test status
Simulation time 10270588469 ps
CPU time 13.69 seconds
Started Apr 18 03:19:26 PM PDT 24
Finished Apr 18 03:19:40 PM PDT 24
Peak memory 292340 kb
Host smart-0217e465-a147-41f6-9421-db7763b93dd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209802385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.4209802385
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2081592989
Short name T260
Test name
Test status
Simulation time 1400558845 ps
CPU time 2.12 seconds
Started Apr 18 03:19:22 PM PDT 24
Finished Apr 18 03:19:24 PM PDT 24
Peak memory 203924 kb
Host smart-89d0ccc4-294c-4c7d-8911-890a082ce597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081592989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2081592989
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1338386091
Short name T488
Test name
Test status
Simulation time 831456684 ps
CPU time 4 seconds
Started Apr 18 03:19:14 PM PDT 24
Finished Apr 18 03:19:18 PM PDT 24
Peak memory 204040 kb
Host smart-ddc946e1-94f6-48ee-a4f2-9f97bcb670c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338386091 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1338386091
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3578002229
Short name T875
Test name
Test status
Simulation time 16165144661 ps
CPU time 26.19 seconds
Started Apr 18 03:19:20 PM PDT 24
Finished Apr 18 03:19:46 PM PDT 24
Peak memory 546524 kb
Host smart-7943515c-8339-46b5-9037-768bf02f9973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578002229 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3578002229
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1353048857
Short name T1233
Test name
Test status
Simulation time 1316371122 ps
CPU time 19.99 seconds
Started Apr 18 03:19:17 PM PDT 24
Finished Apr 18 03:19:37 PM PDT 24
Peak memory 204008 kb
Host smart-2aee5a28-b82e-4d73-b9f9-3b99ddc11753
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353048857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1353048857
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3930315668
Short name T1236
Test name
Test status
Simulation time 6370352673 ps
CPU time 23.17 seconds
Started Apr 18 03:19:14 PM PDT 24
Finished Apr 18 03:19:38 PM PDT 24
Peak memory 233568 kb
Host smart-18ae388a-31ec-49dc-a75e-11705169f7aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930315668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3930315668
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2775424666
Short name T1223
Test name
Test status
Simulation time 57275672376 ps
CPU time 525.98 seconds
Started Apr 18 03:19:15 PM PDT 24
Finished Apr 18 03:28:01 PM PDT 24
Peak memory 4650064 kb
Host smart-757df803-6ea4-42f8-80ed-0e1fba179fc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775424666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2775424666
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.4101143715
Short name T583
Test name
Test status
Simulation time 11668819473 ps
CPU time 378.96 seconds
Started Apr 18 03:19:15 PM PDT 24
Finished Apr 18 03:25:34 PM PDT 24
Peak memory 2801532 kb
Host smart-923bb764-0df4-458c-b07e-1c4f4898ffbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101143715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.4101143715
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1527130388
Short name T349
Test name
Test status
Simulation time 1406637213 ps
CPU time 6.74 seconds
Started Apr 18 03:19:20 PM PDT 24
Finished Apr 18 03:19:27 PM PDT 24
Peak memory 220196 kb
Host smart-2dc7930a-40d4-41cf-a3de-3b97ad479cad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527130388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1527130388
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.3807585639
Short name T656
Test name
Test status
Simulation time 1386001053 ps
CPU time 4.06 seconds
Started Apr 18 03:19:20 PM PDT 24
Finished Apr 18 03:19:24 PM PDT 24
Peak memory 203996 kb
Host smart-b750bd35-9d08-4f63-a656-44309c93f1d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807585639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.i2c_target_unexp_stop.3807585639
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2151774036
Short name T389
Test name
Test status
Simulation time 150637913 ps
CPU time 0.59 seconds
Started Apr 18 03:19:37 PM PDT 24
Finished Apr 18 03:19:38 PM PDT 24
Peak memory 203600 kb
Host smart-04c987aa-bf7f-4648-aac9-766186da21f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151774036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2151774036
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1426398541
Short name T1297
Test name
Test status
Simulation time 99863097 ps
CPU time 1.75 seconds
Started Apr 18 03:19:33 PM PDT 24
Finished Apr 18 03:19:35 PM PDT 24
Peak memory 215464 kb
Host smart-1afdcea4-08ef-4c7e-9776-e1d05492ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426398541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1426398541
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.822336453
Short name T797
Test name
Test status
Simulation time 262446317 ps
CPU time 12 seconds
Started Apr 18 03:19:28 PM PDT 24
Finished Apr 18 03:19:40 PM PDT 24
Peak memory 249212 kb
Host smart-d7ac357e-6252-47aa-9537-9ee45a921079
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822336453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.822336453
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.514693710
Short name T1181
Test name
Test status
Simulation time 2254173296 ps
CPU time 83.57 seconds
Started Apr 18 03:19:31 PM PDT 24
Finished Apr 18 03:20:55 PM PDT 24
Peak memory 737092 kb
Host smart-efc73af1-e220-4cc4-b4ec-a0b3bddbb51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514693710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.514693710
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2927829363
Short name T1149
Test name
Test status
Simulation time 1706632559 ps
CPU time 118.93 seconds
Started Apr 18 03:19:27 PM PDT 24
Finished Apr 18 03:21:26 PM PDT 24
Peak memory 599852 kb
Host smart-0885160c-61c7-4383-b4b1-7b95c491d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927829363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2927829363
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.359388313
Short name T68
Test name
Test status
Simulation time 422084196 ps
CPU time 1.09 seconds
Started Apr 18 03:19:30 PM PDT 24
Finished Apr 18 03:19:32 PM PDT 24
Peak memory 203944 kb
Host smart-feb45508-3507-4d44-94ad-6cae237ccf20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359388313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.359388313
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3921871134
Short name T558
Test name
Test status
Simulation time 238811429 ps
CPU time 3.23 seconds
Started Apr 18 03:19:30 PM PDT 24
Finished Apr 18 03:19:34 PM PDT 24
Peak memory 203860 kb
Host smart-8123173b-7b77-4d4f-9688-4dc300a48f6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921871134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3921871134
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.187025119
Short name T964
Test name
Test status
Simulation time 17783970063 ps
CPU time 142.62 seconds
Started Apr 18 03:19:30 PM PDT 24
Finished Apr 18 03:21:54 PM PDT 24
Peak memory 1309212 kb
Host smart-7416a976-1ecf-4bba-8a3b-0245c0b2839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187025119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.187025119
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3886308753
Short name T1029
Test name
Test status
Simulation time 3813865788 ps
CPU time 3.67 seconds
Started Apr 18 03:19:42 PM PDT 24
Finished Apr 18 03:19:46 PM PDT 24
Peak memory 203980 kb
Host smart-9dd85d5d-9d05-4e40-9384-d258389d449c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886308753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3886308753
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3913349202
Short name T447
Test name
Test status
Simulation time 1641018369 ps
CPU time 80.07 seconds
Started Apr 18 03:19:36 PM PDT 24
Finished Apr 18 03:20:56 PM PDT 24
Peak memory 345824 kb
Host smart-e6e0d35a-5582-4af9-9722-4e42c2819de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913349202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3913349202
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2896046209
Short name T1361
Test name
Test status
Simulation time 406106103 ps
CPU time 0.67 seconds
Started Apr 18 03:19:28 PM PDT 24
Finished Apr 18 03:19:29 PM PDT 24
Peak memory 203664 kb
Host smart-d52bbcbf-ea3c-4726-89b9-e1854f0fdb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896046209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2896046209
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.382523522
Short name T888
Test name
Test status
Simulation time 2842401865 ps
CPU time 24.65 seconds
Started Apr 18 03:19:25 PM PDT 24
Finished Apr 18 03:19:50 PM PDT 24
Peak memory 342004 kb
Host smart-89e3f355-2642-4b73-a144-0b9a828e6ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382523522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.382523522
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.1387702705
Short name T229
Test name
Test status
Simulation time 23540994721 ps
CPU time 761.03 seconds
Started Apr 18 03:19:32 PM PDT 24
Finished Apr 18 03:32:13 PM PDT 24
Peak memory 2592100 kb
Host smart-85b84e9a-df22-4ed8-afb2-31dd39e6f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387702705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.1387702705
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.3498141107
Short name T1025
Test name
Test status
Simulation time 303139832 ps
CPU time 13.32 seconds
Started Apr 18 03:19:32 PM PDT 24
Finished Apr 18 03:19:46 PM PDT 24
Peak memory 212248 kb
Host smart-e4ee2d2d-ada9-404b-a3f2-9d3e29d88a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498141107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.3498141107
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2244102351
Short name T307
Test name
Test status
Simulation time 4409670776 ps
CPU time 3.45 seconds
Started Apr 18 03:19:39 PM PDT 24
Finished Apr 18 03:19:43 PM PDT 24
Peak memory 204040 kb
Host smart-d37faa18-4b8e-4cbf-a29e-68eed0549907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244102351 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2244102351
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1333096411
Short name T274
Test name
Test status
Simulation time 10093544495 ps
CPU time 31.98 seconds
Started Apr 18 03:19:35 PM PDT 24
Finished Apr 18 03:20:07 PM PDT 24
Peak memory 347596 kb
Host smart-6bb7cca2-2be6-4f1b-a1ee-fa0f476651c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333096411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1333096411
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3436815610
Short name T1115
Test name
Test status
Simulation time 10536617343 ps
CPU time 4.57 seconds
Started Apr 18 03:19:33 PM PDT 24
Finished Apr 18 03:19:38 PM PDT 24
Peak memory 243300 kb
Host smart-923824ad-400d-4edd-b4c8-adbc0051c0e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436815610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3436815610
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1312430154
Short name T1274
Test name
Test status
Simulation time 1970641329 ps
CPU time 1.58 seconds
Started Apr 18 03:19:38 PM PDT 24
Finished Apr 18 03:19:40 PM PDT 24
Peak memory 204008 kb
Host smart-d5e5a809-51c6-4306-ac94-f72af7c0eab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312430154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1312430154
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1223530175
Short name T1
Test name
Test status
Simulation time 4479177920 ps
CPU time 4.23 seconds
Started Apr 18 03:19:33 PM PDT 24
Finished Apr 18 03:19:37 PM PDT 24
Peak memory 204040 kb
Host smart-77966a82-980b-41e4-8054-667d0e1e800f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223530175 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1223530175
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2600854467
Short name T871
Test name
Test status
Simulation time 9437346889 ps
CPU time 29.8 seconds
Started Apr 18 03:19:32 PM PDT 24
Finished Apr 18 03:20:02 PM PDT 24
Peak memory 631628 kb
Host smart-9c6ad6cd-e23b-4f1a-8cc9-f462935c7f26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600854467 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2600854467
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1794779589
Short name T1010
Test name
Test status
Simulation time 3913438770 ps
CPU time 13.33 seconds
Started Apr 18 03:19:38 PM PDT 24
Finished Apr 18 03:19:52 PM PDT 24
Peak memory 204188 kb
Host smart-88225898-45a1-41dc-8242-9a8ea6120259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794779589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1794779589
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.4141393524
Short name T319
Test name
Test status
Simulation time 3344075794 ps
CPU time 73.72 seconds
Started Apr 18 03:19:38 PM PDT 24
Finished Apr 18 03:20:52 PM PDT 24
Peak memory 210024 kb
Host smart-4ac15f49-16db-4878-a29a-0342bc48e4b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141393524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.4141393524
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.82321310
Short name T891
Test name
Test status
Simulation time 10456464186 ps
CPU time 5.73 seconds
Started Apr 18 03:19:32 PM PDT 24
Finished Apr 18 03:19:38 PM PDT 24
Peak memory 204016 kb
Host smart-c551eb0f-1ef3-44c7-8b9d-844cde5fef2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82321310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stress_wr.82321310
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2474913901
Short name T621
Test name
Test status
Simulation time 7008609165 ps
CPU time 31.06 seconds
Started Apr 18 03:19:33 PM PDT 24
Finished Apr 18 03:20:04 PM PDT 24
Peak memory 515604 kb
Host smart-b0cea7a1-4525-4e08-b9fd-2a6ca3e36c80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474913901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2474913901
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.1762390312
Short name T735
Test name
Test status
Simulation time 3192656302 ps
CPU time 7.47 seconds
Started Apr 18 03:19:38 PM PDT 24
Finished Apr 18 03:19:46 PM PDT 24
Peak memory 220220 kb
Host smart-52ed9b62-5e56-4ff1-87f9-e53ae2145dae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762390312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.1762390312
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1970633509
Short name T617
Test name
Test status
Simulation time 17517911 ps
CPU time 0.62 seconds
Started Apr 18 03:20:03 PM PDT 24
Finished Apr 18 03:20:04 PM PDT 24
Peak memory 203560 kb
Host smart-8fe8fd9e-6a5e-468d-bd5a-6fb0be76c62f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970633509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1970633509
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.4011821368
Short name T333
Test name
Test status
Simulation time 69293168 ps
CPU time 1.42 seconds
Started Apr 18 03:19:42 PM PDT 24
Finished Apr 18 03:19:44 PM PDT 24
Peak memory 204060 kb
Host smart-77760a27-136e-4e34-a422-e1532f998d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011821368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.4011821368
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3269052673
Short name T10
Test name
Test status
Simulation time 301288534 ps
CPU time 5.27 seconds
Started Apr 18 03:19:48 PM PDT 24
Finished Apr 18 03:19:54 PM PDT 24
Peak memory 252396 kb
Host smart-c5a62d1a-9e57-4135-8de6-75d87b52c20c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269052673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3269052673
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.809564421
Short name T120
Test name
Test status
Simulation time 1338609234 ps
CPU time 78.91 seconds
Started Apr 18 03:19:42 PM PDT 24
Finished Apr 18 03:21:02 PM PDT 24
Peak memory 462340 kb
Host smart-6a310759-7a54-4dd4-b0bf-0cb23703c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809564421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.809564421
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2405973408
Short name T1265
Test name
Test status
Simulation time 2631169613 ps
CPU time 32.74 seconds
Started Apr 18 03:19:42 PM PDT 24
Finished Apr 18 03:20:16 PM PDT 24
Peak memory 516076 kb
Host smart-2403808a-e6ba-4b04-9434-b1eec2f02752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405973408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2405973408
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2424026201
Short name T88
Test name
Test status
Simulation time 467924970 ps
CPU time 0.98 seconds
Started Apr 18 03:19:43 PM PDT 24
Finished Apr 18 03:19:44 PM PDT 24
Peak memory 203676 kb
Host smart-b8bd58ef-71d2-4ff1-9c30-bdb5fff795ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424026201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2424026201
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.732626456
Short name T41
Test name
Test status
Simulation time 444279758 ps
CPU time 2.96 seconds
Started Apr 18 03:19:45 PM PDT 24
Finished Apr 18 03:19:49 PM PDT 24
Peak memory 221116 kb
Host smart-82de2715-1c1e-4af5-ba78-343714e4de33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732626456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
732626456
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2952773933
Short name T757
Test name
Test status
Simulation time 4508661055 ps
CPU time 314.42 seconds
Started Apr 18 03:19:42 PM PDT 24
Finished Apr 18 03:24:57 PM PDT 24
Peak memory 1179832 kb
Host smart-48be8fc5-7df6-4c9f-9a93-9041829ec885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952773933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2952773933
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2700155340
Short name T213
Test name
Test status
Simulation time 652562509 ps
CPU time 9.95 seconds
Started Apr 18 03:19:59 PM PDT 24
Finished Apr 18 03:20:09 PM PDT 24
Peak memory 203924 kb
Host smart-03c259e0-31ad-4ff8-ad24-02be62e24141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700155340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2700155340
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2322884622
Short name T535
Test name
Test status
Simulation time 5043441896 ps
CPU time 62.5 seconds
Started Apr 18 03:20:04 PM PDT 24
Finished Apr 18 03:21:06 PM PDT 24
Peak memory 359216 kb
Host smart-d5eb51c1-5e7b-42c5-b7ca-42c067dc12e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322884622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2322884622
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.119979714
Short name T183
Test name
Test status
Simulation time 29265544 ps
CPU time 0.65 seconds
Started Apr 18 03:19:47 PM PDT 24
Finished Apr 18 03:19:48 PM PDT 24
Peak memory 203844 kb
Host smart-b7e3f5b1-32e1-4a15-9e9a-d0b3f04fe403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119979714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.119979714
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3960188886
Short name T249
Test name
Test status
Simulation time 652236689 ps
CPU time 14.48 seconds
Started Apr 18 03:19:43 PM PDT 24
Finished Apr 18 03:19:58 PM PDT 24
Peak memory 236672 kb
Host smart-a8edb5c1-0363-4d5b-8832-a044dc86c8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960188886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3960188886
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.15415443
Short name T585
Test name
Test status
Simulation time 2881011124 ps
CPU time 24.95 seconds
Started Apr 18 03:19:36 PM PDT 24
Finished Apr 18 03:20:01 PM PDT 24
Peak memory 304140 kb
Host smart-c1267d73-d4eb-4016-949e-b47e22aadeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15415443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.15415443
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3696827974
Short name T172
Test name
Test status
Simulation time 16878101292 ps
CPU time 306.72 seconds
Started Apr 18 03:19:43 PM PDT 24
Finished Apr 18 03:24:50 PM PDT 24
Peak memory 1501488 kb
Host smart-a3ab804f-0edd-4f35-992f-fa07dd4147f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696827974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3696827974
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1947781661
Short name T1284
Test name
Test status
Simulation time 1810983729 ps
CPU time 19.97 seconds
Started Apr 18 03:19:43 PM PDT 24
Finished Apr 18 03:20:04 PM PDT 24
Peak memory 212200 kb
Host smart-405a958b-09f6-4122-9d3f-0541222332a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947781661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1947781661
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3863465545
Short name T296
Test name
Test status
Simulation time 2301872988 ps
CPU time 2.82 seconds
Started Apr 18 03:19:53 PM PDT 24
Finished Apr 18 03:19:56 PM PDT 24
Peak memory 204072 kb
Host smart-66d32d55-038d-415d-920e-0ea7187c8d1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863465545 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3863465545
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.517174320
Short name T54
Test name
Test status
Simulation time 10055863840 ps
CPU time 60.21 seconds
Started Apr 18 03:19:49 PM PDT 24
Finished Apr 18 03:20:50 PM PDT 24
Peak memory 485136 kb
Host smart-66af37a4-f6a1-468b-9222-b47db5f826ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517174320 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.517174320
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2966486730
Short name T58
Test name
Test status
Simulation time 10076012735 ps
CPU time 73.46 seconds
Started Apr 18 03:19:49 PM PDT 24
Finished Apr 18 03:21:03 PM PDT 24
Peak memory 582008 kb
Host smart-bb9b20da-718e-460e-851a-889bec674734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966486730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2966486730
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1161669995
Short name T909
Test name
Test status
Simulation time 488076578 ps
CPU time 2.59 seconds
Started Apr 18 03:19:52 PM PDT 24
Finished Apr 18 03:19:55 PM PDT 24
Peak memory 204008 kb
Host smart-a0775ded-09a5-44df-81f4-858d6e5f4e7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161669995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1161669995
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2803610452
Short name T434
Test name
Test status
Simulation time 621216206 ps
CPU time 3.06 seconds
Started Apr 18 03:19:48 PM PDT 24
Finished Apr 18 03:19:52 PM PDT 24
Peak memory 203960 kb
Host smart-997ab931-44ab-423e-a843-7978a9e039a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803610452 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2803610452
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.3805986118
Short name T702
Test name
Test status
Simulation time 18050526243 ps
CPU time 94.91 seconds
Started Apr 18 03:19:48 PM PDT 24
Finished Apr 18 03:21:23 PM PDT 24
Peak memory 1326556 kb
Host smart-5f0b851c-f06b-44f8-82da-1a517fefcb49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805986118 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3805986118
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.895316417
Short name T457
Test name
Test status
Simulation time 1490721065 ps
CPU time 11.54 seconds
Started Apr 18 03:19:43 PM PDT 24
Finished Apr 18 03:19:55 PM PDT 24
Peak memory 204004 kb
Host smart-3b972311-bbf7-47a8-8de2-430cb31aa2da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895316417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.895316417
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1047713836
Short name T827
Test name
Test status
Simulation time 3555756737 ps
CPU time 15.05 seconds
Started Apr 18 03:19:50 PM PDT 24
Finished Apr 18 03:20:05 PM PDT 24
Peak memory 209192 kb
Host smart-494edb93-536a-43dd-82b5-07482347f698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047713836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1047713836
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.164601844
Short name T252
Test name
Test status
Simulation time 8713017583 ps
CPU time 5.51 seconds
Started Apr 18 03:19:42 PM PDT 24
Finished Apr 18 03:19:48 PM PDT 24
Peak memory 204060 kb
Host smart-cac1f658-3f0a-43bd-b934-3cac89d2e517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164601844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.164601844
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1277456485
Short name T320
Test name
Test status
Simulation time 4432930766 ps
CPU time 107.89 seconds
Started Apr 18 03:19:48 PM PDT 24
Finished Apr 18 03:21:36 PM PDT 24
Peak memory 1194896 kb
Host smart-41496e61-734a-4709-9ba3-95322e92404c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277456485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1277456485
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1641472166
Short name T1276
Test name
Test status
Simulation time 1338733834 ps
CPU time 6.4 seconds
Started Apr 18 03:19:49 PM PDT 24
Finished Apr 18 03:19:56 PM PDT 24
Peak memory 220196 kb
Host smart-68d6dc56-19ac-4e2c-b91e-e1d350b8013d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641472166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1641472166
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.866335599
Short name T1217
Test name
Test status
Simulation time 19262400 ps
CPU time 0.61 seconds
Started Apr 18 03:20:09 PM PDT 24
Finished Apr 18 03:20:10 PM PDT 24
Peak memory 203560 kb
Host smart-849dbdcd-febd-4f20-a8ea-e5b139b0b8ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866335599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.866335599
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.170717923
Short name T864
Test name
Test status
Simulation time 142518063 ps
CPU time 1.24 seconds
Started Apr 18 03:19:59 PM PDT 24
Finished Apr 18 03:20:01 PM PDT 24
Peak memory 212236 kb
Host smart-48484850-e55c-45d2-96ba-c43398d864e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170717923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.170717923
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1274247942
Short name T879
Test name
Test status
Simulation time 653159215 ps
CPU time 8.16 seconds
Started Apr 18 03:19:59 PM PDT 24
Finished Apr 18 03:20:07 PM PDT 24
Peak memory 234496 kb
Host smart-102e2e76-dc67-4627-a874-c63055fa21f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274247942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1274247942
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.4044684032
Short name T141
Test name
Test status
Simulation time 9778554166 ps
CPU time 74.14 seconds
Started Apr 18 03:20:05 PM PDT 24
Finished Apr 18 03:21:20 PM PDT 24
Peak memory 788300 kb
Host smart-2859617f-59cb-4f6a-b0fb-aaca5dc313c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044684032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.4044684032
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.700410032
Short name T1000
Test name
Test status
Simulation time 2268158038 ps
CPU time 160.92 seconds
Started Apr 18 03:19:56 PM PDT 24
Finished Apr 18 03:22:37 PM PDT 24
Peak memory 697696 kb
Host smart-ce4fef84-049b-43de-8259-f10c8368e2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700410032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.700410032
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1483414331
Short name T1050
Test name
Test status
Simulation time 458676763 ps
CPU time 1.13 seconds
Started Apr 18 03:20:00 PM PDT 24
Finished Apr 18 03:20:01 PM PDT 24
Peak memory 203948 kb
Host smart-276fa73e-59cd-4209-9306-2f04a2bc07fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483414331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1483414331
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3779462551
Short name T398
Test name
Test status
Simulation time 225106457 ps
CPU time 2.68 seconds
Started Apr 18 03:19:59 PM PDT 24
Finished Apr 18 03:20:02 PM PDT 24
Peak memory 203932 kb
Host smart-b17b40f5-77d8-42fa-9201-413161aa9080
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779462551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3779462551
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2160753419
Short name T86
Test name
Test status
Simulation time 12808641485 ps
CPU time 165.74 seconds
Started Apr 18 03:19:58 PM PDT 24
Finished Apr 18 03:22:44 PM PDT 24
Peak memory 813832 kb
Host smart-0bdcf097-2cbc-451f-af55-ee845cd3997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160753419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2160753419
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2778684170
Short name T446
Test name
Test status
Simulation time 2050714628 ps
CPU time 5.62 seconds
Started Apr 18 03:20:08 PM PDT 24
Finished Apr 18 03:20:14 PM PDT 24
Peak memory 203980 kb
Host smart-2084f3aa-4b30-459d-abc9-8520491d64ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778684170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2778684170
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2771427853
Short name T984
Test name
Test status
Simulation time 13356403572 ps
CPU time 26.28 seconds
Started Apr 18 03:20:07 PM PDT 24
Finished Apr 18 03:20:34 PM PDT 24
Peak memory 349624 kb
Host smart-70161eb5-28f4-4418-8239-08f387d80136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771427853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2771427853
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2688605434
Short name T1362
Test name
Test status
Simulation time 27070748 ps
CPU time 0.72 seconds
Started Apr 18 03:20:00 PM PDT 24
Finished Apr 18 03:20:01 PM PDT 24
Peak memory 203676 kb
Host smart-11557f83-d849-465f-b854-25f712611a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688605434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2688605434
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2305238913
Short name T1007
Test name
Test status
Simulation time 13236663092 ps
CPU time 1358.31 seconds
Started Apr 18 03:19:59 PM PDT 24
Finished Apr 18 03:42:38 PM PDT 24
Peak memory 1930036 kb
Host smart-827ceea4-2fc0-440d-bdda-099ab595b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305238913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2305238913
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2380577515
Short name T1094
Test name
Test status
Simulation time 17639163338 ps
CPU time 27.54 seconds
Started Apr 18 03:19:56 PM PDT 24
Finished Apr 18 03:20:24 PM PDT 24
Peak memory 346152 kb
Host smart-1a1922b7-7ee2-4dbc-8083-6395e24f4ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380577515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2380577515
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1674048689
Short name T56
Test name
Test status
Simulation time 39144819069 ps
CPU time 1632.96 seconds
Started Apr 18 03:20:00 PM PDT 24
Finished Apr 18 03:47:14 PM PDT 24
Peak memory 1167248 kb
Host smart-365502be-1c5f-45c7-a37e-821b62c181e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674048689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1674048689
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2374118029
Short name T233
Test name
Test status
Simulation time 1240950359 ps
CPU time 11.58 seconds
Started Apr 18 03:19:59 PM PDT 24
Finished Apr 18 03:20:11 PM PDT 24
Peak memory 216136 kb
Host smart-036ba2f7-563c-4755-a4cc-4b8afa13eefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374118029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2374118029
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2698248187
Short name T455
Test name
Test status
Simulation time 1192791858 ps
CPU time 3.27 seconds
Started Apr 18 03:20:04 PM PDT 24
Finished Apr 18 03:20:07 PM PDT 24
Peak memory 203976 kb
Host smart-41453d70-8e0d-4fdc-aced-247179ea36b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698248187 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2698248187
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3399229920
Short name T81
Test name
Test status
Simulation time 10101132036 ps
CPU time 69.81 seconds
Started Apr 18 03:20:06 PM PDT 24
Finished Apr 18 03:21:16 PM PDT 24
Peak memory 506288 kb
Host smart-4c662217-02e1-47d6-8775-73938404acc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399229920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3399229920
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.815133437
Short name T1184
Test name
Test status
Simulation time 10087999285 ps
CPU time 29.48 seconds
Started Apr 18 03:20:04 PM PDT 24
Finished Apr 18 03:20:34 PM PDT 24
Peak memory 410768 kb
Host smart-b0b446f3-e037-42f1-a9ae-ccd5b7eb205d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815133437 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_tx.815133437
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3448042921
Short name T1066
Test name
Test status
Simulation time 305837384 ps
CPU time 1.98 seconds
Started Apr 18 03:20:04 PM PDT 24
Finished Apr 18 03:20:07 PM PDT 24
Peak memory 203980 kb
Host smart-8c2990f5-6a00-4151-852e-dda4e7a0671c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448042921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3448042921
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.969832277
Short name T1363
Test name
Test status
Simulation time 1412268260 ps
CPU time 5.85 seconds
Started Apr 18 03:20:05 PM PDT 24
Finished Apr 18 03:20:11 PM PDT 24
Peak memory 212212 kb
Host smart-d49bb2cd-6b5a-4145-ac6f-39e7bd1ba6c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969832277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.969832277
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.203351647
Short name T1014
Test name
Test status
Simulation time 3577948601 ps
CPU time 2.75 seconds
Started Apr 18 03:20:03 PM PDT 24
Finished Apr 18 03:20:06 PM PDT 24
Peak memory 203944 kb
Host smart-fba339a2-e080-4723-88bf-2dd1c271818a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203351647 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.203351647
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.3253636874
Short name T884
Test name
Test status
Simulation time 3256635322 ps
CPU time 31.86 seconds
Started Apr 18 03:19:58 PM PDT 24
Finished Apr 18 03:20:30 PM PDT 24
Peak memory 204016 kb
Host smart-c4c13071-6b3b-44f9-ad49-a3d042dc4dfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253636874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.3253636874
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1392184024
Short name T242
Test name
Test status
Simulation time 3467375816 ps
CPU time 66.95 seconds
Started Apr 18 03:20:07 PM PDT 24
Finished Apr 18 03:21:14 PM PDT 24
Peak memory 208484 kb
Host smart-04beedb7-caf4-4ea9-939b-c7182fcb62f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392184024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1392184024
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2959281456
Short name T1317
Test name
Test status
Simulation time 20465866324 ps
CPU time 44.94 seconds
Started Apr 18 03:20:03 PM PDT 24
Finished Apr 18 03:20:49 PM PDT 24
Peak memory 344420 kb
Host smart-87bcb7b0-6f09-42b5-ab83-9c88dc7a7850
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959281456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2959281456
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.4174481624
Short name T548
Test name
Test status
Simulation time 39887263567 ps
CPU time 874.06 seconds
Started Apr 18 03:20:04 PM PDT 24
Finished Apr 18 03:34:38 PM PDT 24
Peak memory 2258936 kb
Host smart-f119146a-2469-4bf9-9c05-f1a6213899af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174481624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.4174481624
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3831253064
Short name T815
Test name
Test status
Simulation time 9796270189 ps
CPU time 6.19 seconds
Started Apr 18 03:20:09 PM PDT 24
Finished Apr 18 03:20:15 PM PDT 24
Peak memory 219732 kb
Host smart-07b068ae-4a43-4300-af42-3d14c96c15d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831253064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3831253064
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1329888333
Short name T1285
Test name
Test status
Simulation time 18614405 ps
CPU time 0.6 seconds
Started Apr 18 03:20:23 PM PDT 24
Finished Apr 18 03:20:24 PM PDT 24
Peak memory 203556 kb
Host smart-913b55f5-581c-4621-95af-22ad612d3883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329888333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1329888333
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3325664829
Short name T1307
Test name
Test status
Simulation time 850805982 ps
CPU time 1.31 seconds
Started Apr 18 03:20:14 PM PDT 24
Finished Apr 18 03:20:15 PM PDT 24
Peak memory 212292 kb
Host smart-403d9e86-9187-40c1-82a1-c255e3ba85a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325664829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3325664829
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.696344458
Short name T851
Test name
Test status
Simulation time 898451194 ps
CPU time 4.33 seconds
Started Apr 18 03:20:19 PM PDT 24
Finished Apr 18 03:20:24 PM PDT 24
Peak memory 247360 kb
Host smart-c83f51fd-826a-4067-939c-25c6627f12e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696344458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.696344458
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.451170329
Short name T456
Test name
Test status
Simulation time 2541612570 ps
CPU time 84.17 seconds
Started Apr 18 03:20:12 PM PDT 24
Finished Apr 18 03:21:37 PM PDT 24
Peak memory 527416 kb
Host smart-4ff1e800-4eb1-42be-a008-44cabe09a20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451170329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.451170329
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3947237678
Short name T704
Test name
Test status
Simulation time 19856122975 ps
CPU time 150.51 seconds
Started Apr 18 03:20:08 PM PDT 24
Finished Apr 18 03:22:39 PM PDT 24
Peak memory 697392 kb
Host smart-f4c0dc7c-84dd-42ef-a44c-bf9c9dbbecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947237678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3947237678
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1961358610
Short name T739
Test name
Test status
Simulation time 169594574 ps
CPU time 1.16 seconds
Started Apr 18 03:20:14 PM PDT 24
Finished Apr 18 03:20:16 PM PDT 24
Peak memory 203904 kb
Host smart-961a796c-31dd-454f-a271-d7b27147b057
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961358610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1961358610
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2138278810
Short name T1133
Test name
Test status
Simulation time 131539139 ps
CPU time 3.31 seconds
Started Apr 18 03:20:13 PM PDT 24
Finished Apr 18 03:20:17 PM PDT 24
Peak memory 203920 kb
Host smart-dadd4221-ebd0-4db8-9bac-3e1caa20a61f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138278810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2138278810
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.366929432
Short name T593
Test name
Test status
Simulation time 2939479456 ps
CPU time 185.56 seconds
Started Apr 18 03:20:08 PM PDT 24
Finished Apr 18 03:23:14 PM PDT 24
Peak memory 902672 kb
Host smart-c1bd7adb-5972-4eb7-b028-2ce92cd14030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366929432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.366929432
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.2184080361
Short name T1077
Test name
Test status
Simulation time 407534390 ps
CPU time 15.75 seconds
Started Apr 18 03:20:20 PM PDT 24
Finished Apr 18 03:20:36 PM PDT 24
Peak memory 203916 kb
Host smart-e64fbc5b-ccf5-44d7-84b9-cde55c115305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184080361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.2184080361
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.4099263087
Short name T575
Test name
Test status
Simulation time 9855127669 ps
CPU time 93.52 seconds
Started Apr 18 03:20:22 PM PDT 24
Finished Apr 18 03:21:56 PM PDT 24
Peak memory 370648 kb
Host smart-4de33a5c-f1fe-4473-9949-2d97d5450637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099263087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.4099263087
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.567337826
Short name T326
Test name
Test status
Simulation time 47397792 ps
CPU time 0.61 seconds
Started Apr 18 03:20:09 PM PDT 24
Finished Apr 18 03:20:10 PM PDT 24
Peak memory 203644 kb
Host smart-2ddbd258-b426-4fa9-afc3-f96cb7bd7181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567337826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.567337826
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.860412075
Short name T922
Test name
Test status
Simulation time 3002435312 ps
CPU time 27.24 seconds
Started Apr 18 03:20:14 PM PDT 24
Finished Apr 18 03:20:42 PM PDT 24
Peak memory 460268 kb
Host smart-2df65ff1-a651-43cf-9ebb-6175f47a26b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860412075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.860412075
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4033287038
Short name T830
Test name
Test status
Simulation time 1526427352 ps
CPU time 32.69 seconds
Started Apr 18 03:20:07 PM PDT 24
Finished Apr 18 03:20:41 PM PDT 24
Peak memory 361036 kb
Host smart-73fd3a62-4a39-4105-b4a4-75c37b8084d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033287038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4033287038
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.323138698
Short name T1151
Test name
Test status
Simulation time 3439013019 ps
CPU time 41.05 seconds
Started Apr 18 03:20:18 PM PDT 24
Finished Apr 18 03:21:00 PM PDT 24
Peak memory 212420 kb
Host smart-ea27ec8d-bb44-4bf7-8f03-fa99303d96c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323138698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.323138698
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.186291036
Short name T1283
Test name
Test status
Simulation time 840464254 ps
CPU time 3.52 seconds
Started Apr 18 03:20:19 PM PDT 24
Finished Apr 18 03:20:23 PM PDT 24
Peak memory 212180 kb
Host smart-99ae7041-1926-4e33-b576-05eb7f959c23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186291036 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.186291036
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3310461995
Short name T433
Test name
Test status
Simulation time 10295999970 ps
CPU time 26.87 seconds
Started Apr 18 03:20:18 PM PDT 24
Finished Apr 18 03:20:45 PM PDT 24
Peak memory 387376 kb
Host smart-00ec4996-9fe5-423c-9ef7-3809f29b744b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310461995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3310461995
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1755808584
Short name T224
Test name
Test status
Simulation time 520250764 ps
CPU time 1.88 seconds
Started Apr 18 03:20:20 PM PDT 24
Finished Apr 18 03:20:22 PM PDT 24
Peak memory 203964 kb
Host smart-02060641-9a25-4544-88ee-5e9826f866f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755808584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1755808584
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.428540855
Short name T501
Test name
Test status
Simulation time 1588380195 ps
CPU time 3.61 seconds
Started Apr 18 03:20:19 PM PDT 24
Finished Apr 18 03:20:23 PM PDT 24
Peak memory 204192 kb
Host smart-66b51771-f174-4f8f-81ad-77fd7d881695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428540855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.428540855
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.4006357543
Short name T520
Test name
Test status
Simulation time 3314904396 ps
CPU time 6.98 seconds
Started Apr 18 03:20:16 PM PDT 24
Finished Apr 18 03:20:23 PM PDT 24
Peak memory 203976 kb
Host smart-488e07c3-51bd-440b-bc5c-f7d955ef5018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006357543 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.4006357543
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.802365309
Short name T7
Test name
Test status
Simulation time 895201945 ps
CPU time 11.66 seconds
Started Apr 18 03:20:13 PM PDT 24
Finished Apr 18 03:20:26 PM PDT 24
Peak memory 203972 kb
Host smart-2c03db49-8b33-4395-b267-28468ab6f2f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802365309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.802365309
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.4017616897
Short name T828
Test name
Test status
Simulation time 4111219082 ps
CPU time 41.44 seconds
Started Apr 18 03:20:14 PM PDT 24
Finished Apr 18 03:20:55 PM PDT 24
Peak memory 204072 kb
Host smart-aebf210a-7601-4125-9ad3-93971cda071b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017616897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.4017616897
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1048101635
Short name T327
Test name
Test status
Simulation time 65976645766 ps
CPU time 2089.38 seconds
Started Apr 18 03:20:15 PM PDT 24
Finished Apr 18 03:55:05 PM PDT 24
Peak memory 11197280 kb
Host smart-b92e38e3-7f6e-48be-b1e3-9b37b1d79000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048101635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1048101635
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.938201334
Short name T425
Test name
Test status
Simulation time 15267295358 ps
CPU time 1876.97 seconds
Started Apr 18 03:20:14 PM PDT 24
Finished Apr 18 03:51:32 PM PDT 24
Peak memory 2949704 kb
Host smart-70b53500-d2fe-4a5d-9e80-36b4d79feb01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938201334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.938201334
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3985001136
Short name T777
Test name
Test status
Simulation time 5918225857 ps
CPU time 6.83 seconds
Started Apr 18 03:20:13 PM PDT 24
Finished Apr 18 03:20:20 PM PDT 24
Peak memory 217168 kb
Host smart-8113be39-c392-4953-ab1e-e57e9c9eb855
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985001136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3985001136
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.1507509699
Short name T16
Test name
Test status
Simulation time 2536080226 ps
CPU time 3.83 seconds
Started Apr 18 03:20:18 PM PDT 24
Finished Apr 18 03:20:22 PM PDT 24
Peak memory 204856 kb
Host smart-9cb456b2-f9e1-45d5-a2ef-142c2744ab97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507509699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.1507509699
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2646282464
Short name T1326
Test name
Test status
Simulation time 47476401 ps
CPU time 0.63 seconds
Started Apr 18 03:06:52 PM PDT 24
Finished Apr 18 03:06:53 PM PDT 24
Peak memory 203564 kb
Host smart-41d8c00d-864f-4ff9-9f47-c9be151f19f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646282464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2646282464
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3365682274
Short name T971
Test name
Test status
Simulation time 68041798 ps
CPU time 1.13 seconds
Started Apr 18 03:06:33 PM PDT 24
Finished Apr 18 03:06:34 PM PDT 24
Peak memory 212320 kb
Host smart-d5c9dab0-86cc-4db0-b142-5c91ddf6528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365682274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3365682274
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.754748634
Short name T773
Test name
Test status
Simulation time 372432377 ps
CPU time 6.74 seconds
Started Apr 18 03:06:28 PM PDT 24
Finished Apr 18 03:06:35 PM PDT 24
Peak memory 280848 kb
Host smart-06f687f9-70b3-4726-bb66-25cde9b8c46b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754748634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.754748634
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.679540781
Short name T50
Test name
Test status
Simulation time 11144061523 ps
CPU time 106.33 seconds
Started Apr 18 03:06:29 PM PDT 24
Finished Apr 18 03:08:16 PM PDT 24
Peak memory 413768 kb
Host smart-49018666-e444-4fe1-a5fe-8e0601f41b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679540781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.679540781
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3158574093
Short name T822
Test name
Test status
Simulation time 4976013418 ps
CPU time 37.46 seconds
Started Apr 18 03:06:26 PM PDT 24
Finished Apr 18 03:07:03 PM PDT 24
Peak memory 502420 kb
Host smart-977e5d02-720a-4079-87cc-b9728d2f952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158574093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3158574093
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3027980259
Short name T1289
Test name
Test status
Simulation time 319652162 ps
CPU time 0.82 seconds
Started Apr 18 03:06:28 PM PDT 24
Finished Apr 18 03:06:29 PM PDT 24
Peak memory 203720 kb
Host smart-a47f768d-4b85-4607-84c8-85b14cb1d3ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027980259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3027980259
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.389626982
Short name T479
Test name
Test status
Simulation time 312340829 ps
CPU time 3.36 seconds
Started Apr 18 03:06:27 PM PDT 24
Finished Apr 18 03:06:31 PM PDT 24
Peak memory 203948 kb
Host smart-f5a82d9c-e024-4b2d-a676-9c839d617e11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389626982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.389626982
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1991814170
Short name T579
Test name
Test status
Simulation time 10198557120 ps
CPU time 59.97 seconds
Started Apr 18 03:06:27 PM PDT 24
Finished Apr 18 03:07:27 PM PDT 24
Peak memory 715072 kb
Host smart-0bc846be-6d64-46ae-a9c4-4ce8845067cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991814170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1991814170
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2664011239
Short name T266
Test name
Test status
Simulation time 284299180 ps
CPU time 3.45 seconds
Started Apr 18 03:06:54 PM PDT 24
Finished Apr 18 03:06:58 PM PDT 24
Peak memory 204012 kb
Host smart-783b74ff-4139-415f-a5df-480a25a156bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664011239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2664011239
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1751950021
Short name T1364
Test name
Test status
Simulation time 5163838649 ps
CPU time 21 seconds
Started Apr 18 03:06:55 PM PDT 24
Finished Apr 18 03:07:16 PM PDT 24
Peak memory 304600 kb
Host smart-7a09f83b-32c4-4bda-a2c0-83f79828bb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751950021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1751950021
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.4267596801
Short name T115
Test name
Test status
Simulation time 66744464 ps
CPU time 0.62 seconds
Started Apr 18 03:06:28 PM PDT 24
Finished Apr 18 03:06:29 PM PDT 24
Peak memory 203668 kb
Host smart-e98be8d9-9b3a-4365-88d4-321f737d5f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267596801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.4267596801
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.734450763
Short name T1200
Test name
Test status
Simulation time 6056102364 ps
CPU time 62.75 seconds
Started Apr 18 03:06:28 PM PDT 24
Finished Apr 18 03:07:31 PM PDT 24
Peak memory 293752 kb
Host smart-575a2a55-743c-42fb-ab65-08f8469a1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734450763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.734450763
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.293461671
Short name T597
Test name
Test status
Simulation time 3881735722 ps
CPU time 17.25 seconds
Started Apr 18 03:06:28 PM PDT 24
Finished Apr 18 03:06:46 PM PDT 24
Peak memory 252228 kb
Host smart-9957a9f5-06de-4738-b0a5-3e570be079cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293461671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.293461671
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.496378681
Short name T87
Test name
Test status
Simulation time 49416959034 ps
CPU time 760.3 seconds
Started Apr 18 03:06:34 PM PDT 24
Finished Apr 18 03:19:14 PM PDT 24
Peak memory 2288936 kb
Host smart-7fa01032-c502-49ca-806b-b0dfb55b4c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496378681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.496378681
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2014592955
Short name T986
Test name
Test status
Simulation time 1194502052 ps
CPU time 10.74 seconds
Started Apr 18 03:06:32 PM PDT 24
Finished Apr 18 03:06:43 PM PDT 24
Peak memory 215304 kb
Host smart-8f168e64-4bfd-4d17-a83e-23e38328a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014592955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2014592955
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1699579036
Short name T494
Test name
Test status
Simulation time 809406382 ps
CPU time 3.63 seconds
Started Apr 18 03:06:46 PM PDT 24
Finished Apr 18 03:06:50 PM PDT 24
Peak memory 204020 kb
Host smart-658ff6bb-5bb9-4169-8369-4f384b056f18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699579036 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1699579036
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2255813825
Short name T201
Test name
Test status
Simulation time 10131766096 ps
CPU time 20.6 seconds
Started Apr 18 03:06:46 PM PDT 24
Finished Apr 18 03:07:07 PM PDT 24
Peak memory 321740 kb
Host smart-86a01cad-05a8-412b-bb8a-4f8952ffe7e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255813825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2255813825
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3194564045
Short name T840
Test name
Test status
Simulation time 10074204740 ps
CPU time 73.91 seconds
Started Apr 18 03:06:45 PM PDT 24
Finished Apr 18 03:08:00 PM PDT 24
Peak memory 546620 kb
Host smart-d3a867fe-1fb3-4023-acab-2ff4f1ff65fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194564045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3194564045
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1529863978
Short name T26
Test name
Test status
Simulation time 774135756 ps
CPU time 2.14 seconds
Started Apr 18 03:06:46 PM PDT 24
Finished Apr 18 03:06:49 PM PDT 24
Peak memory 204028 kb
Host smart-91c492f3-7f63-4496-ba72-92597826eb4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529863978 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1529863978
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1203274807
Short name T1266
Test name
Test status
Simulation time 1253300664 ps
CPU time 5.8 seconds
Started Apr 18 03:06:40 PM PDT 24
Finished Apr 18 03:06:46 PM PDT 24
Peak memory 219080 kb
Host smart-cbabc8dc-addc-4688-9fd3-0236acc42740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203274807 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1203274807
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.418906356
Short name T334
Test name
Test status
Simulation time 23153961714 ps
CPU time 66.15 seconds
Started Apr 18 03:06:39 PM PDT 24
Finished Apr 18 03:07:46 PM PDT 24
Peak memory 985976 kb
Host smart-c5ebe5c0-fc12-4808-bcb1-fe94c1d39235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418906356 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.418906356
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3636398732
Short name T1275
Test name
Test status
Simulation time 1241277861 ps
CPU time 19.44 seconds
Started Apr 18 03:06:33 PM PDT 24
Finished Apr 18 03:06:53 PM PDT 24
Peak memory 203968 kb
Host smart-e7a0af06-b0cd-4682-9376-438dbb2079c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636398732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3636398732
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1623449920
Short name T933
Test name
Test status
Simulation time 1056427403 ps
CPU time 15.56 seconds
Started Apr 18 03:06:39 PM PDT 24
Finished Apr 18 03:06:55 PM PDT 24
Peak memory 224220 kb
Host smart-4f2575b6-eb22-40aa-9c91-a79c4aae501b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623449920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1623449920
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.199185848
Short name T845
Test name
Test status
Simulation time 46955575336 ps
CPU time 929.6 seconds
Started Apr 18 03:06:33 PM PDT 24
Finished Apr 18 03:22:03 PM PDT 24
Peak memory 6868908 kb
Host smart-c2262dae-10d1-485e-a635-f9b049bd68be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199185848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.199185848
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.752312351
Short name T605
Test name
Test status
Simulation time 38227743366 ps
CPU time 876.9 seconds
Started Apr 18 03:06:38 PM PDT 24
Finished Apr 18 03:21:16 PM PDT 24
Peak memory 2272232 kb
Host smart-edf6a0fd-790a-434d-8556-77591b63ee48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752312351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_ta
rget_stretch.752312351
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2930995157
Short name T683
Test name
Test status
Simulation time 9744669768 ps
CPU time 5.96 seconds
Started Apr 18 03:06:40 PM PDT 24
Finished Apr 18 03:06:46 PM PDT 24
Peak memory 203976 kb
Host smart-ed0d4dce-6ee7-4cdf-90b6-54d3f02691c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930995157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2930995157
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2739411173
Short name T974
Test name
Test status
Simulation time 20919328 ps
CPU time 0.61 seconds
Started Apr 18 03:07:25 PM PDT 24
Finished Apr 18 03:07:26 PM PDT 24
Peak memory 203564 kb
Host smart-9514b87e-a985-438e-bd5e-a2d25b45957b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739411173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2739411173
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.555757516
Short name T1054
Test name
Test status
Simulation time 115119202 ps
CPU time 1.62 seconds
Started Apr 18 03:07:05 PM PDT 24
Finished Apr 18 03:07:07 PM PDT 24
Peak memory 212232 kb
Host smart-178a0d51-cee4-4c40-b703-8a21a6deba94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555757516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.555757516
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.665835700
Short name T1166
Test name
Test status
Simulation time 317637068 ps
CPU time 14.61 seconds
Started Apr 18 03:06:57 PM PDT 24
Finished Apr 18 03:07:12 PM PDT 24
Peak memory 255680 kb
Host smart-ea8e6fc9-151a-4a45-8706-e2be03edb49f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665835700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.665835700
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1053268092
Short name T359
Test name
Test status
Simulation time 2151447512 ps
CPU time 53.26 seconds
Started Apr 18 03:07:02 PM PDT 24
Finished Apr 18 03:07:56 PM PDT 24
Peak memory 227312 kb
Host smart-f8b9d852-63ac-4ccf-94d1-6cf9f9eb4286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053268092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1053268092
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.201968857
Short name T423
Test name
Test status
Simulation time 2000792110 ps
CPU time 69.21 seconds
Started Apr 18 03:06:51 PM PDT 24
Finished Apr 18 03:08:01 PM PDT 24
Peak memory 701780 kb
Host smart-6f8f8049-57d8-481d-866f-ea4ce29b58c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201968857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.201968857
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.953937495
Short name T834
Test name
Test status
Simulation time 514190305 ps
CPU time 1.11 seconds
Started Apr 18 03:06:59 PM PDT 24
Finished Apr 18 03:07:01 PM PDT 24
Peak memory 203888 kb
Host smart-5abe9464-4faa-4766-aafa-fe3a8a0e6ca0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953937495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.953937495
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1614050073
Short name T1182
Test name
Test status
Simulation time 1091063088 ps
CPU time 2.82 seconds
Started Apr 18 03:06:58 PM PDT 24
Finished Apr 18 03:07:01 PM PDT 24
Peak memory 203864 kb
Host smart-492bc5a5-6e19-4ea5-8df0-f15953c3ffc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614050073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1614050073
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3661543258
Short name T288
Test name
Test status
Simulation time 4193832503 ps
CPU time 325.35 seconds
Started Apr 18 03:06:51 PM PDT 24
Finished Apr 18 03:12:17 PM PDT 24
Peak memory 1247260 kb
Host smart-983ee5f1-af72-4150-a0bb-5dc5e75bd5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661543258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3661543258
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.102331455
Short name T1079
Test name
Test status
Simulation time 892669456 ps
CPU time 3.02 seconds
Started Apr 18 03:07:25 PM PDT 24
Finished Apr 18 03:07:29 PM PDT 24
Peak memory 203968 kb
Host smart-ddfe8064-6113-4ed2-a8ed-510d25b75fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102331455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.102331455
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2218377388
Short name T1125
Test name
Test status
Simulation time 5006966025 ps
CPU time 83.93 seconds
Started Apr 18 03:07:27 PM PDT 24
Finished Apr 18 03:08:52 PM PDT 24
Peak memory 322660 kb
Host smart-f958f1db-b86a-4544-bb63-c7efc67c62db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218377388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2218377388
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3179158535
Short name T336
Test name
Test status
Simulation time 49962123 ps
CPU time 0.66 seconds
Started Apr 18 03:06:52 PM PDT 24
Finished Apr 18 03:06:53 PM PDT 24
Peak memory 203632 kb
Host smart-01ecc8a3-bf25-47b0-9d2a-017f7b518256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179158535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3179158535
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3206806969
Short name T435
Test name
Test status
Simulation time 12753733028 ps
CPU time 116.34 seconds
Started Apr 18 03:07:03 PM PDT 24
Finished Apr 18 03:09:00 PM PDT 24
Peak memory 673192 kb
Host smart-ff3f0252-2359-4ebc-928c-b5f7572281cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206806969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3206806969
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1145634603
Short name T1096
Test name
Test status
Simulation time 1137626646 ps
CPU time 17.35 seconds
Started Apr 18 03:06:53 PM PDT 24
Finished Apr 18 03:07:11 PM PDT 24
Peak memory 309504 kb
Host smart-ff1c11a2-bac8-47fb-ad5d-380744a4c816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145634603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1145634603
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1361290360
Short name T1279
Test name
Test status
Simulation time 5767531636 ps
CPU time 32.24 seconds
Started Apr 18 03:07:02 PM PDT 24
Finished Apr 18 03:07:34 PM PDT 24
Peak memory 212276 kb
Host smart-7f98d59f-be60-44b5-9fef-7e0555f4a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361290360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1361290360
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.2829611993
Short name T1043
Test name
Test status
Simulation time 1266105442 ps
CPU time 2.76 seconds
Started Apr 18 03:07:18 PM PDT 24
Finished Apr 18 03:07:21 PM PDT 24
Peak memory 204012 kb
Host smart-18363e20-b73d-4106-9ca6-94e2e9637ac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829611993 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2829611993
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.830874789
Short name T919
Test name
Test status
Simulation time 10078360754 ps
CPU time 65.31 seconds
Started Apr 18 03:07:09 PM PDT 24
Finished Apr 18 03:08:14 PM PDT 24
Peak memory 463036 kb
Host smart-910c781f-2f33-4c9a-b086-6638f580b50d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830874789 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.830874789
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2859932715
Short name T876
Test name
Test status
Simulation time 10026195474 ps
CPU time 70.68 seconds
Started Apr 18 03:07:10 PM PDT 24
Finished Apr 18 03:08:21 PM PDT 24
Peak memory 600520 kb
Host smart-05a06d7f-8ee7-4eb8-8004-6305190ad5b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859932715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2859932715
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3366389901
Short name T215
Test name
Test status
Simulation time 3916889640 ps
CPU time 2.02 seconds
Started Apr 18 03:07:18 PM PDT 24
Finished Apr 18 03:07:20 PM PDT 24
Peak memory 204100 kb
Host smart-85a38a9d-ead1-4ae0-99bc-7ef7f3089b5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366389901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3366389901
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1199445618
Short name T226
Test name
Test status
Simulation time 1301398711 ps
CPU time 3.52 seconds
Started Apr 18 03:07:09 PM PDT 24
Finished Apr 18 03:07:12 PM PDT 24
Peak memory 203976 kb
Host smart-5615c1e0-f286-4d73-b9f6-9fd4418cea77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199445618 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1199445618
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3874702365
Short name T21
Test name
Test status
Simulation time 10594019293 ps
CPU time 41.43 seconds
Started Apr 18 03:07:09 PM PDT 24
Finished Apr 18 03:07:51 PM PDT 24
Peak memory 869196 kb
Host smart-6995f682-eba7-4971-bec2-3af9c80b5e5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874702365 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3874702365
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1435400308
Short name T419
Test name
Test status
Simulation time 4891797279 ps
CPU time 47.03 seconds
Started Apr 18 03:07:14 PM PDT 24
Finished Apr 18 03:08:01 PM PDT 24
Peak memory 204060 kb
Host smart-b40113d2-29a5-4ad6-bc2c-14638dc9e97f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435400308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1435400308
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.705905151
Short name T295
Test name
Test status
Simulation time 884959514 ps
CPU time 15.22 seconds
Started Apr 18 03:07:13 PM PDT 24
Finished Apr 18 03:07:29 PM PDT 24
Peak memory 210996 kb
Host smart-613daee0-7e29-423d-aca0-c90c8dca9f0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705905151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_rd.705905151
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1638622906
Short name T800
Test name
Test status
Simulation time 26731102079 ps
CPU time 56.9 seconds
Started Apr 18 03:07:13 PM PDT 24
Finished Apr 18 03:08:10 PM PDT 24
Peak memory 1001540 kb
Host smart-926d3a06-f1e4-4708-a59d-f052f29c2994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638622906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1638622906
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2527837536
Short name T601
Test name
Test status
Simulation time 18541268123 ps
CPU time 117.82 seconds
Started Apr 18 03:07:09 PM PDT 24
Finished Apr 18 03:09:07 PM PDT 24
Peak memory 1128836 kb
Host smart-fa4918a4-f956-49b0-864f-292e04fe5d04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527837536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2527837536
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2501781449
Short name T502
Test name
Test status
Simulation time 1437924183 ps
CPU time 6.34 seconds
Started Apr 18 03:07:09 PM PDT 24
Finished Apr 18 03:07:15 PM PDT 24
Peak memory 220208 kb
Host smart-778fb318-d674-45b9-a54a-b76a1f1e5e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501781449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2501781449
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1741921132
Short name T1356
Test name
Test status
Simulation time 19159245 ps
CPU time 0.61 seconds
Started Apr 18 03:07:45 PM PDT 24
Finished Apr 18 03:07:46 PM PDT 24
Peak memory 203472 kb
Host smart-a9f47be8-e232-4968-bed5-24f099d8416d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741921132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1741921132
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.392069031
Short name T1272
Test name
Test status
Simulation time 743910473 ps
CPU time 1.55 seconds
Started Apr 18 03:07:35 PM PDT 24
Finished Apr 18 03:07:37 PM PDT 24
Peak memory 212332 kb
Host smart-3f8e19c2-b4eb-4061-a0d2-a8105cda1469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392069031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.392069031
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.427283604
Short name T691
Test name
Test status
Simulation time 3753547468 ps
CPU time 8.98 seconds
Started Apr 18 03:07:23 PM PDT 24
Finished Apr 18 03:07:32 PM PDT 24
Peak memory 306196 kb
Host smart-3572f479-f372-4750-852e-95d884884bee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427283604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.427283604
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1496328352
Short name T720
Test name
Test status
Simulation time 4460106491 ps
CPU time 142.27 seconds
Started Apr 18 03:07:24 PM PDT 24
Finished Apr 18 03:09:46 PM PDT 24
Peak memory 653404 kb
Host smart-1286edda-0724-43db-96a0-3443d23ad42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496328352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1496328352
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2417285348
Short name T471
Test name
Test status
Simulation time 2739525722 ps
CPU time 43.01 seconds
Started Apr 18 03:07:25 PM PDT 24
Finished Apr 18 03:08:08 PM PDT 24
Peak memory 542832 kb
Host smart-66fc2734-e59e-4e86-899a-e20c00261991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417285348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2417285348
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1268082125
Short name T358
Test name
Test status
Simulation time 224835983 ps
CPU time 0.86 seconds
Started Apr 18 03:07:24 PM PDT 24
Finished Apr 18 03:07:25 PM PDT 24
Peak memory 203740 kb
Host smart-07510fe6-c921-47d1-94a7-4730628eea9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268082125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1268082125
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1002993012
Short name T1046
Test name
Test status
Simulation time 165966610 ps
CPU time 3.1 seconds
Started Apr 18 03:07:25 PM PDT 24
Finished Apr 18 03:07:28 PM PDT 24
Peak memory 203964 kb
Host smart-91cf7396-787c-47e9-ad6f-5cab2d6a2279
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002993012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1002993012
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3047033731
Short name T641
Test name
Test status
Simulation time 2794438836 ps
CPU time 65.95 seconds
Started Apr 18 03:07:24 PM PDT 24
Finished Apr 18 03:08:30 PM PDT 24
Peak memory 896084 kb
Host smart-920809bf-3810-4fb4-b8a2-caa6f6012eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047033731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3047033731
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.835125665
Short name T469
Test name
Test status
Simulation time 448751565 ps
CPU time 6.75 seconds
Started Apr 18 03:07:43 PM PDT 24
Finished Apr 18 03:07:50 PM PDT 24
Peak memory 203972 kb
Host smart-0502244a-8ae0-40cf-ab12-12529834a1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835125665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.835125665
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1872022290
Short name T999
Test name
Test status
Simulation time 848921840 ps
CPU time 37.15 seconds
Started Apr 18 03:07:43 PM PDT 24
Finished Apr 18 03:08:21 PM PDT 24
Peak memory 228440 kb
Host smart-8340f05e-53ce-4e47-9e34-55f0d0ba68d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872022290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1872022290
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1884530177
Short name T1039
Test name
Test status
Simulation time 47298735 ps
CPU time 0.64 seconds
Started Apr 18 03:07:24 PM PDT 24
Finished Apr 18 03:07:25 PM PDT 24
Peak memory 203660 kb
Host smart-63192a32-65eb-41a1-b049-dd3f633d8dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884530177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1884530177
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.506064273
Short name T63
Test name
Test status
Simulation time 6115711702 ps
CPU time 16.43 seconds
Started Apr 18 03:07:25 PM PDT 24
Finished Apr 18 03:07:42 PM PDT 24
Peak memory 220440 kb
Host smart-e4604006-88ef-4154-b8f2-049642803a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506064273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.506064273
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.4160494110
Short name T1139
Test name
Test status
Simulation time 2895319548 ps
CPU time 66.44 seconds
Started Apr 18 03:07:26 PM PDT 24
Finished Apr 18 03:08:32 PM PDT 24
Peak memory 340096 kb
Host smart-b56d7d51-6770-445d-b85f-1cd83a93ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160494110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.4160494110
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3815317818
Short name T89
Test name
Test status
Simulation time 1270706968 ps
CPU time 10.96 seconds
Started Apr 18 03:07:30 PM PDT 24
Finished Apr 18 03:07:41 PM PDT 24
Peak memory 220240 kb
Host smart-fd2dbedf-fc2f-4d88-8089-e43d4702126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815317818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3815317818
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1216852830
Short name T1042
Test name
Test status
Simulation time 4236540620 ps
CPU time 4.59 seconds
Started Apr 18 03:07:45 PM PDT 24
Finished Apr 18 03:07:49 PM PDT 24
Peak memory 212268 kb
Host smart-cbeac75f-ad3f-49bc-861d-ee1a4010326e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216852830 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1216852830
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3079054537
Short name T276
Test name
Test status
Simulation time 10437613986 ps
CPU time 14.4 seconds
Started Apr 18 03:07:40 PM PDT 24
Finished Apr 18 03:07:55 PM PDT 24
Peak memory 296112 kb
Host smart-8f9f1aa9-d8f9-46d0-8f7c-36647040f963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079054537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3079054537
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2088899070
Short name T1116
Test name
Test status
Simulation time 10329690430 ps
CPU time 13.52 seconds
Started Apr 18 03:07:41 PM PDT 24
Finished Apr 18 03:07:55 PM PDT 24
Peak memory 313376 kb
Host smart-233d0fa1-025c-456e-a28e-611613f8b8a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088899070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2088899070
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.3134647878
Short name T1021
Test name
Test status
Simulation time 1841529236 ps
CPU time 2.62 seconds
Started Apr 18 03:07:44 PM PDT 24
Finished Apr 18 03:07:47 PM PDT 24
Peak memory 203952 kb
Host smart-d41ef105-af12-43ce-bd5f-fa2ff3711fd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134647878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.3134647878
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2617743829
Short name T367
Test name
Test status
Simulation time 837480043 ps
CPU time 4.29 seconds
Started Apr 18 03:07:28 PM PDT 24
Finished Apr 18 03:07:33 PM PDT 24
Peak memory 205924 kb
Host smart-9a6db5c7-2fc3-4744-bff4-112576ca7ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617743829 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2617743829
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3363346140
Short name T979
Test name
Test status
Simulation time 9665643362 ps
CPU time 23.3 seconds
Started Apr 18 03:07:37 PM PDT 24
Finished Apr 18 03:08:01 PM PDT 24
Peak memory 578980 kb
Host smart-0cbf1447-4f9b-4f00-8b7b-9d2749d10cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363346140 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3363346140
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3901162317
Short name T394
Test name
Test status
Simulation time 667932983 ps
CPU time 10.38 seconds
Started Apr 18 03:07:30 PM PDT 24
Finished Apr 18 03:07:41 PM PDT 24
Peak memory 203988 kb
Host smart-98374c6d-2955-4abe-879a-5de086dcc9e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901162317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3901162317
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2139538401
Short name T1308
Test name
Test status
Simulation time 2498060808 ps
CPU time 27.03 seconds
Started Apr 18 03:07:33 PM PDT 24
Finished Apr 18 03:08:00 PM PDT 24
Peak memory 204088 kb
Host smart-31c7f076-365f-41b6-b89b-7f7bafa5a762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139538401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2139538401
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2973065596
Short name T1160
Test name
Test status
Simulation time 36050759139 ps
CPU time 31.6 seconds
Started Apr 18 03:07:30 PM PDT 24
Finished Apr 18 03:08:02 PM PDT 24
Peak memory 707736 kb
Host smart-b8b7c7bd-104e-418c-bcf4-81629b0510e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973065596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2973065596
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.1120405800
Short name T853
Test name
Test status
Simulation time 28662729907 ps
CPU time 119.74 seconds
Started Apr 18 03:07:29 PM PDT 24
Finished Apr 18 03:09:30 PM PDT 24
Peak memory 1062196 kb
Host smart-feee37a9-53c6-458c-8f9a-6d6b268948e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120405800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.1120405800
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2386917785
Short name T890
Test name
Test status
Simulation time 4740692375 ps
CPU time 6.37 seconds
Started Apr 18 03:07:39 PM PDT 24
Finished Apr 18 03:07:46 PM PDT 24
Peak memory 220284 kb
Host smart-4dc8e35a-d3d5-4be8-8fb0-eb5dd511c3b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386917785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2386917785
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3518816687
Short name T103
Test name
Test status
Simulation time 21704338 ps
CPU time 0.59 seconds
Started Apr 18 03:08:06 PM PDT 24
Finished Apr 18 03:08:07 PM PDT 24
Peak memory 203536 kb
Host smart-6d4dc0c2-a4aa-4c53-8fbe-bed615129ea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518816687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3518816687
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3484932479
Short name T849
Test name
Test status
Simulation time 215548578 ps
CPU time 1.92 seconds
Started Apr 18 03:07:56 PM PDT 24
Finished Apr 18 03:07:58 PM PDT 24
Peak memory 212320 kb
Host smart-c8ba5d85-dae4-42dd-9079-77858889a4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484932479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3484932479
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.52099672
Short name T790
Test name
Test status
Simulation time 630754333 ps
CPU time 16.71 seconds
Started Apr 18 03:07:51 PM PDT 24
Finished Apr 18 03:08:08 PM PDT 24
Peak memory 269836 kb
Host smart-b134db46-7110-4f99-987b-a47dbad3fd0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52099672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.52099672
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3440889504
Short name T1017
Test name
Test status
Simulation time 7714349984 ps
CPU time 49.29 seconds
Started Apr 18 03:07:48 PM PDT 24
Finished Apr 18 03:08:38 PM PDT 24
Peak memory 619400 kb
Host smart-e018a616-3cc3-48b7-be67-74d64e982b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440889504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3440889504
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1448382666
Short name T1159
Test name
Test status
Simulation time 1520156364 ps
CPU time 118.92 seconds
Started Apr 18 03:07:50 PM PDT 24
Finished Apr 18 03:09:49 PM PDT 24
Peak memory 577172 kb
Host smart-d33ddb7f-51f9-42de-9120-2f17f5614aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448382666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1448382666
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1793282272
Short name T551
Test name
Test status
Simulation time 162723676 ps
CPU time 1.01 seconds
Started Apr 18 03:07:50 PM PDT 24
Finished Apr 18 03:07:51 PM PDT 24
Peak memory 203892 kb
Host smart-2224dec5-649d-42b4-8e9d-e67471562610
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793282272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1793282272
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1494491651
Short name T937
Test name
Test status
Simulation time 418086321 ps
CPU time 10.67 seconds
Started Apr 18 03:07:52 PM PDT 24
Finished Apr 18 03:08:03 PM PDT 24
Peak memory 203924 kb
Host smart-090dd28d-ebc6-4057-b70b-bea1377bd71a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494491651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1494491651
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2231667063
Short name T803
Test name
Test status
Simulation time 17705353712 ps
CPU time 115.1 seconds
Started Apr 18 03:07:49 PM PDT 24
Finished Apr 18 03:09:44 PM PDT 24
Peak memory 1307504 kb
Host smart-e10cf7b4-d048-4e8e-961e-313939e240f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231667063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2231667063
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2622516153
Short name T1174
Test name
Test status
Simulation time 427185971 ps
CPU time 4.69 seconds
Started Apr 18 03:08:06 PM PDT 24
Finished Apr 18 03:08:11 PM PDT 24
Peak memory 203980 kb
Host smart-8e1706bb-a879-416d-8f16-0f0df911c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622516153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2622516153
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.4085802161
Short name T813
Test name
Test status
Simulation time 31527085528 ps
CPU time 31.94 seconds
Started Apr 18 03:08:06 PM PDT 24
Finished Apr 18 03:08:39 PM PDT 24
Peak memory 350360 kb
Host smart-e7531302-0efb-4b37-9be9-c62c07b435e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085802161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.4085802161
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.78957869
Short name T804
Test name
Test status
Simulation time 16594433 ps
CPU time 0.65 seconds
Started Apr 18 03:07:50 PM PDT 24
Finished Apr 18 03:07:51 PM PDT 24
Peak memory 203652 kb
Host smart-432134a2-33fa-499c-9b3c-49cd1b73148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78957869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.78957869
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.486090823
Short name T572
Test name
Test status
Simulation time 52577470427 ps
CPU time 731.26 seconds
Started Apr 18 03:07:51 PM PDT 24
Finished Apr 18 03:20:03 PM PDT 24
Peak memory 2663560 kb
Host smart-8650726d-f30e-4275-a79d-71c7b3779eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486090823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.486090823
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1711728493
Short name T1334
Test name
Test status
Simulation time 4134284021 ps
CPU time 50.16 seconds
Started Apr 18 03:07:45 PM PDT 24
Finished Apr 18 03:08:36 PM PDT 24
Peak memory 313820 kb
Host smart-b59a597f-2f50-4f9a-a4dc-cdd0a7e94da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711728493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1711728493
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.3530273602
Short name T240
Test name
Test status
Simulation time 6389894486 ps
CPU time 228.46 seconds
Started Apr 18 03:08:00 PM PDT 24
Finished Apr 18 03:11:49 PM PDT 24
Peak memory 1265932 kb
Host smart-041aa784-0298-4271-ac20-0b152f112df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530273602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.3530273602
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2740579740
Short name T982
Test name
Test status
Simulation time 7568871883 ps
CPU time 12.1 seconds
Started Apr 18 03:07:50 PM PDT 24
Finished Apr 18 03:08:02 PM PDT 24
Peak memory 228912 kb
Host smart-03d61d8a-144b-4189-835a-fa935f93d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740579740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2740579740
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.671533331
Short name T314
Test name
Test status
Simulation time 562437614 ps
CPU time 2.68 seconds
Started Apr 18 03:08:09 PM PDT 24
Finished Apr 18 03:08:12 PM PDT 24
Peak memory 203976 kb
Host smart-ff12b6d3-8701-4bfe-af52-2983ee846c6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671533331 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.671533331
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3153642782
Short name T578
Test name
Test status
Simulation time 10145793173 ps
CPU time 14.81 seconds
Started Apr 18 03:08:00 PM PDT 24
Finished Apr 18 03:08:15 PM PDT 24
Peak memory 284748 kb
Host smart-ad8580d9-9220-4cf3-ae5d-642071dcaa91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153642782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3153642782
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3270455201
Short name T826
Test name
Test status
Simulation time 405510007 ps
CPU time 2.56 seconds
Started Apr 18 03:08:06 PM PDT 24
Finished Apr 18 03:08:09 PM PDT 24
Peak memory 204000 kb
Host smart-e6eff45c-7255-4c0e-bdd5-9478daef6463
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270455201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3270455201
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2066079024
Short name T298
Test name
Test status
Simulation time 7405089475 ps
CPU time 3.73 seconds
Started Apr 18 03:08:02 PM PDT 24
Finished Apr 18 03:08:06 PM PDT 24
Peak memory 204532 kb
Host smart-5c3c067c-34f9-457b-beda-5bf2c033571c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066079024 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2066079024
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3935838493
Short name T315
Test name
Test status
Simulation time 15591387881 ps
CPU time 6.29 seconds
Started Apr 18 03:08:00 PM PDT 24
Finished Apr 18 03:08:06 PM PDT 24
Peak memory 204080 kb
Host smart-8569c2fe-f3d8-4a15-9b4a-de71f4ba8672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935838493 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3935838493
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3427960843
Short name T1172
Test name
Test status
Simulation time 1625252931 ps
CPU time 26.6 seconds
Started Apr 18 03:07:54 PM PDT 24
Finished Apr 18 03:08:21 PM PDT 24
Peak memory 203912 kb
Host smart-defc3000-a1eb-4cec-9790-eaad8945db1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427960843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3427960843
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2258386132
Short name T255
Test name
Test status
Simulation time 2601020504 ps
CPU time 25.67 seconds
Started Apr 18 03:08:02 PM PDT 24
Finished Apr 18 03:08:28 PM PDT 24
Peak memory 232628 kb
Host smart-2a424f96-2641-4ba4-bb20-a4100807b4e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258386132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2258386132
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.388972570
Short name T1237
Test name
Test status
Simulation time 51432335529 ps
CPU time 166.23 seconds
Started Apr 18 03:07:54 PM PDT 24
Finished Apr 18 03:10:40 PM PDT 24
Peak memory 2098288 kb
Host smart-ae22dfe5-3ba7-468c-878d-13142dda8c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388972570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.388972570
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2267976403
Short name T1370
Test name
Test status
Simulation time 36703327117 ps
CPU time 128.19 seconds
Started Apr 18 03:08:00 PM PDT 24
Finished Apr 18 03:10:09 PM PDT 24
Peak memory 546988 kb
Host smart-b07bdd76-40ce-4c9c-93bd-800908afeb95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267976403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2267976403
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1535325172
Short name T1023
Test name
Test status
Simulation time 1556849484 ps
CPU time 6.49 seconds
Started Apr 18 03:07:59 PM PDT 24
Finished Apr 18 03:08:06 PM PDT 24
Peak memory 204020 kb
Host smart-85855945-c0eb-499e-b638-10eedeb9c452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535325172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1535325172
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.818766585
Short name T736
Test name
Test status
Simulation time 54536191 ps
CPU time 0.61 seconds
Started Apr 18 03:08:39 PM PDT 24
Finished Apr 18 03:08:41 PM PDT 24
Peak memory 203560 kb
Host smart-db544a97-f678-4fda-bac4-eecc22c0d16b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818766585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.818766585
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3959556763
Short name T281
Test name
Test status
Simulation time 270110543 ps
CPU time 1.05 seconds
Started Apr 18 03:08:17 PM PDT 24
Finished Apr 18 03:08:19 PM PDT 24
Peak memory 212268 kb
Host smart-1e824dc8-6ff4-4bd0-984e-5bb8b283a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959556763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3959556763
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2115616262
Short name T1008
Test name
Test status
Simulation time 161476791 ps
CPU time 8.13 seconds
Started Apr 18 03:08:11 PM PDT 24
Finished Apr 18 03:08:20 PM PDT 24
Peak memory 229272 kb
Host smart-9103aad4-bb18-453c-90eb-ba48baa15382
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115616262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2115616262
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1062554762
Short name T1061
Test name
Test status
Simulation time 21374482761 ps
CPU time 82.84 seconds
Started Apr 18 03:08:18 PM PDT 24
Finished Apr 18 03:09:42 PM PDT 24
Peak memory 696628 kb
Host smart-abcf5270-510b-4718-9c18-d121254d577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062554762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1062554762
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.4001458209
Short name T509
Test name
Test status
Simulation time 2162896253 ps
CPU time 153.5 seconds
Started Apr 18 03:08:10 PM PDT 24
Finished Apr 18 03:10:44 PM PDT 24
Peak memory 707804 kb
Host smart-1f001725-8e77-41f2-af18-0f8eb6ffefed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001458209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.4001458209
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2650798225
Short name T517
Test name
Test status
Simulation time 699896385 ps
CPU time 1.05 seconds
Started Apr 18 03:08:13 PM PDT 24
Finished Apr 18 03:08:14 PM PDT 24
Peak memory 203720 kb
Host smart-76e02123-9b7a-43e4-b409-659dd9152bcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650798225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2650798225
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3805316261
Short name T1126
Test name
Test status
Simulation time 559569047 ps
CPU time 3.69 seconds
Started Apr 18 03:08:12 PM PDT 24
Finished Apr 18 03:08:16 PM PDT 24
Peak memory 203892 kb
Host smart-99acfe30-b6b4-417d-b7c7-f8a41355df2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805316261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3805316261
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.4070878806
Short name T464
Test name
Test status
Simulation time 2307908076 ps
CPU time 59.81 seconds
Started Apr 18 03:08:12 PM PDT 24
Finished Apr 18 03:09:12 PM PDT 24
Peak memory 745576 kb
Host smart-08d54be8-6bfa-4d14-a43c-53327b61e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070878806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.4070878806
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.60605177
Short name T311
Test name
Test status
Simulation time 2479336167 ps
CPU time 25.05 seconds
Started Apr 18 03:08:39 PM PDT 24
Finished Apr 18 03:09:05 PM PDT 24
Peak memory 203960 kb
Host smart-2fdca6af-3b96-4fa1-b2aa-b6d2cbd5a143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60605177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.60605177
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2008962912
Short name T966
Test name
Test status
Simulation time 1626322414 ps
CPU time 80.07 seconds
Started Apr 18 03:08:37 PM PDT 24
Finished Apr 18 03:09:58 PM PDT 24
Peak memory 413776 kb
Host smart-0c7cb54d-77a2-4ab9-b4e1-7c4977ad45b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008962912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2008962912
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.1116843859
Short name T187
Test name
Test status
Simulation time 40568691 ps
CPU time 0.65 seconds
Started Apr 18 03:08:04 PM PDT 24
Finished Apr 18 03:08:05 PM PDT 24
Peak memory 203672 kb
Host smart-8db3f440-a8af-48b1-b7d5-22357b38d857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116843859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1116843859
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2445631553
Short name T723
Test name
Test status
Simulation time 469616613 ps
CPU time 2.48 seconds
Started Apr 18 03:08:18 PM PDT 24
Finished Apr 18 03:08:21 PM PDT 24
Peak memory 212180 kb
Host smart-e13889e4-5778-4002-a382-6ccd1819f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445631553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2445631553
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3158858603
Short name T8
Test name
Test status
Simulation time 1238472410 ps
CPU time 58.09 seconds
Started Apr 18 03:08:07 PM PDT 24
Finished Apr 18 03:09:05 PM PDT 24
Peak memory 290736 kb
Host smart-ec3bf804-91a4-4583-a0ae-bd24578557c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158858603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3158858603
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1196824189
Short name T1292
Test name
Test status
Simulation time 46805957464 ps
CPU time 852.53 seconds
Started Apr 18 03:08:18 PM PDT 24
Finished Apr 18 03:22:31 PM PDT 24
Peak memory 2873116 kb
Host smart-97ae82e8-986b-4381-af13-ae1ad627a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196824189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1196824189
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2224398342
Short name T928
Test name
Test status
Simulation time 396694243 ps
CPU time 16.69 seconds
Started Apr 18 03:08:18 PM PDT 24
Finished Apr 18 03:08:35 PM PDT 24
Peak memory 212184 kb
Host smart-749c4081-93f3-47a3-a082-ec0ac257083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224398342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2224398342
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2649288560
Short name T646
Test name
Test status
Simulation time 1723281338 ps
CPU time 3.65 seconds
Started Apr 18 03:08:31 PM PDT 24
Finished Apr 18 03:08:35 PM PDT 24
Peak memory 203968 kb
Host smart-6fd4ef7a-c059-49b5-89f3-19686aa78c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649288560 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2649288560
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3998914286
Short name T361
Test name
Test status
Simulation time 10039612845 ps
CPU time 26.12 seconds
Started Apr 18 03:08:24 PM PDT 24
Finished Apr 18 03:08:50 PM PDT 24
Peak memory 328616 kb
Host smart-05b8a41d-1db3-40dd-93b8-fbdfe11c9d21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998914286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3998914286
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.63671251
Short name T738
Test name
Test status
Simulation time 10416977044 ps
CPU time 9.44 seconds
Started Apr 18 03:08:24 PM PDT 24
Finished Apr 18 03:08:34 PM PDT 24
Peak memory 252880 kb
Host smart-3d3cf972-75c4-4cf8-9061-7ee2e4445882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63671251 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_fifo_reset_tx.63671251
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3945094307
Short name T859
Test name
Test status
Simulation time 2644552195 ps
CPU time 1.81 seconds
Started Apr 18 03:08:39 PM PDT 24
Finished Apr 18 03:08:41 PM PDT 24
Peak memory 204040 kb
Host smart-73532be4-044d-4c18-ba07-dd24fad2d4bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945094307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3945094307
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3290622789
Short name T1261
Test name
Test status
Simulation time 432296081 ps
CPU time 2.78 seconds
Started Apr 18 03:08:24 PM PDT 24
Finished Apr 18 03:08:27 PM PDT 24
Peak memory 203996 kb
Host smart-104a795e-db13-4194-94e5-5666663af7fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290622789 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3290622789
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2397527034
Short name T1100
Test name
Test status
Simulation time 8600114020 ps
CPU time 25.67 seconds
Started Apr 18 03:08:24 PM PDT 24
Finished Apr 18 03:08:50 PM PDT 24
Peak memory 508488 kb
Host smart-0a4884c7-9ced-4a28-b115-bf330cd311c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397527034 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2397527034
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.4215787698
Short name T981
Test name
Test status
Simulation time 1296005639 ps
CPU time 19.14 seconds
Started Apr 18 03:08:20 PM PDT 24
Finished Apr 18 03:08:40 PM PDT 24
Peak memory 204020 kb
Host smart-cf194541-cd60-4f2a-95cc-708c79d47200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215787698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.4215787698
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.498784199
Short name T552
Test name
Test status
Simulation time 4045672151 ps
CPU time 14.35 seconds
Started Apr 18 03:08:28 PM PDT 24
Finished Apr 18 03:08:43 PM PDT 24
Peak memory 213472 kb
Host smart-2cf74034-f0d2-41ab-81c4-90660c416a30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498784199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.498784199
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1645001734
Short name T221
Test name
Test status
Simulation time 58176219956 ps
CPU time 1742.28 seconds
Started Apr 18 03:08:28 PM PDT 24
Finished Apr 18 03:37:31 PM PDT 24
Peak memory 9635288 kb
Host smart-9a2dea47-5d24-4ac7-9345-f5d5f9a8e139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645001734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1645001734
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.793154737
Short name T1012
Test name
Test status
Simulation time 26882224726 ps
CPU time 983.87 seconds
Started Apr 18 03:08:25 PM PDT 24
Finished Apr 18 03:24:49 PM PDT 24
Peak memory 4612240 kb
Host smart-dcf25748-12cc-48ba-825d-ca6ee93b30a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793154737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.793154737
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1522507821
Short name T545
Test name
Test status
Simulation time 1336651083 ps
CPU time 6.4 seconds
Started Apr 18 03:08:28 PM PDT 24
Finished Apr 18 03:08:35 PM PDT 24
Peak memory 210092 kb
Host smart-b74b421f-5380-46c9-8bf7-932e0e7dffdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522507821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1522507821
Directory /workspace/9.i2c_target_timeout/latest
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