Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357	1			T1	5		T3	8		T7	8
all_values[1]	357	1			T1	5		T3	8		T7	8
all_values[2]	357	1			T1	5		T3	8		T7	8
all_values[3]	357	1			T1	5		T3	8		T7	8
all_values[4]	357	1			T1	5		T3	8		T7	8
all_values[5]	357	1			T1	5		T3	8		T7	8
all_values[6]	357	1			T1	5		T3	8		T7	8
all_values[7]	357	1			T1	5		T3	8		T7	8
all_values[8]	357	1			T1	5		T3	8		T7	8
all_values[9]	357	1			T1	5		T3	8		T7	8
all_values[10]	357	1			T1	5		T3	8		T7	8
all_values[11]	357	1			T1	5		T3	8		T7	8
all_values[12]	357	1			T1	5		T3	8		T7	8
all_values[13]	357	1			T1	5		T3	8		T7	8
all_values[14]	357	1			T1	5		T3	8		T7	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3407

1

T1

42

T3

69

T7

74

auto[1]

1948

1

T1

33

T3

51

T7

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T1

11

T3

13

T7

13

auto[1]

4219

1

T1

64

T3

107

T7

107

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80	1			T3	4		T6	4		T9	3
all_values[0]	auto[0]	auto[1]	158	1			T1	4		T3	3		T7	5
all_values[0]	auto[1]	auto[1]	119	1			T1	1		T3	1		T7	3
all_values[1]	auto[0]	auto[0]	68	1			T9	2		T10	1		T11	1
all_values[1]	auto[0]	auto[1]	159	1			T1	3		T3	5		T7	5
all_values[1]	auto[1]	auto[1]	130	1			T1	2		T3	3		T7	3
all_values[2]	auto[0]	auto[0]	64	1			T1	1		T3	1		T11	1
all_values[2]	auto[0]	auto[1]	171	1			T1	2		T3	3		T7	3
all_values[2]	auto[1]	auto[1]	122	1			T1	2		T3	4		T7	5
all_values[3]	auto[0]	auto[0]	75	1			T1	1		T6	2		T11	1
all_values[3]	auto[0]	auto[1]	144	1			T1	1		T3	6		T7	5
all_values[3]	auto[1]	auto[1]	138	1			T1	3		T3	2		T7	3
all_values[4]	auto[0]	auto[0]	89	1			T1	2		T6	1		T9	1
all_values[4]	auto[0]	auto[1]	157	1			T1	2		T3	4		T7	5
all_values[4]	auto[1]	auto[1]	111	1			T1	1		T3	4		T7	3
all_values[5]	auto[0]	auto[0]	63	1			T6	3		T11	1		T12	1
all_values[5]	auto[0]	auto[1]	149	1			T1	2		T3	5		T7	5
all_values[5]	auto[1]	auto[1]	145	1			T1	3		T3	3		T7	3
all_values[6]	auto[0]	auto[0]	70	1			T1	1		T3	2		T7	3
all_values[6]	auto[0]	auto[1]	132	1			T1	4		T3	2		T7	4
all_values[6]	auto[1]	auto[1]	155	1			T3	4		T7	1		T6	7
all_values[7]	auto[0]	auto[0]	70	1			T3	1		T9	2		T10	2
all_values[7]	auto[0]	auto[1]	148	1			T1	1		T3	2		T7	6
all_values[7]	auto[1]	auto[1]	139	1			T1	4		T3	5		T7	2
all_values[8]	auto[0]	auto[0]	85	1			T6	2		T9	2		T10	1
all_values[8]	auto[0]	auto[1]	158	1			T1	2		T3	4		T7	6
all_values[8]	auto[1]	auto[1]	114	1			T1	3		T3	4		T7	2
all_values[9]	auto[0]	auto[0]	81	1			T1	1		T3	1		T7	3
all_values[9]	auto[0]	auto[1]	131	1			T1	1		T3	3		T7	1
all_values[9]	auto[1]	auto[1]	145	1			T1	3		T3	4		T7	4
all_values[10]	auto[0]	auto[0]	71	1			T1	1		T6	2		T9	1
all_values[10]	auto[0]	auto[1]	157	1			T1	3		T3	5		T7	4
all_values[10]	auto[1]	auto[1]	129	1			T1	1		T3	3		T7	4
all_values[11]	auto[0]	auto[0]	76	1			T1	1		T3	1		T7	2
all_values[11]	auto[0]	auto[1]	176	1			T1	2		T3	2		T7	5
all_values[11]	auto[1]	auto[1]	105	1			T1	2		T3	5		T7	1
all_values[12]	auto[0]	auto[0]	79	1			T1	2		T11	1		T12	1
all_values[12]	auto[0]	auto[1]	158	1			T1	2		T3	2		T7	5
all_values[12]	auto[1]	auto[1]	120	1			T1	1		T3	6		T7	3
all_values[13]	auto[0]	auto[0]	101	1			T3	2		T7	1		T9	1
all_values[13]	auto[0]	auto[1]	135	1			T1	1		T3	5		T7	1
all_values[13]	auto[1]	auto[1]	121	1			T1	4		T3	1		T7	6
all_values[14]	auto[0]	auto[0]	64	1			T1	1		T3	1		T7	4
all_values[14]	auto[0]	auto[1]	138	1			T1	1		T3	5		T7	1
all_values[14]	auto[1]	auto[1]	155	1			T1	3		T3	2		T7	3