Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
53.21	41.32	42.93	91.36	0.00	42.98	100.00	53.89

Total tests in report: 146

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
46.60	46.60	39.60	39.60	38.78	38.78	90.77	90.77	0.00	0.00	41.99	41.99	96.18	96.18	18.91	18.91	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1225875674
51.85	5.24	40.82	1.22	41.45	2.67	95.26	4.49	0.00	0.00	42.90	0.91	96.50	0.32	46.01	27.10	/workspace/coverage/cover_reg_top/30.i2c_intr_test.725058562
52.65	0.80	40.82	0.00	42.34	0.89	96.51	1.25	0.00	0.00	42.98	0.08	97.13	0.64	48.74	2.73	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.384141053
53.05	0.41	41.32	0.50	42.46	0.13	96.51	0.00	0.00	0.00	42.98	0.00	99.36	2.23	48.74	0.00	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1338937058
53.40	0.35	41.32	0.00	42.46	0.00	96.51	0.00	0.00	0.00	42.98	0.00	99.36	0.00	51.16	2.42	/workspace/coverage/cover_reg_top/29.i2c_intr_test.625426486
53.58	0.18	41.32	0.00	42.46	0.00	97.26	0.75	0.00	0.00	42.98	0.00	99.68	0.32	51.37	0.21	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.396067747
53.72	0.14	41.32	0.00	42.46	0.00	97.26	0.00	0.00	0.00	42.98	0.00	99.68	0.00	52.31	0.95	/workspace/coverage/cover_reg_top/8.i2c_intr_test.125820389
53.79	0.08	41.32	0.00	42.46	0.00	97.26	0.00	0.00	0.00	42.98	0.00	100.00	0.32	52.52	0.21	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.3903359872
53.85	0.06	41.32	0.00	42.55	0.08	97.51	0.25	0.00	0.00	42.98	0.00	100.00	0.00	52.63	0.11	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2829159696
53.90	0.05	41.32	0.00	42.55	0.00	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	52.94	0.32	/workspace/coverage/cover_reg_top/12.i2c_intr_test.1840417594
53.93	0.03	41.32	0.00	42.76	0.21	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	52.94	0.00	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2715420415
53.96	0.03	41.32	0.00	42.76	0.00	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	53.15	0.21	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.599288693
53.99	0.03	41.32	0.00	42.76	0.00	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	53.36	0.21	/workspace/coverage/cover_reg_top/16.i2c_intr_test.3393340417
54.02	0.03	41.32	0.00	42.76	0.00	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	53.57	0.21	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2027472444
54.04	0.02	41.32	0.00	42.93	0.17	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	53.57	0.00	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2290881813
54.06	0.02	41.32	0.00	42.93	0.00	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	53.68	0.11	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2150118251
54.07	0.02	41.32	0.00	42.93	0.00	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	53.78	0.11	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4210386098
54.09	0.02	41.32	0.00	42.93	0.00	97.51	0.00	0.00	0.00	42.98	0.00	100.00	0.00	53.89	0.11	/workspace/coverage/cover_reg_top/14.i2c_intr_test.1696117431

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.660360009
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.233449966
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1709226144
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1368491160
/workspace/coverage/cover_reg_top/0.i2c_intr_test.2904558132
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3264399446
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.250407630
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1684186581
/workspace/coverage/cover_reg_top/1.i2c_intr_test.620113041
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3238071499
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3914040324
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.505726380
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2020292420
/workspace/coverage/cover_reg_top/10.i2c_intr_test.1041293638
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1908081100
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2919653915
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3662882498
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1729227421
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.169678858
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2482063359
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1265982127
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1314006827
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3317880124
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2534523412
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.3215484011
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1641420113
/workspace/coverage/cover_reg_top/13.i2c_intr_test.1441847689
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1334995531
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.1524164391
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2162187574
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1101585045
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2610367778
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.4002216771
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1325987353
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3555367582
/workspace/coverage/cover_reg_top/15.i2c_intr_test.1127805530
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.352644856
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.845439146
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.919114456
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2564583048
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1525227468
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.901798240
/workspace/coverage/cover_reg_top/17.i2c_intr_test.2592926965
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2354671929
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1324580599
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1170582390
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1467537449
/workspace/coverage/cover_reg_top/18.i2c_intr_test.3897990690
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1200725619
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2785203740
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2936869276
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.505766746
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2970801559
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2156312597
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1638056779
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3960091773
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3469132754
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1354103482
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1731182292
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2133571075
/workspace/coverage/cover_reg_top/2.i2c_intr_test.3501327861
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.246650746
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3256605119
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3791427501
/workspace/coverage/cover_reg_top/21.i2c_intr_test.3112267293
/workspace/coverage/cover_reg_top/22.i2c_intr_test.738525650
/workspace/coverage/cover_reg_top/23.i2c_intr_test.1018953137
/workspace/coverage/cover_reg_top/24.i2c_intr_test.1100335139
/workspace/coverage/cover_reg_top/25.i2c_intr_test.4013895250
/workspace/coverage/cover_reg_top/26.i2c_intr_test.2938684418
/workspace/coverage/cover_reg_top/27.i2c_intr_test.1176840441
/workspace/coverage/cover_reg_top/28.i2c_intr_test.2473713738
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3388263901
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3784054888
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3414479041
/workspace/coverage/cover_reg_top/3.i2c_intr_test.1748939398
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.688910364
/workspace/coverage/cover_reg_top/31.i2c_intr_test.1145444578
/workspace/coverage/cover_reg_top/32.i2c_intr_test.276245278
/workspace/coverage/cover_reg_top/33.i2c_intr_test.1370862002
/workspace/coverage/cover_reg_top/34.i2c_intr_test.495842910
/workspace/coverage/cover_reg_top/35.i2c_intr_test.324091224
/workspace/coverage/cover_reg_top/36.i2c_intr_test.2965709673
/workspace/coverage/cover_reg_top/37.i2c_intr_test.2793680063
/workspace/coverage/cover_reg_top/38.i2c_intr_test.2094832311
/workspace/coverage/cover_reg_top/39.i2c_intr_test.1887349422
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3183300340
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.824700698
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2393440389
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.303813987
/workspace/coverage/cover_reg_top/4.i2c_intr_test.1010636802
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1747303465
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3742346595
/workspace/coverage/cover_reg_top/40.i2c_intr_test.301342975
/workspace/coverage/cover_reg_top/41.i2c_intr_test.2453881205
/workspace/coverage/cover_reg_top/42.i2c_intr_test.2322733212
/workspace/coverage/cover_reg_top/43.i2c_intr_test.590858522
/workspace/coverage/cover_reg_top/44.i2c_intr_test.2652709884
/workspace/coverage/cover_reg_top/45.i2c_intr_test.1288744837
/workspace/coverage/cover_reg_top/46.i2c_intr_test.1458026084
/workspace/coverage/cover_reg_top/47.i2c_intr_test.2840543788
/workspace/coverage/cover_reg_top/48.i2c_intr_test.1398400510
/workspace/coverage/cover_reg_top/49.i2c_intr_test.921359965
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.738636760
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.403027703
/workspace/coverage/cover_reg_top/5.i2c_intr_test.1880213567
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.253127584
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2861390956
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2956049123
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1368915249
/workspace/coverage/cover_reg_top/6.i2c_intr_test.3986198155
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2808727193
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1821665192
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.647930296
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2281142126
/workspace/coverage/cover_reg_top/7.i2c_intr_test.807221737
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4144555747
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.1917762736
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2340150367
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.922820509
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2621912718
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2175899990
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.602753963
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2504378946
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.579193075
/workspace/coverage/cover_reg_top/9.i2c_intr_test.3859031842
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3844408181
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3372089968

Total test records in report: 146

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/7.i2c_intr_test.807221737	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:01 PM PDT 24	38156136 ps
T2	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1225875674	Apr 21 12:56:59 PM PDT 24	Apr 21 12:57:02 PM PDT 24	759737561 ps
T3	/workspace/coverage/cover_reg_top/48.i2c_intr_test.1398400510	Apr 21 12:57:21 PM PDT 24	Apr 21 12:57:22 PM PDT 24	17788510 ps
T4	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1731182292	Apr 21 12:56:58 PM PDT 24	Apr 21 12:57:00 PM PDT 24	107762389 ps
T5	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2829159696	Apr 21 12:57:07 PM PDT 24	Apr 21 12:57:10 PM PDT 24	130609944 ps
T8	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2020292420	Apr 21 12:57:05 PM PDT 24	Apr 21 12:57:06 PM PDT 24	51071027 ps
T7	/workspace/coverage/cover_reg_top/12.i2c_intr_test.1840417594	Apr 21 12:57:04 PM PDT 24	Apr 21 12:57:05 PM PDT 24	30223712 ps
T6	/workspace/coverage/cover_reg_top/30.i2c_intr_test.725058562	Apr 21 12:57:17 PM PDT 24	Apr 21 12:57:18 PM PDT 24	39320370 ps
T9	/workspace/coverage/cover_reg_top/28.i2c_intr_test.2473713738	Apr 21 12:57:23 PM PDT 24	Apr 21 12:57:24 PM PDT 24	32958331 ps
T10	/workspace/coverage/cover_reg_top/9.i2c_intr_test.3859031842	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:04 PM PDT 24	43751517 ps
T11	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.384141053	Apr 21 12:56:53 PM PDT 24	Apr 21 12:56:56 PM PDT 24	262133196 ps
T12	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3256605119	Apr 21 12:56:54 PM PDT 24	Apr 21 12:56:56 PM PDT 24	30820514 ps
T19	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2290881813	Apr 21 12:57:02 PM PDT 24	Apr 21 12:57:05 PM PDT 24	124522234 ps
T57	/workspace/coverage/cover_reg_top/8.i2c_intr_test.125820389	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:04 PM PDT 24	28193512 ps
T58	/workspace/coverage/cover_reg_top/29.i2c_intr_test.625426486	Apr 21 12:57:22 PM PDT 24	Apr 21 12:57:23 PM PDT 24	24020783 ps
T20	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1638056779	Apr 21 12:57:17 PM PDT 24	Apr 21 12:57:18 PM PDT 24	25099538 ps
T13	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2393440389	Apr 21 12:56:57 PM PDT 24	Apr 21 12:56:59 PM PDT 24	53096054 ps
T14	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.922820509	Apr 21 12:57:02 PM PDT 24	Apr 21 12:57:03 PM PDT 24	66219941 ps
T15	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.352644856	Apr 21 12:57:13 PM PDT 24	Apr 21 12:57:14 PM PDT 24	23215395 ps
T21	/workspace/coverage/cover_reg_top/5.i2c_intr_test.1880213567	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:02 PM PDT 24	15378157 ps
T16	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.3215484011	Apr 21 12:57:11 PM PDT 24	Apr 21 12:57:13 PM PDT 24	92617876 ps
T22	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1325987353	Apr 21 12:57:08 PM PDT 24	Apr 21 12:57:10 PM PDT 24	96837143 ps
T17	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2482063359	Apr 21 12:57:06 PM PDT 24	Apr 21 12:57:07 PM PDT 24	132126715 ps
T23	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3183300340	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:05 PM PDT 24	63046739 ps
T24	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2027472444	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:04 PM PDT 24	52371930 ps
T33	/workspace/coverage/cover_reg_top/26.i2c_intr_test.2938684418	Apr 21 12:57:19 PM PDT 24	Apr 21 12:57:21 PM PDT 24	46001952 ps
T34	/workspace/coverage/cover_reg_top/0.i2c_intr_test.2904558132	Apr 21 12:56:54 PM PDT 24	Apr 21 12:56:55 PM PDT 24	15293184 ps
T25	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.396067747	Apr 21 12:56:58 PM PDT 24	Apr 21 12:57:00 PM PDT 24	45366235 ps
T35	/workspace/coverage/cover_reg_top/38.i2c_intr_test.2094832311	Apr 21 12:57:21 PM PDT 24	Apr 21 12:57:22 PM PDT 24	41350040 ps
T36	/workspace/coverage/cover_reg_top/1.i2c_intr_test.620113041	Apr 21 12:56:51 PM PDT 24	Apr 21 12:56:52 PM PDT 24	31222033 ps
T18	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2715420415	Apr 21 12:56:51 PM PDT 24	Apr 21 12:56:53 PM PDT 24	85647054 ps
T37	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3784054888	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:02 PM PDT 24	98701670 ps
T38	/workspace/coverage/cover_reg_top/6.i2c_intr_test.3986198155	Apr 21 12:56:57 PM PDT 24	Apr 21 12:56:58 PM PDT 24	17367370 ps
T26	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1354103482	Apr 21 12:57:00 PM PDT 24	Apr 21 12:57:03 PM PDT 24	77755790 ps
T76	/workspace/coverage/cover_reg_top/45.i2c_intr_test.1288744837	Apr 21 12:57:18 PM PDT 24	Apr 21 12:57:19 PM PDT 24	42558691 ps
T77	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3960091773	Apr 21 12:57:18 PM PDT 24	Apr 21 12:57:20 PM PDT 24	31618786 ps
T64	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2504378946	Apr 21 12:57:05 PM PDT 24	Apr 21 12:57:06 PM PDT 24	87156529 ps
T59	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3662882498	Apr 21 12:57:04 PM PDT 24	Apr 21 12:57:05 PM PDT 24	22843943 ps
T78	/workspace/coverage/cover_reg_top/47.i2c_intr_test.2840543788	Apr 21 12:57:24 PM PDT 24	Apr 21 12:57:25 PM PDT 24	25416917 ps
T27	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.824700698	Apr 21 12:56:56 PM PDT 24	Apr 21 12:56:57 PM PDT 24	33824621 ps
T60	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3844408181	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:05 PM PDT 24	57612338 ps
T65	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2919653915	Apr 21 12:57:08 PM PDT 24	Apr 21 12:57:09 PM PDT 24	92729909 ps
T28	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1338937058	Apr 21 12:56:50 PM PDT 24	Apr 21 12:56:52 PM PDT 24	18588024 ps
T52	/workspace/coverage/cover_reg_top/32.i2c_intr_test.276245278	Apr 21 12:57:21 PM PDT 24	Apr 21 12:57:22 PM PDT 24	37773715 ps
T53	/workspace/coverage/cover_reg_top/2.i2c_intr_test.3501327861	Apr 21 12:57:00 PM PDT 24	Apr 21 12:57:01 PM PDT 24	65502987 ps
T29	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2281142126	Apr 21 12:57:02 PM PDT 24	Apr 21 12:57:04 PM PDT 24	17033273 ps
T54	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.303813987	Apr 21 12:56:59 PM PDT 24	Apr 21 12:57:00 PM PDT 24	68104723 ps
T55	/workspace/coverage/cover_reg_top/18.i2c_intr_test.3897990690	Apr 21 12:57:17 PM PDT 24	Apr 21 12:57:18 PM PDT 24	34608965 ps
T56	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1370862002	Apr 21 12:57:21 PM PDT 24	Apr 21 12:57:22 PM PDT 24	25596970 ps
T30	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1368491160	Apr 21 12:56:53 PM PDT 24	Apr 21 12:56:54 PM PDT 24	30084513 ps
T44	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1127805530	Apr 21 12:57:13 PM PDT 24	Apr 21 12:57:14 PM PDT 24	25179298 ps
T45	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.901798240	Apr 21 12:57:12 PM PDT 24	Apr 21 12:57:13 PM PDT 24	47880651 ps
T46	/workspace/coverage/cover_reg_top/22.i2c_intr_test.738525650	Apr 21 12:57:15 PM PDT 24	Apr 21 12:57:16 PM PDT 24	44313452 ps
T47	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1101585045	Apr 21 12:57:07 PM PDT 24	Apr 21 12:57:08 PM PDT 24	49405545 ps
T48	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3264399446	Apr 21 12:56:53 PM PDT 24	Apr 21 12:56:56 PM PDT 24	568042687 ps
T31	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.599288693	Apr 21 12:56:52 PM PDT 24	Apr 21 12:56:53 PM PDT 24	20734445 ps
T49	/workspace/coverage/cover_reg_top/24.i2c_intr_test.1100335139	Apr 21 12:57:18 PM PDT 24	Apr 21 12:57:19 PM PDT 24	17917777 ps
T50	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.1917762736	Apr 21 12:57:02 PM PDT 24	Apr 21 12:57:05 PM PDT 24	136594247 ps
T51	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.647930296	Apr 21 12:57:02 PM PDT 24	Apr 21 12:57:04 PM PDT 24	38248956 ps
T66	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.579193075	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:04 PM PDT 24	62162266 ps
T67	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.4002216771	Apr 21 12:57:08 PM PDT 24	Apr 21 12:57:10 PM PDT 24	86306453 ps
T71	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.688910364	Apr 21 12:57:00 PM PDT 24	Apr 21 12:57:03 PM PDT 24	132220472 ps
T79	/workspace/coverage/cover_reg_top/43.i2c_intr_test.590858522	Apr 21 12:57:20 PM PDT 24	Apr 21 12:57:21 PM PDT 24	40794530 ps
T80	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3414479041	Apr 21 12:56:59 PM PDT 24	Apr 21 12:57:00 PM PDT 24	49098993 ps
T32	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4144555747	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:02 PM PDT 24	54980274 ps
T81	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.1524164391	Apr 21 12:57:06 PM PDT 24	Apr 21 12:57:09 PM PDT 24	249163389 ps
T82	/workspace/coverage/cover_reg_top/40.i2c_intr_test.301342975	Apr 21 12:57:17 PM PDT 24	Apr 21 12:57:18 PM PDT 24	95788477 ps
T83	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3112267293	Apr 21 12:57:18 PM PDT 24	Apr 21 12:57:19 PM PDT 24	43521059 ps
T63	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.602753963	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:06 PM PDT 24	497079388 ps
T84	/workspace/coverage/cover_reg_top/34.i2c_intr_test.495842910	Apr 21 12:57:21 PM PDT 24	Apr 21 12:57:23 PM PDT 24	33217517 ps
T85	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2936869276	Apr 21 12:57:14 PM PDT 24	Apr 21 12:57:17 PM PDT 24	145623748 ps
T68	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3914040324	Apr 21 12:56:49 PM PDT 24	Apr 21 12:56:52 PM PDT 24	351572272 ps
T86	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.250407630	Apr 21 12:56:53 PM PDT 24	Apr 21 12:56:55 PM PDT 24	30868989 ps
T87	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1314006827	Apr 21 12:57:05 PM PDT 24	Apr 21 12:57:07 PM PDT 24	26780303 ps
T75	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1887349422	Apr 21 12:57:23 PM PDT 24	Apr 21 12:57:24 PM PDT 24	15034658 ps
T39	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.919114456	Apr 21 12:57:13 PM PDT 24	Apr 21 12:57:14 PM PDT 24	29126278 ps
T40	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.403027703	Apr 21 12:56:59 PM PDT 24	Apr 21 12:57:00 PM PDT 24	83974259 ps
T88	/workspace/coverage/cover_reg_top/35.i2c_intr_test.324091224	Apr 21 12:57:20 PM PDT 24	Apr 21 12:57:21 PM PDT 24	40256462 ps
T89	/workspace/coverage/cover_reg_top/46.i2c_intr_test.1458026084	Apr 21 12:57:22 PM PDT 24	Apr 21 12:57:23 PM PDT 24	45653491 ps
T90	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2808727193	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:04 PM PDT 24	93408851 ps
T91	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2956049123	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:03 PM PDT 24	28074495 ps
T70	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3388263901	Apr 21 12:56:59 PM PDT 24	Apr 21 12:57:00 PM PDT 24	20360961 ps
T92	/workspace/coverage/cover_reg_top/41.i2c_intr_test.2453881205	Apr 21 12:57:19 PM PDT 24	Apr 21 12:57:20 PM PDT 24	47340724 ps
T72	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2861390956	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:04 PM PDT 24	429747851 ps
T93	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.233449966	Apr 21 12:56:58 PM PDT 24	Apr 21 12:57:01 PM PDT 24	84368340 ps
T73	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4210386098	Apr 21 12:56:50 PM PDT 24	Apr 21 12:56:53 PM PDT 24	164211555 ps
T94	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1041293638	Apr 21 12:57:08 PM PDT 24	Apr 21 12:57:09 PM PDT 24	194367915 ps
T95	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1145444578	Apr 21 12:57:19 PM PDT 24	Apr 21 12:57:20 PM PDT 24	18621877 ps
T96	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.505726380	Apr 21 12:57:09 PM PDT 24	Apr 21 12:57:10 PM PDT 24	35820653 ps
T97	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2133571075	Apr 21 12:56:54 PM PDT 24	Apr 21 12:56:55 PM PDT 24	16048731 ps
T98	/workspace/coverage/cover_reg_top/42.i2c_intr_test.2322733212	Apr 21 12:57:20 PM PDT 24	Apr 21 12:57:21 PM PDT 24	41116092 ps
T99	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.660360009	Apr 21 12:56:51 PM PDT 24	Apr 21 12:56:53 PM PDT 24	62282727 ps
T100	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3469132754	Apr 21 12:56:55 PM PDT 24	Apr 21 12:56:57 PM PDT 24	261930689 ps
T101	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2564583048	Apr 21 12:57:14 PM PDT 24	Apr 21 12:57:16 PM PDT 24	183532298 ps
T102	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1641420113	Apr 21 12:57:07 PM PDT 24	Apr 21 12:57:09 PM PDT 24	81506070 ps
T103	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2162187574	Apr 21 12:57:13 PM PDT 24	Apr 21 12:57:15 PM PDT 24	98244269 ps
T104	/workspace/coverage/cover_reg_top/25.i2c_intr_test.4013895250	Apr 21 12:57:20 PM PDT 24	Apr 21 12:57:21 PM PDT 24	18563800 ps
T41	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1467537449	Apr 21 12:57:13 PM PDT 24	Apr 21 12:57:14 PM PDT 24	37490265 ps
T74	/workspace/coverage/cover_reg_top/49.i2c_intr_test.921359965	Apr 21 12:57:23 PM PDT 24	Apr 21 12:57:24 PM PDT 24	56306518 ps
T105	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1334995531	Apr 21 12:57:06 PM PDT 24	Apr 21 12:57:07 PM PDT 24	57356149 ps
T106	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.246650746	Apr 21 12:56:54 PM PDT 24	Apr 21 12:56:55 PM PDT 24	164413127 ps
T107	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2534523412	Apr 21 12:57:12 PM PDT 24	Apr 21 12:57:13 PM PDT 24	35489656 ps
T108	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3238071499	Apr 21 12:57:00 PM PDT 24	Apr 21 12:57:01 PM PDT 24	65780134 ps
T109	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3555367582	Apr 21 12:57:12 PM PDT 24	Apr 21 12:57:13 PM PDT 24	27777719 ps
T110	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2175899990	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:05 PM PDT 24	170596463 ps
T111	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1525227468	Apr 21 12:57:14 PM PDT 24	Apr 21 12:57:15 PM PDT 24	39484721 ps
T112	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2610367778	Apr 21 12:57:12 PM PDT 24	Apr 21 12:57:13 PM PDT 24	305245999 ps
T113	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.845439146	Apr 21 12:57:12 PM PDT 24	Apr 21 12:57:13 PM PDT 24	81287484 ps
T114	/workspace/coverage/cover_reg_top/37.i2c_intr_test.2793680063	Apr 21 12:57:22 PM PDT 24	Apr 21 12:57:23 PM PDT 24	34486953 ps
T115	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3742346595	Apr 21 12:57:02 PM PDT 24	Apr 21 12:57:05 PM PDT 24	188157814 ps
T116	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2965709673	Apr 21 12:57:19 PM PDT 24	Apr 21 12:57:20 PM PDT 24	59997676 ps
T117	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.505766746	Apr 21 12:57:17 PM PDT 24	Apr 21 12:57:18 PM PDT 24	35267633 ps
T118	/workspace/coverage/cover_reg_top/4.i2c_intr_test.1010636802	Apr 21 12:56:59 PM PDT 24	Apr 21 12:57:00 PM PDT 24	19227058 ps
T119	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3791427501	Apr 21 12:57:18 PM PDT 24	Apr 21 12:57:20 PM PDT 24	44081235 ps
T120	/workspace/coverage/cover_reg_top/19.i2c_intr_test.2156312597	Apr 21 12:57:15 PM PDT 24	Apr 21 12:57:16 PM PDT 24	15595056 ps
T121	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1170582390	Apr 21 12:57:16 PM PDT 24	Apr 21 12:57:18 PM PDT 24	51032498 ps
T122	/workspace/coverage/cover_reg_top/16.i2c_intr_test.3393340417	Apr 21 12:57:11 PM PDT 24	Apr 21 12:57:12 PM PDT 24	37383413 ps
T123	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1729227421	Apr 21 12:57:10 PM PDT 24	Apr 21 12:57:11 PM PDT 24	32154050 ps
T124	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1200725619	Apr 21 12:57:14 PM PDT 24	Apr 21 12:57:15 PM PDT 24	20432318 ps
T42	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2970801559	Apr 21 12:57:16 PM PDT 24	Apr 21 12:57:17 PM PDT 24	46834835 ps
T125	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2592926965	Apr 21 12:57:18 PM PDT 24	Apr 21 12:57:19 PM PDT 24	15394039 ps
T126	/workspace/coverage/cover_reg_top/44.i2c_intr_test.2652709884	Apr 21 12:57:23 PM PDT 24	Apr 21 12:57:24 PM PDT 24	46685433 ps
T127	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2354671929	Apr 21 12:57:11 PM PDT 24	Apr 21 12:57:14 PM PDT 24	495591121 ps
T128	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3317880124	Apr 21 12:57:07 PM PDT 24	Apr 21 12:57:08 PM PDT 24	77165432 ps
T129	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.169678858	Apr 21 12:57:05 PM PDT 24	Apr 21 12:57:07 PM PDT 24	80044953 ps
T130	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3372089968	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:02 PM PDT 24	61072346 ps
T43	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.3903359872	Apr 21 12:57:11 PM PDT 24	Apr 21 12:57:12 PM PDT 24	29548450 ps
T131	/workspace/coverage/cover_reg_top/3.i2c_intr_test.1748939398	Apr 21 12:56:54 PM PDT 24	Apr 21 12:56:55 PM PDT 24	41731619 ps
T132	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1684186581	Apr 21 12:56:51 PM PDT 24	Apr 21 12:56:52 PM PDT 24	68883326 ps
T133	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1821665192	Apr 21 12:57:00 PM PDT 24	Apr 21 12:57:01 PM PDT 24	52081363 ps
T62	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1265982127	Apr 21 12:57:06 PM PDT 24	Apr 21 12:57:09 PM PDT 24	151998397 ps
T134	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.253127584	Apr 21 12:56:58 PM PDT 24	Apr 21 12:57:01 PM PDT 24	55162623 ps
T61	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2340150367	Apr 21 12:57:01 PM PDT 24	Apr 21 12:57:04 PM PDT 24	296077175 ps
T69	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2150118251	Apr 21 12:56:50 PM PDT 24	Apr 21 12:56:51 PM PDT 24	21032341 ps
T135	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2621912718	Apr 21 12:57:04 PM PDT 24	Apr 21 12:57:05 PM PDT 24	39438854 ps
T136	/workspace/coverage/cover_reg_top/13.i2c_intr_test.1441847689	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:04 PM PDT 24	32039938 ps
T137	/workspace/coverage/cover_reg_top/14.i2c_intr_test.1696117431	Apr 21 12:57:10 PM PDT 24	Apr 21 12:57:11 PM PDT 24	131463059 ps
T138	/workspace/coverage/cover_reg_top/27.i2c_intr_test.1176840441	Apr 21 12:57:19 PM PDT 24	Apr 21 12:57:20 PM PDT 24	38782849 ps
T139	/workspace/coverage/cover_reg_top/23.i2c_intr_test.1018953137	Apr 21 12:57:19 PM PDT 24	Apr 21 12:57:20 PM PDT 24	48413845 ps
T140	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2785203740	Apr 21 12:57:17 PM PDT 24	Apr 21 12:57:18 PM PDT 24	33841642 ps
T141	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1747303465	Apr 21 12:56:59 PM PDT 24	Apr 21 12:57:00 PM PDT 24	271675957 ps
T142	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1324580599	Apr 21 12:57:13 PM PDT 24	Apr 21 12:57:15 PM PDT 24	301110820 ps
T143	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1709226144	Apr 21 12:56:50 PM PDT 24	Apr 21 12:56:52 PM PDT 24	327084008 ps
T144	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1908081100	Apr 21 12:57:06 PM PDT 24	Apr 21 12:57:09 PM PDT 24	504380016 ps
T145	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1368915249	Apr 21 12:57:03 PM PDT 24	Apr 21 12:57:04 PM PDT 24	123879716 ps
T146	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.738636760	Apr 21 12:57:04 PM PDT 24	Apr 21 12:57:05 PM PDT 24	30626141 ps

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1225875674
Short name	T2
Test name
Test status
Simulation time	759737561 ps
CPU time	2.44 seconds
Started	Apr 21 12:56:59 PM PDT 24
Finished	Apr 21 12:57:02 PM PDT 24
Peak memory	203684 kb
Host	smart-ba6f7050-a955-4e8e-b2e3-83e6efce2e1c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225875674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1225875674
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.i2c_intr_test.725058562
Short name	T6
Test name
Test status
Simulation time	39320370 ps
CPU time	0.72 seconds
Started	Apr 21 12:57:17 PM PDT 24
Finished	Apr 21 12:57:18 PM PDT 24
Peak memory	203404 kb
Host	smart-3e2f9734-f230-4f82-ac4b-acaa94aa4e6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725058562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.725058562
Directory	/workspace/30.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.384141053
Short name	T11
Test name
Test status
Simulation time	262133196 ps
CPU time	2.75 seconds
Started	Apr 21 12:56:53 PM PDT 24
Finished	Apr 21 12:56:56 PM PDT 24
Peak memory	203732 kb
Host	smart-17d89978-5647-4226-b66d-5d3e4f96c570
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384141053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.384141053
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1338937058
Short name	T28
Test name
Test status
Simulation time	18588024 ps
CPU time	0.66 seconds
Started	Apr 21 12:56:50 PM PDT 24
Finished	Apr 21 12:56:52 PM PDT 24
Peak memory	203412 kb
Host	smart-d30402e6-7433-44af-824c-14fa582b3f0e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338937058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1338937058
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.625426486
Short name	T58
Test name
Test status
Simulation time	24020783 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:22 PM PDT 24
Finished	Apr 21 12:57:23 PM PDT 24
Peak memory	203324 kb
Host	smart-ff87f2f6-77e4-42d7-a3b2-b24a13ea2b7e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625426486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.625426486
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.396067747
Short name	T25
Test name
Test status
Simulation time	45366235 ps
CPU time	1.15 seconds
Started	Apr 21 12:56:58 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203744 kb
Host	smart-637eb050-9071-4cd0-a38b-47793c22b11c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396067747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out standing.396067747
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.125820389
Short name	T57
Test name
Test status
Simulation time	28193512 ps
CPU time	0.67 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203380 kb
Host	smart-65fcbc74-568e-438a-860b-e02c6f7562eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125820389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.125820389
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.3903359872
Short name	T43
Test name
Test status
Simulation time	29548450 ps
CPU time	0.77 seconds
Started	Apr 21 12:57:11 PM PDT 24
Finished	Apr 21 12:57:12 PM PDT 24
Peak memory	203480 kb
Host	smart-ab0aa501-79cc-488f-8275-27ceeb035cd5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903359872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3903359872
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2829159696
Short name	T5
Test name
Test status
Simulation time	130609944 ps
CPU time	2.35 seconds
Started	Apr 21 12:57:07 PM PDT 24
Finished	Apr 21 12:57:10 PM PDT 24
Peak memory	203780 kb
Host	smart-f8580f41-1fb2-4dc4-b2a2-81df3d91fc95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829159696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2829159696
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_intr_test.1840417594
Short name	T7
Test name
Test status
Simulation time	30223712 ps
CPU time	0.66 seconds
Started	Apr 21 12:57:04 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203268 kb
Host	smart-2130edf3-3604-4722-8dae-bfbc6107e4d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840417594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1840417594
Directory	/workspace/12.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2715420415
Short name	T18
Test name
Test status
Simulation time	85647054 ps
CPU time	1.81 seconds
Started	Apr 21 12:56:51 PM PDT 24
Finished	Apr 21 12:56:53 PM PDT 24
Peak memory	203756 kb
Host	smart-94216051-663a-4fe3-b9b8-9fdd9531037e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715420415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2715420415
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.599288693
Short name	T31
Test name
Test status
Simulation time	20734445 ps
CPU time	0.77 seconds
Started	Apr 21 12:56:52 PM PDT 24
Finished	Apr 21 12:56:53 PM PDT 24
Peak memory	203488 kb
Host	smart-ca51b1e1-58c8-48ce-ad2a-b9b4ec106c75
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599288693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.599288693
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.3393340417
Short name	T122
Test name
Test status
Simulation time	37383413 ps
CPU time	0.67 seconds
Started	Apr 21 12:57:11 PM PDT 24
Finished	Apr 21 12:57:12 PM PDT 24
Peak memory	203348 kb
Host	smart-902589f0-8867-4e71-ae8a-079db7bf28f2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393340417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3393340417
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2027472444
Short name	T24
Test name
Test status
Simulation time	52371930 ps
CPU time	1.12 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203728 kb
Host	smart-2d9d4718-2dbf-4480-9158-61c26e3bf02e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027472444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.2027472444
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2290881813
Short name	T19
Test name
Test status
Simulation time	124522234 ps
CPU time	2.39 seconds
Started	Apr 21 12:57:02 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203752 kb
Host	smart-69d56062-a696-4b47-9f97-df5805558518
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290881813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2290881813
Directory	/workspace/9.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2150118251
Short name	T69
Test name
Test status
Simulation time	21032341 ps
CPU time	0.74 seconds
Started	Apr 21 12:56:50 PM PDT 24
Finished	Apr 21 12:56:51 PM PDT 24
Peak memory	203344 kb
Host	smart-640a6317-d049-4af0-ad8f-42a48e98fe28
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150118251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2150118251
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4210386098
Short name	T73
Test name
Test status
Simulation time	164211555 ps
CPU time	2.13 seconds
Started	Apr 21 12:56:50 PM PDT 24
Finished	Apr 21 12:56:53 PM PDT 24
Peak memory	203780 kb
Host	smart-bc1cbceb-339c-404e-80e4-1a922882faa9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210386098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.4210386098
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.1696117431
Short name	T137
Test name
Test status
Simulation time	131463059 ps
CPU time	0.64 seconds
Started	Apr 21 12:57:10 PM PDT 24
Finished	Apr 21 12:57:11 PM PDT 24
Peak memory	203340 kb
Host	smart-ad47c42f-3e49-401c-a8dc-781ba9435b5e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696117431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1696117431
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.660360009
Short name	T99
Test name
Test status
Simulation time	62282727 ps
CPU time	1.32 seconds
Started	Apr 21 12:56:51 PM PDT 24
Finished	Apr 21 12:56:53 PM PDT 24
Peak memory	203416 kb
Host	smart-396fa683-3262-4fcc-9428-b8983673f282
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660360009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.660360009
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.233449966
Short name	T93
Test name
Test status
Simulation time	84368340 ps
CPU time	2.96 seconds
Started	Apr 21 12:56:58 PM PDT 24
Finished	Apr 21 12:57:01 PM PDT 24
Peak memory	203604 kb
Host	smart-3b1e3a3a-d50f-42c6-954d-f4f489612029
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233449966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.233449966
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1709226144
Short name	T143
Test name
Test status
Simulation time	327084008 ps
CPU time	0.79 seconds
Started	Apr 21 12:56:50 PM PDT 24
Finished	Apr 21 12:56:52 PM PDT 24
Peak memory	203504 kb
Host	smart-ccb274ba-8dc8-40f0-b6c6-8b8f0ec876c3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709226144 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1709226144
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1368491160
Short name	T30
Test name
Test status
Simulation time	30084513 ps
CPU time	0.76 seconds
Started	Apr 21 12:56:53 PM PDT 24
Finished	Apr 21 12:56:54 PM PDT 24
Peak memory	203484 kb
Host	smart-8acb4869-2b45-479e-97a9-01bc32ca0937
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368491160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1368491160
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.2904558132
Short name	T34
Test name
Test status
Simulation time	15293184 ps
CPU time	0.67 seconds
Started	Apr 21 12:56:54 PM PDT 24
Finished	Apr 21 12:56:55 PM PDT 24
Peak memory	203424 kb
Host	smart-ca92a981-01bf-4c07-b9f9-b83c5d3b4080
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904558132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2904558132
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3264399446
Short name	T48
Test name
Test status
Simulation time	568042687 ps
CPU time	2.62 seconds
Started	Apr 21 12:56:53 PM PDT 24
Finished	Apr 21 12:56:56 PM PDT 24
Peak memory	203772 kb
Host	smart-e524d406-4713-4590-b78a-b69bafc0f4a8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264399446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3264399446
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.250407630
Short name	T86
Test name
Test status
Simulation time	30868989 ps
CPU time	1.22 seconds
Started	Apr 21 12:56:53 PM PDT 24
Finished	Apr 21 12:56:55 PM PDT 24
Peak memory	203828 kb
Host	smart-4fa5b211-c960-4843-ae10-0af5d7affbb3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250407630 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.250407630
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1684186581
Short name	T132
Test name
Test status
Simulation time	68883326 ps
CPU time	0.75 seconds
Started	Apr 21 12:56:51 PM PDT 24
Finished	Apr 21 12:56:52 PM PDT 24
Peak memory	203452 kb
Host	smart-9e63ce17-e3ca-4a50-8063-d35769a00cef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684186581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1684186581
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.620113041
Short name	T36
Test name
Test status
Simulation time	31222033 ps
CPU time	0.62 seconds
Started	Apr 21 12:56:51 PM PDT 24
Finished	Apr 21 12:56:52 PM PDT 24
Peak memory	203416 kb
Host	smart-e7376628-ce50-4f14-9071-e7f99a6e1a3f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620113041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.620113041
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3238071499
Short name	T108
Test name
Test status
Simulation time	65780134 ps
CPU time	0.83 seconds
Started	Apr 21 12:57:00 PM PDT 24
Finished	Apr 21 12:57:01 PM PDT 24
Peak memory	203476 kb
Host	smart-23ef4d73-08a5-4a6f-b623-35d14f5eeccf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238071499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.3238071499
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3914040324
Short name	T68
Test name
Test status
Simulation time	351572272 ps
CPU time	1.8 seconds
Started	Apr 21 12:56:49 PM PDT 24
Finished	Apr 21 12:56:52 PM PDT 24
Peak memory	203792 kb
Host	smart-22963653-4b6a-49e6-a4b5-0e98caf25432
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914040324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3914040324
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.505726380
Short name	T96
Test name
Test status
Simulation time	35820653 ps
CPU time	0.96 seconds
Started	Apr 21 12:57:09 PM PDT 24
Finished	Apr 21 12:57:10 PM PDT 24
Peak memory	203552 kb
Host	smart-639c1d74-9cc1-492d-88c3-3a31bafcca0c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505726380 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.505726380
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2020292420
Short name	T8
Test name
Test status
Simulation time	51071027 ps
CPU time	0.74 seconds
Started	Apr 21 12:57:05 PM PDT 24
Finished	Apr 21 12:57:06 PM PDT 24
Peak memory	203320 kb
Host	smart-9efa4e84-53d6-43b8-a7dd-3d6f7315df98
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020292420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2020292420
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1041293638
Short name	T94
Test name
Test status
Simulation time	194367915 ps
CPU time	0.68 seconds
Started	Apr 21 12:57:08 PM PDT 24
Finished	Apr 21 12:57:09 PM PDT 24
Peak memory	203292 kb
Host	smart-1cb09ba1-f1e5-40f4-87ae-2060c2e2a186
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041293638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1041293638
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1908081100
Short name	T144
Test name
Test status
Simulation time	504380016 ps
CPU time	2.44 seconds
Started	Apr 21 12:57:06 PM PDT 24
Finished	Apr 21 12:57:09 PM PDT 24
Peak memory	203716 kb
Host	smart-71eae144-fa49-4ccf-a3df-7846d1716e17
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908081100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1908081100
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2919653915
Short name	T65
Test name
Test status
Simulation time	92729909 ps
CPU time	0.8 seconds
Started	Apr 21 12:57:08 PM PDT 24
Finished	Apr 21 12:57:09 PM PDT 24
Peak memory	203484 kb
Host	smart-316ec11e-7cad-4206-a52a-0378c2237406
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919653915 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2919653915
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3662882498
Short name	T59
Test name
Test status
Simulation time	22843943 ps
CPU time	0.71 seconds
Started	Apr 21 12:57:04 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203460 kb
Host	smart-20bd0882-f938-4e00-95ea-64a231ca6ea4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662882498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3662882498
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1729227421
Short name	T123
Test name
Test status
Simulation time	32154050 ps
CPU time	0.75 seconds
Started	Apr 21 12:57:10 PM PDT 24
Finished	Apr 21 12:57:11 PM PDT 24
Peak memory	203384 kb
Host	smart-73d4173f-f35d-4b6e-be92-61183a3031d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729227421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1729227421
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.169678858
Short name	T129
Test name
Test status
Simulation time	80044953 ps
CPU time	1.18 seconds
Started	Apr 21 12:57:05 PM PDT 24
Finished	Apr 21 12:57:07 PM PDT 24
Peak memory	203696 kb
Host	smart-ea32fb85-d6e9-4eeb-aaa3-b255ca74da6a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169678858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou tstanding.169678858
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2482063359
Short name	T17
Test name
Test status
Simulation time	132126715 ps
CPU time	1.32 seconds
Started	Apr 21 12:57:06 PM PDT 24
Finished	Apr 21 12:57:07 PM PDT 24
Peak memory	203724 kb
Host	smart-d4d5ed17-90f3-448f-8ebe-d2b39c7ff02e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482063359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2482063359
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1265982127
Short name	T62
Test name
Test status
Simulation time	151998397 ps
CPU time	2.43 seconds
Started	Apr 21 12:57:06 PM PDT 24
Finished	Apr 21 12:57:09 PM PDT 24
Peak memory	203680 kb
Host	smart-b21f6078-658c-4f3b-9081-f62c18a8a60e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265982127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1265982127
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1314006827
Short name	T87
Test name
Test status
Simulation time	26780303 ps
CPU time	1.15 seconds
Started	Apr 21 12:57:05 PM PDT 24
Finished	Apr 21 12:57:07 PM PDT 24
Peak memory	203612 kb
Host	smart-52a452a2-6150-45f7-a1c6-8996b829e7ae
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314006827 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1314006827
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3317880124
Short name	T128
Test name
Test status
Simulation time	77165432 ps
CPU time	0.76 seconds
Started	Apr 21 12:57:07 PM PDT 24
Finished	Apr 21 12:57:08 PM PDT 24
Peak memory	203276 kb
Host	smart-c5e2dcf0-0769-492e-b5e7-4bf780192563
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317880124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3317880124
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2534523412
Short name	T107
Test name
Test status
Simulation time	35489656 ps
CPU time	1.01 seconds
Started	Apr 21 12:57:12 PM PDT 24
Finished	Apr 21 12:57:13 PM PDT 24
Peak memory	203420 kb
Host	smart-702f0e87-6867-4a2a-9098-5b593af58348
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534523412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.2534523412
Directory	/workspace/12.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.3215484011
Short name	T16
Test name
Test status
Simulation time	92617876 ps
CPU time	1.92 seconds
Started	Apr 21 12:57:11 PM PDT 24
Finished	Apr 21 12:57:13 PM PDT 24
Peak memory	203716 kb
Host	smart-12d35a58-3678-4573-a855-6864608b1476
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215484011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3215484011
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1641420113
Short name	T102
Test name
Test status
Simulation time	81506070 ps
CPU time	1.24 seconds
Started	Apr 21 12:57:07 PM PDT 24
Finished	Apr 21 12:57:09 PM PDT 24
Peak memory	203848 kb
Host	smart-46af9afc-fa5e-480a-9512-6579e66fa62b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641420113 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1641420113
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.1441847689
Short name	T136
Test name
Test status
Simulation time	32039938 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203384 kb
Host	smart-5052bcd5-30a9-4ec0-bf58-6aa81ef56552
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441847689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1441847689
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1334995531
Short name	T105
Test name
Test status
Simulation time	57356149 ps
CPU time	1.24 seconds
Started	Apr 21 12:57:06 PM PDT 24
Finished	Apr 21 12:57:07 PM PDT 24
Peak memory	203644 kb
Host	smart-2f35c8e1-48b1-4b40-9129-26c3ecd5a157
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334995531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.1334995531
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.1524164391
Short name	T81
Test name
Test status
Simulation time	249163389 ps
CPU time	2.28 seconds
Started	Apr 21 12:57:06 PM PDT 24
Finished	Apr 21 12:57:09 PM PDT 24
Peak memory	203772 kb
Host	smart-ff3dd25b-38d4-4811-9fc2-32ac50090c99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524164391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1524164391
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2162187574
Short name	T103
Test name
Test status
Simulation time	98244269 ps
CPU time	1.44 seconds
Started	Apr 21 12:57:13 PM PDT 24
Finished	Apr 21 12:57:15 PM PDT 24
Peak memory	211940 kb
Host	smart-9de6e50f-7193-4a42-aa02-3ba92c1bbc9d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162187574 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2162187574
Directory	/workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1101585045
Short name	T47
Test name
Test status
Simulation time	49405545 ps
CPU time	0.68 seconds
Started	Apr 21 12:57:07 PM PDT 24
Finished	Apr 21 12:57:08 PM PDT 24
Peak memory	203352 kb
Host	smart-3377fb64-74cc-4c4e-b580-b39a09813102
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101585045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1101585045
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2610367778
Short name	T112
Test name
Test status
Simulation time	305245999 ps
CPU time	0.94 seconds
Started	Apr 21 12:57:12 PM PDT 24
Finished	Apr 21 12:57:13 PM PDT 24
Peak memory	203544 kb
Host	smart-31fca5f3-1b78-4c3a-a4e2-f03d6be3f2e2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610367778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.2610367778
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.4002216771
Short name	T67
Test name
Test status
Simulation time	86306453 ps
CPU time	1.75 seconds
Started	Apr 21 12:57:08 PM PDT 24
Finished	Apr 21 12:57:10 PM PDT 24
Peak memory	203788 kb
Host	smart-7e900143-2a40-481d-96ca-67a238d05c44
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002216771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.4002216771
Directory	/workspace/14.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1325987353
Short name	T22
Test name
Test status
Simulation time	96837143 ps
CPU time	2.24 seconds
Started	Apr 21 12:57:08 PM PDT 24
Finished	Apr 21 12:57:10 PM PDT 24
Peak memory	203788 kb
Host	smart-b2aabbfd-b52d-4194-abdd-577c69640e4e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325987353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1325987353
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3555367582
Short name	T109
Test name
Test status
Simulation time	27777719 ps
CPU time	0.85 seconds
Started	Apr 21 12:57:12 PM PDT 24
Finished	Apr 21 12:57:13 PM PDT 24
Peak memory	203596 kb
Host	smart-d1bd2537-097b-41d1-bb33-809013c04eb8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555367582 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3555367582
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1127805530
Short name	T44
Test name
Test status
Simulation time	25179298 ps
CPU time	0.68 seconds
Started	Apr 21 12:57:13 PM PDT 24
Finished	Apr 21 12:57:14 PM PDT 24
Peak memory	203380 kb
Host	smart-57d26a5a-9721-4e89-892e-aff2fb5b4ca0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127805530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1127805530
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.352644856
Short name	T15
Test name
Test status
Simulation time	23215395 ps
CPU time	1.01 seconds
Started	Apr 21 12:57:13 PM PDT 24
Finished	Apr 21 12:57:14 PM PDT 24
Peak memory	202764 kb
Host	smart-cf56b7ce-00cf-44d9-bc16-96a66039f0d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352644856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.352644856
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.845439146
Short name	T113
Test name
Test status
Simulation time	81287484 ps
CPU time	1.21 seconds
Started	Apr 21 12:57:12 PM PDT 24
Finished	Apr 21 12:57:13 PM PDT 24
Peak memory	203800 kb
Host	smart-0248cfec-c1a9-41a5-8bb9-f3131bf0cd9c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845439146 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.845439146
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.919114456
Short name	T39
Test name
Test status
Simulation time	29126278 ps
CPU time	0.87 seconds
Started	Apr 21 12:57:13 PM PDT 24
Finished	Apr 21 12:57:14 PM PDT 24
Peak memory	203420 kb
Host	smart-5e2cf83d-e710-4f55-8b92-10f6371313f3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919114456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.919114456
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2564583048
Short name	T101
Test name
Test status
Simulation time	183532298 ps
CPU time	2.39 seconds
Started	Apr 21 12:57:14 PM PDT 24
Finished	Apr 21 12:57:16 PM PDT 24
Peak memory	203724 kb
Host	smart-e82ef195-ea3f-47c1-aab0-a862c04863ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564583048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2564583048
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1525227468
Short name	T111
Test name
Test status
Simulation time	39484721 ps
CPU time	0.98 seconds
Started	Apr 21 12:57:14 PM PDT 24
Finished	Apr 21 12:57:15 PM PDT 24
Peak memory	203524 kb
Host	smart-f4a8f3c2-5121-4480-a326-8ab1dd83e1b0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525227468 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1525227468
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.901798240
Short name	T45
Test name
Test status
Simulation time	47880651 ps
CPU time	0.64 seconds
Started	Apr 21 12:57:12 PM PDT 24
Finished	Apr 21 12:57:13 PM PDT 24
Peak memory	203360 kb
Host	smart-5dfe4a57-f1e8-43a2-b7c3-2472e00c529e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901798240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.901798240
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2592926965
Short name	T125
Test name
Test status
Simulation time	15394039 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:18 PM PDT 24
Finished	Apr 21 12:57:19 PM PDT 24
Peak memory	203204 kb
Host	smart-4b97c10d-ede6-463d-8eae-4bb225d0aa66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592926965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2592926965
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2354671929
Short name	T127
Test name
Test status
Simulation time	495591121 ps
CPU time	2.59 seconds
Started	Apr 21 12:57:11 PM PDT 24
Finished	Apr 21 12:57:14 PM PDT 24
Peak memory	203732 kb
Host	smart-650c85d0-a476-452d-9791-c6e11863826b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354671929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2354671929
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1324580599
Short name	T142
Test name
Test status
Simulation time	301110820 ps
CPU time	2.13 seconds
Started	Apr 21 12:57:13 PM PDT 24
Finished	Apr 21 12:57:15 PM PDT 24
Peak memory	202968 kb
Host	smart-bca6580a-3467-48ed-ac15-a0acbbb7af54
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324580599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1324580599
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1170582390
Short name	T121
Test name
Test status
Simulation time	51032498 ps
CPU time	1.27 seconds
Started	Apr 21 12:57:16 PM PDT 24
Finished	Apr 21 12:57:18 PM PDT 24
Peak memory	203840 kb
Host	smart-e127ecd3-03ed-46db-92a2-aed511772c00
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170582390 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1170582390
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1467537449
Short name	T41
Test name
Test status
Simulation time	37490265 ps
CPU time	0.68 seconds
Started	Apr 21 12:57:13 PM PDT 24
Finished	Apr 21 12:57:14 PM PDT 24
Peak memory	203292 kb
Host	smart-5485db84-dabd-421e-ae27-d641d3b45319
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467537449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1467537449
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.3897990690
Short name	T55
Test name
Test status
Simulation time	34608965 ps
CPU time	0.67 seconds
Started	Apr 21 12:57:17 PM PDT 24
Finished	Apr 21 12:57:18 PM PDT 24
Peak memory	203380 kb
Host	smart-e7f8ba6e-92c1-4e60-8a44-119211e2cfd0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897990690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3897990690
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1200725619
Short name	T124
Test name
Test status
Simulation time	20432318 ps
CPU time	0.9 seconds
Started	Apr 21 12:57:14 PM PDT 24
Finished	Apr 21 12:57:15 PM PDT 24
Peak memory	203472 kb
Host	smart-24af4348-26b1-4f9d-b82a-1715fc0b631f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200725619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.1200725619
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2785203740
Short name	T140
Test name
Test status
Simulation time	33841642 ps
CPU time	1.55 seconds
Started	Apr 21 12:57:17 PM PDT 24
Finished	Apr 21 12:57:18 PM PDT 24
Peak memory	203720 kb
Host	smart-22583d93-1eef-4df7-bb0d-00fc8b53970b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785203740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2785203740
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2936869276
Short name	T85
Test name
Test status
Simulation time	145623748 ps
CPU time	2.31 seconds
Started	Apr 21 12:57:14 PM PDT 24
Finished	Apr 21 12:57:17 PM PDT 24
Peak memory	203752 kb
Host	smart-909a3676-3dcd-455b-abd8-0951ec2cbcfa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936869276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2936869276
Directory	/workspace/18.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.505766746
Short name	T117
Test name
Test status
Simulation time	35267633 ps
CPU time	0.89 seconds
Started	Apr 21 12:57:17 PM PDT 24
Finished	Apr 21 12:57:18 PM PDT 24
Peak memory	203620 kb
Host	smart-2b2988b5-4490-4371-a145-7d206063321a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505766746 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.505766746
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2970801559
Short name	T42
Test name
Test status
Simulation time	46834835 ps
CPU time	0.76 seconds
Started	Apr 21 12:57:16 PM PDT 24
Finished	Apr 21 12:57:17 PM PDT 24
Peak memory	203388 kb
Host	smart-c81a80cd-43b9-4b2a-9ee2-487e2b2a4d5e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970801559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2970801559
Directory	/workspace/19.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.2156312597
Short name	T120
Test name
Test status
Simulation time	15595056 ps
CPU time	0.67 seconds
Started	Apr 21 12:57:15 PM PDT 24
Finished	Apr 21 12:57:16 PM PDT 24
Peak memory	203404 kb
Host	smart-e5871080-c805-4db1-841d-9f4c0c7cd8e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156312597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2156312597
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1638056779
Short name	T20
Test name
Test status
Simulation time	25099538 ps
CPU time	0.95 seconds
Started	Apr 21 12:57:17 PM PDT 24
Finished	Apr 21 12:57:18 PM PDT 24
Peak memory	203484 kb
Host	smart-e9827232-5fca-4b21-b34b-a8e34b1afcbb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638056779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.1638056779
Directory	/workspace/19.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3960091773
Short name	T77
Test name
Test status
Simulation time	31618786 ps
CPU time	1.51 seconds
Started	Apr 21 12:57:18 PM PDT 24
Finished	Apr 21 12:57:20 PM PDT 24
Peak memory	203536 kb
Host	smart-945b2dc7-fe0b-4fec-80c1-34475de31570
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960091773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3960091773
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3469132754
Short name	T100
Test name
Test status
Simulation time	261930689 ps
CPU time	1.4 seconds
Started	Apr 21 12:56:55 PM PDT 24
Finished	Apr 21 12:56:57 PM PDT 24
Peak memory	203584 kb
Host	smart-a6169500-0286-4995-9d1f-ac81235ea00f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469132754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3469132754
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1354103482
Short name	T26
Test name
Test status
Simulation time	77755790 ps
CPU time	2.93 seconds
Started	Apr 21 12:57:00 PM PDT 24
Finished	Apr 21 12:57:03 PM PDT 24
Peak memory	203824 kb
Host	smart-988eddeb-7460-40ab-a98c-269cc03aa0ea
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354103482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1354103482
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1731182292
Short name	T4
Test name
Test status
Simulation time	107762389 ps
CPU time	0.91 seconds
Started	Apr 21 12:56:58 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203652 kb
Host	smart-80e6b04d-d7c5-401d-b940-7e0e61fc2b35
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731182292 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1731182292
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2133571075
Short name	T97
Test name
Test status
Simulation time	16048731 ps
CPU time	0.68 seconds
Started	Apr 21 12:56:54 PM PDT 24
Finished	Apr 21 12:56:55 PM PDT 24
Peak memory	203496 kb
Host	smart-e9207802-0591-4ac0-843a-c9fc40e86ec1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133571075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2133571075
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.3501327861
Short name	T53
Test name
Test status
Simulation time	65502987 ps
CPU time	0.64 seconds
Started	Apr 21 12:57:00 PM PDT 24
Finished	Apr 21 12:57:01 PM PDT 24
Peak memory	203360 kb
Host	smart-88c8eb3a-0574-4bbc-8458-395a1a9a8a70
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501327861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3501327861
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.246650746
Short name	T106
Test name
Test status
Simulation time	164413127 ps
CPU time	1.12 seconds
Started	Apr 21 12:56:54 PM PDT 24
Finished	Apr 21 12:56:55 PM PDT 24
Peak memory	203756 kb
Host	smart-24626920-5196-42b6-a457-b60915710f23
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246650746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out standing.246650746
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3256605119
Short name	T12
Test name
Test status
Simulation time	30820514 ps
CPU time	1.48 seconds
Started	Apr 21 12:56:54 PM PDT 24
Finished	Apr 21 12:56:56 PM PDT 24
Peak memory	203756 kb
Host	smart-1016503f-c34a-4fb0-96af-305b85c1d48f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256605119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3256605119
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3791427501
Short name	T119
Test name
Test status
Simulation time	44081235 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:18 PM PDT 24
Finished	Apr 21 12:57:20 PM PDT 24
Peak memory	203368 kb
Host	smart-768567ac-c287-4576-96ca-18b86289ba4d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791427501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3791427501
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3112267293
Short name	T83
Test name
Test status
Simulation time	43521059 ps
CPU time	0.65 seconds
Started	Apr 21 12:57:18 PM PDT 24
Finished	Apr 21 12:57:19 PM PDT 24
Peak memory	203404 kb
Host	smart-d377713c-10f0-452a-ae39-ba249ce04833
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112267293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3112267293
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.738525650
Short name	T46
Test name
Test status
Simulation time	44313452 ps
CPU time	0.63 seconds
Started	Apr 21 12:57:15 PM PDT 24
Finished	Apr 21 12:57:16 PM PDT 24
Peak memory	203392 kb
Host	smart-4e68a8d4-1567-4201-a76b-80b6957ae7dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738525650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.738525650
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.1018953137
Short name	T139
Test name
Test status
Simulation time	48413845 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:19 PM PDT 24
Finished	Apr 21 12:57:20 PM PDT 24
Peak memory	203368 kb
Host	smart-6a7688de-3049-4185-907c-9d8776e2aa2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018953137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1018953137
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.1100335139
Short name	T49
Test name
Test status
Simulation time	17917777 ps
CPU time	0.66 seconds
Started	Apr 21 12:57:18 PM PDT 24
Finished	Apr 21 12:57:19 PM PDT 24
Peak memory	203356 kb
Host	smart-b41e1bd8-3c29-419f-ac2c-3d4ffa9b6ee0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100335139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1100335139
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.4013895250
Short name	T104
Test name
Test status
Simulation time	18563800 ps
CPU time	0.65 seconds
Started	Apr 21 12:57:20 PM PDT 24
Finished	Apr 21 12:57:21 PM PDT 24
Peak memory	203328 kb
Host	smart-8c936046-1ff1-4e82-8ea6-52ef598a8993
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013895250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.4013895250
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.2938684418
Short name	T33
Test name
Test status
Simulation time	46001952 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:19 PM PDT 24
Finished	Apr 21 12:57:21 PM PDT 24
Peak memory	203376 kb
Host	smart-75882728-30b2-470a-8fe4-c56b94156f57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938684418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2938684418
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.1176840441
Short name	T138
Test name
Test status
Simulation time	38782849 ps
CPU time	0.64 seconds
Started	Apr 21 12:57:19 PM PDT 24
Finished	Apr 21 12:57:20 PM PDT 24
Peak memory	203396 kb
Host	smart-9d1a0caf-11da-4f2d-aac9-d78040e200be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176840441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1176840441
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.2473713738
Short name	T9
Test name
Test status
Simulation time	32958331 ps
CPU time	0.71 seconds
Started	Apr 21 12:57:23 PM PDT 24
Finished	Apr 21 12:57:24 PM PDT 24
Peak memory	203360 kb
Host	smart-4c1e9e1f-680d-4e89-b3c6-82fa761b8063
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473713738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2473713738
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3388263901
Short name	T70
Test name
Test status
Simulation time	20360961 ps
CPU time	0.77 seconds
Started	Apr 21 12:56:59 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203492 kb
Host	smart-0b49ac36-3547-4c18-a02c-39f2b0ec4269
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388263901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3388263901
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3784054888
Short name	T37
Test name
Test status
Simulation time	98701670 ps
CPU time	0.95 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:02 PM PDT 24
Peak memory	203600 kb
Host	smart-6848dd75-0992-4fe3-9d5e-a1cd7c8e4cd9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784054888 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3784054888
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3414479041
Short name	T80
Test name
Test status
Simulation time	49098993 ps
CPU time	0.67 seconds
Started	Apr 21 12:56:59 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203464 kb
Host	smart-09d2e1e9-e797-4894-80c8-b84d84653225
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414479041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3414479041
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_intr_test.1748939398
Short name	T131
Test name
Test status
Simulation time	41731619 ps
CPU time	0.62 seconds
Started	Apr 21 12:56:54 PM PDT 24
Finished	Apr 21 12:56:55 PM PDT 24
Peak memory	203388 kb
Host	smart-34809059-374a-465e-b422-536a342c36d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748939398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1748939398
Directory	/workspace/3.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.688910364
Short name	T71
Test name
Test status
Simulation time	132220472 ps
CPU time	2.39 seconds
Started	Apr 21 12:57:00 PM PDT 24
Finished	Apr 21 12:57:03 PM PDT 24
Peak memory	203720 kb
Host	smart-24ae95f6-c069-48b7-88f2-0d5e7ffa2747
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688910364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.688910364
Directory	/workspace/3.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1145444578
Short name	T95
Test name
Test status
Simulation time	18621877 ps
CPU time	0.72 seconds
Started	Apr 21 12:57:19 PM PDT 24
Finished	Apr 21 12:57:20 PM PDT 24
Peak memory	203200 kb
Host	smart-646bb244-4090-45fe-bcbf-f03dc4d74ac3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145444578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1145444578
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.276245278
Short name	T52
Test name
Test status
Simulation time	37773715 ps
CPU time	0.7 seconds
Started	Apr 21 12:57:21 PM PDT 24
Finished	Apr 21 12:57:22 PM PDT 24
Peak memory	203360 kb
Host	smart-877c5f98-e3d6-48af-bf9b-b2a537e107b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276245278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.276245278
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1370862002
Short name	T56
Test name
Test status
Simulation time	25596970 ps
CPU time	0.61 seconds
Started	Apr 21 12:57:21 PM PDT 24
Finished	Apr 21 12:57:22 PM PDT 24
Peak memory	203248 kb
Host	smart-11ee31a8-6618-4b22-b1dc-359daa1c1de5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370862002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1370862002
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.495842910
Short name	T84
Test name
Test status
Simulation time	33217517 ps
CPU time	0.66 seconds
Started	Apr 21 12:57:21 PM PDT 24
Finished	Apr 21 12:57:23 PM PDT 24
Peak memory	203408 kb
Host	smart-c14aac0c-7718-46a2-9787-f0dd7dcd139b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495842910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.495842910
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.324091224
Short name	T88
Test name
Test status
Simulation time	40256462 ps
CPU time	0.73 seconds
Started	Apr 21 12:57:20 PM PDT 24
Finished	Apr 21 12:57:21 PM PDT 24
Peak memory	203360 kb
Host	smart-28ba2761-210a-4a86-9f06-7fddf42a63a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324091224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.324091224
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2965709673
Short name	T116
Test name
Test status
Simulation time	59997676 ps
CPU time	0.63 seconds
Started	Apr 21 12:57:19 PM PDT 24
Finished	Apr 21 12:57:20 PM PDT 24
Peak memory	203380 kb
Host	smart-74e49b7d-c793-47c3-bd05-19d40139c4ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965709673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2965709673
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.2793680063
Short name	T114
Test name
Test status
Simulation time	34486953 ps
CPU time	0.67 seconds
Started	Apr 21 12:57:22 PM PDT 24
Finished	Apr 21 12:57:23 PM PDT 24
Peak memory	203372 kb
Host	smart-fde37cab-60e7-472d-81bc-39f20d47bd65
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793680063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2793680063
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.i2c_intr_test.2094832311
Short name	T35
Test name
Test status
Simulation time	41350040 ps
CPU time	0.66 seconds
Started	Apr 21 12:57:21 PM PDT 24
Finished	Apr 21 12:57:22 PM PDT 24
Peak memory	203416 kb
Host	smart-86522bd9-5df6-4430-9579-8197e118fc89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094832311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2094832311
Directory	/workspace/38.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1887349422
Short name	T75
Test name
Test status
Simulation time	15034658 ps
CPU time	0.67 seconds
Started	Apr 21 12:57:23 PM PDT 24
Finished	Apr 21 12:57:24 PM PDT 24
Peak memory	203356 kb
Host	smart-3f67a7a3-28ca-41da-81d9-4c39bb40b85d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887349422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1887349422
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3183300340
Short name	T23
Test name
Test status
Simulation time	63046739 ps
CPU time	1.33 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203576 kb
Host	smart-54d966fb-de9a-4da2-b3dc-864b0954a921
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183300340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3183300340
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.824700698
Short name	T27
Test name
Test status
Simulation time	33824621 ps
CPU time	0.66 seconds
Started	Apr 21 12:56:56 PM PDT 24
Finished	Apr 21 12:56:57 PM PDT 24
Peak memory	203380 kb
Host	smart-caf7e77f-8133-4ca7-b517-a04b9b736d42
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824700698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.824700698
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2393440389
Short name	T13
Test name
Test status
Simulation time	53096054 ps
CPU time	1 seconds
Started	Apr 21 12:56:57 PM PDT 24
Finished	Apr 21 12:56:59 PM PDT 24
Peak memory	203488 kb
Host	smart-30514e03-29c4-4268-8e07-d1f74945d941
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393440389 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2393440389
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.303813987
Short name	T54
Test name
Test status
Simulation time	68104723 ps
CPU time	0.71 seconds
Started	Apr 21 12:56:59 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203464 kb
Host	smart-5d86e990-215f-4531-8021-67ad16d01a21
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303813987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.303813987
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.1010636802
Short name	T118
Test name
Test status
Simulation time	19227058 ps
CPU time	0.7 seconds
Started	Apr 21 12:56:59 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203396 kb
Host	smart-f2439575-cbfc-462d-b3d9-de07a27de3c1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010636802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1010636802
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1747303465
Short name	T141
Test name
Test status
Simulation time	271675957 ps
CPU time	1.19 seconds
Started	Apr 21 12:56:59 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203704 kb
Host	smart-2df5bdf0-9ca6-47f5-91b0-2b590fee2111
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747303465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.1747303465
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3742346595
Short name	T115
Test name
Test status
Simulation time	188157814 ps
CPU time	2.8 seconds
Started	Apr 21 12:57:02 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203656 kb
Host	smart-4acc4f1b-d329-4d57-a0dd-d230831dbb61
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742346595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3742346595
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.301342975
Short name	T82
Test name
Test status
Simulation time	95788477 ps
CPU time	0.66 seconds
Started	Apr 21 12:57:17 PM PDT 24
Finished	Apr 21 12:57:18 PM PDT 24
Peak memory	203380 kb
Host	smart-621d4fda-f42d-4902-9561-ce6693d9c4dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301342975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.301342975
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.2453881205
Short name	T92
Test name
Test status
Simulation time	47340724 ps
CPU time	0.65 seconds
Started	Apr 21 12:57:19 PM PDT 24
Finished	Apr 21 12:57:20 PM PDT 24
Peak memory	203376 kb
Host	smart-d5a9cc3c-dc8a-4fc5-bb02-b10050750a75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453881205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2453881205
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.2322733212
Short name	T98
Test name
Test status
Simulation time	41116092 ps
CPU time	0.63 seconds
Started	Apr 21 12:57:20 PM PDT 24
Finished	Apr 21 12:57:21 PM PDT 24
Peak memory	203332 kb
Host	smart-c92ae315-c9f9-49ce-80f6-5b519b9e230f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322733212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2322733212
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.590858522
Short name	T79
Test name
Test status
Simulation time	40794530 ps
CPU time	0.64 seconds
Started	Apr 21 12:57:20 PM PDT 24
Finished	Apr 21 12:57:21 PM PDT 24
Peak memory	203324 kb
Host	smart-c61e20e2-2d58-4df0-8eaf-53a8035045e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590858522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.590858522
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.2652709884
Short name	T126
Test name
Test status
Simulation time	46685433 ps
CPU time	0.68 seconds
Started	Apr 21 12:57:23 PM PDT 24
Finished	Apr 21 12:57:24 PM PDT 24
Peak memory	203356 kb
Host	smart-aa0ef5e4-6655-4917-8946-931dce329471
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652709884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2652709884
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.1288744837
Short name	T76
Test name
Test status
Simulation time	42558691 ps
CPU time	0.62 seconds
Started	Apr 21 12:57:18 PM PDT 24
Finished	Apr 21 12:57:19 PM PDT 24
Peak memory	203384 kb
Host	smart-7e30dc6d-2d15-4e1e-929d-5d9144b1c8d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288744837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1288744837
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.1458026084
Short name	T89
Test name
Test status
Simulation time	45653491 ps
CPU time	0.7 seconds
Started	Apr 21 12:57:22 PM PDT 24
Finished	Apr 21 12:57:23 PM PDT 24
Peak memory	203404 kb
Host	smart-92d45919-58f1-45f1-91f5-6a4f969c2c5c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458026084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1458026084
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.2840543788
Short name	T78
Test name
Test status
Simulation time	25416917 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:24 PM PDT 24
Finished	Apr 21 12:57:25 PM PDT 24
Peak memory	203352 kb
Host	smart-6803ada6-3a89-4f89-bc70-4a2bf048df93
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840543788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2840543788
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.1398400510
Short name	T3
Test name
Test status
Simulation time	17788510 ps
CPU time	0.68 seconds
Started	Apr 21 12:57:21 PM PDT 24
Finished	Apr 21 12:57:22 PM PDT 24
Peak memory	203380 kb
Host	smart-657be8bb-796e-428d-a159-60739138e9c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398400510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1398400510
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.i2c_intr_test.921359965
Short name	T74
Test name
Test status
Simulation time	56306518 ps
CPU time	0.7 seconds
Started	Apr 21 12:57:23 PM PDT 24
Finished	Apr 21 12:57:24 PM PDT 24
Peak memory	203316 kb
Host	smart-f74c855a-10ed-4d26-8cb3-cb4625ff0161
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921359965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.921359965
Directory	/workspace/49.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.738636760
Short name	T146
Test name
Test status
Simulation time	30626141 ps
CPU time	0.78 seconds
Started	Apr 21 12:57:04 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203440 kb
Host	smart-e9c627a4-818e-47a5-b07c-63dd9597d677
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738636760 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.738636760
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.403027703
Short name	T40
Test name
Test status
Simulation time	83974259 ps
CPU time	0.65 seconds
Started	Apr 21 12:56:59 PM PDT 24
Finished	Apr 21 12:57:00 PM PDT 24
Peak memory	203504 kb
Host	smart-a1ec7772-edb0-4bf5-bd2e-69a764d8606d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403027703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.403027703
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.1880213567
Short name	T21
Test name
Test status
Simulation time	15378157 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:02 PM PDT 24
Peak memory	203200 kb
Host	smart-9f161e8d-da70-4b75-81b0-3ad0fca5b293
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880213567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1880213567
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.253127584
Short name	T134
Test name
Test status
Simulation time	55162623 ps
CPU time	2.45 seconds
Started	Apr 21 12:56:58 PM PDT 24
Finished	Apr 21 12:57:01 PM PDT 24
Peak memory	203716 kb
Host	smart-3de85f45-731a-4ca6-b294-d7d894ce8e58
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253127584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.253127584
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2861390956
Short name	T72
Test name
Test status
Simulation time	429747851 ps
CPU time	1.59 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203728 kb
Host	smart-083e6070-7d01-4968-8466-3ea1e685db55
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861390956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2861390956
Directory	/workspace/5.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2956049123
Short name	T91
Test name
Test status
Simulation time	28074495 ps
CPU time	0.88 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:03 PM PDT 24
Peak memory	203640 kb
Host	smart-8344f16b-d48f-4987-8e84-55f078f6657a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956049123 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2956049123
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1368915249
Short name	T145
Test name
Test status
Simulation time	123879716 ps
CPU time	0.77 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203344 kb
Host	smart-135396e9-1f63-424b-92dc-5c088ea10fd1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368915249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1368915249
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.3986198155
Short name	T38
Test name
Test status
Simulation time	17367370 ps
CPU time	0.62 seconds
Started	Apr 21 12:56:57 PM PDT 24
Finished	Apr 21 12:56:58 PM PDT 24
Peak memory	203388 kb
Host	smart-4c1b3102-d542-45fa-87b5-49b874ffab0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986198155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3986198155
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2808727193
Short name	T90
Test name
Test status
Simulation time	93408851 ps
CPU time	2.58 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203744 kb
Host	smart-12d80b79-e8e1-400f-bb47-89bc51130bc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808727193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2808727193
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1821665192
Short name	T133
Test name
Test status
Simulation time	52081363 ps
CPU time	1.39 seconds
Started	Apr 21 12:57:00 PM PDT 24
Finished	Apr 21 12:57:01 PM PDT 24
Peak memory	203768 kb
Host	smart-76ac8ce7-de19-4e43-96c6-9dbc35422088
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821665192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1821665192
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.647930296
Short name	T51
Test name
Test status
Simulation time	38248956 ps
CPU time	0.92 seconds
Started	Apr 21 12:57:02 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203524 kb
Host	smart-2b19bd7b-e617-4752-b358-10f137b9f6b1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647930296 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.647930296
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2281142126
Short name	T29
Test name
Test status
Simulation time	17033273 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:02 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203396 kb
Host	smart-c2b2689d-fba6-4864-bf26-c9a0aade8e8b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281142126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2281142126
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.807221737
Short name	T1
Test name
Test status
Simulation time	38156136 ps
CPU time	0.64 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:01 PM PDT 24
Peak memory	203392 kb
Host	smart-d182a7c1-28d1-478a-b5e0-41135c62f82d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807221737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.807221737
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4144555747
Short name	T32
Test name
Test status
Simulation time	54980274 ps
CPU time	1.14 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:02 PM PDT 24
Peak memory	203756 kb
Host	smart-85226f75-4cbb-4273-a441-6a5a71d8ca7f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144555747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.4144555747
Directory	/workspace/7.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.1917762736
Short name	T50
Test name
Test status
Simulation time	136594247 ps
CPU time	2.31 seconds
Started	Apr 21 12:57:02 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203768 kb
Host	smart-6a0553c4-b7c4-44fb-9213-96d64b6cc6df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917762736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1917762736
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2340150367
Short name	T61
Test name
Test status
Simulation time	296077175 ps
CPU time	2.34 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203760 kb
Host	smart-2abf5c71-5dcd-4ef3-b046-f114bdd300e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340150367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2340150367
Directory	/workspace/7.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.922820509
Short name	T14
Test name
Test status
Simulation time	66219941 ps
CPU time	1.02 seconds
Started	Apr 21 12:57:02 PM PDT 24
Finished	Apr 21 12:57:03 PM PDT 24
Peak memory	203620 kb
Host	smart-45d9857d-1c7b-4e4c-abfb-ff20044f64dc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922820509 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.922820509
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2621912718
Short name	T135
Test name
Test status
Simulation time	39438854 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:04 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203340 kb
Host	smart-4f4b5bc5-22f6-4ebd-9726-f95a4d717be6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621912718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2621912718
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2175899990
Short name	T110
Test name
Test status
Simulation time	170596463 ps
CPU time	1.6 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203740 kb
Host	smart-1d1b5bef-c8ae-44b6-8fa7-fb2d32cf108e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175899990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2175899990
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.602753963
Short name	T63
Test name
Test status
Simulation time	497079388 ps
CPU time	2.53 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:06 PM PDT 24
Peak memory	203760 kb
Host	smart-82df6e70-634a-4974-8242-4d0451058326
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602753963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.602753963
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2504378946
Short name	T64
Test name
Test status
Simulation time	87156529 ps
CPU time	1.04 seconds
Started	Apr 21 12:57:05 PM PDT 24
Finished	Apr 21 12:57:06 PM PDT 24
Peak memory	203436 kb
Host	smart-ee801a63-e04e-47bd-aa26-cf27033a131e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504378946 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2504378946
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.579193075
Short name	T66
Test name
Test status
Simulation time	62162266 ps
CPU time	0.71 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203460 kb
Host	smart-a45cfb49-7e9f-452c-a3bd-230d658d1152
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579193075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.579193075
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.3859031842
Short name	T10
Test name
Test status
Simulation time	43751517 ps
CPU time	0.69 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:04 PM PDT 24
Peak memory	203416 kb
Host	smart-b52699f3-335f-4336-9944-7fd805cd19a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859031842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3859031842
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3844408181
Short name	T60
Test name
Test status
Simulation time	57612338 ps
CPU time	0.85 seconds
Started	Apr 21 12:57:03 PM PDT 24
Finished	Apr 21 12:57:05 PM PDT 24
Peak memory	203532 kb
Host	smart-3f76a33c-6e07-4368-83e9-dcd8548fcb19
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844408181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.3844408181
Directory	/workspace/9.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3372089968
Short name	T130
Test name
Test status
Simulation time	61072346 ps
CPU time	1.45 seconds
Started	Apr 21 12:57:01 PM PDT 24
Finished	Apr 21 12:57:02 PM PDT 24
Peak memory	203756 kb
Host	smart-f7215b67-f046-4ca0-8d3a-91afffb00b74
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372089968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3372089968
Directory	/workspace/9.i2c_tl_errors/latest