Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357	1			T1	5		T3	8		T7	8
all_pins[1]	357	1			T1	5		T3	8		T7	8
all_pins[2]	357	1			T1	5		T3	8		T7	8
all_pins[3]	357	1			T1	5		T3	8		T7	8
all_pins[4]	357	1			T1	5		T3	8		T7	8
all_pins[5]	357	1			T1	5		T3	8		T7	8
all_pins[6]	357	1			T1	5		T3	8		T7	8
all_pins[7]	357	1			T1	5		T3	8		T7	8
all_pins[8]	357	1			T1	5		T3	8		T7	8
all_pins[9]	357	1			T1	5		T3	8		T7	8
all_pins[10]	357	1			T1	5		T3	8		T7	8
all_pins[11]	357	1			T1	5		T3	8		T7	8
all_pins[12]	357	1			T1	5		T3	8		T7	8
all_pins[13]	357	1			T1	5		T3	8		T7	8
all_pins[14]	357	1			T1	5		T3	8		T7	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4372	1			T1	61		T3	93		T7	96
values[0x1]	983	1			T1	14		T3	27		T7	24
transitions[0x0=>0x1]	713	1			T1	12		T3	17		T7	19
transitions[0x1=>0x0]	723	1			T1	12		T3	17		T7	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	288	1			T1	4		T3	8		T7	7
all_pins[0]	values[0x1]	69	1			T1	1		T7	1		T6	1
all_pins[0]	transitions[0x0=>0x1]	52	1			T1	1		T7	1		T6	1
all_pins[0]	transitions[0x1=>0x0]	42	1			T7	2		T6	2		T9	2
all_pins[1]	values[0x0]	298	1			T1	5		T3	8		T7	6
all_pins[1]	values[0x1]	59	1			T7	2		T6	2		T9	2
all_pins[1]	transitions[0x0=>0x1]	40	1			T7	2		T6	2		T9	1
all_pins[1]	transitions[0x1=>0x0]	44	1			T1	1		T3	2		T6	1
all_pins[2]	values[0x0]	294	1			T1	4		T3	6		T7	8
all_pins[2]	values[0x1]	63	1			T1	1		T3	2		T6	1
all_pins[2]	transitions[0x0=>0x1]	47	1			T1	1		T3	1		T6	1
all_pins[2]	transitions[0x1=>0x0]	54	1			T1	1		T7	3		T6	2
all_pins[3]	values[0x0]	287	1			T1	4		T3	7		T7	5
all_pins[3]	values[0x1]	70	1			T1	1		T3	1		T7	3
all_pins[3]	transitions[0x0=>0x1]	55	1			T1	1		T3	1		T7	2
all_pins[3]	transitions[0x1=>0x0]	37	1			T1	1		T3	1		T7	1
all_pins[4]	values[0x0]	305	1			T1	4		T3	7		T7	6
all_pins[4]	values[0x1]	52	1			T1	1		T3	1		T7	2
all_pins[4]	transitions[0x0=>0x1]	39	1			T3	1		T7	1		T6	2
all_pins[4]	transitions[0x1=>0x0]	60	1			T1	2		T3	2		T7	2
all_pins[5]	values[0x0]	284	1			T1	2		T3	6		T7	5
all_pins[5]	values[0x1]	73	1			T1	3		T3	2		T7	3
all_pins[5]	transitions[0x0=>0x1]	51	1			T1	3		T3	1		T7	2
all_pins[5]	transitions[0x1=>0x0]	58	1			T3	1		T6	3		T10	1
all_pins[6]	values[0x0]	277	1			T1	5		T3	6		T7	7
all_pins[6]	values[0x1]	80	1			T3	2		T7	1		T6	5
all_pins[6]	transitions[0x0=>0x1]	58	1			T3	1		T7	1		T10	1
all_pins[6]	transitions[0x1=>0x0]	53	1			T1	1		T3	2		T6	1
all_pins[7]	values[0x0]	282	1			T1	4		T3	5		T7	8
all_pins[7]	values[0x1]	75	1			T1	1		T3	3		T6	6
all_pins[7]	transitions[0x0=>0x1]	61	1			T1	1		T3	2		T6	5
all_pins[7]	transitions[0x1=>0x0]	38	1			T1	2		T3	1		T57	1
all_pins[8]	values[0x0]	305	1			T1	3		T3	6		T7	8
all_pins[8]	values[0x1]	52	1			T1	2		T3	2		T6	1
all_pins[8]	transitions[0x0=>0x1]	34	1			T1	2		T3	1		T6	1
all_pins[8]	transitions[0x1=>0x0]	51	1			T3	1		T7	1		T6	1
all_pins[9]	values[0x0]	288	1			T1	5		T3	6		T7	7
all_pins[9]	values[0x1]	69	1			T3	2		T7	1		T6	1
all_pins[9]	transitions[0x0=>0x1]	55	1			T3	2		T7	1		T6	1
all_pins[9]	transitions[0x1=>0x0]	58	1			T1	1		T3	1		T7	2
all_pins[10]	values[0x0]	285	1			T1	4		T3	7		T7	6
all_pins[10]	values[0x1]	72	1			T1	1		T3	1		T7	2
all_pins[10]	transitions[0x0=>0x1]	54	1			T7	2		T6	2		T9	2
all_pins[10]	transitions[0x1=>0x0]	38	1			T3	4		T7	1		T9	3
all_pins[11]	values[0x0]	301	1			T1	4		T3	3		T7	7
all_pins[11]	values[0x1]	56	1			T1	1		T3	5		T7	1
all_pins[11]	transitions[0x0=>0x1]	39	1			T1	1		T3	2		T7	1
all_pins[11]	transitions[0x1=>0x0]	40	1			T3	1		T7	1		T6	2
all_pins[12]	values[0x0]	300	1			T1	5		T3	4		T7	7
all_pins[12]	values[0x1]	57	1			T3	4		T7	1		T6	2
all_pins[12]	transitions[0x0=>0x1]	39	1			T3	3		T7	1		T6	1
all_pins[12]	transitions[0x1=>0x0]	38	1			T7	4		T6	1		T58	3
all_pins[13]	values[0x0]	301	1			T1	5		T3	7		T7	4
all_pins[13]	values[0x1]	56	1			T3	1		T7	4		T6	2
all_pins[13]	transitions[0x0=>0x1]	39	1			T3	1		T7	3		T6	1
all_pins[13]	transitions[0x1=>0x0]	63	1			T1	2		T3	1		T7	2
all_pins[14]	values[0x0]	277	1			T1	3		T3	7		T7	5
all_pins[14]	values[0x1]	80	1			T1	2		T3	1		T7	3
all_pins[14]	transitions[0x0=>0x1]	50	1			T1	2		T3	1		T7	2
all_pins[14]	transitions[0x1=>0x0]	49	1			T1	1		T9	1		T10	4