Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T1	4		T3	7		T7	7
all_values[1]	287	1			T1	4		T3	7		T7	7
all_values[2]	287	1			T1	4		T3	7		T7	7
all_values[3]	287	1			T1	4		T3	7		T7	7
all_values[4]	287	1			T1	4		T3	7		T7	7
all_values[5]	287	1			T1	4		T3	7		T7	7
all_values[6]	287	1			T1	4		T3	7		T7	7
all_values[7]	287	1			T1	4		T3	7		T7	7
all_values[8]	287	1			T1	4		T3	7		T7	7
all_values[9]	287	1			T1	4		T3	7		T7	7
all_values[10]	287	1			T1	4		T3	7		T7	7
all_values[11]	287	1			T1	4		T3	7		T7	7
all_values[12]	287	1			T1	4		T3	7		T7	7
all_values[13]	287	1			T1	4		T3	7		T7	7
all_values[14]	287	1			T1	4		T3	7		T7	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2337

1

T1

30

T3

45

T7

53

auto[1]

1968

1

T1

30

T3

60

T7

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

786

1

T1

11

T3

13

T7

13

auto[1]

3519

1

T1

49

T3

92

T7

92

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2510

1

T1

34

T3

57

T7

61

auto[1]

1795

1

T1

26

T3

48

T7

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T3	2		T6	3		T9	1
all_values[0]	auto[0]	auto[0]	auto[1]	60	1			T3	2		T7	3		T6	1
all_values[0]	auto[0]	auto[1]	auto[0]	23	1			T3	2		T6	1		T9	2
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T1	3		T7	1		T9	2
all_values[0]	auto[1]	auto[0]	auto[1]	49	1			T7	2		T6	1		T58	2
all_values[0]	auto[1]	auto[1]	auto[1]	70	1			T1	1		T3	1		T7	1
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T9	2		T58	4		T33	1
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T1	2		T3	3		T7	2
all_values[1]	auto[0]	auto[1]	auto[0]	13	1			T10	1		T58	1		T34	1
all_values[1]	auto[0]	auto[1]	auto[1]	48	1			T3	1		T7	2		T6	2
all_values[1]	auto[1]	auto[0]	auto[1]	74	1			T1	2		T3	2		T7	1
all_values[1]	auto[1]	auto[1]	auto[1]	56	1			T3	1		T7	2		T6	1
all_values[2]	auto[0]	auto[0]	auto[0]	34	1			T1	1		T3	1		T58	1
all_values[2]	auto[0]	auto[0]	auto[1]	53	1			T3	1		T7	2		T6	1
all_values[2]	auto[0]	auto[1]	auto[0]	8	1			T21	1		T35	1		T74	2
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T1	1		T3	1		T6	1
all_values[2]	auto[1]	auto[0]	auto[1]	74	1			T1	1		T3	1		T7	5
all_values[2]	auto[1]	auto[1]	auto[1]	48	1			T1	1		T3	3		T6	1
all_values[3]	auto[0]	auto[0]	auto[0]	31	1			T6	1		T57	2		T33	3
all_values[3]	auto[0]	auto[0]	auto[1]	55	1			T1	1		T3	2		T7	1
all_values[3]	auto[0]	auto[1]	auto[0]	22	1			T1	1		T6	1		T36	2
all_values[3]	auto[0]	auto[1]	auto[1]	63	1			T3	3		T7	3		T6	2
all_values[3]	auto[1]	auto[0]	auto[1]	63	1			T1	1		T3	1		T6	1
all_values[3]	auto[1]	auto[1]	auto[1]	53	1			T1	1		T3	1		T7	3
all_values[4]	auto[0]	auto[0]	auto[0]	47	1			T1	2		T6	1		T9	1
all_values[4]	auto[0]	auto[0]	auto[1]	54	1			T3	2		T7	3		T6	3
all_values[4]	auto[0]	auto[1]	auto[0]	18	1			T34	1		T53	1		T49	1
all_values[4]	auto[0]	auto[1]	auto[1]	57	1			T1	1		T3	1		T7	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1			T3	4		T7	1		T10	2
all_values[4]	auto[1]	auto[1]	auto[1]	51	1			T1	1		T7	2		T6	2
all_values[5]	auto[0]	auto[0]	auto[0]	26	1			T6	1		T57	1		T58	1
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T7	1		T9	3		T10	2
all_values[5]	auto[0]	auto[1]	auto[0]	15	1			T6	2		T58	1		T36	1
all_values[5]	auto[0]	auto[1]	auto[1]	56	1			T1	2		T3	4		T7	1
all_values[5]	auto[1]	auto[0]	auto[1]	69	1			T3	2		T7	1		T6	1
all_values[5]	auto[1]	auto[1]	auto[1]	52	1			T1	2		T3	1		T7	4
all_values[6]	auto[0]	auto[0]	auto[0]	27	1			T9	1		T58	1		T21	3
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T1	2		T3	1		T7	2
all_values[6]	auto[0]	auto[1]	auto[0]	21	1			T1	1		T3	2		T7	3
all_values[6]	auto[0]	auto[1]	auto[1]	56	1			T3	1		T6	1		T10	2
all_values[6]	auto[1]	auto[0]	auto[1]	63	1			T7	1		T6	2		T9	2
all_values[6]	auto[1]	auto[1]	auto[1]	58	1			T1	1		T3	3		T7	1
all_values[7]	auto[0]	auto[0]	auto[0]	35	1			T9	2		T10	2		T57	1
all_values[7]	auto[0]	auto[0]	auto[1]	59	1			T1	1		T3	2		T7	3
all_values[7]	auto[0]	auto[1]	auto[0]	13	1			T3	1		T56	2		T75	1
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T3	2		T7	2		T6	4
all_values[7]	auto[1]	auto[0]	auto[1]	59	1			T1	1		T3	1		T7	2
all_values[7]	auto[1]	auto[1]	auto[1]	59	1			T1	2		T3	1		T6	2
all_values[8]	auto[0]	auto[0]	auto[0]	38	1			T6	1		T9	1		T10	1
all_values[8]	auto[0]	auto[0]	auto[1]	54	1			T1	1		T7	1		T9	1
all_values[8]	auto[0]	auto[1]	auto[0]	21	1			T6	1		T9	1		T21	5
all_values[8]	auto[0]	auto[1]	auto[1]	59	1			T1	1		T3	3		T7	2
all_values[8]	auto[1]	auto[0]	auto[1]	61	1			T1	1		T3	2		T7	2
all_values[8]	auto[1]	auto[1]	auto[1]	54	1			T1	1		T3	2		T7	2
all_values[9]	auto[0]	auto[0]	auto[0]	28	1			T1	1		T3	1		T7	1
all_values[9]	auto[0]	auto[0]	auto[1]	56	1			T1	1		T3	1		T7	3
all_values[9]	auto[0]	auto[1]	auto[0]	29	1			T7	2		T6	1		T9	3
all_values[9]	auto[0]	auto[1]	auto[1]	58	1			T3	2		T10	1		T57	1
all_values[9]	auto[1]	auto[0]	auto[1]	65	1			T1	2		T3	1		T6	2
all_values[9]	auto[1]	auto[1]	auto[1]	51	1			T3	2		T7	1		T6	1
all_values[10]	auto[0]	auto[0]	auto[0]	30	1			T6	1		T9	1		T57	1
all_values[10]	auto[0]	auto[0]	auto[1]	50	1			T1	2		T3	2		T7	3
all_values[10]	auto[0]	auto[1]	auto[0]	17	1			T1	1		T6	1		T21	4
all_values[10]	auto[0]	auto[1]	auto[1]	61	1			T3	2		T6	3		T9	2
all_values[10]	auto[1]	auto[0]	auto[1]	66	1			T3	2		T7	2		T10	3
all_values[10]	auto[1]	auto[1]	auto[1]	63	1			T1	1		T3	1		T7	2
all_values[11]	auto[0]	auto[0]	auto[0]	33	1			T7	1		T58	1		T33	1
all_values[11]	auto[0]	auto[0]	auto[1]	73	1			T1	1		T7	3		T6	3
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T1	1		T3	1		T7	1
all_values[11]	auto[0]	auto[1]	auto[1]	55	1			T3	1		T7	1		T6	2
all_values[11]	auto[1]	auto[0]	auto[1]	58	1			T1	1		T6	2		T9	1
all_values[11]	auto[1]	auto[1]	auto[1]	47	1			T1	1		T3	5		T7	1
all_values[12]	auto[0]	auto[0]	auto[0]	37	1			T57	2		T33	1		T34	2
all_values[12]	auto[0]	auto[0]	auto[1]	54	1			T1	1		T3	1		T7	1
all_values[12]	auto[0]	auto[1]	auto[0]	18	1			T1	2		T57	2		T21	1
all_values[12]	auto[0]	auto[1]	auto[1]	58	1			T7	3		T6	2		T9	3
all_values[12]	auto[1]	auto[0]	auto[1]	66	1			T1	1		T3	1		T7	2
all_values[12]	auto[1]	auto[1]	auto[1]	54	1			T3	5		T7	1		T6	1
all_values[13]	auto[0]	auto[0]	auto[0]	56	1			T3	2		T7	1		T9	1
all_values[13]	auto[0]	auto[0]	auto[1]	51	1			T1	1		T7	2		T6	3
all_values[13]	auto[0]	auto[1]	auto[0]	17	1			T57	2		T36	3		T44	2
all_values[13]	auto[0]	auto[1]	auto[1]	49	1			T3	3		T10	1		T58	2
all_values[13]	auto[1]	auto[0]	auto[1]	68	1			T1	3		T3	1		T6	2
all_values[13]	auto[1]	auto[1]	auto[1]	46	1			T3	1		T7	4		T6	2
all_values[14]	auto[0]	auto[0]	auto[0]	28	1			T7	1		T58	2		T33	2
all_values[14]	auto[0]	auto[0]	auto[1]	42	1			T3	1		T9	2		T10	1
all_values[14]	auto[0]	auto[1]	auto[0]	15	1			T1	1		T3	1		T7	3
all_values[14]	auto[0]	auto[1]	auto[1]	64	1			T1	2		T3	2		T7	2
all_values[14]	auto[1]	auto[0]	auto[1]	71	1			T3	3		T6	3		T9	1
all_values[14]	auto[1]	auto[1]	auto[1]	67	1			T1	1		T7	1		T9	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal