Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

167143

1

T2

96

T6

145

T43

704

ack

14727

1

T2

22

T4

47

T6

20

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	708	1			T4	1		T43	5		T67	2
high	37171	1			T2	19		T4	9		T6	61
med	67676	1			T2	46		T4	4		T6	63
sml	75616	1			T2	53		T4	33		T6	40
all_zero	699	1			T6	1		T43	4		T44	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90903

1

T2

67

T4

23

T6

80

auto[1]

90967

1

T2

51

T4

24

T6

85

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124886

1

T2

86

T4

33

T6

120

auto[1]

56984

1

T2

32

T4

14

T6

45

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174006

1

T2

109

T4

17

T6

165

auto[1]

7864

1

T2

9

T4

30

T7

6

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171725

1

T2

100

T4

30

T6

145

auto[1]

10145

1

T2

18

T4

17

T6

20

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172613

1

T2

100

T4

31

T6

145

auto[1]

9257

1

T2

18

T4

16

T6

20

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90903

1

T2

67

T4

23

T6

80

auto[1]

90967

1

T2

51

T4

24

T6

85

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124886

1

T2

86

T4

33

T6

120

auto[1]

56984

1

T2

32

T4

14

T6

45

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174006

1

T2

109

T4

17

T6

165

auto[1]

7864

1

T2

9

T4

30

T7

6

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171725

1

T2

100

T4

30

T6

145

auto[1]

10145

1

T2

18

T4

17

T6

20

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172613

1

T2

100

T4

31

T6

145

auto[1]

9257

1

T2

18

T4

16

T6

20

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T168

1

T227

1

T228

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T167

1

T229

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T230

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

317

1

T2

1

T43

1

T42

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

160

1

T2

1

T42

1

T45

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

173

1

T45

1

T146

1

T75

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

578

1

T2

1

T43

3

T44

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

284

1

T2

1

T43

2

T69

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

262

1

T68

1

T45

1

T75

6

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

552

1

T2

1

T43

2

T42

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

233

1

T2

1

T43

1

T75

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

325

1

T42

1

T68

1

T45

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T231

1

T232

1

T233

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T234

1

T175

1

T235

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T236

1

T237

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	53295	1			T2	32		T6	48		T43	231
write_address_byte	10145	1			T2	18		T4	17		T6	20
read_with_ack	2277	1			T4	14		T60	1		T67	1
read_with_nack	5587	1			T2	9		T4	16		T7	6
stop_byte	9257	1			T2	18		T4	16		T6	20
write_address_byte_nak	5298	1			T2	10		T43	18		T67	2
data_byte_nack	167143	1			T2	96		T6	145		T43	704
stop_byte_nack	5613	1			T2	11		T6	20		T43	17
nakok_byte_nack	83628	1			T2	42		T6	71		T43	358
nakok_addr_byte_nack	2694	1			T2	5		T43	9		T67	1