Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44560490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9992007

1

T1

13

T2

2282

T3

202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53625067	1			T1	13		T2	16684		T3	526
values[0x0]	464219	1			T1	8		T2	177		T3	103
values[0x1]	463211	1			T1	6		T2	188		T3	98

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31735211	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22817286

1

T1

14

T2

6920

T3

376

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	195778	1			T2	38		T3	5		T4	6
valid_sources[0x01]	214686	1			T3	1		T4	5		T6	77
valid_sources[0x02]	191562	1			T3	4		T4	166		T6	88
valid_sources[0x03]	187119	1			T3	1		T4	5		T6	62
valid_sources[0x04]	184762	1			T3	4		T4	289		T6	63
valid_sources[0x05]	196408	1			T2	37		T3	3		T4	431
valid_sources[0x06]	192508	1			T4	5		T5	727		T6	76
valid_sources[0x07]	197893	1			T3	6		T4	586		T6	75
valid_sources[0x08]	292737	1			T3	4		T4	1		T6	80
valid_sources[0x09]	242874	1			T2	336		T3	3		T4	4
valid_sources[0x0a]	190589	1			T3	5		T4	868		T6	97
valid_sources[0x0b]	197031	1			T2	1088		T3	3		T4	4
valid_sources[0x0c]	189779	1			T4	13		T6	6		T7	84
valid_sources[0x0d]	193440	1			T3	1		T4	1		T6	50
valid_sources[0x0e]	196715	1			T4	2		T6	3		T7	69
valid_sources[0x0f]	229979	1			T3	3		T4	4		T6	58
valid_sources[0x10]	190569	1			T3	2		T4	6		T6	43
valid_sources[0x11]	200529	1			T3	2		T4	8		T6	18
valid_sources[0x12]	203249	1			T3	5		T4	3		T6	20
valid_sources[0x13]	620961	1			T2	37		T3	1		T4	3
valid_sources[0x14]	185490	1			T2	1295		T3	5		T4	5
valid_sources[0x15]	182814	1			T3	1		T4	11		T6	45
valid_sources[0x16]	209690	1			T2	35		T3	3		T4	8
valid_sources[0x17]	224708	1			T3	1		T4	6		T6	17
valid_sources[0x18]	200435	1			T2	37		T3	2		T4	291
valid_sources[0x19]	203420	1			T3	3		T4	574		T6	7
valid_sources[0x1a]	208969	1			T3	2		T4	2		T6	41
valid_sources[0x1b]	193652	1			T2	37		T3	3		T4	6
valid_sources[0x1c]	208113	1			T3	5		T4	8		T6	79
valid_sources[0x1d]	202406	1			T4	3		T6	75		T7	106
valid_sources[0x1e]	195522	1			T3	4		T6	14		T7	81
valid_sources[0x1f]	298357	1			T2	1043		T3	5		T4	5
valid_sources[0x20]	198017	1			T3	1		T4	285		T6	91
valid_sources[0x21]	209810	1			T3	6		T4	5		T6	72
valid_sources[0x22]	191137	1			T3	2		T4	3		T6	19
valid_sources[0x23]	195516	1			T3	4		T4	7		T6	37
valid_sources[0x24]	205160	1			T2	38		T3	4		T4	20
valid_sources[0x25]	192108	1			T3	4		T4	5		T6	18
valid_sources[0x26]	189106	1			T2	982		T3	4		T4	2
valid_sources[0x27]	202344	1			T3	4		T4	7		T6	34
valid_sources[0x28]	194825	1			T3	3		T4	291		T6	46
valid_sources[0x29]	201812	1			T2	35		T3	4		T4	3
valid_sources[0x2a]	196500	1			T1	2		T2	33		T6	13
valid_sources[0x2b]	200788	1			T3	1		T4	7		T6	20
valid_sources[0x2c]	203032	1			T2	35		T3	3		T4	5
valid_sources[0x2d]	197866	1			T2	1434		T3	1		T4	5
valid_sources[0x2e]	281589	1			T2	850		T3	3		T4	13
valid_sources[0x2f]	191861	1			T3	3		T4	2		T6	32
valid_sources[0x30]	391355	1			T1	3		T3	1		T4	7
valid_sources[0x31]	195695	1			T3	3		T4	298		T6	99
valid_sources[0x32]	188859	1			T3	6		T4	4		T6	13
valid_sources[0x33]	663109	1			T2	38		T3	4		T4	10
valid_sources[0x34]	210674	1			T3	4		T4	6		T6	35
valid_sources[0x35]	239937	1			T1	1		T3	2		T4	3
valid_sources[0x36]	190388	1			T2	42		T3	4		T4	3
valid_sources[0x37]	194232	1			T3	4		T4	597		T6	66
valid_sources[0x38]	196073	1			T1	3		T2	38		T3	3
valid_sources[0x39]	197945	1			T2	37		T3	4		T4	19
valid_sources[0x3a]	194862	1			T1	1		T2	35		T3	5
valid_sources[0x3b]	210197	1			T3	1		T4	3		T6	83
valid_sources[0x3c]	198372	1			T4	151		T6	44		T7	91
valid_sources[0x3d]	204466	1			T3	3		T4	3		T6	48
valid_sources[0x3e]	194214	1			T3	5		T4	152		T6	58
valid_sources[0x3f]	204955	1			T2	37		T3	3		T4	166
valid_sources[0x40]	190675	1			T3	5		T4	5		T6	63
valid_sources[0x41]	200863	1			T3	3		T4	2		T6	46
valid_sources[0x42]	188982	1			T2	1009		T3	4		T4	9
valid_sources[0x43]	222583	1			T3	2		T4	152		T6	58
valid_sources[0x44]	199728	1			T3	6		T4	16		T6	77
valid_sources[0x45]	203870	1			T2	37		T3	3		T4	4
valid_sources[0x46]	204574	1			T3	3		T4	427		T6	110
valid_sources[0x47]	199279	1			T3	5		T4	7		T6	166
valid_sources[0x48]	197422	1			T2	37		T3	5		T4	5
valid_sources[0x49]	216982	1			T2	33		T3	2		T4	554
valid_sources[0x4a]	199849	1			T2	245		T3	2		T4	7
valid_sources[0x4b]	195945	1			T2	33		T4	8		T6	61
valid_sources[0x4c]	193371	1			T3	2		T4	1130		T6	18
valid_sources[0x4d]	191258	1			T2	87		T3	2		T4	143
valid_sources[0x4e]	196065	1			T3	3		T4	3		T6	69
valid_sources[0x4f]	198538	1			T1	2		T2	33		T3	1
valid_sources[0x50]	191161	1			T3	1		T4	293		T6	16
valid_sources[0x51]	186505	1			T3	2		T4	297		T6	37
valid_sources[0x52]	195537	1			T3	1		T4	9		T6	24
valid_sources[0x53]	198974	1			T1	1		T3	2		T4	425
valid_sources[0x54]	190251	1			T3	1		T4	290		T6	51
valid_sources[0x55]	190227	1			T4	7		T6	19		T7	83
valid_sources[0x56]	190566	1			T4	9		T6	35		T7	84
valid_sources[0x57]	202070	1			T3	2		T4	6		T6	83
valid_sources[0x58]	213051	1			T3	1		T4	3		T6	37
valid_sources[0x59]	188033	1			T3	3		T4	5		T6	41
valid_sources[0x5a]	191187	1			T2	35		T3	3		T4	4
valid_sources[0x5b]	203497	1			T3	3		T4	1294		T6	34
valid_sources[0x5c]	184098	1			T1	1		T2	37		T3	3
valid_sources[0x5d]	185529	1			T3	1		T4	3		T6	32
valid_sources[0x5e]	244266	1			T2	35		T3	1		T4	10
valid_sources[0x5f]	200763	1			T2	73		T3	1		T4	5
valid_sources[0x60]	196975	1			T1	1		T3	2		T4	17
valid_sources[0x61]	222988	1			T3	3		T4	9		T6	35
valid_sources[0x62]	218484	1			T3	1		T4	727		T6	45
valid_sources[0x63]	199313	1			T4	6		T6	29		T7	82
valid_sources[0x64]	195752	1			T4	4		T6	48		T7	71
valid_sources[0x65]	204012	1			T2	37		T3	3		T4	162
valid_sources[0x66]	194920	1			T1	1		T3	2		T4	150
valid_sources[0x67]	203735	1			T3	2		T4	6		T6	17
valid_sources[0x68]	194605	1			T3	4		T4	4		T6	13
valid_sources[0x69]	203660	1			T2	38		T3	2		T4	5
valid_sources[0x6a]	215441	1			T2	35		T3	2		T4	7
valid_sources[0x6b]	200451	1			T3	1		T4	4		T6	35
valid_sources[0x6c]	198408	1			T3	6		T4	2		T6	39
valid_sources[0x6d]	185410	1			T2	126		T3	4		T4	159
valid_sources[0x6e]	197246	1			T3	4		T4	3		T6	91
valid_sources[0x6f]	207850	1			T3	3		T4	11		T6	91
valid_sources[0x70]	194094	1			T3	4		T4	9		T6	33
valid_sources[0x71]	205477	1			T3	4		T4	5		T6	23
valid_sources[0x72]	377078	1			T2	685		T3	3		T4	2
valid_sources[0x73]	194135	1			T3	5		T4	6		T6	84
valid_sources[0x74]	194268	1			T3	6		T4	6		T6	82
valid_sources[0x75]	187453	1			T2	37		T3	6		T4	9
valid_sources[0x76]	188854	1			T2	35		T3	3		T4	2
valid_sources[0x77]	208165	1			T2	37		T3	5		T4	719
valid_sources[0x78]	233102	1			T2	416		T3	1		T4	9
valid_sources[0x79]	200110	1			T3	7		T4	8		T6	58
valid_sources[0x7a]	210472	1			T2	37		T3	3		T4	3
valid_sources[0x7b]	291548	1			T3	2		T4	300		T6	25
valid_sources[0x7c]	196282	1			T3	4		T4	5		T6	52
valid_sources[0x7d]	211323	1			T3	5		T4	9		T6	62
valid_sources[0x7e]	194030	1			T2	367		T3	5		T4	429
valid_sources[0x7f]	201073	1			T3	6		T4	179		T6	39
valid_sources[0x80]	195185	1			T2	297		T4	11		T6	80

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9584583

1

T1

8

T2

2059

T3

124

values[0x0]

all_enables

biggest_size

240533

1

T1

5

T2

117

T3

50

values[0x1]

all_enables

biggest_size

166891

1

T2

106

T3

28

T4

237