Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41713669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10034102

1

T1

846

T2

3717

T3

4702

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50823378	1			T1	3161		T2	12597		T3	15230
values[0x0]	462138	1			T1	19		T2	244		T3	440
values[0x1]	462255	1			T1	29		T2	263		T3	438

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29742489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22005282

1

T1

1524

T2

6397

T3

7826

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	200804	1			T1	35		T2	65		T3	8
valid_sources[0x01]	190104	1			T1	1		T2	42		T3	4
valid_sources[0x02]	190065	1			T2	47		T3	111		T4	3
valid_sources[0x03]	292763	1			T2	43		T3	2		T4	3
valid_sources[0x04]	197025	1			T1	54		T2	49		T3	3
valid_sources[0x05]	208238	1			T1	53		T2	43		T3	407
valid_sources[0x06]	186722	1			T2	59		T3	8		T6	307
valid_sources[0x07]	200053	1			T2	50		T3	11		T6	217
valid_sources[0x08]	181121	1			T2	52		T3	6		T4	4
valid_sources[0x09]	198739	1			T1	8		T2	46		T3	6
valid_sources[0x0a]	210445	1			T1	1		T2	73		T3	3
valid_sources[0x0b]	205242	1			T1	1		T2	61		T3	3
valid_sources[0x0c]	266158	1			T1	9		T2	55		T3	111
valid_sources[0x0d]	196001	1			T2	51		T3	17		T6	268
valid_sources[0x0e]	180635	1			T2	62		T3	2		T6	268
valid_sources[0x0f]	546686	1			T2	50		T3	2		T6	220
valid_sources[0x10]	196243	1			T2	38		T3	8		T6	265
valid_sources[0x11]	177651	1			T1	37		T2	49		T3	4
valid_sources[0x12]	245690	1			T1	1		T2	45		T3	5
valid_sources[0x13]	183992	1			T1	69		T2	47		T3	304
valid_sources[0x14]	186392	1			T1	86		T2	41		T3	6
valid_sources[0x15]	189678	1			T2	58		T3	306		T6	256
valid_sources[0x16]	195027	1			T1	14		T2	66		T3	1
valid_sources[0x17]	250166	1			T2	50		T3	3		T4	3
valid_sources[0x18]	179655	1			T1	14		T2	73		T3	1
valid_sources[0x19]	198314	1			T2	57		T3	6		T4	3
valid_sources[0x1a]	182871	1			T2	53		T3	19		T4	2
valid_sources[0x1b]	188918	1			T2	69		T6	247		T7	45
valid_sources[0x1c]	189540	1			T2	52		T3	6		T4	5
valid_sources[0x1d]	202095	1			T2	25		T3	389		T4	1
valid_sources[0x1e]	187671	1			T1	47		T2	57		T3	4
valid_sources[0x1f]	287135	1			T2	34		T3	2		T6	242
valid_sources[0x20]	196176	1			T2	43		T3	2		T6	287
valid_sources[0x21]	195903	1			T2	41		T3	605		T6	287
valid_sources[0x22]	196684	1			T2	45		T3	7		T4	17
valid_sources[0x23]	209114	1			T2	44		T3	9		T4	7
valid_sources[0x24]	185320	1			T2	64		T3	6		T6	244
valid_sources[0x25]	181568	1			T2	45		T3	4		T6	291
valid_sources[0x26]	199458	1			T1	4		T2	58		T3	4
valid_sources[0x27]	177350	1			T2	42		T3	4		T4	2
valid_sources[0x28]	192784	1			T1	27		T2	44		T3	2
valid_sources[0x29]	215432	1			T2	51		T3	23		T6	223
valid_sources[0x2a]	189586	1			T1	66		T2	60		T3	3
valid_sources[0x2b]	179583	1			T2	39		T3	527		T6	218
valid_sources[0x2c]	234951	1			T1	28		T2	42		T3	1
valid_sources[0x2d]	201570	1			T2	47		T3	6		T6	263
valid_sources[0x2e]	194964	1			T2	42		T3	2		T6	191
valid_sources[0x2f]	188267	1			T1	10		T2	44		T3	13
valid_sources[0x30]	198123	1			T2	61		T3	9		T6	234
valid_sources[0x31]	197898	1			T2	30		T3	10		T4	2
valid_sources[0x32]	203642	1			T1	53		T2	40		T3	4
valid_sources[0x33]	192085	1			T1	17		T2	45		T3	2
valid_sources[0x34]	203024	1			T1	10		T2	60		T3	8
valid_sources[0x35]	184702	1			T2	49		T3	12		T4	1
valid_sources[0x36]	191148	1			T1	1		T2	42		T3	11
valid_sources[0x37]	198528	1			T2	57		T3	17		T4	1
valid_sources[0x38]	182828	1			T2	57		T3	9		T6	275
valid_sources[0x39]	201018	1			T1	45		T2	73		T3	3
valid_sources[0x3a]	197161	1			T1	29		T2	65		T3	205
valid_sources[0x3b]	198142	1			T1	36		T2	50		T3	102
valid_sources[0x3c]	216689	1			T1	1		T2	39		T3	102
valid_sources[0x3d]	182805	1			T2	39		T3	4		T6	260
valid_sources[0x3e]	192593	1			T1	6		T2	56		T3	2
valid_sources[0x3f]	201390	1			T2	36		T3	580		T6	245
valid_sources[0x40]	187366	1			T1	8		T2	40		T3	1
valid_sources[0x41]	193182	1			T1	17		T2	65		T3	11
valid_sources[0x42]	191071	1			T1	8		T2	58		T3	5
valid_sources[0x43]	198297	1			T1	3		T2	48		T3	5
valid_sources[0x44]	215918	1			T1	1		T2	46		T3	130
valid_sources[0x45]	213220	1			T1	36		T2	63		T3	9
valid_sources[0x46]	188792	1			T1	40		T2	50		T3	110
valid_sources[0x47]	180184	1			T2	66		T3	3		T6	207
valid_sources[0x48]	190589	1			T1	8		T2	66		T3	5
valid_sources[0x49]	182624	1			T1	1		T2	53		T3	299
valid_sources[0x4a]	196776	1			T1	35		T2	51		T6	329
valid_sources[0x4b]	291216	1			T2	39		T3	8		T6	212
valid_sources[0x4c]	210976	1			T1	3		T2	52		T3	6
valid_sources[0x4d]	203601	1			T2	62		T3	109		T4	14
valid_sources[0x4e]	186973	1			T2	36		T3	12		T6	268
valid_sources[0x4f]	182631	1			T2	50		T3	203		T4	4
valid_sources[0x50]	188399	1			T1	9		T2	49		T3	107
valid_sources[0x51]	185921	1			T1	20		T2	58		T3	4
valid_sources[0x52]	179920	1			T2	38		T3	9		T4	4
valid_sources[0x53]	210358	1			T1	20		T2	46		T3	12
valid_sources[0x54]	193791	1			T2	41		T3	6		T6	274
valid_sources[0x55]	183444	1			T2	74		T3	11		T6	286
valid_sources[0x56]	186459	1			T2	56		T3	105		T6	285
valid_sources[0x57]	189147	1			T2	68		T3	1		T6	225
valid_sources[0x58]	195594	1			T1	63		T2	39		T3	3
valid_sources[0x59]	191359	1			T1	1		T2	50		T3	9
valid_sources[0x5a]	202611	1			T2	52		T3	1		T6	317
valid_sources[0x5b]	192466	1			T1	23		T2	62		T3	3
valid_sources[0x5c]	191176	1			T2	60		T3	10		T4	6
valid_sources[0x5d]	206704	1			T1	10		T2	41		T3	292
valid_sources[0x5e]	206705	1			T1	8		T2	54		T3	110
valid_sources[0x5f]	221780	1			T1	27		T2	64		T3	3
valid_sources[0x60]	192525	1			T1	21		T2	43		T3	1
valid_sources[0x61]	195892	1			T1	60		T2	50		T3	209
valid_sources[0x62]	189896	1			T2	66		T3	225		T6	225
valid_sources[0x63]	208469	1			T1	12		T2	56		T3	7
valid_sources[0x64]	214054	1			T2	87		T3	212		T4	7
valid_sources[0x65]	180508	1			T2	50		T3	5		T6	279
valid_sources[0x66]	188345	1			T1	11		T2	63		T3	8
valid_sources[0x67]	185227	1			T1	4		T2	38		T3	111
valid_sources[0x68]	197181	1			T1	28		T2	41		T3	11
valid_sources[0x69]	201706	1			T2	30		T3	6		T4	1
valid_sources[0x6a]	188993	1			T2	57		T3	117		T6	271
valid_sources[0x6b]	209843	1			T2	65		T3	6		T6	317
valid_sources[0x6c]	189503	1			T2	36		T3	5		T6	251
valid_sources[0x6d]	196804	1			T2	55		T3	110		T6	272
valid_sources[0x6e]	183881	1			T2	35		T3	5		T6	289
valid_sources[0x6f]	285945	1			T1	8		T2	79		T3	6
valid_sources[0x70]	191922	1			T2	53		T3	14		T6	255
valid_sources[0x71]	191208	1			T1	43		T2	44		T3	108
valid_sources[0x72]	297866	1			T1	17		T2	62		T3	7
valid_sources[0x73]	197054	1			T1	19		T2	38		T3	5
valid_sources[0x74]	190408	1			T1	66		T2	38		T3	2
valid_sources[0x75]	186188	1			T2	64		T3	1		T6	312
valid_sources[0x76]	203846	1			T1	63		T2	33		T3	3
valid_sources[0x77]	289122	1			T1	61		T2	52		T3	5
valid_sources[0x78]	210138	1			T1	20		T2	51		T3	5
valid_sources[0x79]	281306	1			T2	40		T3	5		T6	274
valid_sources[0x7a]	184678	1			T2	57		T3	10		T4	5
valid_sources[0x7b]	194082	1			T1	18		T2	58		T3	2
valid_sources[0x7c]	193270	1			T1	18		T2	42		T3	6
valid_sources[0x7d]	195749	1			T1	5		T2	53		T3	4
valid_sources[0x7e]	198206	1			T1	7		T2	43		T3	26
valid_sources[0x7f]	208360	1			T1	5		T2	36		T3	6
valid_sources[0x80]	200899	1			T2	55		T3	7		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9631179

1

T1

821

T2

3400

T3

4171

values[0x0]

all_enables

biggest_size

237420

1

T1

10

T2

170

T3

280

values[0x1]

all_enables

biggest_size

165503

1

T1

15

T2

147

T3

251