Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	433206463	6652	0	0
ctrl_rd_A	433206463	1137	0	0
host_fifo_config_rd_A	433206463	4571	0	0
host_nack_handler_timeout_rd_A	433206463	803	0	0
host_timeout_ctrl_rd_A	433206463	700	0	0
intr_enable_rd_A	433206463	2628	0	0
ovrd_rd_A	433206463	1593	0	0
target_fifo_config_rd_A	433206463	1020	0	0
target_id_rd_A	433206463	902	0	0
target_timeout_ctrl_rd_A	433206463	834	0	0
timeout_ctrl_rd_A	433206463	837	0	0
timing0_rd_A	433206463	856	0	0
timing1_rd_A	433206463	778	0	0
timing2_rd_A	433206463	808	0	0
timing3_rd_A	433206463	804	0	0
timing4_rd_A	433206463	817	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	6652	0	0
T74	1886	1	0	0
T108	2740	100	0	0
T109	9147	577	0	0
T116	5285	205	0	0
T117	12445	466	0	0
T126	2012	18	0	0
T127	5444	200	0	0
T132	1883	6	0	0
T133	3295	6	0	0
T134	2499	17	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	1137	0	0
T75	13190	205	0	0
T76	6195	63	0	0
T116	5285	2	0	0
T121	14080	25	0	0
T122	11078	151	0	0
T137	2673	27	0	0
T145	1682	15	0	0
T152	1893	1	0	0
T153	12690	7	0	0
T154	3784	43	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	4571	0	0
T13	135510	0	0	0
T22	354463	0	0	0
T65	22000	0	0	0
T86	301948	157	0	0
T97	0	181	0	0
T102	134931	0	0	0
T103	72656	0	0	0
T104	122736	0	0	0
T105	101928	0	0	0
T107	0	154	0	0
T110	3002	0	0	0
T115	102167	0	0	0
T155	0	138	0	0
T156	0	109	0	0
T157	0	181	0	0
T158	0	71	0	0
T159	0	99	0	0
T160	0	246	0	0
T161	0	150	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	803	0	0
T75	13190	226	0	0
T76	6195	10	0	0
T116	5285	4	0	0
T121	14080	28	0	0
T127	5444	10	0	0
T137	2673	23	0	0
T145	1682	3	0	0
T152	1893	2	0	0
T153	12690	31	0	0
T154	3784	18	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	700	0	0
T75	13190	238	0	0
T76	6195	13	0	0
T116	5285	2	0	0
T121	14080	7	0	0
T122	11078	31	0	0
T137	2673	9	0	0
T149	3863	38	0	0
T152	1893	5	0	0
T153	12690	23	0	0
T154	3784	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	2628	0	0
T31	971999	0	0	0
T32	92140	0	0	0
T33	244748	0	0	0
T40	185272	0	0	0
T42	666774	6	0	0
T43	220122	0	0	0
T64	39413	0	0	0
T68	14758	0	0	0
T71	0	31	0	0
T80	0	4	0	0
T85	17998	0	0	0
T97	0	8	0	0
T157	0	42	0	0
T160	0	10	0	0
T162	0	21	0	0
T163	0	9	0	0
T164	0	20	0	0
T165	0	18	0	0
T166	19050	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	1593	0	0
T15	238184	0	0	0
T28	64133	0	0	0
T38	2918	56	0	0
T39	0	46	0	0
T70	9312	0	0	0
T84	956851	0	0	0
T89	178531	0	0	0
T91	228866	0	0	0
T92	177876	0	0	0
T93	499876	0	0	0
T94	867	0	0	0
T167	0	26	0	0
T168	0	67	0	0
T169	0	32	0	0
T170	0	69	0	0
T171	0	55	0	0
T172	0	31	0	0
T173	0	38	0	0
T174	0	50	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	1020	0	0
T75	13190	163	0	0
T76	6195	52	0	0
T121	14080	9	0	0
T122	11078	75	0	0
T127	5444	17	0	0
T137	2673	8	0	0
T145	1682	16	0	0
T152	1893	3	0	0
T153	12690	40	0	0
T154	3784	15	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	902	0	0
T75	13190	224	0	0
T76	6195	60	0	0
T121	14080	31	0	0
T122	11078	59	0	0
T127	5444	4	0	0
T137	2673	10	0	0
T145	1682	8	0	0
T152	1893	21	0	0
T153	12690	34	0	0
T154	3784	20	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	834	0	0
T75	13190	198	0	0
T76	6195	64	0	0
T116	5285	4	0	0
T121	14080	26	0	0
T127	5444	2	0	0
T137	2673	17	0	0
T145	1682	7	0	0
T152	1893	5	0	0
T153	12690	18	0	0
T154	3784	19	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	837	0	0
T75	13190	232	0	0
T76	6195	74	0	0
T121	14080	37	0	0
T122	11078	63	0	0
T127	5444	19	0	0
T137	2673	6	0	0
T145	1682	7	0	0
T152	1893	3	0	0
T153	12690	25	0	0
T154	3784	18	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	856	0	0
T75	13190	185	0	0
T76	6195	22	0	0
T116	5285	3	0	0
T121	14080	30	0	0
T127	5444	13	0	0
T137	2673	29	0	0
T145	1682	6	0	0
T152	1893	10	0	0
T153	12690	13	0	0
T154	3784	35	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	778	0	0
T75	13190	218	0	0
T76	6195	33	0	0
T116	5285	4	0	0
T121	14080	19	0	0
T127	5444	21	0	0
T137	2673	13	0	0
T145	1682	4	0	0
T152	1893	8	0	0
T153	12690	29	0	0
T154	3784	23	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	808	0	0
T75	13190	219	0	0
T76	6195	28	0	0
T121	14080	21	0	0
T122	11078	83	0	0
T127	5444	4	0	0
T137	2673	3	0	0
T145	1682	7	0	0
T152	1893	1	0	0
T153	12690	4	0	0
T154	3784	16	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	804	0	0
T75	13190	200	0	0
T76	6195	26	0	0
T121	14080	26	0	0
T122	11078	58	0	0
T127	5444	8	0	0
T137	2673	11	0	0
T145	1682	10	0	0
T152	1893	12	0	0
T153	12690	16	0	0
T154	3784	26	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433206463	817	0	0
T75	13190	204	0	0
T76	6195	47	0	0
T116	5285	8	0	0
T121	14080	3	0	0
T127	5444	19	0	0
T137	2673	9	0	0
T145	1682	7	0	0
T152	1893	5	0	0
T153	12690	17	0	0
T154	3784	7	0	0