Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

160632

1

T1

80

T2

960

T10

960

ack

14013

1

T1

1

T2

30

T10

30

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	630	1			T1	2		T2	8		T10	1
high	35984	1			T1	12		T2	206		T10	206
med	65024	1			T1	34		T2	375		T10	374
sml	72317	1			T1	31		T2	396		T10	404
all_zero	690	1			T1	2		T2	5		T10	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87192

1

T1

35

T2

502

T10

468

auto[1]

87453

1

T1

46

T2

488

T10

522

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119662

1

T1

53

T2

672

T10

645

auto[1]

54983

1

T1

28

T2

318

T10

345

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167218

1

T1

81

T2

976

T10

976

auto[1]

7427

1

T2

14

T10

14

T40

14

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164860

1

T1

80

T2

961

T10

961

auto[1]

9785

1

T1

1

T2

29

T10

29

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165709

1

T1

80

T2

962

T10

962

auto[1]

8936

1

T1

1

T2

28

T10

28

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87192

1

T1

35

T2

502

T10

468

auto[1]

87453

1

T1

46

T2

488

T10

522

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119662

1

T1

53

T2

672

T10

645

auto[1]

54983

1

T1

28

T2

318

T10

345

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167218

1

T1

81

T2

976

T10

976

auto[1]

7427

1

T2

14

T10

14

T40

14

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164860

1

T1

80

T2

961

T10

961

auto[1]

9785

1

T1

1

T2

29

T10

29

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165709

1

T1

80

T2

962

T10

962

auto[1]

8936

1

T1

1

T2

28

T10

28

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T84

1

T180

1

T247

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T248

1

T249

1

T201

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T250

1

T251

1

T199

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

296

1

T2

2

T10

4

T40

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

136

1

T10

2

T44

1

T252

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

134

1

T2

1

T44

1

T66

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

503

1

T2

4

T10

1

T40

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

269

1

T2

3

T10

3

T40

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

265

1

T2

2

T10

1

T44

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

551

1

T2

3

T10

2

T40

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

249

1

T2

1

T10

1

T40

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

230

1

T2

1

T40

2

T44

8

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T253

1

T254

1

T201

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T250

1

T255

1

T256

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T257

1

T200

1

T227

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50854	1			T1	21		T2	311		T10	281
write_address_byte	9785	1			T1	1		T2	29		T10	29
read_with_ack	2075	1			T80	8		T69	4		T44	12
read_with_nack	5352	1			T2	14		T10	14		T40	14
stop_byte	8936	1			T1	1		T2	28		T10	28
write_address_byte_nak	5004	1			T2	26		T10	26		T40	22
data_byte_nack	160632	1			T1	80		T2	960		T10	960
stop_byte_nack	5448	1			T1	1		T2	25		T10	25
nakok_byte_nack	80480	1			T1	46		T2	472		T10	512
nakok_addr_byte_nack	2559	1			T2	13		T10	17		T40	15