Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37570463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8388112

1

T1

529

T2

11580

T3

264

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	45130911	1			T1	1221		T2	47873		T3	839
values[0x0]	413052	1			T1	44		T2	602		T3	162
values[0x1]	414612	1			T1	50		T2	591		T3	185

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26948569	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19010006

1

T1

702

T2

22342

T3

531

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	159522	1			T2	5		T3	7		T5	1
valid_sources[0x01]	171004	1			T2	2		T3	4		T5	4
valid_sources[0x02]	180062	1			T2	2		T3	2		T5	2
valid_sources[0x03]	158296	1			T2	1468		T3	6		T5	4
valid_sources[0x04]	145426	1			T2	4		T3	6		T5	6
valid_sources[0x05]	150546	1			T2	1675		T3	4		T5	4
valid_sources[0x06]	167006	1			T2	2		T3	6		T5	2
valid_sources[0x07]	160534	1			T2	5		T3	2		T5	1
valid_sources[0x08]	364054	1			T2	7		T3	10		T6	3
valid_sources[0x09]	152583	1			T2	3		T3	4		T5	1
valid_sources[0x0a]	162211	1			T2	2053		T3	1		T5	2
valid_sources[0x0b]	159229	1			T2	4		T3	4		T5	6
valid_sources[0x0c]	152032	1			T2	6		T3	5		T6	8
valid_sources[0x0d]	162442	1			T2	1509		T3	5		T6	5
valid_sources[0x0e]	184383	1			T2	4		T3	3		T5	3
valid_sources[0x0f]	155619	1			T2	5		T3	3		T5	2
valid_sources[0x10]	157555	1			T2	3		T3	5		T6	8
valid_sources[0x11]	154389	1			T2	3		T3	4		T5	1
valid_sources[0x12]	158119	1			T2	2		T3	1		T6	5
valid_sources[0x13]	162099	1			T2	4		T3	4		T6	9
valid_sources[0x14]	162891	1			T2	3		T3	1		T6	12
valid_sources[0x15]	179629	1			T2	4		T3	6		T5	2
valid_sources[0x16]	161789	1			T2	1614		T3	3		T5	1
valid_sources[0x17]	171685	1			T2	8		T3	7		T6	7
valid_sources[0x18]	226870	1			T2	3		T3	1		T5	2
valid_sources[0x19]	161620	1			T2	4		T3	5		T5	2
valid_sources[0x1a]	171286	1			T2	3		T3	4		T5	1
valid_sources[0x1b]	161266	1			T2	8		T3	3		T6	8
valid_sources[0x1c]	155071	1			T2	5		T3	5		T5	4
valid_sources[0x1d]	147937	1			T2	5		T3	9		T5	1
valid_sources[0x1e]	174399	1			T2	1592		T3	5		T5	1
valid_sources[0x1f]	159098	1			T2	6		T3	4		T5	9
valid_sources[0x20]	152878	1			T2	1708		T3	4		T5	1
valid_sources[0x21]	165446	1			T2	4		T3	1		T5	1
valid_sources[0x22]	181198	1			T2	193		T3	14		T5	2
valid_sources[0x23]	159542	1			T2	3		T3	5		T5	1
valid_sources[0x24]	236455	1			T2	1319		T3	2		T6	10
valid_sources[0x25]	170672	1			T2	4		T3	4		T5	3
valid_sources[0x26]	185195	1			T2	2		T3	7		T5	1
valid_sources[0x27]	158916	1			T2	8		T3	2		T5	3
valid_sources[0x28]	157509	1			T2	2		T3	1		T5	2
valid_sources[0x29]	204070	1			T2	1		T3	3		T5	5
valid_sources[0x2a]	151991	1			T2	2		T3	3		T5	4
valid_sources[0x2b]	168123	1			T2	5		T3	5		T5	2
valid_sources[0x2c]	164126	1			T2	2		T3	2		T6	9
valid_sources[0x2d]	158934	1			T2	7		T3	4		T5	1
valid_sources[0x2e]	160296	1			T2	4		T3	1		T5	3
valid_sources[0x2f]	160185	1			T2	3		T3	9		T5	3
valid_sources[0x30]	160982	1			T2	9		T3	2		T5	4
valid_sources[0x31]	160478	1			T2	3		T3	7		T5	2
valid_sources[0x32]	158404	1			T2	4		T3	6		T5	5
valid_sources[0x33]	146606	1			T2	4		T3	4		T5	3
valid_sources[0x34]	224695	1			T2	4		T3	8		T5	5
valid_sources[0x35]	152680	1			T2	2		T3	5		T5	5
valid_sources[0x36]	249831	1			T2	8		T3	8		T6	8
valid_sources[0x37]	218584	1			T2	3		T3	7		T4	1
valid_sources[0x38]	173731	1			T2	5		T3	6		T5	2
valid_sources[0x39]	162537	1			T2	5		T3	4		T5	1
valid_sources[0x3a]	161741	1			T2	5		T3	3		T5	3
valid_sources[0x3b]	193991	1			T2	3		T3	7		T5	2
valid_sources[0x3c]	174530	1			T2	5		T3	2		T5	3
valid_sources[0x3d]	153262	1			T2	1032		T3	2		T5	1
valid_sources[0x3e]	166374	1			T2	1		T3	7		T6	2
valid_sources[0x3f]	160042	1			T2	6		T3	6		T5	3
valid_sources[0x40]	158852	1			T2	5		T3	4		T5	5
valid_sources[0x41]	160665	1			T2	1		T3	8		T5	2
valid_sources[0x42]	265701	1			T2	4		T3	10		T5	2
valid_sources[0x43]	163653	1			T2	7		T3	6		T5	6
valid_sources[0x44]	161887	1			T2	4		T3	7		T6	6
valid_sources[0x45]	166553	1			T2	4794		T3	6		T5	3
valid_sources[0x46]	164373	1			T2	4		T3	7		T5	8
valid_sources[0x47]	180626	1			T2	5		T3	4		T5	3
valid_sources[0x48]	243881	1			T2	6		T3	6		T5	2
valid_sources[0x49]	206683	1			T2	2		T3	11		T5	1
valid_sources[0x4a]	164914	1			T2	1038		T3	4		T5	1
valid_sources[0x4b]	166965	1			T2	5		T3	8		T5	1
valid_sources[0x4c]	151461	1			T2	2		T3	7		T4	1
valid_sources[0x4d]	167438	1			T1	1315		T2	5		T3	5
valid_sources[0x4e]	163138	1			T2	4		T3	2		T5	4
valid_sources[0x4f]	167612	1			T2	1393		T3	4		T6	4
valid_sources[0x50]	163586	1			T2	2		T3	4		T5	4
valid_sources[0x51]	163499	1			T2	7		T3	6		T5	2
valid_sources[0x52]	145388	1			T2	3		T3	5		T5	1
valid_sources[0x53]	186429	1			T2	4		T3	4		T6	7
valid_sources[0x54]	153955	1			T2	3		T3	3		T5	3
valid_sources[0x55]	263304	1			T2	3		T3	5		T5	1
valid_sources[0x56]	162683	1			T2	2		T3	4		T5	2
valid_sources[0x57]	195696	1			T2	3		T3	4		T5	2
valid_sources[0x58]	293627	1			T2	1		T3	3		T5	2
valid_sources[0x59]	160493	1			T2	3		T3	1		T5	1
valid_sources[0x5a]	152847	1			T2	4		T3	3		T5	1
valid_sources[0x5b]	151742	1			T2	8		T3	8		T5	7
valid_sources[0x5c]	172543	1			T2	2		T3	4		T5	2
valid_sources[0x5d]	255390	1			T3	2		T6	15		T7	2
valid_sources[0x5e]	153421	1			T2	1131		T3	2		T5	2
valid_sources[0x5f]	152063	1			T2	1		T3	8		T5	2
valid_sources[0x60]	166844	1			T2	5		T3	5		T5	5
valid_sources[0x61]	157858	1			T2	5		T3	2		T5	1
valid_sources[0x62]	150337	1			T2	59		T3	4		T5	6
valid_sources[0x63]	203448	1			T2	4		T3	5		T6	7
valid_sources[0x64]	150538	1			T2	4		T3	7		T5	6
valid_sources[0x65]	151672	1			T2	10		T3	5		T5	3
valid_sources[0x66]	255018	1			T2	6		T3	6		T5	5
valid_sources[0x67]	196471	1			T2	3		T3	5		T4	1
valid_sources[0x68]	155049	1			T2	656		T3	6		T5	4
valid_sources[0x69]	157895	1			T2	6		T3	2		T5	3
valid_sources[0x6a]	155312	1			T2	4		T3	2		T6	15
valid_sources[0x6b]	160152	1			T2	5		T3	3		T5	5
valid_sources[0x6c]	164574	1			T2	3		T3	6		T5	5
valid_sources[0x6d]	159368	1			T2	4		T6	11		T7	1
valid_sources[0x6e]	150591	1			T2	3		T3	3		T5	5
valid_sources[0x6f]	152836	1			T2	1		T3	5		T6	8
valid_sources[0x70]	164906	1			T2	2		T3	2		T5	2
valid_sources[0x71]	150302	1			T2	3		T3	3		T4	1
valid_sources[0x72]	159603	1			T2	7		T3	4		T5	3
valid_sources[0x73]	172569	1			T2	5		T3	2		T5	3
valid_sources[0x74]	154657	1			T2	4		T3	5		T5	3
valid_sources[0x75]	152244	1			T2	2		T3	2		T5	2
valid_sources[0x76]	159125	1			T2	1		T3	2		T5	2
valid_sources[0x77]	186150	1			T2	3		T3	3		T5	1
valid_sources[0x78]	174443	1			T2	1790		T3	6		T5	3
valid_sources[0x79]	148098	1			T2	2		T3	3		T6	11
valid_sources[0x7a]	150259	1			T2	4		T3	7		T5	2
valid_sources[0x7b]	169890	1			T2	2		T3	4		T6	12
valid_sources[0x7c]	212762	1			T2	5		T3	3		T5	2
valid_sources[0x7d]	157761	1			T2	2		T3	3		T5	2
valid_sources[0x7e]	164410	1			T2	5		T3	3		T5	1
valid_sources[0x7f]	184754	1			T2	1		T3	7		T6	5
valid_sources[0x80]	155578	1			T2	2		T3	6		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8018385

1

T1

491

T2

11004

T3

145

values[0x0]

all_enables

biggest_size

216313

1

T1

23

T2

342

T3

72

values[0x1]

all_enables

biggest_size

153414

1

T1

15

T2

234

T3

47