Unified Coverage Report :: Group :: i2c_env_pkg::i2c_acq_fifo_cg

Group : i2c_env_pkg::i2c_acq_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.acq_fifo_cg	95.83	1	100	1	64	64

---

Group Instance : i2c_env_pkg.acq_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.acq_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	13	1	12	92.31

Variables for Group Instance i2c_env_pkg.acq_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_abyte	5	0	5	100.00	100	1	1	0
cp_action	4	0	4	100.00	100	1	1	0
cp_request_type	2	0	2	100.00	100	1	1	0
cp_target_read_ack_nack	0	0	0				1	0

Crosses for Group Instance i2c_env_pkg.acq_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_abyte_X_cp_action	13	1	12	92.31	100	1	1	0

Summary for Variable cp_abyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_abyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	896	1			T6	2		T32	2		T13	3
high	55542	1			T3	50		T5	20		T6	207
med	104267	1			T3	80		T5	61		T6	277
sml	102948	1			T3	147		T5	33		T6	193
all_zero	1216	1			T6	5		T9	2		T11	1

---

Summary for Variable cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
rstart	42205	1			T3	38		T5	22		T6	120
start	12923	1			T3	12		T5	6		T6	36
stop	12933	1			T3	12		T5	12		T6	30
none	196808	1			T3	215		T5	74		T6	498

---

Summary for Variable cp_request_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_request_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

write

5566

1

T3

4

T5

2

T6

16

read

7357

1

T3

8

T5

4

T6

20

---

Summary for Variable cp_target_read_ack_nack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	0	0	0

User Defined Bins for cp_target_read_ack_nack

Excluded/Illegal bins

NAME	COUNT	STATUS
read_req_nack_before_rstart	0	Excluded
read_req_ack_before_stop	0	Excluded
read_req_nack_before_stop	0	Excluded
read_req_ack_before_rstart	0	Excluded

---

Summary for Cross cp_abyte_X_cp_action

Samples crossed: cp_abyte cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	1	12	92.31	1
Automatically Generated Cross Bins	10	1	9	90.00	1
User Defined Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for cp_abyte_X_cp_action

Uncovered bins

cp_abyte	cp_action	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[stop]	0	1	1

Covered bins

cp_abyte	cp_action	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	rstart	97	1			T243	11		T85	21		T244	3
high	rstart	8724	1			T6	70		T11	15		T13	57
high	stop	2684	1			T3	3		T5	5		T6	5
med	rstart	17183	1			T5	22		T6	50		T7	14
med	stop	5081	1			T3	7		T5	3		T6	11
sml	rstart	15937	1			T3	38		T7	6		T8	43
sml	stop	5073	1			T3	2		T5	4		T6	12
all_zero	rstart	264	1			T27	2		T243	11		T245	32
all_zero	stop	95	1			T6	2		T13	3		T246	1

User Defined Cross Bins for cp_abyte_X_cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
write_address_byte	12923	1			T3	12		T5	6		T6	36
read_address_byte	12923	1			T3	12		T5	6		T6	36
data_byte	196808	1			T3	215		T5	74		T6	498