Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	390326642	7560	0	0
ctrl_rd_A	390326642	1696	0	0
host_fifo_config_rd_A	390326642	6619	0	0
host_nack_handler_timeout_rd_A	390326642	1161	0	0
host_timeout_ctrl_rd_A	390326642	1116	0	0
intr_enable_rd_A	390326642	3552	0	0
ovrd_rd_A	390326642	2075	0	0
target_fifo_config_rd_A	390326642	1286	0	0
target_id_rd_A	390326642	1664	0	0
target_timeout_ctrl_rd_A	390326642	1163	0	0
timeout_ctrl_rd_A	390326642	1056	0	0
timing0_rd_A	390326642	1114	0	0
timing1_rd_A	390326642	1300	0	0
timing2_rd_A	390326642	1149	0	0
timing3_rd_A	390326642	1148	0	0
timing4_rd_A	390326642	1173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	7560	0	0
T82	2188	6	0	0
T112	8813	393	0	0
T127	6206	144	0	0
T129	9551	3	0	0
T130	3280	13	0	0
T131	15145	478	0	0
T144	3193	9	0	0
T151	1960	6	0	0
T152	2213	6	0	0
T153	2289	10	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1696	0	0
T82	2188	13	0	0
T112	8813	11	0	0
T131	15145	41	0	0
T132	16223	27	0	0
T144	3193	46	0	0
T153	2289	11	0	0
T156	2017	8	0	0
T170	2175	23	0	0
T175	2177	2	0	0
T176	4416	3	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	6619	0	0
T30	182397	0	0	0
T31	195149	0	0	0
T45	779291	0	0	0
T126	0	95	0	0
T177	224684	80	0	0
T178	0	110	0	0
T179	0	102	0	0
T180	0	251	0	0
T181	0	232	0	0
T182	0	194	0	0
T183	0	361	0	0
T184	0	162	0	0
T185	0	222	0	0
T186	115202	0	0	0
T187	33200	0	0	0
T188	106489	0	0	0
T189	271794	0	0	0
T190	140418	0	0	0
T191	900070	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1161	0	0
T82	2188	3	0	0
T112	8813	48	0	0
T131	15145	28	0	0
T132	16223	28	0	0
T144	3193	22	0	0
T153	2289	12	0	0
T170	2175	9	0	0
T175	2177	5	0	0
T176	4416	8	0	0
T192	2055	9	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1116	0	0
T82	2188	8	0	0
T112	8813	11	0	0
T131	15145	41	0	0
T132	16223	37	0	0
T144	3193	22	0	0
T153	2289	2	0	0
T170	2175	14	0	0
T175	2177	3	0	0
T176	4416	7	0	0
T193	1707	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	3552	0	0
T30	182397	0	0	0
T31	195149	0	0	0
T45	779291	18	0	0
T49	489158	0	0	0
T56	486503	0	0	0
T190	140418	0	0	0
T191	900070	0	0	0
T194	0	18	0	0
T195	0	33	0	0
T196	0	37	0	0
T197	0	18	0	0
T198	0	32	0	0
T199	0	22	0	0
T200	0	17	0	0
T201	0	26	0	0
T202	0	14	0	0
T203	794819	0	0	0
T204	10005	0	0	0
T205	268003	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	2075	0	0
T13	717324	0	0	0
T32	80745	0	0	0
T33	127758	0	0	0
T35	2897	59	0	0
T43	82300	0	0	0
T60	145463	0	0	0
T61	89797	0	0	0
T65	121399	0	0	0
T154	100417	0	0	0
T206	0	25	0	0
T207	0	25	0	0
T208	0	32	0	0
T209	0	54	0	0
T210	0	37	0	0
T211	0	52	0	0
T212	0	54	0	0
T213	0	64	0	0
T214	0	52	0	0
T215	39472	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1286	0	0
T112	8813	22	0	0
T131	15145	42	0	0
T132	16223	21	0	0
T144	3193	25	0	0
T153	2289	3	0	0
T156	2017	7	0	0
T170	2175	20	0	0
T175	2177	10	0	0
T176	4416	11	0	0
T192	2055	15	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1664	0	0
T82	2188	12	0	0
T112	8813	4	0	0
T131	15145	27	0	0
T132	16223	46	0	0
T144	3193	21	0	0
T153	2289	17	0	0
T170	2175	11	0	0
T175	2177	7	0	0
T176	4416	2	0	0
T192	2055	9	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1163	0	0
T82	2188	12	0	0
T131	15145	31	0	0
T132	16223	38	0	0
T144	3193	19	0	0
T153	2289	5	0	0
T156	2017	3	0	0
T170	2175	23	0	0
T175	2177	4	0	0
T192	2055	10	0	0
T193	1707	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1056	0	0
T112	8813	9	0	0
T131	15145	19	0	0
T132	16223	39	0	0
T144	3193	15	0	0
T153	2289	18	0	0
T170	2175	13	0	0
T175	2177	3	0	0
T193	1707	2	0	0
T216	2540	3	0	0
T217	13377	27	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1114	0	0
T82	2188	10	0	0
T112	8813	16	0	0
T131	15145	17	0	0
T132	16223	12	0	0
T144	3193	39	0	0
T153	2289	14	0	0
T156	2017	2	0	0
T170	2175	6	0	0
T175	2177	5	0	0
T176	4416	3	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1300	0	0
T112	8813	16	0	0
T131	15145	54	0	0
T132	16223	33	0	0
T144	3193	15	0	0
T153	2289	17	0	0
T170	2175	10	0	0
T175	2177	5	0	0
T176	4416	1	0	0
T192	2055	12	0	0
T216	2540	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1149	0	0
T112	8813	8	0	0
T131	15145	20	0	0
T132	16223	36	0	0
T144	3193	23	0	0
T153	2289	14	0	0
T156	2017	16	0	0
T170	2175	6	0	0
T175	2177	4	0	0
T192	2055	5	0	0
T193	1707	4	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1148	0	0
T82	2188	12	0	0
T112	8813	9	0	0
T131	15145	29	0	0
T132	16223	43	0	0
T144	3193	22	0	0
T153	2289	8	0	0
T170	2175	7	0	0
T192	2055	9	0	0
T193	1707	6	0	0
T216	2540	8	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390326642	1173	0	0
T82	2188	18	0	0
T112	8813	10	0	0
T131	15145	27	0	0
T132	16223	24	0	0
T144	3193	20	0	0
T153	2289	16	0	0
T156	2017	2	0	0
T170	2175	16	0	0
T175	2177	1	0	0
T192	2055	3	0	0