Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

179664

1

T2

256

T7

105

T8

136

ack

14944

1

T2

3

T7

40

T8

26

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	785	1			T2	1		T7	4		T8	1
high	39767	1			T2	57		T7	27		T8	29
med	72996	1			T2	95		T7	45		T8	65
sml	80257	1			T2	104		T7	69		T8	67
all_zero	803	1			T2	2		T9	2		T43	4

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97070

1

T2

125

T7

71

T8

79

auto[1]

97538

1

T2

134

T7

74

T8

83

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133370

1

T2

160

T7

111

T8

121

auto[1]

61238

1

T2

99

T7

34

T8

41

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

186623

1

T2

258

T7

128

T8

151

auto[1]

7985

1

T2

1

T7

17

T8

11

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184220

1

T2

257

T7

110

T8

139

auto[1]

10388

1

T2

2

T7

35

T8

23

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185127

1

T2

258

T7

111

T8

140

auto[1]

9481

1

T2

1

T7

34

T8

22

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97070

1

T2

125

T7

71

T8

79

auto[1]

97538

1

T2

134

T7

74

T8

83

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133370

1

T2

160

T7

111

T8

121

auto[1]

61238

1

T2

99

T7

34

T8

41

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

186623

1

T2

258

T7

128

T8

151

auto[1]

7985

1

T2

1

T7

17

T8

11

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184220

1

T2

257

T7

110

T8

139

auto[1]

10388

1

T2

2

T7

35

T8

23

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185127

1

T2

258

T7

111

T8

140

auto[1]

9481

1

T2

1

T7

34

T8

22

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T68

1

T65

1

T239

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T240

1

T241

1

T242

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T243

1

T244

1

T245

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

277

1

T7

2

T68

5

T55

4

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

169

1

T44

1

T45

1

T68

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

161

1

T7

1

T45

2

T68

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

620

1

T7

2

T68

9

T55

7

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

282

1

T7

3

T8

1

T43

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

287

1

T7

1

T8

3

T43

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

595

1

T7

1

T8

2

T43

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

286

1

T7

1

T8

1

T61

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

277

1

T7

2

T8

1

T61

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

12

1

T167

1

T246

1

T48

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T68

1

T195

1

T247

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T59

1

T248

1

T165

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	57229	1			T2	80		T7	21		T8	38
write_address_byte	10388	1			T2	2		T7	35		T8	23
read_with_ack	2274	1			T2	1		T9	3		T40	12
read_with_nack	5711	1			T7	17		T8	11		T9	3
stop_byte	9481	1			T2	1		T7	34		T8	22
write_address_byte_nak	5452	1			T7	24		T8	16		T9	8
data_byte_nack	179664	1			T2	256		T7	105		T8	136
stop_byte_nack	5787	1			T2	1		T7	23		T8	17
nakok_byte_nack	90008	1			T2	134		T7	53		T8	70
nakok_addr_byte_nack	2758	1			T7	5		T8	8		T9	5