Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41445658	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9666994

1

T1

277

T2

20308

T3

446

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50179314	1			T1	1122		T2	111528		T3	1023
values[0x0]	465981	1			T1	15		T2	1671		T3	321
values[0x1]	467357	1			T1	11		T2	1534		T3	291

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29461459	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21651193

1

T1

491

T2

48972

T3

788

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	181290	1			T1	3		T2	450		T6	1
valid_sources[0x01]	189779	1			T1	7		T2	454		T6	2
valid_sources[0x02]	180175	1			T1	5		T2	438		T3	5
valid_sources[0x03]	188226	1			T1	4		T2	431		T3	4
valid_sources[0x04]	288096	1			T1	4		T2	441		T3	3
valid_sources[0x05]	182062	1			T1	6		T2	458		T6	6
valid_sources[0x06]	174789	1			T1	3		T2	467		T6	12
valid_sources[0x07]	180428	1			T1	3		T2	415		T3	24
valid_sources[0x08]	185125	1			T1	4		T2	438		T6	1
valid_sources[0x09]	175562	1			T1	5		T2	447		T7	122
valid_sources[0x0a]	407971	1			T1	5		T2	423		T6	2
valid_sources[0x0b]	176253	1			T1	6		T2	455		T6	9
valid_sources[0x0c]	182956	1			T1	3		T2	467		T6	4
valid_sources[0x0d]	248514	1			T1	4		T2	430		T5	1
valid_sources[0x0e]	235170	1			T1	4		T2	467		T6	5
valid_sources[0x0f]	177346	1			T1	2		T2	496		T3	15
valid_sources[0x10]	180800	1			T1	1		T2	413		T6	9
valid_sources[0x11]	183291	1			T1	2		T2	445		T4	1
valid_sources[0x12]	173987	1			T1	5		T2	440		T4	1
valid_sources[0x13]	177535	1			T1	3		T2	421		T6	5
valid_sources[0x14]	348526	1			T1	5		T2	485		T3	11
valid_sources[0x15]	222136	1			T1	5		T2	478		T3	7
valid_sources[0x16]	179682	1			T1	5		T2	458		T4	2
valid_sources[0x17]	179997	1			T1	2		T2	460		T4	1
valid_sources[0x18]	170941	1			T1	5		T2	473		T3	28
valid_sources[0x19]	275034	1			T1	5		T2	441		T3	10
valid_sources[0x1a]	168389	1			T1	4		T2	444		T6	9
valid_sources[0x1b]	183206	1			T1	7		T2	452		T4	3
valid_sources[0x1c]	183055	1			T1	7		T2	446		T6	5
valid_sources[0x1d]	189245	1			T1	7		T2	396		T4	1
valid_sources[0x1e]	178056	1			T1	5		T2	457		T3	2
valid_sources[0x1f]	189074	1			T1	4		T2	482		T3	30
valid_sources[0x20]	181076	1			T1	4		T2	458		T3	36
valid_sources[0x21]	355038	1			T1	5		T2	428		T3	15
valid_sources[0x22]	182366	1			T1	6		T2	465		T3	13
valid_sources[0x23]	164745	1			T1	5		T2	424		T6	14
valid_sources[0x24]	171379	1			T1	5		T2	483		T4	1
valid_sources[0x25]	178077	1			T1	6		T2	415		T6	13
valid_sources[0x26]	357521	1			T1	3		T2	416		T3	11
valid_sources[0x27]	190976	1			T1	2		T2	400		T4	1
valid_sources[0x28]	175708	1			T1	5		T2	429		T6	5
valid_sources[0x29]	255055	1			T1	3		T2	454		T4	1
valid_sources[0x2a]	192383	1			T1	3		T2	446		T3	22
valid_sources[0x2b]	186863	1			T1	4		T2	462		T6	11
valid_sources[0x2c]	206615	1			T1	3		T2	422		T3	7
valid_sources[0x2d]	201059	1			T1	8		T2	426		T6	3
valid_sources[0x2e]	183909	1			T1	3		T2	427		T4	2
valid_sources[0x2f]	341713	1			T1	7		T2	453		T3	2
valid_sources[0x30]	296439	1			T1	7		T2	478		T6	3
valid_sources[0x31]	189227	1			T1	4		T2	478		T3	49
valid_sources[0x32]	178321	1			T1	7		T2	450		T4	1
valid_sources[0x33]	190066	1			T1	6		T2	479		T6	3
valid_sources[0x34]	190719	1			T1	1		T2	407		T3	19
valid_sources[0x35]	178906	1			T1	2		T2	450		T3	17
valid_sources[0x36]	191273	1			T1	3		T2	409		T3	5
valid_sources[0x37]	189013	1			T1	10		T2	439		T3	8
valid_sources[0x38]	198922	1			T1	9		T2	428		T4	2
valid_sources[0x39]	174800	1			T1	4		T2	478		T3	25
valid_sources[0x3a]	191104	1			T1	3		T2	447		T6	9
valid_sources[0x3b]	276444	1			T1	2		T2	474		T4	1
valid_sources[0x3c]	185215	1			T1	4		T2	491		T6	2
valid_sources[0x3d]	276364	1			T1	4		T2	421		T4	1
valid_sources[0x3e]	174253	1			T1	2		T2	431		T6	4
valid_sources[0x3f]	164963	1			T1	6		T2	422		T6	1
valid_sources[0x40]	181167	1			T1	4		T2	473		T6	5
valid_sources[0x41]	180711	1			T1	1		T2	506		T3	39
valid_sources[0x42]	191977	1			T1	3		T2	433		T4	1
valid_sources[0x43]	201130	1			T1	3		T2	454		T6	11
valid_sources[0x44]	211887	1			T1	2		T2	502		T6	7
valid_sources[0x45]	157337	1			T1	5		T2	421		T6	6
valid_sources[0x46]	202160	1			T1	1		T2	477		T6	6
valid_sources[0x47]	175271	1			T1	2		T2	464		T6	3
valid_sources[0x48]	171851	1			T1	1		T2	437		T3	7
valid_sources[0x49]	171726	1			T1	6		T2	425		T6	4
valid_sources[0x4a]	211183	1			T1	3		T2	449		T3	9
valid_sources[0x4b]	188108	1			T1	8		T2	415		T3	5
valid_sources[0x4c]	178038	1			T1	2		T2	446		T3	4
valid_sources[0x4d]	180171	1			T1	3		T2	432		T6	9
valid_sources[0x4e]	180458	1			T1	8		T2	455		T6	5
valid_sources[0x4f]	189378	1			T1	5		T2	394		T6	4
valid_sources[0x50]	175396	1			T1	4		T2	441		T3	11
valid_sources[0x51]	184021	1			T1	5		T2	458		T4	1
valid_sources[0x52]	182839	1			T1	6		T2	441		T3	16
valid_sources[0x53]	200595	1			T1	7		T2	426		T3	6
valid_sources[0x54]	175753	1			T1	4		T2	422		T3	15
valid_sources[0x55]	175048	1			T1	3		T2	445		T6	6
valid_sources[0x56]	205425	1			T1	2		T2	456		T6	2
valid_sources[0x57]	164424	1			T1	8		T2	481		T3	28
valid_sources[0x58]	179833	1			T1	7		T2	426		T6	4
valid_sources[0x59]	192845	1			T1	3		T2	451		T4	1
valid_sources[0x5a]	185281	1			T1	2		T2	470		T6	2
valid_sources[0x5b]	176663	1			T1	4		T2	434		T3	12
valid_sources[0x5c]	175056	1			T1	7		T2	479		T3	9
valid_sources[0x5d]	171651	1			T1	8		T2	515		T6	4
valid_sources[0x5e]	171723	1			T1	5		T2	432		T6	6
valid_sources[0x5f]	189031	1			T1	1		T2	429		T6	1
valid_sources[0x60]	172015	1			T1	7		T2	417		T6	8
valid_sources[0x61]	178667	1			T1	8		T2	428		T7	121
valid_sources[0x62]	167155	1			T1	5		T2	409		T6	1
valid_sources[0x63]	186106	1			T1	4		T2	467		T3	2
valid_sources[0x64]	180059	1			T1	6		T2	423		T3	5
valid_sources[0x65]	174119	1			T1	4		T2	452		T3	19
valid_sources[0x66]	180760	1			T1	5		T2	428		T3	11
valid_sources[0x67]	209204	1			T1	3		T2	447		T3	26
valid_sources[0x68]	190332	1			T1	7		T2	451		T3	23
valid_sources[0x69]	183957	1			T1	9		T2	438		T6	9
valid_sources[0x6a]	180706	1			T1	8		T2	432		T4	1
valid_sources[0x6b]	172085	1			T1	3		T2	462		T3	20
valid_sources[0x6c]	172797	1			T1	5		T2	453		T3	42
valid_sources[0x6d]	182508	1			T1	6		T2	468		T4	1
valid_sources[0x6e]	187512	1			T1	2		T2	448		T3	4
valid_sources[0x6f]	248005	1			T1	8		T2	474		T3	26
valid_sources[0x70]	175699	1			T1	3		T2	423		T4	4
valid_sources[0x71]	181947	1			T1	7		T2	482		T3	1
valid_sources[0x72]	638113	1			T1	3		T2	456		T6	7
valid_sources[0x73]	197136	1			T1	3		T2	419		T3	12
valid_sources[0x74]	180650	1			T1	3		T2	422		T6	14
valid_sources[0x75]	190779	1			T1	3		T2	427		T3	8
valid_sources[0x76]	171722	1			T1	4		T2	414		T3	12
valid_sources[0x77]	185297	1			T1	4		T2	486		T4	1
valid_sources[0x78]	182461	1			T1	1		T2	466		T3	10
valid_sources[0x79]	171968	1			T1	4		T2	447		T4	1
valid_sources[0x7a]	196452	1			T1	1		T2	472		T6	3
valid_sources[0x7b]	171700	1			T1	10		T2	409		T3	32
valid_sources[0x7c]	192586	1			T1	3		T2	430		T4	2
valid_sources[0x7d]	179480	1			T1	5		T2	503		T4	1
valid_sources[0x7e]	183612	1			T1	5		T2	482		T3	15
valid_sources[0x7f]	174627	1			T1	4		T2	428		T3	11
valid_sources[0x80]	195125	1			T1	8		T2	442		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9258633

1

T1

256

T2

19193

T3

203

values[0x0]

all_enables

biggest_size

241401

1

T1

12

T2

761

T3

149

values[0x1]

all_enables

biggest_size

166960

1

T1

9

T2

354

T3

94