Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Module :
i2c_fifo_sync_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 43 | 84.31 |
Logical | 51 | 43 | 84.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T41,T42 |
1 | 1 | Covered | T2,T3,T4 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T52,T53,T49 |
1 | 1 | Covered | T2,T3,T4 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T2,T3,T4 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T6 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T4 |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T34,T52,T53 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T34,T52,T53 |
1 | Covered | T2,T3,T4 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T34,T52,T53 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T6 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T6 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T6 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T4 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T4 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T6,T40 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T6,T40 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T40 |
Branch Coverage for Module :
i2c_fifo_sync_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T2,T3,T6 |
1 |
0 |
- |
Covered |
T2,T3,T4 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
i2c_fifo_sync_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5236 |
5236 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5236 |
5236 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1680578756 |
1679886740 |
0 |
0 |
T1 |
721396 |
721192 |
0 |
0 |
T2 |
408164 |
408132 |
0 |
0 |
T3 |
638416 |
638084 |
0 |
0 |
T4 |
43824 |
43508 |
0 |
0 |
T5 |
2916 |
2648 |
0 |
0 |
T6 |
592080 |
591700 |
0 |
0 |
T7 |
261828 |
261452 |
0 |
0 |
T8 |
163168 |
162808 |
0 |
0 |
T9 |
179028 |
178824 |
0 |
0 |
T10 |
4140 |
3804 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1680578756 |
1318520495 |
0 |
0 |
T1 |
721396 |
544535 |
0 |
0 |
T2 |
408164 |
857115 |
0 |
0 |
T3 |
638416 |
525713 |
0 |
0 |
T4 |
43824 |
37626 |
0 |
0 |
T5 |
2916 |
2648 |
0 |
0 |
T6 |
592080 |
395894 |
0 |
0 |
T7 |
261828 |
248710 |
0 |
0 |
T8 |
163168 |
143499 |
0 |
0 |
T9 |
179028 |
156654 |
0 |
0 |
T10 |
4140 |
3804 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1680578756 |
30500775 |
0 |
0 |
T2 |
102041 |
346414 |
0 |
0 |
T3 |
159604 |
0 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
0 |
0 |
0 |
T7 |
65457 |
0 |
0 |
0 |
T8 |
40792 |
0 |
0 |
0 |
T9 |
44757 |
0 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T15 |
207983 |
21 |
0 |
0 |
T21 |
0 |
22 |
0 |
0 |
T22 |
42779 |
0 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
169826 |
7362 |
0 |
0 |
T41 |
0 |
2316 |
0 |
0 |
T42 |
0 |
2753 |
0 |
0 |
T43 |
0 |
40187 |
0 |
0 |
T44 |
0 |
383 |
0 |
0 |
T45 |
0 |
158 |
0 |
0 |
T49 |
0 |
56437 |
0 |
0 |
T55 |
0 |
7412 |
0 |
0 |
T59 |
0 |
75739 |
0 |
0 |
T60 |
0 |
3197 |
0 |
0 |
T62 |
0 |
3456 |
0 |
0 |
T68 |
0 |
41617 |
0 |
0 |
T79 |
0 |
3 |
0 |
0 |
T83 |
0 |
19500 |
0 |
0 |
T88 |
0 |
1898 |
0 |
0 |
T89 |
0 |
21473 |
0 |
0 |
T90 |
0 |
3406 |
0 |
0 |
T91 |
890 |
0 |
0 |
0 |
T92 |
8000 |
0 |
0 |
0 |
T93 |
217808 |
0 |
0 |
0 |
T94 |
398622 |
0 |
0 |
0 |
T95 |
132965 |
0 |
0 |
0 |
T96 |
1505 |
0 |
0 |
0 |
T97 |
249160 |
0 |
0 |
0 |
T98 |
403694 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1680578756 |
726015 |
0 |
0 |
T1 |
180349 |
529 |
0 |
0 |
T2 |
204082 |
257 |
0 |
0 |
T3 |
319208 |
296 |
0 |
0 |
T4 |
21912 |
0 |
0 |
0 |
T5 |
1458 |
0 |
0 |
0 |
T6 |
296040 |
348 |
0 |
0 |
T7 |
130914 |
85 |
0 |
0 |
T8 |
81584 |
123 |
0 |
0 |
T9 |
89514 |
62 |
0 |
0 |
T10 |
2070 |
0 |
0 |
0 |
T11 |
138097 |
297 |
0 |
0 |
T12 |
123189 |
364 |
0 |
0 |
T13 |
0 |
741 |
0 |
0 |
T17 |
0 |
369 |
0 |
0 |
T30 |
136708 |
0 |
0 |
0 |
T31 |
50712 |
162 |
0 |
0 |
T33 |
0 |
569 |
0 |
0 |
T34 |
0 |
1031 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
T36 |
765 |
0 |
0 |
0 |
T39 |
11459 |
0 |
0 |
0 |
T40 |
0 |
45 |
0 |
0 |
T41 |
144850 |
744 |
0 |
0 |
T42 |
177838 |
0 |
0 |
0 |
T43 |
181262 |
758 |
0 |
0 |
T44 |
0 |
1500 |
0 |
0 |
T61 |
0 |
75 |
0 |
0 |
T62 |
0 |
95 |
0 |
0 |
T79 |
11708 |
0 |
0 |
0 |
T99 |
0 |
48 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1680578756 |
726015 |
0 |
0 |
T1 |
180349 |
529 |
0 |
0 |
T2 |
204082 |
257 |
0 |
0 |
T3 |
319208 |
296 |
0 |
0 |
T4 |
21912 |
0 |
0 |
0 |
T5 |
1458 |
0 |
0 |
0 |
T6 |
296040 |
348 |
0 |
0 |
T7 |
130914 |
85 |
0 |
0 |
T8 |
81584 |
123 |
0 |
0 |
T9 |
89514 |
62 |
0 |
0 |
T10 |
2070 |
0 |
0 |
0 |
T11 |
138097 |
297 |
0 |
0 |
T12 |
123189 |
364 |
0 |
0 |
T13 |
0 |
741 |
0 |
0 |
T17 |
0 |
369 |
0 |
0 |
T30 |
136708 |
0 |
0 |
0 |
T31 |
50712 |
162 |
0 |
0 |
T33 |
0 |
569 |
0 |
0 |
T34 |
0 |
1031 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
T36 |
765 |
0 |
0 |
0 |
T39 |
11459 |
0 |
0 |
0 |
T40 |
0 |
45 |
0 |
0 |
T41 |
144850 |
744 |
0 |
0 |
T42 |
177838 |
0 |
0 |
0 |
T43 |
181262 |
758 |
0 |
0 |
T44 |
0 |
1500 |
0 |
0 |
T61 |
0 |
75 |
0 |
0 |
T62 |
0 |
95 |
0 |
0 |
T79 |
11708 |
0 |
0 |
0 |
T99 |
0 |
48 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T4,T7 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T46,T47,T48 |
1 | 1 | Covered | T2,T4,T7 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T2,T4,T7 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T7,T8 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T7,T8 |
1 | 0 | Covered | T46,T47,T48 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T46,T47,T48 |
1 | Covered | T2,T4,T7 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T46,T47,T48 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T7,T8 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T7,T8 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T7,T8 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T7 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T7 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T43,T62 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T43,T62 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T43,T62 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T7,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T2,T7,T8 |
1 |
0 |
- |
Covered |
T2,T4,T7 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
419971685 |
0 |
0 |
T1 |
180349 |
180298 |
0 |
0 |
T2 |
102041 |
102033 |
0 |
0 |
T3 |
159604 |
159521 |
0 |
0 |
T4 |
10956 |
10877 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
147925 |
0 |
0 |
T7 |
65457 |
65363 |
0 |
0 |
T8 |
40792 |
40702 |
0 |
0 |
T9 |
44757 |
44706 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
352288306 |
0 |
0 |
T1 |
180349 |
180298 |
0 |
0 |
T2 |
102041 |
551016 |
0 |
0 |
T3 |
159604 |
159521 |
0 |
0 |
T4 |
10956 |
4995 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
147925 |
0 |
0 |
T7 |
65457 |
52621 |
0 |
0 |
T8 |
40792 |
21393 |
0 |
0 |
T9 |
44757 |
22536 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
24078810 |
0 |
0 |
T2 |
102041 |
346414 |
0 |
0 |
T3 |
159604 |
0 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
0 |
0 |
0 |
T7 |
65457 |
0 |
0 |
0 |
T8 |
40792 |
0 |
0 |
0 |
T9 |
44757 |
0 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
T43 |
0 |
40175 |
0 |
0 |
T49 |
0 |
56437 |
0 |
0 |
T55 |
0 |
7412 |
0 |
0 |
T59 |
0 |
75739 |
0 |
0 |
T62 |
0 |
3456 |
0 |
0 |
T68 |
0 |
41617 |
0 |
0 |
T83 |
0 |
19500 |
0 |
0 |
T89 |
0 |
21473 |
0 |
0 |
T90 |
0 |
3406 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
181645 |
0 |
0 |
T2 |
102041 |
257 |
0 |
0 |
T3 |
159604 |
0 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
0 |
0 |
0 |
T7 |
65457 |
85 |
0 |
0 |
T8 |
40792 |
123 |
0 |
0 |
T9 |
44757 |
62 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
T40 |
0 |
45 |
0 |
0 |
T43 |
0 |
696 |
0 |
0 |
T44 |
0 |
756 |
0 |
0 |
T61 |
0 |
75 |
0 |
0 |
T62 |
0 |
95 |
0 |
0 |
T99 |
0 |
48 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
181645 |
0 |
0 |
T2 |
102041 |
257 |
0 |
0 |
T3 |
159604 |
0 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
0 |
0 |
0 |
T7 |
65457 |
85 |
0 |
0 |
T8 |
40792 |
123 |
0 |
0 |
T9 |
44757 |
62 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
T40 |
0 |
45 |
0 |
0 |
T43 |
0 |
696 |
0 |
0 |
T44 |
0 |
756 |
0 |
0 |
T61 |
0 |
75 |
0 |
0 |
T62 |
0 |
95 |
0 |
0 |
T99 |
0 |
48 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T6,T11 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T52,T53,T54 |
1 | 1 | Covered | T3,T6,T11 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T11 |
1 | 1 | Covered | T3,T6,T11 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T11 |
1 | 1 | Covered | T3,T6,T11 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T6,T11 |
0 | 1 | Covered | T3,T6,T11 |
1 | 0 | Covered | T34 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T34 |
1 | Covered | T3,T6,T11 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T34 |
0 | 1 | Covered | T3,T6,T11 |
1 | 0 | Covered | T3,T6,T11 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T6,T11 |
1 | 1 | Covered | T3,T6,T11 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T6,T11 |
1 | 1 | Covered | T3,T6,T11 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T6,T11 |
1 | 1 | Covered | T3,T6,T11 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T6,T11 |
1 | 1 | Covered | T3,T6,T11 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T11 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T6,T11 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T6,T11 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T30,T33 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T30,T33 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T11 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T6,T30,T33 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T6,T11 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T3,T6,T11 |
1 |
0 |
- |
Covered |
T3,T6,T11 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
419971685 |
0 |
0 |
T1 |
180349 |
180298 |
0 |
0 |
T2 |
102041 |
102033 |
0 |
0 |
T3 |
159604 |
159521 |
0 |
0 |
T4 |
10956 |
10877 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
147925 |
0 |
0 |
T7 |
65457 |
65363 |
0 |
0 |
T8 |
40792 |
40702 |
0 |
0 |
T9 |
44757 |
44706 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
348794677 |
0 |
0 |
T1 |
180349 |
180298 |
0 |
0 |
T2 |
102041 |
102033 |
0 |
0 |
T3 |
159604 |
104159 |
0 |
0 |
T4 |
10956 |
10877 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
5827 |
0 |
0 |
T7 |
65457 |
65363 |
0 |
0 |
T8 |
40792 |
40702 |
0 |
0 |
T9 |
44757 |
44706 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
5831317 |
0 |
0 |
T6 |
148020 |
12719 |
0 |
0 |
T7 |
65457 |
0 |
0 |
0 |
T8 |
40792 |
0 |
0 |
0 |
T9 |
44757 |
0 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T11 |
138097 |
0 |
0 |
0 |
T13 |
228732 |
0 |
0 |
0 |
T30 |
0 |
103937 |
0 |
0 |
T33 |
0 |
15869 |
0 |
0 |
T34 |
0 |
21652 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
T40 |
169826 |
0 |
0 |
0 |
T41 |
144850 |
0 |
0 |
0 |
T52 |
0 |
67177 |
0 |
0 |
T53 |
0 |
49824 |
0 |
0 |
T56 |
0 |
63228 |
0 |
0 |
T57 |
0 |
91363 |
0 |
0 |
T100 |
0 |
36913 |
0 |
0 |
T101 |
0 |
71241 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
188940 |
0 |
0 |
T3 |
159604 |
256 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
323 |
0 |
0 |
T7 |
65457 |
0 |
0 |
0 |
T8 |
40792 |
0 |
0 |
0 |
T9 |
44757 |
0 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T11 |
0 |
214 |
0 |
0 |
T12 |
0 |
204 |
0 |
0 |
T13 |
228732 |
0 |
0 |
0 |
T17 |
0 |
129 |
0 |
0 |
T30 |
0 |
428 |
0 |
0 |
T31 |
0 |
81 |
0 |
0 |
T32 |
0 |
46 |
0 |
0 |
T33 |
0 |
1801 |
0 |
0 |
T34 |
0 |
2702 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
188940 |
0 |
0 |
T3 |
159604 |
256 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
323 |
0 |
0 |
T7 |
65457 |
0 |
0 |
0 |
T8 |
40792 |
0 |
0 |
0 |
T9 |
44757 |
0 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T11 |
0 |
214 |
0 |
0 |
T12 |
0 |
204 |
0 |
0 |
T13 |
228732 |
0 |
0 |
0 |
T17 |
0 |
129 |
0 |
0 |
T30 |
0 |
428 |
0 |
0 |
T31 |
0 |
81 |
0 |
0 |
T32 |
0 |
46 |
0 |
0 |
T33 |
0 |
1801 |
0 |
0 |
T34 |
0 |
2702 |
0 |
0 |
T35 |
5013 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T15,T21 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T6 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T6 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T34,T52,T53 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T34,T52,T53 |
1 | Covered | T1,T3,T6 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T34,T52,T53 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T15,T21 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T15,T21 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T15,T21 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T3,T6 |
1 |
0 |
- |
Covered |
T1,T3,T6 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
419971685 |
0 |
0 |
T1 |
180349 |
180298 |
0 |
0 |
T2 |
102041 |
102033 |
0 |
0 |
T3 |
159604 |
159521 |
0 |
0 |
T4 |
10956 |
10877 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
147925 |
0 |
0 |
T7 |
65457 |
65363 |
0 |
0 |
T8 |
40792 |
40702 |
0 |
0 |
T9 |
44757 |
44706 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
228515989 |
0 |
0 |
T1 |
180349 |
3641 |
0 |
0 |
T2 |
102041 |
102033 |
0 |
0 |
T3 |
159604 |
102512 |
0 |
0 |
T4 |
10956 |
10877 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
94217 |
0 |
0 |
T7 |
65457 |
65363 |
0 |
0 |
T8 |
40792 |
40702 |
0 |
0 |
T9 |
44757 |
44706 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
43 |
0 |
0 |
T15 |
207983 |
21 |
0 |
0 |
T21 |
0 |
22 |
0 |
0 |
T22 |
42779 |
0 |
0 |
0 |
T91 |
890 |
0 |
0 |
0 |
T92 |
8000 |
0 |
0 |
0 |
T93 |
217808 |
0 |
0 |
0 |
T94 |
398622 |
0 |
0 |
0 |
T95 |
132965 |
0 |
0 |
0 |
T96 |
1505 |
0 |
0 |
0 |
T97 |
249160 |
0 |
0 |
0 |
T98 |
403694 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
174884 |
0 |
0 |
T1 |
180349 |
529 |
0 |
0 |
T2 |
102041 |
0 |
0 |
0 |
T3 |
159604 |
296 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
348 |
0 |
0 |
T7 |
65457 |
0 |
0 |
0 |
T8 |
40792 |
0 |
0 |
0 |
T9 |
44757 |
0 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T11 |
0 |
297 |
0 |
0 |
T12 |
0 |
364 |
0 |
0 |
T13 |
0 |
741 |
0 |
0 |
T17 |
0 |
369 |
0 |
0 |
T31 |
0 |
162 |
0 |
0 |
T33 |
0 |
569 |
0 |
0 |
T34 |
0 |
1031 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
174884 |
0 |
0 |
T1 |
180349 |
529 |
0 |
0 |
T2 |
102041 |
0 |
0 |
0 |
T3 |
159604 |
296 |
0 |
0 |
T4 |
10956 |
0 |
0 |
0 |
T5 |
729 |
0 |
0 |
0 |
T6 |
148020 |
348 |
0 |
0 |
T7 |
65457 |
0 |
0 |
0 |
T8 |
40792 |
0 |
0 |
0 |
T9 |
44757 |
0 |
0 |
0 |
T10 |
1035 |
0 |
0 |
0 |
T11 |
0 |
297 |
0 |
0 |
T12 |
0 |
364 |
0 |
0 |
T13 |
0 |
741 |
0 |
0 |
T17 |
0 |
369 |
0 |
0 |
T31 |
0 |
162 |
0 |
0 |
T33 |
0 |
569 |
0 |
0 |
T34 |
0 |
1031 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 43 | 84.31 |
Logical | 51 | 43 | 84.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T41,T42 |
1 | 1 | Covered | T2,T7,T8 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T49,T50,T51 |
1 | 1 | Covered | T40,T41,T39 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T41,T42,T43 |
1 | 1 | Covered | T40,T41,T39 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T41,T39 |
1 | 1 | Covered | T41,T42,T43 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T40,T41,T39 |
0 | 1 | Covered | T41,T42,T43 |
1 | 0 | Covered | T49,T50,T51 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T49,T50,T51 |
1 | Covered | T40,T41,T39 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T49,T50,T51 |
0 | 1 | Covered | T40,T41,T39 |
1 | 0 | Covered | T41,T42,T43 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T40,T41,T39 |
1 | 1 | Covered | T41,T42,T43 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T40,T41,T39 |
1 | 1 | Covered | T41,T42,T43 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T40,T41,T39 |
1 | 1 | Covered | T40,T41,T39 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T40,T41,T39 |
1 | 1 | Covered | T40,T41,T39 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T41,T42,T43 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T40,T41,T39 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T40,T41,T39 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T41,T39 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T40,T41,T39 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T40,T41,T39 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T40,T41,T39 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T41,T42,T43 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T41,T42,T43 |
1 |
0 |
- |
Covered |
T40,T41,T39 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1309 |
1309 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
419971685 |
0 |
0 |
T1 |
180349 |
180298 |
0 |
0 |
T2 |
102041 |
102033 |
0 |
0 |
T3 |
159604 |
159521 |
0 |
0 |
T4 |
10956 |
10877 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
147925 |
0 |
0 |
T7 |
65457 |
65363 |
0 |
0 |
T8 |
40792 |
40702 |
0 |
0 |
T9 |
44757 |
44706 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
388921523 |
0 |
0 |
T1 |
180349 |
180298 |
0 |
0 |
T2 |
102041 |
102033 |
0 |
0 |
T3 |
159604 |
159521 |
0 |
0 |
T4 |
10956 |
10877 |
0 |
0 |
T5 |
729 |
662 |
0 |
0 |
T6 |
148020 |
147925 |
0 |
0 |
T7 |
65457 |
65363 |
0 |
0 |
T8 |
40792 |
40702 |
0 |
0 |
T9 |
44757 |
44706 |
0 |
0 |
T10 |
1035 |
951 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
590605 |
0 |
0 |
T11 |
138097 |
0 |
0 |
0 |
T12 |
123189 |
0 |
0 |
0 |
T30 |
136708 |
0 |
0 |
0 |
T31 |
50712 |
0 |
0 |
0 |
T39 |
11459 |
3 |
0 |
0 |
T40 |
169826 |
7362 |
0 |
0 |
T41 |
144850 |
2316 |
0 |
0 |
T42 |
177838 |
2753 |
0 |
0 |
T43 |
181262 |
12 |
0 |
0 |
T44 |
0 |
383 |
0 |
0 |
T45 |
0 |
158 |
0 |
0 |
T60 |
0 |
3197 |
0 |
0 |
T79 |
11708 |
3 |
0 |
0 |
T88 |
0 |
1898 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
180546 |
0 |
0 |
T11 |
138097 |
0 |
0 |
0 |
T12 |
123189 |
0 |
0 |
0 |
T30 |
136708 |
0 |
0 |
0 |
T31 |
50712 |
0 |
0 |
0 |
T36 |
765 |
0 |
0 |
0 |
T39 |
11459 |
0 |
0 |
0 |
T41 |
144850 |
744 |
0 |
0 |
T42 |
177838 |
1116 |
0 |
0 |
T43 |
181262 |
62 |
0 |
0 |
T44 |
0 |
744 |
0 |
0 |
T45 |
0 |
930 |
0 |
0 |
T55 |
0 |
1922 |
0 |
0 |
T60 |
0 |
1054 |
0 |
0 |
T68 |
0 |
2461 |
0 |
0 |
T79 |
11708 |
0 |
0 |
0 |
T88 |
0 |
744 |
0 |
0 |
T102 |
0 |
992 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420144689 |
180546 |
0 |
0 |
T11 |
138097 |
0 |
0 |
0 |
T12 |
123189 |
0 |
0 |
0 |
T30 |
136708 |
0 |
0 |
0 |
T31 |
50712 |
0 |
0 |
0 |
T36 |
765 |
0 |
0 |
0 |
T39 |
11459 |
0 |
0 |
0 |
T41 |
144850 |
744 |
0 |
0 |
T42 |
177838 |
1116 |
0 |
0 |
T43 |
181262 |
62 |
0 |
0 |
T44 |
0 |
744 |
0 |
0 |
T45 |
0 |
930 |
0 |
0 |
T55 |
0 |
1922 |
0 |
0 |
T60 |
0 |
1054 |
0 |
0 |
T68 |
0 |
2461 |
0 |
0 |
T79 |
11708 |
0 |
0 |
0 |
T88 |
0 |
744 |
0 |
0 |
T102 |
0 |
992 |
0 |
0 |