Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	420675323	6692	0	0
ctrl_rd_A	420675323	1529	0	0
host_fifo_config_rd_A	420675323	5162	0	0
host_nack_handler_timeout_rd_A	420675323	1198	0	0
host_timeout_ctrl_rd_A	420675323	1148	0	0
intr_enable_rd_A	420675323	3344	0	0
ovrd_rd_A	420675323	1869	0	0
target_fifo_config_rd_A	420675323	1328	0	0
target_id_rd_A	420675323	1354	0	0
target_timeout_ctrl_rd_A	420675323	1174	0	0
timeout_ctrl_rd_A	420675323	1314	0	0
timing0_rd_A	420675323	1239	0	0
timing1_rd_A	420675323	1268	0	0
timing2_rd_A	420675323	1171	0	0
timing3_rd_A	420675323	1250	0	0
timing4_rd_A	420675323	1130	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	6692	0	0
T105	2961	123	0	0
T106	3928	17	0	0
T119	1305	6	0	0
T120	6828	1	0	0
T121	6428	269	0	0
T122	4199	521	0	0
T123	7898	2	0	0
T124	10184	219	0	0
T127	2418	9	0	0
T129	3714	14	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1529	0	0
T106	3928	50	0	0
T124	10184	17	0	0
T125	4922	2	0	0
T136	7902	80	0	0
T140	2591	6	0	0
T141	1614	12	0	0
T156	6772	103	0	0
T157	8994	13	0	0
T158	3654	5	0	0
T159	2933	23	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	5162	0	0
T19	155428	0	0	0
T20	359703	0	0	0
T55	777842	0	0	0
T56	100605	0	0	0
T68	112348	386	0	0
T69	64643	0	0	0
T94	0	184	0	0
T101	97373	0	0	0
T102	374323	85	0	0
T103	1073	0	0	0
T160	0	132	0	0
T161	0	162	0	0
T162	0	121	0	0
T163	0	58	0	0
T164	0	81	0	0
T165	0	229	0	0
T166	0	144	0	0
T167	232993	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1198	0	0
T106	3928	15	0	0
T125	4922	7	0	0
T136	7902	55	0	0
T140	2591	10	0	0
T141	1614	9	0	0
T154	6047	24	0	0
T156	6772	118	0	0
T157	8994	4	0	0
T158	3654	11	0	0
T159	2933	15	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1148	0	0
T106	3928	20	0	0
T124	10184	12	0	0
T125	4922	8	0	0
T136	7902	34	0	0
T140	2591	6	0	0
T141	1614	8	0	0
T156	6772	117	0	0
T157	8994	24	0	0
T158	3654	23	0	0
T159	2933	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	3344	0	0
T86	275863	0	0	0
T106	0	106	0	0
T166	0	61	0	0
T168	232535	32	0	0
T169	0	11	0	0
T170	0	27	0	0
T171	0	12	0	0
T172	0	20	0	0
T173	0	37	0	0
T174	0	29	0	0
T175	0	8	0	0
T176	215154	0	0	0
T177	83039	0	0	0
T178	73379	0	0	0
T179	34065	0	0	0
T180	1639	0	0	0
T181	110656	0	0	0
T182	74213	0	0	0
T183	36949	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1869	0	0
T184	2154	71	0	0
T185	0	49	0	0
T186	0	28	0	0
T187	0	64	0	0
T188	0	16	0	0
T189	0	82	0	0
T190	0	25	0	0
T191	0	17	0	0
T192	0	63	0	0
T193	0	40	0	0
T194	702792	0	0	0
T195	387257	0	0	0
T196	27312	0	0	0
T197	124150	0	0	0
T198	491973	0	0	0
T199	196398	0	0	0
T200	4450	0	0	0
T201	5679	0	0	0
T202	185453	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1328	0	0
T106	3928	39	0	0
T124	10184	10	0	0
T125	4922	2	0	0
T136	7902	53	0	0
T140	2591	9	0	0
T154	6047	29	0	0
T156	6772	129	0	0
T157	8994	7	0	0
T158	3654	19	0	0
T159	2933	14	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1354	0	0
T106	3928	13	0	0
T124	10184	13	0	0
T136	7902	66	0	0
T140	2591	14	0	0
T141	1614	6	0	0
T154	6047	8	0	0
T156	6772	132	0	0
T157	8994	4	0	0
T158	3654	15	0	0
T159	2933	27	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1174	0	0
T106	3928	24	0	0
T124	10184	6	0	0
T125	4922	8	0	0
T136	7902	55	0	0
T141	1614	9	0	0
T154	6047	39	0	0
T155	5639	50	0	0
T156	6772	108	0	0
T158	3654	22	0	0
T159	2933	13	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1314	0	0
T106	3928	34	0	0
T124	10184	8	0	0
T136	7902	45	0	0
T140	2591	6	0	0
T154	6047	26	0	0
T155	5639	15	0	0
T156	6772	140	0	0
T157	8994	20	0	0
T158	3654	12	0	0
T159	2933	15	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1239	0	0
T106	3928	33	0	0
T124	10184	26	0	0
T136	7902	74	0	0
T140	2591	8	0	0
T154	6047	59	0	0
T155	5639	42	0	0
T156	6772	120	0	0
T157	8994	9	0	0
T158	3654	27	0	0
T159	2933	22	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1268	0	0
T106	3928	21	0	0
T124	10184	20	0	0
T125	4922	19	0	0
T136	7902	60	0	0
T140	2591	7	0	0
T141	1614	6	0	0
T156	6772	143	0	0
T157	8994	10	0	0
T158	3654	33	0	0
T159	2933	23	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1171	0	0
T106	3928	11	0	0
T124	10184	26	0	0
T125	4922	9	0	0
T136	7902	44	0	0
T140	2591	16	0	0
T141	1614	3	0	0
T156	6772	125	0	0
T157	8994	10	0	0
T158	3654	16	0	0
T159	2933	11	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1250	0	0
T106	3928	18	0	0
T124	10184	8	0	0
T125	4922	8	0	0
T136	7902	60	0	0
T140	2591	9	0	0
T141	1614	11	0	0
T154	6047	36	0	0
T156	6772	116	0	0
T158	3654	30	0	0
T159	2933	13	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420675323	1130	0	0
T106	3928	7	0	0
T124	10184	9	0	0
T125	4922	5	0	0
T136	7902	54	0	0
T154	6047	12	0	0
T155	5639	32	0	0
T156	6772	98	0	0
T157	8994	21	0	0
T158	3654	39	0	0
T159	2933	16	0	0