Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	709891	1			T1	2		T2	3		T3	248
all_values[1]	709891	1			T1	2		T2	3		T3	248
all_values[2]	709891	1			T1	2		T2	3		T3	248
all_values[3]	709891	1			T1	2		T2	3		T3	248
all_values[4]	709891	1			T1	2		T2	3		T3	248
all_values[5]	709891	1			T1	2		T2	3		T3	248
all_values[6]	709891	1			T1	2		T2	3		T3	248
all_values[7]	709891	1			T1	2		T2	3		T3	248
all_values[8]	709891	1			T1	2		T2	3		T3	248
all_values[9]	709891	1			T1	2		T2	3		T3	248
all_values[10]	709891	1			T1	2		T2	3		T3	248
all_values[11]	709891	1			T1	2		T2	3		T3	248
all_values[12]	709891	1			T1	2		T2	3		T3	248
all_values[13]	709891	1			T1	2		T2	3		T3	248
all_values[14]	709891	1			T1	2		T2	3		T3	248

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7484535

1

T1

26

T2

38

T3

3071

auto[1]

3163830

1

T1

4

T2

7

T3

649

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9157091

1

T1

30

T2

45

T3

3720

auto[1]

1491274

1

T41

48612

T51

72069

T69

173

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	47244	1			T3	5		T4	1		T6	2
all_values[0]	auto[0]	auto[1]	8483	1			T41	21		T51	366		T69	9
all_values[0]	auto[1]	auto[0]	573636	1			T1	2		T2	3		T3	243
all_values[0]	auto[1]	auto[1]	80528	1			T41	3263		T51	4440		T69	4
all_values[1]	auto[0]	auto[0]	617533	1			T1	2		T2	3		T3	244
all_values[1]	auto[0]	auto[1]	91858	1			T41	3279		T51	4800		T69	4
all_values[1]	auto[1]	auto[0]	219	1			T3	4		T8	6		T73	1
all_values[1]	auto[1]	auto[1]	281	1			T41	6		T51	6		T69	5
all_values[2]	auto[0]	auto[0]	611612	1			T1	2		T2	3		T3	248
all_values[2]	auto[0]	auto[1]	98045	1			T41	3277		T51	4802		T69	5
all_values[2]	auto[1]	auto[1]	234	1			T41	8		T51	4		T69	4
all_values[3]	auto[0]	auto[0]	614788	1			T1	2		T2	3		T3	248
all_values[3]	auto[0]	auto[1]	94858	1			T41	3060		T51	4800		T69	5
all_values[3]	auto[1]	auto[1]	245	1			T41	7		T51	5		T69	8
all_values[4]	auto[0]	auto[0]	608989	1			T1	2		T2	3		T3	248
all_values[4]	auto[0]	auto[1]	100680	1			T41	3063		T51	4799		T69	10
all_values[4]	auto[1]	auto[0]	19	1			T70	1		T72	2		T212	1
all_values[4]	auto[1]	auto[1]	203	1			T41	3		T51	7		T69	3
all_values[5]	auto[0]	auto[0]	613091	1			T1	2		T2	3		T3	248
all_values[5]	auto[0]	auto[1]	96447	1			T41	3279		T51	4802		T69	13
all_values[5]	auto[1]	auto[0]	115	1			T77	115		-	-		-	-
all_values[5]	auto[1]	auto[1]	238	1			T41	4		T51	3		T69	1
all_values[6]	auto[0]	auto[0]	105615	1			T1	2		T2	3		T3	238
all_values[6]	auto[0]	auto[1]	21354	1			T41	555		T51	96		T69	8
all_values[6]	auto[1]	auto[0]	514265	1			T3	10		T4	1		T6	2
all_values[6]	auto[1]	auto[1]	68657	1			T41	2730		T51	4702		T69	5
all_values[7]	auto[0]	auto[0]	589488	1			T1	2		T2	3		T3	171
all_values[7]	auto[0]	auto[1]	95262	1			T41	3045		T51	4639		T69	7
all_values[7]	auto[1]	auto[0]	21423	1			T3	77		T6	8		T8	128
all_values[7]	auto[1]	auto[1]	3718	1			T41	239		T51	159		T69	5
all_values[8]	auto[0]	auto[0]	76856	1			T1	2		T2	3		T3	189
all_values[8]	auto[0]	auto[1]	24831	1			T41	494		T51	60		T69	5
all_values[8]	auto[1]	auto[0]	531915	1			T3	59		T4	1		T6	5
all_values[8]	auto[1]	auto[1]	76289	1			T41	2791		T51	4746		T69	7
all_values[9]	auto[0]	auto[0]	98607	1			T1	2		T2	2		T3	235
all_values[9]	auto[0]	auto[1]	26840	1			T41	550		T51	85		T69	6
all_values[9]	auto[1]	auto[0]	502013	1			T2	1		T3	13		T4	1
all_values[9]	auto[1]	auto[1]	82431	1			T41	2735		T51	4721		T69	3
all_values[10]	auto[0]	auto[0]	605633	1			T1	2		T2	3		T3	248
all_values[10]	auto[0]	auto[1]	104064	1			T41	3279		T51	4801		T69	4
all_values[10]	auto[1]	auto[1]	194	1			T41	5		T51	5		T69	1
all_values[11]	auto[0]	auto[0]	2783	1			T3	5		T4	1		T6	2
all_values[11]	auto[0]	auto[1]	623	1			T41	15		T51	39		T69	8
all_values[11]	auto[1]	auto[0]	598134	1			T1	2		T2	3		T3	243
all_values[11]	auto[1]	auto[1]	108351	1			T41	3269		T51	4767		T69	6
all_values[12]	auto[0]	auto[0]	600622	1			T1	2		T2	3		T3	248
all_values[12]	auto[0]	auto[1]	109048	1			T41	3281		T51	4802		T69	9
all_values[12]	auto[1]	auto[1]	221	1			T41	3		T51	2		T69	5
all_values[13]	auto[0]	auto[0]	611392	1			T1	2		T2	3		T3	248
all_values[13]	auto[0]	auto[1]	98244	1			T41	3277		T51	4801		T69	5
all_values[13]	auto[1]	auto[1]	255	1			T41	7		T51	5		T69	4
all_values[14]	auto[0]	auto[0]	611099	1			T1	2		T2	3		T3	248
all_values[14]	auto[0]	auto[1]	98546	1			T41	3064		T51	4802		T69	8
all_values[14]	auto[1]	auto[1]	246	1			T41	3		T51	3		T69	6