Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	709891	1			T1	2		T2	3		T3	248
all_pins[1]	709891	1			T1	2		T2	3		T3	248
all_pins[2]	709891	1			T1	2		T2	3		T3	248
all_pins[3]	709891	1			T1	2		T2	3		T3	248
all_pins[4]	709891	1			T1	2		T2	3		T3	248
all_pins[5]	709891	1			T1	2		T2	3		T3	248
all_pins[6]	709891	1			T1	2		T2	3		T3	248
all_pins[7]	709891	1			T1	2		T2	3		T3	248
all_pins[8]	709891	1			T1	2		T2	3		T3	248
all_pins[9]	709891	1			T1	2		T2	3		T3	248
all_pins[10]	709891	1			T1	2		T2	3		T3	248
all_pins[11]	709891	1			T1	2		T2	3		T3	248
all_pins[12]	709891	1			T1	2		T2	3		T3	248
all_pins[13]	709891	1			T1	2		T2	3		T3	248
all_pins[14]	709891	1			T1	2		T2	3		T3	248

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7490201	1			T1	26		T2	38		T3	3057
values[0x1]	3158164	1			T1	4		T2	7		T3	663
transitions[0x0=>0x1]	2538960	1			T1	4		T2	7		T3	623
transitions[0x1=>0x0]	2537942	1			T1	3		T2	6		T3	622

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	58839	1			T3	5		T4	1		T6	2
all_pins[0]	values[0x1]	651052	1			T1	2		T2	3		T3	243
all_pins[0]	transitions[0x0=>0x1]	650692	1			T1	2		T2	3		T3	238
all_pins[0]	transitions[0x1=>0x0]	94	1			T41	1		T51	4		T69	1
all_pins[1]	values[0x0]	709437	1			T1	2		T2	3		T3	243
all_pins[1]	values[0x1]	454	1			T3	5		T8	8		T41	3
all_pins[1]	transitions[0x0=>0x1]	432	1			T3	5		T8	8		T41	3
all_pins[1]	transitions[0x1=>0x0]	87	1			T41	2		T69	1		T81	1
all_pins[2]	values[0x0]	709782	1			T1	2		T2	3		T3	248
all_pins[2]	values[0x1]	109	1			T41	2		T51	2		T69	1
all_pins[2]	transitions[0x0=>0x1]	91	1			T41	2		T51	2		T69	1
all_pins[2]	transitions[0x1=>0x0]	94	1			T41	4		T51	4		T69	3
all_pins[3]	values[0x0]	709779	1			T1	2		T2	3		T3	248
all_pins[3]	values[0x1]	112	1			T41	4		T51	4		T69	3
all_pins[3]	transitions[0x0=>0x1]	88	1			T41	4		T51	2		T69	2
all_pins[3]	transitions[0x1=>0x0]	95	1			T70	1		T51	1		T72	2
all_pins[4]	values[0x0]	709772	1			T1	2		T2	3		T3	248
all_pins[4]	values[0x1]	119	1			T70	1		T51	3		T72	2
all_pins[4]	transitions[0x0=>0x1]	99	1			T70	1		T51	2		T72	2
all_pins[4]	transitions[0x1=>0x0]	234	1			T41	2		T51	1		T69	1
all_pins[5]	values[0x0]	709637	1			T1	2		T2	3		T3	248
all_pins[5]	values[0x1]	254	1			T41	2		T51	2		T69	1
all_pins[5]	transitions[0x0=>0x1]	200	1			T51	2		T69	1		T94	1
all_pins[5]	transitions[0x1=>0x0]	582488	1			T3	10		T4	1		T6	2
all_pins[6]	values[0x0]	127349	1			T1	2		T2	3		T3	238
all_pins[6]	values[0x1]	582542	1			T3	10		T4	1		T6	2
all_pins[6]	transitions[0x0=>0x1]	565461	1			T3	5		T4	1		T6	2
all_pins[6]	transitions[0x1=>0x0]	10668	1			T3	80		T6	8		T39	26
all_pins[7]	values[0x0]	682142	1			T1	2		T2	3		T3	163
all_pins[7]	values[0x1]	27749	1			T3	85		T6	8		T8	153
all_pins[7]	transitions[0x0=>0x1]	8556	1			T3	61		T6	7		T39	26
all_pins[7]	transitions[0x1=>0x0]	588739	1			T3	40		T4	1		T6	4
all_pins[8]	values[0x0]	101959	1			T1	2		T2	3		T3	184
all_pins[8]	values[0x1]	607932	1			T3	64		T4	1		T6	5
all_pins[8]	transitions[0x0=>0x1]	25702	1			T3	58		T6	4		T8	276
all_pins[8]	transitions[0x1=>0x0]	2097	1			T2	1		T3	7		T6	2
all_pins[9]	values[0x0]	125564	1			T1	2		T2	2		T3	235
all_pins[9]	values[0x1]	584327	1			T2	1		T3	13		T4	1
all_pins[9]	transitions[0x0=>0x1]	584306	1			T2	1		T3	13		T4	1
all_pins[9]	transitions[0x1=>0x0]	84	1			T41	3		T51	4		T69	1
all_pins[10]	values[0x0]	709786	1			T1	2		T2	3		T3	248
all_pins[10]	values[0x1]	105	1			T41	3		T51	4		T69	1
all_pins[10]	transitions[0x0=>0x1]	74	1			T51	3		T69	1		T94	1
all_pins[10]	transitions[0x1=>0x0]	703003	1			T1	2		T2	3		T3	243
all_pins[11]	values[0x0]	6857	1			T3	5		T4	1		T6	2
all_pins[11]	values[0x1]	703034	1			T1	2		T2	3		T3	243
all_pins[11]	transitions[0x0=>0x1]	702999	1			T1	2		T2	3		T3	243
all_pins[11]	transitions[0x1=>0x0]	82	1			T51	1		T69	3		T81	1
all_pins[12]	values[0x0]	709774	1			T1	2		T2	3		T3	248
all_pins[12]	values[0x1]	117	1			T41	1		T51	1		T69	3
all_pins[12]	transitions[0x0=>0x1]	86	1			T41	1		T51	1		T69	3
all_pins[12]	transitions[0x1=>0x0]	97	1			T41	2		T51	3		T69	4
all_pins[13]	values[0x0]	709763	1			T1	2		T2	3		T3	248
all_pins[13]	values[0x1]	128	1			T41	2		T51	3		T69	4
all_pins[13]	transitions[0x0=>0x1]	95	1			T41	2		T51	3		T69	3
all_pins[13]	transitions[0x1=>0x0]	97	1			T41	2		T51	2		T69	3
all_pins[14]	values[0x0]	709761	1			T1	2		T2	3		T3	248
all_pins[14]	values[0x1]	130	1			T41	2		T51	2		T69	4
all_pins[14]	transitions[0x0=>0x1]	79	1			T41	1		T69	4		T94	2
all_pins[14]	transitions[0x1=>0x0]	649983	1			T1	1		T2	2		T3	242