Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	529	1			T41	11		T51	11		T69	11
all_values[1]	529	1			T41	11		T51	11		T69	11
all_values[2]	529	1			T41	11		T51	11		T69	11
all_values[3]	529	1			T41	11		T51	11		T69	11
all_values[4]	529	1			T41	11		T51	11		T69	11
all_values[5]	529	1			T41	11		T51	11		T69	11
all_values[6]	529	1			T41	11		T51	11		T69	11
all_values[7]	529	1			T41	11		T51	11		T69	11
all_values[8]	529	1			T41	11		T51	11		T69	11
all_values[9]	529	1			T41	11		T51	11		T69	11
all_values[10]	529	1			T41	11		T51	11		T69	11
all_values[11]	529	1			T41	11		T51	11		T69	11
all_values[12]	529	1			T41	11		T51	11		T69	11
all_values[13]	529	1			T41	11		T51	11		T69	11
all_values[14]	529	1			T41	11		T51	11		T69	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4103

1

T41

92

T51

66

T69

74

auto[1]

3832

1

T41

73

T51

99

T69

91

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1273

1

T41

21

T51

13

T69

32

auto[1]

6662

1

T41

144

T51

152

T69

133

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4698

1

T41

95

T51

105

T69

102

auto[1]

3237

1

T41

70

T51

60

T69

63

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	52	1			T81	1		T241	1		T242	4
all_values[0]	auto[0]	auto[0]	auto[1]	130	1			T41	4		T51	2		T69	4
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T41	1		T69	1		T184	2
all_values[0]	auto[0]	auto[1]	auto[1]	121	1			T41	1		T51	7		T69	2
all_values[0]	auto[1]	auto[0]	auto[1]	106	1			T41	3		T69	2		T94	1
all_values[0]	auto[1]	auto[1]	auto[1]	90	1			T41	2		T51	2		T69	2
all_values[1]	auto[0]	auto[0]	auto[0]	47	1			T69	1		T81	1		T58	1
all_values[1]	auto[0]	auto[0]	auto[1]	110	1			T41	6		T69	1		T94	1
all_values[1]	auto[0]	auto[1]	auto[0]	43	1			T69	3		T94	3		T58	3
all_values[1]	auto[0]	auto[1]	auto[1]	115	1			T41	1		T51	5		T69	1
all_values[1]	auto[1]	auto[0]	auto[1]	113	1			T41	4		T51	1		T69	5
all_values[1]	auto[1]	auto[1]	auto[1]	101	1			T51	5		T94	2		T169	2
all_values[2]	auto[0]	auto[0]	auto[0]	43	1			T69	2		T241	2		T242	2
all_values[2]	auto[0]	auto[0]	auto[1]	124	1			T41	2		T51	5		T69	2
all_values[2]	auto[0]	auto[1]	auto[0]	23	1			T69	2		T198	1		T241	2
all_values[2]	auto[0]	auto[1]	auto[1]	105	1			T41	1		T51	2		T69	1
all_values[2]	auto[1]	auto[0]	auto[1]	119	1			T41	6		T51	2		T69	3
all_values[2]	auto[1]	auto[1]	auto[1]	115	1			T41	2		T51	2		T69	1
all_values[3]	auto[0]	auto[0]	auto[0]	52	1			T41	2		T81	4		T169	1
all_values[3]	auto[0]	auto[0]	auto[1]	109	1			T51	2		T69	1		T94	2
all_values[3]	auto[0]	auto[1]	auto[0]	40	1			T41	2		T51	1		T69	1
all_values[3]	auto[0]	auto[1]	auto[1]	108	1			T41	2		T51	5		T69	3
all_values[3]	auto[1]	auto[0]	auto[1]	127	1			T41	2		T51	3		T69	4
all_values[3]	auto[1]	auto[1]	auto[1]	93	1			T41	3		T69	2		T243	1
all_values[4]	auto[0]	auto[0]	auto[0]	56	1			T41	3		T94	4		T184	2
all_values[4]	auto[0]	auto[0]	auto[1]	124	1			T41	2		T51	2		T69	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1			T41	2		T69	1		T94	3
all_values[4]	auto[0]	auto[1]	auto[1]	103	1			T41	1		T51	2		T69	6
all_values[4]	auto[1]	auto[0]	auto[1]	106	1			T41	3		T51	3		T69	1
all_values[4]	auto[1]	auto[1]	auto[1]	97	1			T51	4		T69	2		T81	2
all_values[5]	auto[0]	auto[0]	auto[0]	30	1			T41	2		T81	1		T58	1
all_values[5]	auto[0]	auto[0]	auto[1]	99	1			T41	3		T51	2		T94	1
all_values[5]	auto[0]	auto[1]	auto[0]	38	1			T51	1		T218	1		T241	1
all_values[5]	auto[0]	auto[1]	auto[1]	131	1			T41	2		T51	5		T69	7
all_values[5]	auto[1]	auto[0]	auto[1]	115	1			T41	1		T51	3		T69	1
all_values[5]	auto[1]	auto[1]	auto[1]	116	1			T41	3		T69	3		T94	1
all_values[6]	auto[0]	auto[0]	auto[0]	50	1			T51	1		T169	1		T58	3
all_values[6]	auto[0]	auto[0]	auto[1]	117	1			T41	3		T51	2		T69	5
all_values[6]	auto[0]	auto[1]	auto[0]	40	1			T51	3		T69	1		T94	1
all_values[6]	auto[0]	auto[1]	auto[1]	102	1			T41	3		T51	2		T69	1
all_values[6]	auto[1]	auto[0]	auto[1]	125	1			T41	1		T69	4		T94	2
all_values[6]	auto[1]	auto[1]	auto[1]	95	1			T41	4		T51	3		T94	3
all_values[7]	auto[0]	auto[0]	auto[0]	43	1			T41	1		T51	2		T69	1
all_values[7]	auto[0]	auto[0]	auto[1]	119	1			T41	3		T51	1		T69	1
all_values[7]	auto[0]	auto[1]	auto[0]	40	1			T51	2		T69	1		T169	2
all_values[7]	auto[0]	auto[1]	auto[1]	110	1			T41	2		T51	3		T69	4
all_values[7]	auto[1]	auto[0]	auto[1]	99	1			T41	2		T51	3		T69	2
all_values[7]	auto[1]	auto[1]	auto[1]	118	1			T41	3		T69	2		T94	1
all_values[8]	auto[0]	auto[0]	auto[0]	53	1			T69	1		T183	1		T184	3
all_values[8]	auto[0]	auto[0]	auto[1]	100	1			T41	5		T51	5		T69	1
all_values[8]	auto[0]	auto[1]	auto[0]	31	1			T69	1		T94	1		T198	2
all_values[8]	auto[0]	auto[1]	auto[1]	118	1			T41	1		T51	1		T69	4
all_values[8]	auto[1]	auto[0]	auto[1]	113	1			T41	1		T51	2		T69	2
all_values[8]	auto[1]	auto[1]	auto[1]	114	1			T41	4		T51	3		T69	2
all_values[9]	auto[0]	auto[0]	auto[0]	46	1			T69	2		T169	2		T184	1
all_values[9]	auto[0]	auto[0]	auto[1]	134	1			T41	1		T51	5		T69	3
all_values[9]	auto[0]	auto[1]	auto[0]	31	1			T69	2		T218	1		T244	2
all_values[9]	auto[0]	auto[1]	auto[1]	103	1			T41	4		T51	2		T69	1
all_values[9]	auto[1]	auto[0]	auto[1]	121	1			T41	4		T51	2		T69	1
all_values[9]	auto[1]	auto[1]	auto[1]	94	1			T41	2		T51	2		T69	2
all_values[10]	auto[0]	auto[0]	auto[0]	59	1			T69	6		T198	3		T183	1
all_values[10]	auto[0]	auto[0]	auto[1]	108	1			T41	3		T51	3		T94	4
all_values[10]	auto[0]	auto[1]	auto[0]	52	1			T41	1		T69	2		T81	1
all_values[10]	auto[0]	auto[1]	auto[1]	116	1			T41	2		T51	3		T69	2
all_values[10]	auto[1]	auto[0]	auto[1]	92	1			T41	3		T94	1		T81	2
all_values[10]	auto[1]	auto[1]	auto[1]	102	1			T41	2		T51	5		T69	1
all_values[11]	auto[0]	auto[0]	auto[0]	48	1			T41	1		T184	2		T245	2
all_values[11]	auto[0]	auto[0]	auto[1]	110	1			T51	2		T69	2		T94	2
all_values[11]	auto[0]	auto[1]	auto[0]	45	1			T198	1		T243	3		T218	2
all_values[11]	auto[0]	auto[1]	auto[1]	124	1			T41	7		T51	4		T69	3
all_values[11]	auto[1]	auto[0]	auto[1]	107	1			T41	1		T51	1		T69	4
all_values[11]	auto[1]	auto[1]	auto[1]	95	1			T41	2		T51	4		T69	2
all_values[12]	auto[0]	auto[0]	auto[0]	37	1			T41	1		T218	1		T183	1
all_values[12]	auto[0]	auto[0]	auto[1]	111	1			T41	4		T51	4		T69	3
all_values[12]	auto[0]	auto[1]	auto[0]	37	1			T51	2		T198	1		T218	3
all_values[12]	auto[0]	auto[1]	auto[1]	123	1			T41	3		T51	3		T69	3
all_values[12]	auto[1]	auto[0]	auto[1]	108	1			T41	2		T51	1		T69	2
all_values[12]	auto[1]	auto[1]	auto[1]	113	1			T41	1		T51	1		T69	3
all_values[13]	auto[0]	auto[0]	auto[0]	47	1			T69	2		T169	2		T245	1
all_values[13]	auto[0]	auto[0]	auto[1]	107	1			T41	3		T51	2		T94	4
all_values[13]	auto[0]	auto[1]	auto[0]	39	1			T41	1		T69	2		T94	1
all_values[13]	auto[0]	auto[1]	auto[1]	105	1			T41	1		T51	5		T69	3
all_values[13]	auto[1]	auto[0]	auto[1]	121	1			T41	4		T51	1		T69	1
all_values[13]	auto[1]	auto[1]	auto[1]	110	1			T41	2		T51	3		T69	3
all_values[14]	auto[0]	auto[0]	auto[0]	45	1			T41	2		T94	1		T169	2
all_values[14]	auto[0]	auto[0]	auto[1]	128	1			T41	2		T51	2		T69	2
all_values[14]	auto[0]	auto[1]	auto[0]	33	1			T41	2		T51	1		T94	1
all_values[14]	auto[0]	auto[1]	auto[1]	111	1			T41	2		T51	4		T69	3
all_values[14]	auto[1]	auto[0]	auto[1]	93	1			T41	2		T51	2		T69	1
all_values[14]	auto[1]	auto[1]	auto[1]	119	1			T41	1		T51	2		T69	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal