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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.76 97.32 92.08 97.66 83.74 94.83 98.67 92.02


Total test records in report: 1443
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T1306 /workspace/coverage/default/18.i2c_target_intr_stress_wr.4152787967 May 02 01:44:34 PM PDT 24 May 02 01:44:42 PM PDT 24 3197041044 ps
T1307 /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3040447029 May 02 01:44:35 PM PDT 24 May 02 01:45:38 PM PDT 24 10068207222 ps
T1308 /workspace/coverage/default/0.i2c_target_intr_smoke.3591214904 May 02 01:41:48 PM PDT 24 May 02 01:41:56 PM PDT 24 1274720776 ps
T1309 /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3785458184 May 02 01:47:41 PM PDT 24 May 02 01:48:50 PM PDT 24 10070976643 ps
T1310 /workspace/coverage/default/28.i2c_target_stress_rd.4192650147 May 02 01:46:25 PM PDT 24 May 02 01:46:37 PM PDT 24 3914404929 ps
T1311 /workspace/coverage/default/49.i2c_target_hrst.2210324373 May 02 01:50:22 PM PDT 24 May 02 01:50:26 PM PDT 24 455536980 ps
T1312 /workspace/coverage/default/7.i2c_target_smoke.4038821294 May 02 01:42:44 PM PDT 24 May 02 01:43:03 PM PDT 24 1283992484 ps
T1313 /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1779096908 May 02 01:46:28 PM PDT 24 May 02 01:46:43 PM PDT 24 10474977902 ps
T1314 /workspace/coverage/default/2.i2c_host_mode_toggle.3801271955 May 02 01:42:05 PM PDT 24 May 02 01:42:29 PM PDT 24 4614001428 ps
T1315 /workspace/coverage/default/8.i2c_target_timeout.2211317843 May 02 01:42:52 PM PDT 24 May 02 01:42:59 PM PDT 24 2814322324 ps
T1316 /workspace/coverage/default/1.i2c_target_stretch.1215185093 May 02 01:41:49 PM PDT 24 May 02 02:13:20 PM PDT 24 33538317326 ps
T1317 /workspace/coverage/default/46.i2c_target_stress_rd.3450028178 May 02 01:49:47 PM PDT 24 May 02 01:50:17 PM PDT 24 2920635837 ps
T1318 /workspace/coverage/default/7.i2c_alert_test.1784134259 May 02 01:42:45 PM PDT 24 May 02 01:42:46 PM PDT 24 18633993 ps
T1319 /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3204004015 May 02 01:49:04 PM PDT 24 May 02 01:49:14 PM PDT 24 433591513 ps
T1320 /workspace/coverage/default/30.i2c_target_timeout.3091986304 May 02 01:46:47 PM PDT 24 May 02 01:46:55 PM PDT 24 5398672529 ps
T1321 /workspace/coverage/default/47.i2c_host_smoke.3981497867 May 02 01:50:00 PM PDT 24 May 02 01:50:17 PM PDT 24 1040654261 ps
T1322 /workspace/coverage/default/22.i2c_host_override.1569959402 May 02 01:45:16 PM PDT 24 May 02 01:45:18 PM PDT 24 112389580 ps
T1323 /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3380999546 May 02 01:41:58 PM PDT 24 May 02 01:42:01 PM PDT 24 461353807 ps
T1324 /workspace/coverage/default/17.i2c_alert_test.2884887117 May 02 01:44:29 PM PDT 24 May 02 01:44:31 PM PDT 24 25308726 ps
T1325 /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3365943237 May 02 01:49:41 PM PDT 24 May 02 01:49:53 PM PDT 24 10159991765 ps
T1326 /workspace/coverage/default/12.i2c_host_override.2877624341 May 02 01:43:35 PM PDT 24 May 02 01:43:37 PM PDT 24 32975817 ps
T1327 /workspace/coverage/default/44.i2c_host_perf.2349111775 May 02 01:49:25 PM PDT 24 May 02 01:49:45 PM PDT 24 1360716794 ps
T1328 /workspace/coverage/default/49.i2c_target_intr_stress_wr.1404013637 May 02 01:50:21 PM PDT 24 May 02 01:50:33 PM PDT 24 11864618755 ps
T203 /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2774155773 May 02 01:48:48 PM PDT 24 May 02 01:50:17 PM PDT 24 10125203015 ps
T1329 /workspace/coverage/default/12.i2c_host_stress_all.3579592297 May 02 01:43:34 PM PDT 24 May 02 01:50:25 PM PDT 24 11700565777 ps
T1330 /workspace/coverage/default/6.i2c_host_error_intr.3859292962 May 02 01:42:38 PM PDT 24 May 02 01:42:41 PM PDT 24 235087197 ps
T1331 /workspace/coverage/default/22.i2c_alert_test.122089517 May 02 01:45:25 PM PDT 24 May 02 01:45:26 PM PDT 24 20871344 ps
T1332 /workspace/coverage/default/33.i2c_target_stress_all.447816573 May 02 01:47:25 PM PDT 24 May 02 01:48:34 PM PDT 24 28966475443 ps
T1333 /workspace/coverage/default/43.i2c_target_intr_smoke.1045819985 May 02 01:49:13 PM PDT 24 May 02 01:49:18 PM PDT 24 754169544 ps
T1334 /workspace/coverage/default/49.i2c_host_error_intr.3603334964 May 02 01:50:21 PM PDT 24 May 02 01:50:24 PM PDT 24 313295889 ps
T1335 /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2971447525 May 02 01:48:58 PM PDT 24 May 02 01:50:10 PM PDT 24 10034334195 ps
T1336 /workspace/coverage/default/13.i2c_host_stretch_timeout.403566625 May 02 01:43:47 PM PDT 24 May 02 01:44:09 PM PDT 24 1944604559 ps
T1337 /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3312106095 May 02 01:42:28 PM PDT 24 May 02 01:43:09 PM PDT 24 10078714057 ps
T1338 /workspace/coverage/default/31.i2c_host_mode_toggle.371921728 May 02 01:47:00 PM PDT 24 May 02 01:47:19 PM PDT 24 5184866954 ps
T1339 /workspace/coverage/default/0.i2c_host_fifo_watermark.3316737388 May 02 01:41:49 PM PDT 24 May 02 01:42:57 PM PDT 24 11751925855 ps
T1340 /workspace/coverage/default/29.i2c_host_smoke.3675791051 May 02 01:46:26 PM PDT 24 May 02 01:46:47 PM PDT 24 1073975409 ps
T1341 /workspace/coverage/default/23.i2c_host_error_intr.3153495298 May 02 01:45:25 PM PDT 24 May 02 01:45:27 PM PDT 24 463378944 ps
T1342 /workspace/coverage/default/13.i2c_target_stress_wr.1789270172 May 02 01:43:41 PM PDT 24 May 02 01:48:53 PM PDT 24 33057359076 ps
T1343 /workspace/coverage/default/46.i2c_target_stress_wr.1500020041 May 02 01:49:46 PM PDT 24 May 02 02:18:05 PM PDT 24 58021126942 ps
T1344 /workspace/coverage/default/1.i2c_target_hrst.4034239286 May 02 01:41:56 PM PDT 24 May 02 01:42:01 PM PDT 24 2399894878 ps
T1345 /workspace/coverage/default/11.i2c_target_timeout.1279673197 May 02 01:43:26 PM PDT 24 May 02 01:43:33 PM PDT 24 1251465520 ps
T1346 /workspace/coverage/default/21.i2c_host_fifo_watermark.2221899671 May 02 01:45:07 PM PDT 24 May 02 01:47:22 PM PDT 24 19129695438 ps
T1347 /workspace/coverage/default/40.i2c_host_override.3991268462 May 02 01:48:46 PM PDT 24 May 02 01:48:48 PM PDT 24 45076510 ps
T1348 /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2551256327 May 02 01:49:24 PM PDT 24 May 02 01:49:25 PM PDT 24 489080711 ps
T1349 /workspace/coverage/default/26.i2c_target_hrst.2729711708 May 02 01:46:06 PM PDT 24 May 02 01:46:09 PM PDT 24 467670010 ps
T187 /workspace/coverage/default/33.i2c_host_stress_all.1326749283 May 02 01:47:17 PM PDT 24 May 02 01:51:44 PM PDT 24 9870467072 ps
T1350 /workspace/coverage/default/3.i2c_target_stress_all.585016656 May 02 01:42:06 PM PDT 24 May 02 01:59:43 PM PDT 24 32917186546 ps
T1351 /workspace/coverage/default/15.i2c_target_stress_all.1714205182 May 02 01:44:02 PM PDT 24 May 02 01:45:03 PM PDT 24 97840050059 ps
T1352 /workspace/coverage/default/36.i2c_host_error_intr.2844277443 May 02 01:47:58 PM PDT 24 May 02 01:48:00 PM PDT 24 914125851 ps
T1353 /workspace/coverage/default/19.i2c_target_stress_wr.1771731675 May 02 01:44:42 PM PDT 24 May 02 01:48:56 PM PDT 24 43806202117 ps
T115 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.576223352 May 02 01:36:36 PM PDT 24 May 02 01:36:38 PM PDT 24 158930607 ps
T66 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2452129375 May 02 01:36:42 PM PDT 24 May 02 01:36:44 PM PDT 24 18804909 ps
T67 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3551050611 May 02 01:36:51 PM PDT 24 May 02 01:36:53 PM PDT 24 33284295 ps
T68 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.768151308 May 02 01:36:11 PM PDT 24 May 02 01:36:15 PM PDT 24 109644264 ps
T161 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.567469825 May 02 01:36:33 PM PDT 24 May 02 01:36:35 PM PDT 24 261864791 ps
T1354 /workspace/coverage/cover_reg_top/0.i2c_intr_test.2572066474 May 02 01:36:16 PM PDT 24 May 02 01:36:18 PM PDT 24 27638915 ps
T1355 /workspace/coverage/cover_reg_top/44.i2c_intr_test.996939906 May 02 01:36:50 PM PDT 24 May 02 01:36:52 PM PDT 24 24321525 ps
T116 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3535373285 May 02 01:36:26 PM PDT 24 May 02 01:36:28 PM PDT 24 62971104 ps
T188 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2195727118 May 02 01:36:43 PM PDT 24 May 02 01:36:46 PM PDT 24 47189412 ps
T127 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.131176197 May 02 01:36:23 PM PDT 24 May 02 01:36:27 PM PDT 24 2818392923 ps
T1356 /workspace/coverage/cover_reg_top/8.i2c_intr_test.680693387 May 02 01:36:26 PM PDT 24 May 02 01:36:28 PM PDT 24 19949194 ps
T182 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3713355178 May 02 01:36:23 PM PDT 24 May 02 01:36:25 PM PDT 24 62210717 ps
T128 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2900667293 May 02 01:36:42 PM PDT 24 May 02 01:36:46 PM PDT 24 298558518 ps
T147 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3417192972 May 02 01:36:34 PM PDT 24 May 02 01:36:36 PM PDT 24 116452202 ps
T1357 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1789404852 May 02 01:36:42 PM PDT 24 May 02 01:36:44 PM PDT 24 26185199 ps
T162 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2187555869 May 02 01:36:42 PM PDT 24 May 02 01:36:45 PM PDT 24 44670538 ps
T1358 /workspace/coverage/cover_reg_top/11.i2c_intr_test.349457635 May 02 01:36:36 PM PDT 24 May 02 01:36:38 PM PDT 24 54515163 ps
T146 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1793271671 May 02 01:36:26 PM PDT 24 May 02 01:36:28 PM PDT 24 82686225 ps
T132 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4276189558 May 02 01:36:26 PM PDT 24 May 02 01:36:29 PM PDT 24 103529214 ps
T163 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.228645578 May 02 01:36:22 PM PDT 24 May 02 01:36:25 PM PDT 24 85885533 ps
T1359 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2320292896 May 02 01:36:50 PM PDT 24 May 02 01:36:52 PM PDT 24 22334652 ps
T137 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1939329810 May 02 01:36:42 PM PDT 24 May 02 01:36:44 PM PDT 24 79612665 ps
T1360 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2559381249 May 02 01:36:50 PM PDT 24 May 02 01:36:53 PM PDT 24 18461482 ps
T148 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2115808918 May 02 01:36:28 PM PDT 24 May 02 01:36:30 PM PDT 24 219970393 ps
T149 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1562127947 May 02 01:36:43 PM PDT 24 May 02 01:36:46 PM PDT 24 29798420 ps
T129 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2793267274 May 02 01:36:43 PM PDT 24 May 02 01:36:46 PM PDT 24 220752408 ps
T164 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1309004373 May 02 01:36:27 PM PDT 24 May 02 01:36:29 PM PDT 24 28568618 ps
T1361 /workspace/coverage/cover_reg_top/35.i2c_intr_test.490187264 May 02 01:36:49 PM PDT 24 May 02 01:36:51 PM PDT 24 92261788 ps
T130 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2393997104 May 02 01:36:27 PM PDT 24 May 02 01:36:30 PM PDT 24 247090098 ps
T150 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1435703434 May 02 01:36:34 PM PDT 24 May 02 01:36:36 PM PDT 24 53048000 ps
T165 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2916724768 May 02 01:36:27 PM PDT 24 May 02 01:36:29 PM PDT 24 45910769 ps
T144 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1718926175 May 02 01:36:23 PM PDT 24 May 02 01:36:26 PM PDT 24 27279641 ps
T170 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3189206697 May 02 01:36:35 PM PDT 24 May 02 01:36:37 PM PDT 24 38278659 ps
T166 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.7222458 May 02 01:36:10 PM PDT 24 May 02 01:36:13 PM PDT 24 41922411 ps
T151 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3876509777 May 02 01:36:11 PM PDT 24 May 02 01:36:13 PM PDT 24 25245740 ps
T171 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1836364915 May 02 01:36:18 PM PDT 24 May 02 01:36:20 PM PDT 24 77131822 ps
T1362 /workspace/coverage/cover_reg_top/26.i2c_intr_test.29695260 May 02 01:36:40 PM PDT 24 May 02 01:36:41 PM PDT 24 21965725 ps
T1363 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2075237641 May 02 01:36:26 PM PDT 24 May 02 01:36:29 PM PDT 24 107389659 ps
T1364 /workspace/coverage/cover_reg_top/34.i2c_intr_test.324901780 May 02 01:36:50 PM PDT 24 May 02 01:36:53 PM PDT 24 38257988 ps
T1365 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2642967892 May 02 01:36:53 PM PDT 24 May 02 01:36:55 PM PDT 24 38851212 ps
T1366 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3100040967 May 02 01:36:51 PM PDT 24 May 02 01:36:53 PM PDT 24 28110745 ps
T1367 /workspace/coverage/cover_reg_top/37.i2c_intr_test.2749501590 May 02 01:36:53 PM PDT 24 May 02 01:36:55 PM PDT 24 49368159 ps
T131 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.290226772 May 02 01:36:12 PM PDT 24 May 02 01:36:15 PM PDT 24 79688050 ps
T1368 /workspace/coverage/cover_reg_top/32.i2c_intr_test.597025017 May 02 01:36:53 PM PDT 24 May 02 01:36:55 PM PDT 24 75436595 ps
T1369 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.471542973 May 02 01:36:12 PM PDT 24 May 02 01:36:16 PM PDT 24 27854865 ps
T1370 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1410450832 May 02 01:36:35 PM PDT 24 May 02 01:36:37 PM PDT 24 21039192 ps
T1371 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3898545737 May 02 01:36:43 PM PDT 24 May 02 01:36:46 PM PDT 24 15464483 ps
T167 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1265895676 May 02 01:36:13 PM PDT 24 May 02 01:36:16 PM PDT 24 20671392 ps
T135 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1025832042 May 02 01:36:11 PM PDT 24 May 02 01:36:14 PM PDT 24 85273711 ps
T1372 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3648961658 May 02 01:36:36 PM PDT 24 May 02 01:36:38 PM PDT 24 19164783 ps
T168 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3532869682 May 02 01:36:28 PM PDT 24 May 02 01:36:30 PM PDT 24 114313413 ps
T1373 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2534605671 May 02 01:36:26 PM PDT 24 May 02 01:36:29 PM PDT 24 211786264 ps
T133 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3195417888 May 02 01:36:19 PM PDT 24 May 02 01:36:22 PM PDT 24 72297212 ps
T1374 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2554070979 May 02 01:36:41 PM PDT 24 May 02 01:36:43 PM PDT 24 183099726 ps
T1375 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.628411306 May 02 01:36:35 PM PDT 24 May 02 01:36:37 PM PDT 24 20835709 ps
T138 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2952641334 May 02 01:36:34 PM PDT 24 May 02 01:36:36 PM PDT 24 453664070 ps
T134 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.880914776 May 02 01:36:19 PM PDT 24 May 02 01:36:22 PM PDT 24 46404909 ps
T1376 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3345879677 May 02 01:36:42 PM PDT 24 May 02 01:36:44 PM PDT 24 22393440 ps
T139 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.244862017 May 02 01:36:43 PM PDT 24 May 02 01:36:46 PM PDT 24 139147886 ps
T143 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3817015800 May 02 01:36:18 PM PDT 24 May 02 01:36:21 PM PDT 24 135759836 ps
T1377 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3502743515 May 02 01:36:43 PM PDT 24 May 02 01:36:45 PM PDT 24 21626687 ps
T1378 /workspace/coverage/cover_reg_top/24.i2c_intr_test.100490847 May 02 01:36:43 PM PDT 24 May 02 01:36:46 PM PDT 24 19051198 ps
T172 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3152246010 May 02 01:36:18 PM PDT 24 May 02 01:36:20 PM PDT 24 165645617 ps
T1379 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.374487883 May 02 01:36:18 PM PDT 24 May 02 01:36:20 PM PDT 24 25753342 ps
T1380 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2580833704 May 02 01:36:19 PM PDT 24 May 02 01:36:22 PM PDT 24 69274146 ps
T142 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2578160754 May 02 01:36:44 PM PDT 24 May 02 01:36:48 PM PDT 24 543338174 ps
T152 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3217366033 May 02 01:36:12 PM PDT 24 May 02 01:36:15 PM PDT 24 24956712 ps
T1381 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.556641000 May 02 01:36:10 PM PDT 24 May 02 01:36:13 PM PDT 24 26564316 ps
T1382 /workspace/coverage/cover_reg_top/43.i2c_intr_test.439489305 May 02 01:36:52 PM PDT 24 May 02 01:36:55 PM PDT 24 18642042 ps
T1383 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2733274203 May 02 01:36:21 PM PDT 24 May 02 01:36:23 PM PDT 24 104264343 ps
T1384 /workspace/coverage/cover_reg_top/3.i2c_intr_test.509429300 May 02 01:36:20 PM PDT 24 May 02 01:36:22 PM PDT 24 15697248 ps
T1385 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1865569129 May 02 01:36:52 PM PDT 24 May 02 01:36:54 PM PDT 24 38962839 ps
T1386 /workspace/coverage/cover_reg_top/22.i2c_intr_test.3550036711 May 02 01:36:44 PM PDT 24 May 02 01:36:46 PM PDT 24 50027167 ps
T1387 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1778534610 May 02 01:36:11 PM PDT 24 May 02 01:36:16 PM PDT 24 881006521 ps
T1388 /workspace/coverage/cover_reg_top/5.i2c_intr_test.146736721 May 02 01:36:21 PM PDT 24 May 02 01:36:23 PM PDT 24 22291511 ps
T1389 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1155160845 May 02 01:36:35 PM PDT 24 May 02 01:36:37 PM PDT 24 58061298 ps
T1390 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3445438134 May 02 01:36:33 PM PDT 24 May 02 01:36:35 PM PDT 24 17262530 ps
T1391 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1359612278 May 02 01:36:10 PM PDT 24 May 02 01:36:12 PM PDT 24 55583042 ps
T1392 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3945234020 May 02 01:36:13 PM PDT 24 May 02 01:36:16 PM PDT 24 14581277 ps
T1393 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1053797047 May 02 01:36:48 PM PDT 24 May 02 01:36:49 PM PDT 24 26105096 ps
T1394 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1336646975 May 02 01:36:46 PM PDT 24 May 02 01:36:48 PM PDT 24 66643158 ps
T1395 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1450471767 May 02 01:36:44 PM PDT 24 May 02 01:36:47 PM PDT 24 56180025 ps
T1396 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.595542558 May 02 01:36:21 PM PDT 24 May 02 01:36:23 PM PDT 24 17414427 ps
T153 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2115161316 May 02 01:36:35 PM PDT 24 May 02 01:36:36 PM PDT 24 20726849 ps
T1397 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2467354933 May 02 01:36:42 PM PDT 24 May 02 01:36:44 PM PDT 24 20853177 ps
T1398 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3095521813 May 02 01:36:20 PM PDT 24 May 02 01:36:22 PM PDT 24 70851031 ps
T1399 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1869600153 May 02 01:36:26 PM PDT 24 May 02 01:36:30 PM PDT 24 754113170 ps
T1400 /workspace/coverage/cover_reg_top/36.i2c_intr_test.406384654 May 02 01:36:51 PM PDT 24 May 02 01:36:53 PM PDT 24 42794854 ps
T1401 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2370378987 May 02 01:36:27 PM PDT 24 May 02 01:36:30 PM PDT 24 166330389 ps
T1402 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1039785030 May 02 01:36:50 PM PDT 24 May 02 01:36:52 PM PDT 24 49354355 ps
T1403 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1805872094 May 02 01:36:43 PM PDT 24 May 02 01:36:45 PM PDT 24 20245918 ps
T154 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.549629022 May 02 01:36:20 PM PDT 24 May 02 01:36:22 PM PDT 24 34189612 ps
T1404 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3106923518 May 02 01:36:43 PM PDT 24 May 02 01:36:45 PM PDT 24 62987526 ps
T1405 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1542543314 May 02 01:36:50 PM PDT 24 May 02 01:36:53 PM PDT 24 17574012 ps
T1406 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3689692107 May 02 01:36:16 PM PDT 24 May 02 01:36:20 PM PDT 24 177903929 ps
T155 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2497263055 May 02 01:36:13 PM PDT 24 May 02 01:36:17 PM PDT 24 65378209 ps
T1407 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2468169049 May 02 01:36:41 PM PDT 24 May 02 01:36:43 PM PDT 24 242244399 ps
T1408 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3930081179 May 02 01:36:44 PM PDT 24 May 02 01:36:46 PM PDT 24 45995924 ps
T1409 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1221099992 May 02 01:36:28 PM PDT 24 May 02 01:36:30 PM PDT 24 30153996 ps
T1410 /workspace/coverage/cover_reg_top/28.i2c_intr_test.743593574 May 02 01:36:41 PM PDT 24 May 02 01:36:43 PM PDT 24 33094188 ps
T1411 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3471999973 May 02 01:36:23 PM PDT 24 May 02 01:36:25 PM PDT 24 42579494 ps
T1412 /workspace/coverage/cover_reg_top/38.i2c_intr_test.1881713543 May 02 01:36:48 PM PDT 24 May 02 01:36:50 PM PDT 24 67067120 ps
T1413 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2579006549 May 02 01:36:42 PM PDT 24 May 02 01:36:44 PM PDT 24 21045617 ps
T1414 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1908974364 May 02 01:36:36 PM PDT 24 May 02 01:36:38 PM PDT 24 84499124 ps
T1415 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2131801547 May 02 01:36:52 PM PDT 24 May 02 01:36:54 PM PDT 24 38000550 ps
T1416 /workspace/coverage/cover_reg_top/9.i2c_intr_test.4193469723 May 02 01:36:26 PM PDT 24 May 02 01:36:28 PM PDT 24 29436957 ps
T156 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1509071766 May 02 01:36:11 PM PDT 24 May 02 01:36:14 PM PDT 24 154023845 ps
T1417 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3405704698 May 02 01:36:44 PM PDT 24 May 02 01:36:47 PM PDT 24 107443686 ps
T1418 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1265567522 May 02 01:36:20 PM PDT 24 May 02 01:36:23 PM PDT 24 155510122 ps
T1419 /workspace/coverage/cover_reg_top/27.i2c_intr_test.1078835507 May 02 01:36:42 PM PDT 24 May 02 01:36:43 PM PDT 24 38057006 ps
T1420 /workspace/coverage/cover_reg_top/40.i2c_intr_test.816328622 May 02 01:36:49 PM PDT 24 May 02 01:36:51 PM PDT 24 16080504 ps
T140 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1003510841 May 02 01:36:29 PM PDT 24 May 02 01:36:32 PM PDT 24 104448320 ps
T1421 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3168343677 May 02 01:36:27 PM PDT 24 May 02 01:36:30 PM PDT 24 299260487 ps
T1422 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.683928385 May 02 01:36:10 PM PDT 24 May 02 01:36:12 PM PDT 24 130944468 ps
T1423 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2416860678 May 02 01:36:44 PM PDT 24 May 02 01:36:47 PM PDT 24 102904126 ps
T157 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2295551867 May 02 01:36:13 PM PDT 24 May 02 01:36:16 PM PDT 24 38767077 ps
T1424 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3843027579 May 02 01:36:21 PM PDT 24 May 02 01:36:24 PM PDT 24 168278933 ps
T1425 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2495046876 May 02 01:36:36 PM PDT 24 May 02 01:36:38 PM PDT 24 66580937 ps
T1426 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2638698313 May 02 01:36:13 PM PDT 24 May 02 01:36:17 PM PDT 24 85418488 ps
T1427 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1650223044 May 02 01:36:43 PM PDT 24 May 02 01:36:45 PM PDT 24 19023919 ps
T1428 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.211348579 May 02 01:36:20 PM PDT 24 May 02 01:36:24 PM PDT 24 168196652 ps
T1429 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3677078175 May 02 01:36:37 PM PDT 24 May 02 01:36:40 PM PDT 24 168803033 ps
T1430 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2924712022 May 02 01:36:44 PM PDT 24 May 02 01:36:47 PM PDT 24 64842045 ps
T1431 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1551114916 May 02 01:36:20 PM PDT 24 May 02 01:36:22 PM PDT 24 60160089 ps
T158 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2560141507 May 02 01:36:43 PM PDT 24 May 02 01:36:45 PM PDT 24 22875265 ps
T145 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2976195769 May 02 01:36:45 PM PDT 24 May 02 01:36:49 PM PDT 24 529392591 ps
T1432 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1667488664 May 02 01:36:21 PM PDT 24 May 02 01:36:24 PM PDT 24 20792604 ps
T1433 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2913234051 May 02 01:36:35 PM PDT 24 May 02 01:36:37 PM PDT 24 100204157 ps
T1434 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2694756722 May 02 01:36:19 PM PDT 24 May 02 01:36:21 PM PDT 24 148635517 ps
T1435 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3524348763 May 02 01:36:21 PM PDT 24 May 02 01:36:24 PM PDT 24 54003074 ps
T1436 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.359027937 May 02 01:36:20 PM PDT 24 May 02 01:36:23 PM PDT 24 21488118 ps
T1437 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4166321792 May 02 01:36:18 PM PDT 24 May 02 01:36:20 PM PDT 24 112406328 ps
T247 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2003482734 May 02 01:36:20 PM PDT 24 May 02 01:36:22 PM PDT 24 28537103 ps
T159 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.58911980 May 02 01:36:27 PM PDT 24 May 02 01:36:28 PM PDT 24 18859367 ps
T1438 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2065637596 May 02 01:36:43 PM PDT 24 May 02 01:36:46 PM PDT 24 120563260 ps
T1439 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2744609925 May 02 01:36:29 PM PDT 24 May 02 01:36:32 PM PDT 24 114740484 ps
T141 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.616634872 May 02 01:36:20 PM PDT 24 May 02 01:36:24 PM PDT 24 87273886 ps
T160 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.908821829 May 02 01:36:40 PM PDT 24 May 02 01:36:43 PM PDT 24 81225014 ps
T1440 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1612891047 May 02 01:36:41 PM PDT 24 May 02 01:36:43 PM PDT 24 50503515 ps
T136 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.421808632 May 02 01:36:16 PM PDT 24 May 02 01:36:20 PM PDT 24 151144534 ps
T1441 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1473842209 May 02 01:36:48 PM PDT 24 May 02 01:36:50 PM PDT 24 27754318 ps
T1442 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1995361002 May 02 01:36:11 PM PDT 24 May 02 01:36:14 PM PDT 24 57766049 ps
T1443 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.108103353 May 02 01:36:22 PM PDT 24 May 02 01:36:25 PM PDT 24 70984531 ps

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2780028170
Short name T10
Test name
Test status
Simulation time 2578868298 ps
CPU time 4.09 seconds
Started May 02 01:47:02 PM PDT 24
Finished May 02 01:47:07 PM PDT 24
Peak memory 212316 kb
Host smart-2c561ef7-70e2-4a1a-8a08-244931222757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780028170 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2780028170
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2267889511
Short name T70
Test name
Test status
Simulation time 1842005852 ps
CPU time 7.52 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:47:35 PM PDT 24
Peak memory 204120 kb
Host smart-bd139d94-de0a-4ac0-88e1-a30c07deae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267889511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2267889511
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.2451204638
Short name T41
Test name
Test status
Simulation time 11697510804 ps
CPU time 555.88 seconds
Started May 02 01:48:04 PM PDT 24
Finished May 02 01:57:21 PM PDT 24
Peak memory 1557120 kb
Host smart-5a755c57-5209-4232-811c-55d185f1f367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451204638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.2451204638
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.2256494946
Short name T19
Test name
Test status
Simulation time 13056777410 ps
CPU time 9.2 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:00 PM PDT 24
Peak memory 204408 kb
Host smart-d22d3623-d6e0-4408-963f-dba404fb3255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256494946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.2256494946
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.131176197
Short name T127
Test name
Test status
Simulation time 2818392923 ps
CPU time 2.35 seconds
Started May 02 01:36:23 PM PDT 24
Finished May 02 01:36:27 PM PDT 24
Peak memory 204340 kb
Host smart-c5c6699c-a540-43b0-9b18-0ff8eb812552
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131176197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.131176197
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1088764486
Short name T9
Test name
Test status
Simulation time 10184652761 ps
CPU time 15.79 seconds
Started May 02 01:44:13 PM PDT 24
Finished May 02 01:44:30 PM PDT 24
Peak memory 290332 kb
Host smart-e0889907-64c3-4471-a459-c00e7acff799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088764486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1088764486
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.3504068970
Short name T69
Test name
Test status
Simulation time 105519944176 ps
CPU time 829.03 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 02:01:16 PM PDT 24
Peak memory 2867436 kb
Host smart-2fdba08b-4657-4f51-951d-8b571145406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504068970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.3504068970
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2289853065
Short name T20
Test name
Test status
Simulation time 11928777974 ps
CPU time 12.71 seconds
Started May 02 01:44:43 PM PDT 24
Finished May 02 01:44:57 PM PDT 24
Peak memory 360172 kb
Host smart-8e319020-ee65-4a6c-a762-9a3203eded9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289853065 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2289853065
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3535373285
Short name T116
Test name
Test status
Simulation time 62971104 ps
CPU time 1.47 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:28 PM PDT 24
Peak memory 204196 kb
Host smart-969d5065-8c76-4660-8052-507ad8500bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535373285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3535373285
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/37.i2c_host_override.3298598534
Short name T36
Test name
Test status
Simulation time 18354852 ps
CPU time 0.7 seconds
Started May 02 01:47:56 PM PDT 24
Finished May 02 01:47:58 PM PDT 24
Peak memory 203852 kb
Host smart-365a4703-4944-41c5-864e-18e5c5435595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298598534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3298598534
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1275046488
Short name T117
Test name
Test status
Simulation time 43332520 ps
CPU time 0.82 seconds
Started May 02 01:42:07 PM PDT 24
Finished May 02 01:42:08 PM PDT 24
Peak memory 221468 kb
Host smart-aec533ca-eaa5-427e-8f8f-05ada16bc208
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275046488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1275046488
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.952465279
Short name T81
Test name
Test status
Simulation time 60645419699 ps
CPU time 2046.26 seconds
Started May 02 01:48:57 PM PDT 24
Finished May 02 02:23:05 PM PDT 24
Peak memory 1252404 kb
Host smart-4dcbd380-66ea-42a0-b8c2-18dbeaed145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952465279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.952465279
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1435703434
Short name T150
Test name
Test status
Simulation time 53048000 ps
CPU time 0.77 seconds
Started May 02 01:36:34 PM PDT 24
Finished May 02 01:36:36 PM PDT 24
Peak memory 204036 kb
Host smart-9bd263ae-0d28-435c-94b0-0d87816416f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435703434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1435703434
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.4161693993
Short name T4
Test name
Test status
Simulation time 130734259 ps
CPU time 2.84 seconds
Started May 02 01:42:31 PM PDT 24
Finished May 02 01:42:35 PM PDT 24
Peak memory 204092 kb
Host smart-292d05ed-8f77-4ea6-af2c-eb578c691aeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161693993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
4161693993
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.4041858691
Short name T77
Test name
Test status
Simulation time 120964768638 ps
CPU time 566.65 seconds
Started May 02 01:49:25 PM PDT 24
Finished May 02 01:58:53 PM PDT 24
Peak memory 2163308 kb
Host smart-117977cb-a8ee-4e5e-a2e1-e6513402cc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041858691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.4041858691
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3403843161
Short name T206
Test name
Test status
Simulation time 1052583065 ps
CPU time 0.75 seconds
Started May 02 01:45:21 PM PDT 24
Finished May 02 01:45:23 PM PDT 24
Peak memory 203956 kb
Host smart-db790049-86c3-4d2f-91bc-0c3e6a8c2a88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403843161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3403843161
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1266846122
Short name T87
Test name
Test status
Simulation time 10062608618 ps
CPU time 54.71 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:48:40 PM PDT 24
Peak memory 398372 kb
Host smart-cdc9d379-c6f6-4424-9aff-d8ed5c1918dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266846122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1266846122
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2449030082
Short name T51
Test name
Test status
Simulation time 30740355383 ps
CPU time 254.94 seconds
Started May 02 01:45:59 PM PDT 24
Finished May 02 01:50:15 PM PDT 24
Peak memory 1024088 kb
Host smart-6eeaad9c-3051-4b91-a604-4a156fcecda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449030082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2449030082
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_alert_test.4285797024
Short name T329
Test name
Test status
Simulation time 24770608 ps
CPU time 0.59 seconds
Started May 02 01:41:51 PM PDT 24
Finished May 02 01:41:53 PM PDT 24
Peak memory 203900 kb
Host smart-469e220a-a70f-48bc-a5cd-f2354fae33ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285797024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.4285797024
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2874506306
Short name T73
Test name
Test status
Simulation time 1527259066 ps
CPU time 23.82 seconds
Started May 02 01:41:59 PM PDT 24
Finished May 02 01:42:24 PM PDT 24
Peak memory 382364 kb
Host smart-7f8c7ad8-53b5-4607-9c3b-a8ceba8ef6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874506306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2874506306
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3715789860
Short name T45
Test name
Test status
Simulation time 18064072085 ps
CPU time 3012.95 seconds
Started May 02 01:45:06 PM PDT 24
Finished May 02 02:35:20 PM PDT 24
Peak memory 4284136 kb
Host smart-53591e69-9cc1-46b6-8c45-f41da56d051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715789860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3715789860
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.440701607
Short name T225
Test name
Test status
Simulation time 1431577578 ps
CPU time 6.62 seconds
Started May 02 01:41:53 PM PDT 24
Finished May 02 01:42:01 PM PDT 24
Peak memory 212436 kb
Host smart-bb5b5a46-4bd6-4562-9d2d-9de302e35eba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440701607 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.440701607
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.226334492
Short name T14
Test name
Test status
Simulation time 5034110654 ps
CPU time 2.69 seconds
Started May 02 01:43:26 PM PDT 24
Finished May 02 01:43:29 PM PDT 24
Peak memory 204204 kb
Host smart-514a1ad0-9d27-4d0c-8068-3aaeda0186b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226334492 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.226334492
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.2924662860
Short name T17
Test name
Test status
Simulation time 1039848138 ps
CPU time 6.05 seconds
Started May 02 01:46:26 PM PDT 24
Finished May 02 01:46:33 PM PDT 24
Peak memory 213148 kb
Host smart-78c11c5c-78c9-490d-9a70-9b5f19c4a7dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924662860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.2924662860
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.616634872
Short name T141
Test name
Test status
Simulation time 87273886 ps
CPU time 2.19 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:24 PM PDT 24
Peak memory 204268 kb
Host smart-52843451-6325-4127-b9d0-71a936f5009b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616634872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.616634872
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.2734568312
Short name T47
Test name
Test status
Simulation time 5300797146 ps
CPU time 165.7 seconds
Started May 02 01:43:42 PM PDT 24
Finished May 02 01:46:29 PM PDT 24
Peak memory 723788 kb
Host smart-faa9fdf8-dc28-41f5-b57b-ccddf7192cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734568312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2734568312
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3168003775
Short name T83
Test name
Test status
Simulation time 33981227122 ps
CPU time 325.05 seconds
Started May 02 01:44:21 PM PDT 24
Finished May 02 01:49:47 PM PDT 24
Peak memory 1540816 kb
Host smart-9222184b-1ee2-4baa-aabd-35f7e43a3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168003775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3168003775
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.327096060
Short name T211
Test name
Test status
Simulation time 487051281 ps
CPU time 0.87 seconds
Started May 02 01:44:50 PM PDT 24
Finished May 02 01:44:52 PM PDT 24
Peak memory 203972 kb
Host smart-09f1cbf3-e58c-49dc-ac95-952abe51d5d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327096060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.327096060
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.827602981
Short name T202
Test name
Test status
Simulation time 10382946323 ps
CPU time 12.6 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:42:18 PM PDT 24
Peak memory 256668 kb
Host smart-b426741f-c0c5-4855-af69-ab5610d11cfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827602981 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.827602981
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.3770281906
Short name T104
Test name
Test status
Simulation time 842607849 ps
CPU time 2.34 seconds
Started May 02 01:49:39 PM PDT 24
Finished May 02 01:49:43 PM PDT 24
Peak memory 204180 kb
Host smart-4e82b74d-0a40-4b17-b36a-4b0be61b7829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770281906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.3770281906
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.421808632
Short name T136
Test name
Test status
Simulation time 151144534 ps
CPU time 2.24 seconds
Started May 02 01:36:16 PM PDT 24
Finished May 02 01:36:20 PM PDT 24
Peak memory 204240 kb
Host smart-5cd2d88b-02c3-43a8-9810-fcbafd648f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421808632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.421808632
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.576223352
Short name T115
Test name
Test status
Simulation time 158930607 ps
CPU time 1.17 seconds
Started May 02 01:36:36 PM PDT 24
Finished May 02 01:36:38 PM PDT 24
Peak memory 204228 kb
Host smart-68e519f5-ff13-4d6c-ba7f-baff893a7557
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576223352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.576223352
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.54473488
Short name T88
Test name
Test status
Simulation time 10078290778 ps
CPU time 57.63 seconds
Started May 02 01:45:50 PM PDT 24
Finished May 02 01:46:48 PM PDT 24
Peak memory 481004 kb
Host smart-904d2dc3-6954-4d36-b12d-e51e122d5415
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54473488 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_acq.54473488
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2539157408
Short name T381
Test name
Test status
Simulation time 53980663801 ps
CPU time 1325.48 seconds
Started May 02 01:43:36 PM PDT 24
Finished May 02 02:05:43 PM PDT 24
Peak memory 8301068 kb
Host smart-c684bd31-729e-4626-98ec-a616952cc49f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539157408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2539157408
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2003482734
Short name T247
Test name
Test status
Simulation time 28537103 ps
CPU time 0.8 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 204080 kb
Host smart-3425d7e2-ef53-4c15-a579-5f286ee75eeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003482734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2003482734
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1856079848
Short name T8
Test name
Test status
Simulation time 386758940 ps
CPU time 17.83 seconds
Started May 02 01:43:18 PM PDT 24
Finished May 02 01:43:38 PM PDT 24
Peak memory 212356 kb
Host smart-d9cacccf-d7cc-44d9-955f-e07cb6d392ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856079848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1856079848
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.2370735915
Short name T1250
Test name
Test status
Simulation time 59612056745 ps
CPU time 943.75 seconds
Started May 02 01:43:42 PM PDT 24
Finished May 02 01:59:27 PM PDT 24
Peak memory 3367912 kb
Host smart-4253c00c-7e0d-4b51-9ae8-83b4ea1194f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370735915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2370735915
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1240666022
Short name T220
Test name
Test status
Simulation time 1202037639 ps
CPU time 49.99 seconds
Started May 02 01:43:40 PM PDT 24
Finished May 02 01:44:31 PM PDT 24
Peak memory 204132 kb
Host smart-ee098bf5-60c5-4c1f-b8ba-3455728cde77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240666022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1240666022
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1238735905
Short name T234
Test name
Test status
Simulation time 21824582691 ps
CPU time 681.75 seconds
Started May 02 01:44:06 PM PDT 24
Finished May 02 01:55:28 PM PDT 24
Peak memory 2363932 kb
Host smart-5050149c-2133-4054-8f2a-68ad41b1508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238735905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1238735905
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1997975002
Short name T242
Test name
Test status
Simulation time 35740268552 ps
CPU time 2816.65 seconds
Started May 02 01:46:16 PM PDT 24
Finished May 02 02:33:14 PM PDT 24
Peak memory 2042804 kb
Host smart-1631a65d-81ec-4c65-846d-250dcd1c716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997975002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1997975002
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2930378100
Short name T97
Test name
Test status
Simulation time 68572777456 ps
CPU time 1734.68 seconds
Started May 02 01:50:06 PM PDT 24
Finished May 02 02:19:02 PM PDT 24
Peak memory 2455776 kb
Host smart-42e06ac1-364b-4889-9cc1-eeb56c924a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930378100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2930378100
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3689692107
Short name T1406
Test name
Test status
Simulation time 177903929 ps
CPU time 2.7 seconds
Started May 02 01:36:16 PM PDT 24
Finished May 02 01:36:20 PM PDT 24
Peak memory 204260 kb
Host smart-fb97ad60-aa03-4d80-b15b-f7b823092729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689692107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3689692107
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2578160754
Short name T142
Test name
Test status
Simulation time 543338174 ps
CPU time 2.36 seconds
Started May 02 01:36:44 PM PDT 24
Finished May 02 01:36:48 PM PDT 24
Peak memory 204304 kb
Host smart-3314b476-33b0-4dc8-b432-c63b68a7568d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578160754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2578160754
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.290226772
Short name T131
Test name
Test status
Simulation time 79688050 ps
CPU time 1.34 seconds
Started May 02 01:36:12 PM PDT 24
Finished May 02 01:36:15 PM PDT 24
Peak memory 204252 kb
Host smart-a61dccf0-495c-47b2-a9d1-a8d00f96ae85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290226772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.290226772
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1509071766
Short name T156
Test name
Test status
Simulation time 154023845 ps
CPU time 1.87 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:14 PM PDT 24
Peak memory 204256 kb
Host smart-13e57fab-3cef-4490-8479-0bdae0ae215f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509071766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1509071766
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3217366033
Short name T152
Test name
Test status
Simulation time 24956712 ps
CPU time 0.69 seconds
Started May 02 01:36:12 PM PDT 24
Finished May 02 01:36:15 PM PDT 24
Peak memory 203940 kb
Host smart-74f533a8-6109-4ef2-b22a-d69465693f57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217366033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3217366033
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.683928385
Short name T1422
Test name
Test status
Simulation time 130944468 ps
CPU time 0.95 seconds
Started May 02 01:36:10 PM PDT 24
Finished May 02 01:36:12 PM PDT 24
Peak memory 204056 kb
Host smart-bfcc00e3-a5d0-4b02-8d1d-cfb7e1b18bcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683928385 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.683928385
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.7222458
Short name T166
Test name
Test status
Simulation time 41922411 ps
CPU time 0.77 seconds
Started May 02 01:36:10 PM PDT 24
Finished May 02 01:36:13 PM PDT 24
Peak memory 204060 kb
Host smart-e8e9ddd4-5269-4cdf-9d8a-d4ab9e2103bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7222458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.7222458
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.2572066474
Short name T1354
Test name
Test status
Simulation time 27638915 ps
CPU time 0.66 seconds
Started May 02 01:36:16 PM PDT 24
Finished May 02 01:36:18 PM PDT 24
Peak memory 203980 kb
Host smart-c5afe0d3-e153-4026-ae8c-bb549090455e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572066474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2572066474
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1265895676
Short name T167
Test name
Test status
Simulation time 20671392 ps
CPU time 0.82 seconds
Started May 02 01:36:13 PM PDT 24
Finished May 02 01:36:16 PM PDT 24
Peak memory 203968 kb
Host smart-5a709501-b384-47eb-adad-9acd243d0c92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265895676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1265895676
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.768151308
Short name T68
Test name
Test status
Simulation time 109644264 ps
CPU time 2.08 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:15 PM PDT 24
Peak memory 204216 kb
Host smart-80b93118-2ff4-422e-a140-706689a9d4a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768151308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.768151308
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3876509777
Short name T151
Test name
Test status
Simulation time 25245740 ps
CPU time 0.73 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:13 PM PDT 24
Peak memory 204088 kb
Host smart-c1f54b0d-4f9a-4650-b4be-71891d01ec29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876509777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3876509777
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2638698313
Short name T1426
Test name
Test status
Simulation time 85418488 ps
CPU time 0.86 seconds
Started May 02 01:36:13 PM PDT 24
Finished May 02 01:36:17 PM PDT 24
Peak memory 204024 kb
Host smart-78052397-da59-4876-9c8c-da86e88dcfee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638698313 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2638698313
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2295551867
Short name T157
Test name
Test status
Simulation time 38767077 ps
CPU time 0.74 seconds
Started May 02 01:36:13 PM PDT 24
Finished May 02 01:36:16 PM PDT 24
Peak memory 203956 kb
Host smart-37775f4d-0976-4fc8-9f41-b6f2cabc1e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295551867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2295551867
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1359612278
Short name T1391
Test name
Test status
Simulation time 55583042 ps
CPU time 0.64 seconds
Started May 02 01:36:10 PM PDT 24
Finished May 02 01:36:12 PM PDT 24
Peak memory 203940 kb
Host smart-1ce1db24-62cc-4830-9935-7c535cbeb83f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359612278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1359612278
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.471542973
Short name T1369
Test name
Test status
Simulation time 27854865 ps
CPU time 1.38 seconds
Started May 02 01:36:12 PM PDT 24
Finished May 02 01:36:16 PM PDT 24
Peak memory 204180 kb
Host smart-b5b5178f-97cd-497d-9b76-851b890cab5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471542973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.471542973
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1025832042
Short name T135
Test name
Test status
Simulation time 85273711 ps
CPU time 1.37 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:14 PM PDT 24
Peak memory 204280 kb
Host smart-23e8b57c-0a4f-40a6-8fa8-0661d8819b07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025832042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1025832042
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3168343677
Short name T1421
Test name
Test status
Simulation time 299260487 ps
CPU time 1.66 seconds
Started May 02 01:36:27 PM PDT 24
Finished May 02 01:36:30 PM PDT 24
Peak memory 204380 kb
Host smart-c0740aef-f354-45ce-ad73-a8bd14d39487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168343677 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3168343677
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2916724768
Short name T165
Test name
Test status
Simulation time 45910769 ps
CPU time 0.67 seconds
Started May 02 01:36:27 PM PDT 24
Finished May 02 01:36:29 PM PDT 24
Peak memory 204048 kb
Host smart-fc5fb459-c213-4c6b-8e25-9540dcf00689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916724768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2916724768
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1221099992
Short name T1409
Test name
Test status
Simulation time 30153996 ps
CPU time 0.62 seconds
Started May 02 01:36:28 PM PDT 24
Finished May 02 01:36:30 PM PDT 24
Peak memory 203964 kb
Host smart-6875221a-c372-41f7-a31a-177b03a5ca5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221099992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1221099992
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1003510841
Short name T140
Test name
Test status
Simulation time 104448320 ps
CPU time 1.53 seconds
Started May 02 01:36:29 PM PDT 24
Finished May 02 01:36:32 PM PDT 24
Peak memory 204332 kb
Host smart-bab1e651-cd5d-46e2-b01c-87fdeea88f30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003510841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1003510841
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3189206697
Short name T170
Test name
Test status
Simulation time 38278659 ps
CPU time 0.94 seconds
Started May 02 01:36:35 PM PDT 24
Finished May 02 01:36:37 PM PDT 24
Peak memory 204132 kb
Host smart-6b4ea2b5-0726-4c93-8b28-7b06f74fa29c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189206697 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3189206697
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.349457635
Short name T1358
Test name
Test status
Simulation time 54515163 ps
CPU time 0.68 seconds
Started May 02 01:36:36 PM PDT 24
Finished May 02 01:36:38 PM PDT 24
Peak memory 203964 kb
Host smart-8ea8248c-9b4c-401c-a537-e3c4998713cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349457635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.349457635
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1869600153
Short name T1399
Test name
Test status
Simulation time 754113170 ps
CPU time 2.04 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:30 PM PDT 24
Peak memory 204144 kb
Host smart-031cadd6-ac6a-4570-80b3-8bb9fc59060a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869600153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1869600153
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3648961658
Short name T1372
Test name
Test status
Simulation time 19164783 ps
CPU time 0.86 seconds
Started May 02 01:36:36 PM PDT 24
Finished May 02 01:36:38 PM PDT 24
Peak memory 204040 kb
Host smart-8383b493-68f2-423e-9c77-ccc65548fb32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648961658 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3648961658
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2115161316
Short name T153
Test name
Test status
Simulation time 20726849 ps
CPU time 0.77 seconds
Started May 02 01:36:35 PM PDT 24
Finished May 02 01:36:36 PM PDT 24
Peak memory 204084 kb
Host smart-e0fdc3e6-37fe-4540-8402-09907da9c451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115161316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2115161316
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3445438134
Short name T1390
Test name
Test status
Simulation time 17262530 ps
CPU time 0.66 seconds
Started May 02 01:36:33 PM PDT 24
Finished May 02 01:36:35 PM PDT 24
Peak memory 203988 kb
Host smart-9c586e26-4529-4679-82df-86b1d9b5c434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445438134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3445438134
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2913234051
Short name T1433
Test name
Test status
Simulation time 100204157 ps
CPU time 1.12 seconds
Started May 02 01:36:35 PM PDT 24
Finished May 02 01:36:37 PM PDT 24
Peak memory 204232 kb
Host smart-ab48358a-a72e-4cc7-86c0-e6562e104e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913234051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2913234051
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3417192972
Short name T147
Test name
Test status
Simulation time 116452202 ps
CPU time 0.77 seconds
Started May 02 01:36:34 PM PDT 24
Finished May 02 01:36:36 PM PDT 24
Peak memory 204152 kb
Host smart-1811072f-1406-4035-a42c-544ca1922e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417192972 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3417192972
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.628411306
Short name T1375
Test name
Test status
Simulation time 20835709 ps
CPU time 0.69 seconds
Started May 02 01:36:35 PM PDT 24
Finished May 02 01:36:37 PM PDT 24
Peak memory 204028 kb
Host smart-e61ec850-2aa3-4b0d-a07f-5803dfe7f1f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628411306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.628411306
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2495046876
Short name T1425
Test name
Test status
Simulation time 66580937 ps
CPU time 0.67 seconds
Started May 02 01:36:36 PM PDT 24
Finished May 02 01:36:38 PM PDT 24
Peak memory 203968 kb
Host smart-428180b9-d620-44a1-931e-aa885ac6ffc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495046876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2495046876
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.567469825
Short name T161
Test name
Test status
Simulation time 261864791 ps
CPU time 0.87 seconds
Started May 02 01:36:33 PM PDT 24
Finished May 02 01:36:35 PM PDT 24
Peak memory 204072 kb
Host smart-a361cefd-db24-4dc5-a434-d644e8c98a78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567469825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.567469825
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1155160845
Short name T1389
Test name
Test status
Simulation time 58061298 ps
CPU time 1.35 seconds
Started May 02 01:36:35 PM PDT 24
Finished May 02 01:36:37 PM PDT 24
Peak memory 204256 kb
Host smart-dbe9271a-ac3e-4be2-8e12-fab476c03fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155160845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1155160845
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1562127947
Short name T149
Test name
Test status
Simulation time 29798420 ps
CPU time 0.87 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 204140 kb
Host smart-fa1b652b-b9f2-44d5-b09b-9ceba305b0f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562127947 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1562127947
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1908974364
Short name T1414
Test name
Test status
Simulation time 84499124 ps
CPU time 0.68 seconds
Started May 02 01:36:36 PM PDT 24
Finished May 02 01:36:38 PM PDT 24
Peak memory 203972 kb
Host smart-d5a36cb4-3650-4d00-8739-c035d7e2fc34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908974364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1908974364
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1410450832
Short name T1370
Test name
Test status
Simulation time 21039192 ps
CPU time 0.69 seconds
Started May 02 01:36:35 PM PDT 24
Finished May 02 01:36:37 PM PDT 24
Peak memory 203996 kb
Host smart-21eed066-d6cf-4fc9-ae9a-5077f23a2d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410450832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1410450832
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3677078175
Short name T1429
Test name
Test status
Simulation time 168803033 ps
CPU time 1.99 seconds
Started May 02 01:36:37 PM PDT 24
Finished May 02 01:36:40 PM PDT 24
Peak memory 204288 kb
Host smart-28ebcf38-e108-4065-aae6-b5eb13b4929b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677078175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3677078175
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2952641334
Short name T138
Test name
Test status
Simulation time 453664070 ps
CPU time 1.42 seconds
Started May 02 01:36:34 PM PDT 24
Finished May 02 01:36:36 PM PDT 24
Peak memory 204176 kb
Host smart-c2eb4d94-d59b-4b80-9e1e-4ad9f3797724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952641334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2952641334
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2452129375
Short name T66
Test name
Test status
Simulation time 18804909 ps
CPU time 0.89 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:44 PM PDT 24
Peak memory 204048 kb
Host smart-b47b8510-2eb1-4c0e-a6b0-423e18d54860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452129375 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2452129375
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2560141507
Short name T158
Test name
Test status
Simulation time 22875265 ps
CPU time 0.77 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:45 PM PDT 24
Peak memory 204060 kb
Host smart-56d6d2c4-355d-42f4-a708-b5400ef21c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560141507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2560141507
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2579006549
Short name T1413
Test name
Test status
Simulation time 21045617 ps
CPU time 0.65 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:44 PM PDT 24
Peak memory 203948 kb
Host smart-110f3457-2bd7-4811-a82a-ea7d37872f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579006549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2579006549
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2900667293
Short name T128
Test name
Test status
Simulation time 298558518 ps
CPU time 1.9 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 204128 kb
Host smart-3d7600d8-2e7f-49a2-a265-0b64a0df9fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900667293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2900667293
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.244862017
Short name T139
Test name
Test status
Simulation time 139147886 ps
CPU time 1.64 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 204184 kb
Host smart-2ed1596f-344d-4471-8514-ded7a9f27bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244862017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.244862017
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2467354933
Short name T1397
Test name
Test status
Simulation time 20853177 ps
CPU time 0.87 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:44 PM PDT 24
Peak memory 204152 kb
Host smart-7c2d4a2e-85b7-4e9f-b529-f33a173a4c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467354933 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2467354933
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.908821829
Short name T160
Test name
Test status
Simulation time 81225014 ps
CPU time 0.78 seconds
Started May 02 01:36:40 PM PDT 24
Finished May 02 01:36:43 PM PDT 24
Peak memory 203952 kb
Host smart-8e7211f9-2cb9-4545-8094-f4389c258b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908821829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.908821829
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3345879677
Short name T1376
Test name
Test status
Simulation time 22393440 ps
CPU time 0.66 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:44 PM PDT 24
Peak memory 203996 kb
Host smart-b13ddd84-f19a-48a1-8fc9-f3c86d15ab74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345879677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3345879677
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2468169049
Short name T1407
Test name
Test status
Simulation time 242244399 ps
CPU time 0.9 seconds
Started May 02 01:36:41 PM PDT 24
Finished May 02 01:36:43 PM PDT 24
Peak memory 204048 kb
Host smart-11f4500d-b002-49a2-9b2e-cb7768d8a4a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468169049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.2468169049
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2065637596
Short name T1438
Test name
Test status
Simulation time 120563260 ps
CPU time 1.83 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 204188 kb
Host smart-dc495f15-4c7b-479e-979e-26872cc3f4b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065637596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2065637596
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2976195769
Short name T145
Test name
Test status
Simulation time 529392591 ps
CPU time 2.35 seconds
Started May 02 01:36:45 PM PDT 24
Finished May 02 01:36:49 PM PDT 24
Peak memory 204292 kb
Host smart-100d2353-a152-4445-91ae-682a2f2ac6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976195769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2976195769
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1612891047
Short name T1440
Test name
Test status
Simulation time 50503515 ps
CPU time 0.86 seconds
Started May 02 01:36:41 PM PDT 24
Finished May 02 01:36:43 PM PDT 24
Peak memory 204052 kb
Host smart-a1956d83-57b3-47f6-ade3-23f2b309aaac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612891047 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1612891047
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1805872094
Short name T1403
Test name
Test status
Simulation time 20245918 ps
CPU time 0.68 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:45 PM PDT 24
Peak memory 203920 kb
Host smart-a3b6b6f2-2e75-40bb-8c30-c154825ae543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805872094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1805872094
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3405704698
Short name T1417
Test name
Test status
Simulation time 107443686 ps
CPU time 1.12 seconds
Started May 02 01:36:44 PM PDT 24
Finished May 02 01:36:47 PM PDT 24
Peak memory 204156 kb
Host smart-1d45142e-c82d-459b-a440-44b55ec8f2df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405704698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3405704698
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1336646975
Short name T1394
Test name
Test status
Simulation time 66643158 ps
CPU time 1 seconds
Started May 02 01:36:46 PM PDT 24
Finished May 02 01:36:48 PM PDT 24
Peak memory 204196 kb
Host smart-4ce04f61-eb72-4c86-8fd8-cb9b8ea2deab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336646975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1336646975
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1450471767
Short name T1395
Test name
Test status
Simulation time 56180025 ps
CPU time 0.91 seconds
Started May 02 01:36:44 PM PDT 24
Finished May 02 01:36:47 PM PDT 24
Peak memory 204064 kb
Host smart-a4cb50dd-a50d-4473-a941-fc0a6dffa9bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450471767 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1450471767
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3930081179
Short name T1408
Test name
Test status
Simulation time 45995924 ps
CPU time 0.62 seconds
Started May 02 01:36:44 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 203932 kb
Host smart-a4e56ae0-6237-42ad-8d87-8ca2f78afaa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930081179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3930081179
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1939329810
Short name T137
Test name
Test status
Simulation time 79612665 ps
CPU time 1.16 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:44 PM PDT 24
Peak memory 204236 kb
Host smart-f6e35bdf-25b7-495e-b3cf-4eaf86732b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939329810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1939329810
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2554070979
Short name T1374
Test name
Test status
Simulation time 183099726 ps
CPU time 1.05 seconds
Started May 02 01:36:41 PM PDT 24
Finished May 02 01:36:43 PM PDT 24
Peak memory 204104 kb
Host smart-9a65ddd9-ffa5-4f12-8d1a-d2b9160a8ca3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554070979 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2554070979
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2924712022
Short name T1430
Test name
Test status
Simulation time 64842045 ps
CPU time 0.68 seconds
Started May 02 01:36:44 PM PDT 24
Finished May 02 01:36:47 PM PDT 24
Peak memory 204048 kb
Host smart-b0aa60ef-5dca-48ac-8526-849c4e943d43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924712022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2924712022
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1650223044
Short name T1427
Test name
Test status
Simulation time 19023919 ps
CPU time 0.75 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:45 PM PDT 24
Peak memory 204000 kb
Host smart-c3b4a6d9-77d3-4538-adfd-3c158fb5df6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650223044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1650223044
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2187555869
Short name T162
Test name
Test status
Simulation time 44670538 ps
CPU time 0.86 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:45 PM PDT 24
Peak memory 204024 kb
Host smart-0ce07c38-f7b1-4e03-8e70-b02318756866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187555869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2187555869
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2793267274
Short name T129
Test name
Test status
Simulation time 220752408 ps
CPU time 2.05 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 204252 kb
Host smart-175cfc5e-ab0e-43e1-8b13-da833bb8d5e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793267274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2793267274
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2497263055
Short name T155
Test name
Test status
Simulation time 65378209 ps
CPU time 1.4 seconds
Started May 02 01:36:13 PM PDT 24
Finished May 02 01:36:17 PM PDT 24
Peak memory 204132 kb
Host smart-5650a387-8b1a-4b39-a0c7-bae24ce294d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497263055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2497263055
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1995361002
Short name T1442
Test name
Test status
Simulation time 57766049 ps
CPU time 0.73 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:14 PM PDT 24
Peak memory 204008 kb
Host smart-638ba3be-d0ca-4f34-8457-799650b46a8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995361002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1995361002
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3152246010
Short name T172
Test name
Test status
Simulation time 165645617 ps
CPU time 0.91 seconds
Started May 02 01:36:18 PM PDT 24
Finished May 02 01:36:20 PM PDT 24
Peak memory 204024 kb
Host smart-77e54de5-137b-4cf9-92a7-0148ee47c709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152246010 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3152246010
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.556641000
Short name T1381
Test name
Test status
Simulation time 26564316 ps
CPU time 0.77 seconds
Started May 02 01:36:10 PM PDT 24
Finished May 02 01:36:13 PM PDT 24
Peak memory 204056 kb
Host smart-96659a2b-d94f-4901-ae80-d8d1daa5bc10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556641000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.556641000
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3945234020
Short name T1392
Test name
Test status
Simulation time 14581277 ps
CPU time 0.64 seconds
Started May 02 01:36:13 PM PDT 24
Finished May 02 01:36:16 PM PDT 24
Peak memory 203884 kb
Host smart-38646fcc-fe73-4e79-992f-f1f4d8ee4fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945234020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3945234020
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3551050611
Short name T67
Test name
Test status
Simulation time 33284295 ps
CPU time 0.88 seconds
Started May 02 01:36:51 PM PDT 24
Finished May 02 01:36:53 PM PDT 24
Peak memory 204048 kb
Host smart-794b43b9-631f-413c-87a2-ad46fcf00903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551050611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3551050611
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1778534610
Short name T1387
Test name
Test status
Simulation time 881006521 ps
CPU time 2.41 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:16 PM PDT 24
Peak memory 204232 kb
Host smart-8951e542-706f-490d-9ecb-703ec1f62061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778534610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1778534610
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3106923518
Short name T1404
Test name
Test status
Simulation time 62987526 ps
CPU time 0.65 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:45 PM PDT 24
Peak memory 203956 kb
Host smart-f558be10-26e4-4a0e-9938-f3d811a789d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106923518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3106923518
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2195727118
Short name T188
Test name
Test status
Simulation time 47189412 ps
CPU time 0.73 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 203992 kb
Host smart-d98f23e2-bf85-4118-bb8a-cb70a3f74e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195727118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2195727118
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3550036711
Short name T1386
Test name
Test status
Simulation time 50027167 ps
CPU time 0.69 seconds
Started May 02 01:36:44 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 203964 kb
Host smart-0eafbcfe-968d-4c1c-9384-ec51a420b78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550036711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3550036711
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1789404852
Short name T1357
Test name
Test status
Simulation time 26185199 ps
CPU time 0.66 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:44 PM PDT 24
Peak memory 203868 kb
Host smart-be47024a-316b-4b36-bbdc-74fb05b7e164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789404852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1789404852
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.100490847
Short name T1378
Test name
Test status
Simulation time 19051198 ps
CPU time 0.7 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 203984 kb
Host smart-77361466-d3fe-406a-a315-a9971b797560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100490847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.100490847
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3502743515
Short name T1377
Test name
Test status
Simulation time 21626687 ps
CPU time 0.68 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:45 PM PDT 24
Peak memory 203964 kb
Host smart-1c582c1b-b4ec-436f-bff5-c1d42acfa922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502743515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3502743515
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.29695260
Short name T1362
Test name
Test status
Simulation time 21965725 ps
CPU time 0.64 seconds
Started May 02 01:36:40 PM PDT 24
Finished May 02 01:36:41 PM PDT 24
Peak memory 203984 kb
Host smart-487d157c-8e4c-464b-8a72-0b2587668d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29695260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.29695260
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1078835507
Short name T1419
Test name
Test status
Simulation time 38057006 ps
CPU time 0.65 seconds
Started May 02 01:36:42 PM PDT 24
Finished May 02 01:36:43 PM PDT 24
Peak memory 203972 kb
Host smart-f44f3bc5-c27a-4404-a5e3-d39f8640e430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078835507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1078835507
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.743593574
Short name T1410
Test name
Test status
Simulation time 33094188 ps
CPU time 0.69 seconds
Started May 02 01:36:41 PM PDT 24
Finished May 02 01:36:43 PM PDT 24
Peak memory 203936 kb
Host smart-e1838eed-1b78-43c4-b5ac-923890b2e202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743593574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.743593574
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2416860678
Short name T1423
Test name
Test status
Simulation time 102904126 ps
CPU time 0.71 seconds
Started May 02 01:36:44 PM PDT 24
Finished May 02 01:36:47 PM PDT 24
Peak memory 203980 kb
Host smart-8c1214b1-7f97-4994-835c-05f58ce1553d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416860678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2416860678
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1836364915
Short name T171
Test name
Test status
Simulation time 77131822 ps
CPU time 1.41 seconds
Started May 02 01:36:18 PM PDT 24
Finished May 02 01:36:20 PM PDT 24
Peak memory 204248 kb
Host smart-1c5aad7a-866b-4a69-bb7d-30ae31001fbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836364915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1836364915
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.359027937
Short name T1436
Test name
Test status
Simulation time 21488118 ps
CPU time 0.77 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:23 PM PDT 24
Peak memory 204068 kb
Host smart-e3f85cef-7e0f-49cd-8b89-e7ed5be6cc1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359027937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.359027937
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1265567522
Short name T1418
Test name
Test status
Simulation time 155510122 ps
CPU time 0.96 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:23 PM PDT 24
Peak memory 204152 kb
Host smart-e11b5eee-1a8c-4ab3-88c5-7be16b739671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265567522 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1265567522
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.374487883
Short name T1379
Test name
Test status
Simulation time 25753342 ps
CPU time 0.84 seconds
Started May 02 01:36:18 PM PDT 24
Finished May 02 01:36:20 PM PDT 24
Peak memory 204088 kb
Host smart-db1ca968-72ce-46f8-8cf5-db4595287aaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374487883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.374487883
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.509429300
Short name T1384
Test name
Test status
Simulation time 15697248 ps
CPU time 0.66 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 203968 kb
Host smart-140a3355-4f27-46e8-8960-656b1b179bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509429300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.509429300
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.211348579
Short name T1428
Test name
Test status
Simulation time 168196652 ps
CPU time 2.19 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:24 PM PDT 24
Peak memory 204220 kb
Host smart-eb2e1ddb-bbc0-4f73-bb65-d4443cd9a997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211348579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.211348579
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4166321792
Short name T1437
Test name
Test status
Simulation time 112406328 ps
CPU time 1.38 seconds
Started May 02 01:36:18 PM PDT 24
Finished May 02 01:36:20 PM PDT 24
Peak memory 204180 kb
Host smart-b0f427fe-797f-4800-b95d-c75f652b4db8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166321792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.4166321792
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3898545737
Short name T1371
Test name
Test status
Simulation time 15464483 ps
CPU time 0.66 seconds
Started May 02 01:36:43 PM PDT 24
Finished May 02 01:36:46 PM PDT 24
Peak memory 203948 kb
Host smart-33b9795a-011e-4ea9-aea8-fb5bd86639fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898545737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3898545737
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2320292896
Short name T1359
Test name
Test status
Simulation time 22334652 ps
CPU time 0.63 seconds
Started May 02 01:36:50 PM PDT 24
Finished May 02 01:36:52 PM PDT 24
Peak memory 203984 kb
Host smart-a7a6ce2c-caba-4c89-88f9-ee82c39b457a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320292896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2320292896
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.597025017
Short name T1368
Test name
Test status
Simulation time 75436595 ps
CPU time 0.63 seconds
Started May 02 01:36:53 PM PDT 24
Finished May 02 01:36:55 PM PDT 24
Peak memory 203876 kb
Host smart-152c733c-7ecd-47fc-8b9f-f0e7f8b65f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597025017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.597025017
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1473842209
Short name T1441
Test name
Test status
Simulation time 27754318 ps
CPU time 0.64 seconds
Started May 02 01:36:48 PM PDT 24
Finished May 02 01:36:50 PM PDT 24
Peak memory 203940 kb
Host smart-88b3d250-43bd-47ad-9642-a9db832d0af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473842209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1473842209
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.324901780
Short name T1364
Test name
Test status
Simulation time 38257988 ps
CPU time 0.63 seconds
Started May 02 01:36:50 PM PDT 24
Finished May 02 01:36:53 PM PDT 24
Peak memory 203936 kb
Host smart-04e9d807-80cc-45d8-8acb-f4318a3c0eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324901780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.324901780
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.490187264
Short name T1361
Test name
Test status
Simulation time 92261788 ps
CPU time 0.68 seconds
Started May 02 01:36:49 PM PDT 24
Finished May 02 01:36:51 PM PDT 24
Peak memory 203960 kb
Host smart-b9233c20-fd6c-4d80-9f06-920c50471e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490187264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.490187264
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.406384654
Short name T1400
Test name
Test status
Simulation time 42794854 ps
CPU time 0.68 seconds
Started May 02 01:36:51 PM PDT 24
Finished May 02 01:36:53 PM PDT 24
Peak memory 203968 kb
Host smart-5a8b1f62-4ca1-4a98-b51f-6638c0dad26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406384654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.406384654
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2749501590
Short name T1367
Test name
Test status
Simulation time 49368159 ps
CPU time 0.66 seconds
Started May 02 01:36:53 PM PDT 24
Finished May 02 01:36:55 PM PDT 24
Peak memory 203876 kb
Host smart-01264acb-bf82-4212-b109-d98908ddd293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749501590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2749501590
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1881713543
Short name T1412
Test name
Test status
Simulation time 67067120 ps
CPU time 0.66 seconds
Started May 02 01:36:48 PM PDT 24
Finished May 02 01:36:50 PM PDT 24
Peak memory 203952 kb
Host smart-4a9b6654-ceea-4b10-9a69-cd08f7505408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881713543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1881713543
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1542543314
Short name T1405
Test name
Test status
Simulation time 17574012 ps
CPU time 0.68 seconds
Started May 02 01:36:50 PM PDT 24
Finished May 02 01:36:53 PM PDT 24
Peak memory 204008 kb
Host smart-0c0510d1-a896-4e13-914d-b11439e58e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542543314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1542543314
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3524348763
Short name T1435
Test name
Test status
Simulation time 54003074 ps
CPU time 1.28 seconds
Started May 02 01:36:21 PM PDT 24
Finished May 02 01:36:24 PM PDT 24
Peak memory 204188 kb
Host smart-3ef39e04-dcbf-4690-9673-70b4e3990846
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524348763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3524348763
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1718926175
Short name T144
Test name
Test status
Simulation time 27279641 ps
CPU time 1.15 seconds
Started May 02 01:36:23 PM PDT 24
Finished May 02 01:36:26 PM PDT 24
Peak memory 204196 kb
Host smart-bf6ebbe5-78bb-484a-a202-4b7a4ab03669
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718926175 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1718926175
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.549629022
Short name T154
Test name
Test status
Simulation time 34189612 ps
CPU time 0.69 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 204056 kb
Host smart-1dcb138e-287e-4190-beaf-b26c35d5d186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549629022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.549629022
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1667488664
Short name T1432
Test name
Test status
Simulation time 20792604 ps
CPU time 0.72 seconds
Started May 02 01:36:21 PM PDT 24
Finished May 02 01:36:24 PM PDT 24
Peak memory 203996 kb
Host smart-2f5fbd9e-07e5-4e23-a68f-8101ae2d798d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667488664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1667488664
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.108103353
Short name T1443
Test name
Test status
Simulation time 70984531 ps
CPU time 1.19 seconds
Started May 02 01:36:22 PM PDT 24
Finished May 02 01:36:25 PM PDT 24
Peak memory 204276 kb
Host smart-ec3efca3-ebef-4137-9afa-2bd403588610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108103353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.108103353
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3817015800
Short name T143
Test name
Test status
Simulation time 135759836 ps
CPU time 2.09 seconds
Started May 02 01:36:18 PM PDT 24
Finished May 02 01:36:21 PM PDT 24
Peak memory 204264 kb
Host smart-bf4310e1-420b-4976-a877-cd4c6cc45a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817015800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3817015800
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.816328622
Short name T1420
Test name
Test status
Simulation time 16080504 ps
CPU time 0.67 seconds
Started May 02 01:36:49 PM PDT 24
Finished May 02 01:36:51 PM PDT 24
Peak memory 203972 kb
Host smart-468665ec-e308-46a9-9a6e-30e4b81a3837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816328622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.816328622
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1039785030
Short name T1402
Test name
Test status
Simulation time 49354355 ps
CPU time 0.63 seconds
Started May 02 01:36:50 PM PDT 24
Finished May 02 01:36:52 PM PDT 24
Peak memory 203948 kb
Host smart-35583d71-8e1a-41a4-9898-68da79814c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039785030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1039785030
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2131801547
Short name T1415
Test name
Test status
Simulation time 38000550 ps
CPU time 0.66 seconds
Started May 02 01:36:52 PM PDT 24
Finished May 02 01:36:54 PM PDT 24
Peak memory 203960 kb
Host smart-0ba1e0ad-3397-4a5f-b598-2cd3c2c5484e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131801547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2131801547
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.439489305
Short name T1382
Test name
Test status
Simulation time 18642042 ps
CPU time 0.68 seconds
Started May 02 01:36:52 PM PDT 24
Finished May 02 01:36:55 PM PDT 24
Peak memory 203992 kb
Host smart-c09c59d5-47db-4347-b34d-2451ea8e19c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439489305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.439489305
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.996939906
Short name T1355
Test name
Test status
Simulation time 24321525 ps
CPU time 0.65 seconds
Started May 02 01:36:50 PM PDT 24
Finished May 02 01:36:52 PM PDT 24
Peak memory 203960 kb
Host smart-be2cb51c-edcf-4948-9281-9019d7030792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996939906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.996939906
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1053797047
Short name T1393
Test name
Test status
Simulation time 26105096 ps
CPU time 0.61 seconds
Started May 02 01:36:48 PM PDT 24
Finished May 02 01:36:49 PM PDT 24
Peak memory 203212 kb
Host smart-fc260cf6-85d8-4c88-a159-9c6c4b6c9a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053797047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1053797047
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2559381249
Short name T1360
Test name
Test status
Simulation time 18461482 ps
CPU time 0.67 seconds
Started May 02 01:36:50 PM PDT 24
Finished May 02 01:36:53 PM PDT 24
Peak memory 203940 kb
Host smart-27e0b9af-ac3a-49a2-8d6c-190d881e9d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559381249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2559381249
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2642967892
Short name T1365
Test name
Test status
Simulation time 38851212 ps
CPU time 0.62 seconds
Started May 02 01:36:53 PM PDT 24
Finished May 02 01:36:55 PM PDT 24
Peak memory 203868 kb
Host smart-c724ef5e-1c45-4270-81c1-c6d41fe3c53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642967892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2642967892
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3100040967
Short name T1366
Test name
Test status
Simulation time 28110745 ps
CPU time 0.65 seconds
Started May 02 01:36:51 PM PDT 24
Finished May 02 01:36:53 PM PDT 24
Peak memory 203948 kb
Host smart-4891dc91-158a-43cb-8ced-078ceeeaeddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100040967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3100040967
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1865569129
Short name T1385
Test name
Test status
Simulation time 38962839 ps
CPU time 0.63 seconds
Started May 02 01:36:52 PM PDT 24
Finished May 02 01:36:54 PM PDT 24
Peak memory 203952 kb
Host smart-bc37b912-c1b9-466d-8a6d-0f96939546ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865569129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1865569129
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2694756722
Short name T1434
Test name
Test status
Simulation time 148635517 ps
CPU time 0.98 seconds
Started May 02 01:36:19 PM PDT 24
Finished May 02 01:36:21 PM PDT 24
Peak memory 204156 kb
Host smart-6db2ca8a-6cd3-42c6-b036-79d7fd488f63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694756722 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2694756722
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1551114916
Short name T1431
Test name
Test status
Simulation time 60160089 ps
CPU time 0.66 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 203936 kb
Host smart-91dc8405-710d-45e8-afdd-09d21d386e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551114916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1551114916
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.146736721
Short name T1388
Test name
Test status
Simulation time 22291511 ps
CPU time 0.65 seconds
Started May 02 01:36:21 PM PDT 24
Finished May 02 01:36:23 PM PDT 24
Peak memory 203988 kb
Host smart-5b906ba2-2fb0-42e9-bf66-6ffe225234d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146736721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.146736721
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.880914776
Short name T134
Test name
Test status
Simulation time 46404909 ps
CPU time 2.33 seconds
Started May 02 01:36:19 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 204212 kb
Host smart-3adf69c4-9056-44a1-b6d4-82904454d3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880914776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.880914776
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3095521813
Short name T1398
Test name
Test status
Simulation time 70851031 ps
CPU time 0.96 seconds
Started May 02 01:36:20 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 204124 kb
Host smart-7cfe21fd-696b-4255-9eae-7c851ee9fba0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095521813 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3095521813
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.595542558
Short name T1396
Test name
Test status
Simulation time 17414427 ps
CPU time 0.79 seconds
Started May 02 01:36:21 PM PDT 24
Finished May 02 01:36:23 PM PDT 24
Peak memory 204036 kb
Host smart-5cf56f4d-6fe9-44e9-a9d8-b502f367b265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595542558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.595542558
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2733274203
Short name T1383
Test name
Test status
Simulation time 104264343 ps
CPU time 0.64 seconds
Started May 02 01:36:21 PM PDT 24
Finished May 02 01:36:23 PM PDT 24
Peak memory 203948 kb
Host smart-61aa8b66-b2c8-4d3f-9b37-3c58deb9f921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733274203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2733274203
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2580833704
Short name T1380
Test name
Test status
Simulation time 69274146 ps
CPU time 0.9 seconds
Started May 02 01:36:19 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 204080 kb
Host smart-6e516ca7-f8ef-43ce-93d6-be422ed6222c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580833704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2580833704
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3195417888
Short name T133
Test name
Test status
Simulation time 72297212 ps
CPU time 1.99 seconds
Started May 02 01:36:19 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 204304 kb
Host smart-24233a5c-af1c-4047-a425-3425f0e805bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195417888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3195417888
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3843027579
Short name T1424
Test name
Test status
Simulation time 168278933 ps
CPU time 1.41 seconds
Started May 02 01:36:21 PM PDT 24
Finished May 02 01:36:24 PM PDT 24
Peak memory 204212 kb
Host smart-416b56d7-2f16-42c4-9596-16f8af28ca40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843027579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3843027579
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2075237641
Short name T1363
Test name
Test status
Simulation time 107389659 ps
CPU time 1.31 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:29 PM PDT 24
Peak memory 204356 kb
Host smart-027c651f-0439-4704-9f53-e7d73b92a294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075237641 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2075237641
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3713355178
Short name T182
Test name
Test status
Simulation time 62210717 ps
CPU time 0.68 seconds
Started May 02 01:36:23 PM PDT 24
Finished May 02 01:36:25 PM PDT 24
Peak memory 204032 kb
Host smart-82358855-0a94-4b1e-bea9-634c4abd82e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713355178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3713355178
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3471999973
Short name T1411
Test name
Test status
Simulation time 42579494 ps
CPU time 0.63 seconds
Started May 02 01:36:23 PM PDT 24
Finished May 02 01:36:25 PM PDT 24
Peak memory 203960 kb
Host smart-64eb1eb4-1cc0-48dd-8b60-2e9ea5193db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471999973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3471999973
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.228645578
Short name T163
Test name
Test status
Simulation time 85885533 ps
CPU time 1.09 seconds
Started May 02 01:36:22 PM PDT 24
Finished May 02 01:36:25 PM PDT 24
Peak memory 204148 kb
Host smart-3ffcf48a-90b6-4e07-b557-da424814f4e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228645578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.228645578
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4276189558
Short name T132
Test name
Test status
Simulation time 103529214 ps
CPU time 2.24 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:29 PM PDT 24
Peak memory 204196 kb
Host smart-05742484-a648-4c41-9957-19c5331f1264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276189558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4276189558
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1793271671
Short name T146
Test name
Test status
Simulation time 82686225 ps
CPU time 0.84 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:28 PM PDT 24
Peak memory 204132 kb
Host smart-100cca6c-e7bd-454b-abaf-944b3c1f7463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793271671 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1793271671
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.58911980
Short name T159
Test name
Test status
Simulation time 18859367 ps
CPU time 0.68 seconds
Started May 02 01:36:27 PM PDT 24
Finished May 02 01:36:28 PM PDT 24
Peak memory 204056 kb
Host smart-38177fe9-6af3-4c09-a8d4-2660f5707cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58911980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.58911980
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.680693387
Short name T1356
Test name
Test status
Simulation time 19949194 ps
CPU time 0.75 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:28 PM PDT 24
Peak memory 203952 kb
Host smart-063295be-67bc-4e3a-b0e9-8afd89744f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680693387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.680693387
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2370378987
Short name T1401
Test name
Test status
Simulation time 166330389 ps
CPU time 1.17 seconds
Started May 02 01:36:27 PM PDT 24
Finished May 02 01:36:30 PM PDT 24
Peak memory 204232 kb
Host smart-ab7d82ec-ee23-44cc-be43-d0d61d00d653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370378987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2370378987
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2534605671
Short name T1373
Test name
Test status
Simulation time 211786264 ps
CPU time 1.3 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:29 PM PDT 24
Peak memory 204112 kb
Host smart-d400a0aa-cf0d-427f-b400-ea3f85949678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534605671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2534605671
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2115808918
Short name T148
Test name
Test status
Simulation time 219970393 ps
CPU time 0.75 seconds
Started May 02 01:36:28 PM PDT 24
Finished May 02 01:36:30 PM PDT 24
Peak memory 204120 kb
Host smart-5a759cb8-b91e-433f-8624-042bd323b329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115808918 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2115808918
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1309004373
Short name T164
Test name
Test status
Simulation time 28568618 ps
CPU time 0.77 seconds
Started May 02 01:36:27 PM PDT 24
Finished May 02 01:36:29 PM PDT 24
Peak memory 204048 kb
Host smart-0e102b8e-b167-492c-ac7f-dc4ef2428416
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309004373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1309004373
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.4193469723
Short name T1416
Test name
Test status
Simulation time 29436957 ps
CPU time 0.65 seconds
Started May 02 01:36:26 PM PDT 24
Finished May 02 01:36:28 PM PDT 24
Peak memory 203900 kb
Host smart-f4dabde2-b379-471d-a725-45ef425f5ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193469723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4193469723
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3532869682
Short name T168
Test name
Test status
Simulation time 114313413 ps
CPU time 0.87 seconds
Started May 02 01:36:28 PM PDT 24
Finished May 02 01:36:30 PM PDT 24
Peak memory 204040 kb
Host smart-5d914c49-373b-40a3-80ee-bcccb5c02033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532869682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3532869682
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2744609925
Short name T1439
Test name
Test status
Simulation time 114740484 ps
CPU time 2.18 seconds
Started May 02 01:36:29 PM PDT 24
Finished May 02 01:36:32 PM PDT 24
Peak memory 204192 kb
Host smart-bf4e3408-1051-42a0-986e-4d1826a2e7e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744609925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2744609925
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2393997104
Short name T130
Test name
Test status
Simulation time 247090098 ps
CPU time 2.33 seconds
Started May 02 01:36:27 PM PDT 24
Finished May 02 01:36:30 PM PDT 24
Peak memory 204236 kb
Host smart-d80626dc-88be-4b5f-8f7b-a438ef1ea3db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393997104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2393997104
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3881270912
Short name T585
Test name
Test status
Simulation time 91571825 ps
CPU time 1.56 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:41:51 PM PDT 24
Peak memory 212476 kb
Host smart-75e9cdd7-0219-479c-9c9d-3af0d83cdc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881270912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3881270912
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3076019178
Short name T530
Test name
Test status
Simulation time 419495575 ps
CPU time 9.14 seconds
Started May 02 01:41:47 PM PDT 24
Finished May 02 01:41:57 PM PDT 24
Peak memory 294548 kb
Host smart-fbb59190-0151-48c4-af1f-b173b66c1b1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076019178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3076019178
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3161844521
Short name T539
Test name
Test status
Simulation time 10076531585 ps
CPU time 170.63 seconds
Started May 02 01:41:44 PM PDT 24
Finished May 02 01:44:36 PM PDT 24
Peak memory 755544 kb
Host smart-915473e3-f735-4d63-818d-57a383b1323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161844521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3161844521
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.4153135393
Short name T1166
Test name
Test status
Simulation time 2144448774 ps
CPU time 69.92 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:43:00 PM PDT 24
Peak memory 459640 kb
Host smart-cb6577c3-b12f-4c79-937b-23feb1f00c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153135393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.4153135393
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.4249024883
Short name T522
Test name
Test status
Simulation time 813843582 ps
CPU time 0.91 seconds
Started May 02 01:41:44 PM PDT 24
Finished May 02 01:41:47 PM PDT 24
Peak memory 203980 kb
Host smart-cb3ef49e-0212-42f9-beb3-a474f582a782
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249024883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.4249024883
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.850411109
Short name T821
Test name
Test status
Simulation time 2379175628 ps
CPU time 3.84 seconds
Started May 02 01:41:45 PM PDT 24
Finished May 02 01:41:50 PM PDT 24
Peak memory 225612 kb
Host smart-e6aaea2e-7a0d-4816-88f6-c0219a706c23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850411109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.850411109
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3316737388
Short name T1339
Test name
Test status
Simulation time 11751925855 ps
CPU time 65.37 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:57 PM PDT 24
Peak memory 934588 kb
Host smart-d0673ca4-ca42-4b74-8114-3832a53ba284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316737388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3316737388
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1258570048
Short name T505
Test name
Test status
Simulation time 671991068 ps
CPU time 6.5 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:41:57 PM PDT 24
Peak memory 204068 kb
Host smart-ff3acdcc-e628-4e05-9407-51d3eaa039fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258570048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1258570048
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.348608416
Short name T586
Test name
Test status
Simulation time 2322161246 ps
CPU time 51.25 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:42 PM PDT 24
Peak memory 268188 kb
Host smart-46c3235f-01a5-450e-aeaf-a6e9e177467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348608416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.348608416
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.4249723304
Short name T1141
Test name
Test status
Simulation time 76166992 ps
CPU time 0.65 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:41:51 PM PDT 24
Peak memory 203800 kb
Host smart-28105379-3ba3-4067-96d0-3bc9bec6b672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249723304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4249723304
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1728333658
Short name T756
Test name
Test status
Simulation time 6739759740 ps
CPU time 38.79 seconds
Started May 02 01:41:46 PM PDT 24
Finished May 02 01:42:26 PM PDT 24
Peak memory 540580 kb
Host smart-cddf7997-531d-426c-8f0d-01bcca5b5498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728333658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1728333658
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.860530371
Short name T389
Test name
Test status
Simulation time 3062689646 ps
CPU time 28.1 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:42:18 PM PDT 24
Peak memory 293596 kb
Host smart-c84802cd-6ad6-422b-940b-09c2db9d95ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860530371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.860530371
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.538645981
Short name T1123
Test name
Test status
Simulation time 2257070835 ps
CPU time 17.02 seconds
Started May 02 01:41:40 PM PDT 24
Finished May 02 01:41:59 PM PDT 24
Peak memory 220460 kb
Host smart-d86a7809-05f2-4e94-8e8c-df5846ad1907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538645981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.538645981
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1091071605
Short name T120
Test name
Test status
Simulation time 168808491 ps
CPU time 0.81 seconds
Started May 02 01:41:55 PM PDT 24
Finished May 02 01:41:57 PM PDT 24
Peak memory 221376 kb
Host smart-91058473-be2a-46f1-9b8a-e11b8665657f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091071605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1091071605
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3983972256
Short name T604
Test name
Test status
Simulation time 1341029643 ps
CPU time 2.96 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:41:53 PM PDT 24
Peak memory 204236 kb
Host smart-0b2dd752-d22b-4a7a-85d9-0713325c7bae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983972256 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3983972256
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2513509906
Short name T1177
Test name
Test status
Simulation time 10061834655 ps
CPU time 66.41 seconds
Started May 02 01:41:53 PM PDT 24
Finished May 02 01:43:00 PM PDT 24
Peak memory 482200 kb
Host smart-b08acaa9-67e9-473c-b174-a1f91ab2f6b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513509906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2513509906
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3447976478
Short name T650
Test name
Test status
Simulation time 10488981605 ps
CPU time 12.54 seconds
Started May 02 01:41:47 PM PDT 24
Finished May 02 01:42:01 PM PDT 24
Peak memory 278976 kb
Host smart-59f5c096-73d2-40dd-bd0b-c56234b028c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447976478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3447976478
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1736043175
Short name T23
Test name
Test status
Simulation time 2193655575 ps
CPU time 10.04 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:01 PM PDT 24
Peak memory 204264 kb
Host smart-c4d802d1-4552-4ce1-94ca-e4ee9c5cb437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736043175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1736043175
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3486649715
Short name T223
Test name
Test status
Simulation time 1435335409 ps
CPU time 2.3 seconds
Started May 02 01:41:50 PM PDT 24
Finished May 02 01:41:54 PM PDT 24
Peak memory 204180 kb
Host smart-20fa6e74-b984-4b7c-82bd-30205bac4122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486649715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3486649715
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3591214904
Short name T1308
Test name
Test status
Simulation time 1274720776 ps
CPU time 6.18 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:41:56 PM PDT 24
Peak memory 211512 kb
Host smart-d74caa16-6889-4185-bd1b-17a62a3379aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591214904 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3591214904
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.940515988
Short name T603
Test name
Test status
Simulation time 19874108990 ps
CPU time 118.83 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:43:50 PM PDT 24
Peak memory 1577584 kb
Host smart-23e2c54e-9d90-4db4-8e95-ec280e76a946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940515988 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.940515988
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2140048678
Short name T679
Test name
Test status
Simulation time 6093735597 ps
CPU time 16.57 seconds
Started May 02 01:41:44 PM PDT 24
Finished May 02 01:42:02 PM PDT 24
Peak memory 204232 kb
Host smart-28f70572-c9a6-46a1-aba1-0eef6767eb25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140048678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2140048678
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2188635183
Short name T250
Test name
Test status
Simulation time 1832785577 ps
CPU time 19.68 seconds
Started May 02 01:41:45 PM PDT 24
Finished May 02 01:42:06 PM PDT 24
Peak memory 204096 kb
Host smart-b515960b-3199-44ba-ac4a-3dac02041294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188635183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2188635183
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3184922332
Short name T905
Test name
Test status
Simulation time 15822924278 ps
CPU time 14.44 seconds
Started May 02 01:41:41 PM PDT 24
Finished May 02 01:41:56 PM PDT 24
Peak memory 204212 kb
Host smart-d4a7d222-2c30-431d-9bbc-e023a16ae357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184922332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3184922332
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3303585993
Short name T770
Test name
Test status
Simulation time 21093504480 ps
CPU time 409.89 seconds
Started May 02 01:41:45 PM PDT 24
Finished May 02 01:48:37 PM PDT 24
Peak memory 1284468 kb
Host smart-1e4abecc-8cd5-4a2f-89d4-11e3c77bc67f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303585993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3303585993
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2073972675
Short name T942
Test name
Test status
Simulation time 3373292979 ps
CPU time 7.73 seconds
Started May 02 01:41:45 PM PDT 24
Finished May 02 01:41:54 PM PDT 24
Peak memory 212372 kb
Host smart-14a9371f-1425-4860-bca2-9845e91d42d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073972675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2073972675
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.253985634
Short name T1053
Test name
Test status
Simulation time 16919033 ps
CPU time 0.64 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:10 PM PDT 24
Peak memory 203772 kb
Host smart-a28d1d85-10da-4be9-96a1-1f727b669fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253985634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.253985634
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2358232804
Short name T847
Test name
Test status
Simulation time 79493521 ps
CPU time 1.24 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:41:52 PM PDT 24
Peak memory 204192 kb
Host smart-2cfd6a32-28cb-46a9-9cbf-3eab6124f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358232804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2358232804
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.784260149
Short name T1104
Test name
Test status
Simulation time 638490099 ps
CPU time 5.74 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:41:56 PM PDT 24
Peak memory 269356 kb
Host smart-c7e4f573-21b7-457d-a3a7-5fe18579b27e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784260149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.784260149
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1656332639
Short name T1051
Test name
Test status
Simulation time 9096719344 ps
CPU time 160.74 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:44:32 PM PDT 24
Peak memory 723892 kb
Host smart-5cf7f097-e762-4f63-9fc1-8c5747fc0f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656332639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1656332639
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2556159687
Short name T853
Test name
Test status
Simulation time 2910930423 ps
CPU time 37.41 seconds
Started May 02 01:41:50 PM PDT 24
Finished May 02 01:42:29 PM PDT 24
Peak memory 520324 kb
Host smart-80000831-b898-45c2-b3b2-085e67b6ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556159687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2556159687
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1390067443
Short name T746
Test name
Test status
Simulation time 143661214 ps
CPU time 1.1 seconds
Started May 02 01:41:55 PM PDT 24
Finished May 02 01:41:57 PM PDT 24
Peak memory 204048 kb
Host smart-3e96bcd2-2753-4134-bb1d-370ce3d14da7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390067443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1390067443
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1226656279
Short name T90
Test name
Test status
Simulation time 633734472 ps
CPU time 4.86 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:41:56 PM PDT 24
Peak memory 233676 kb
Host smart-c72d7f00-cbb3-4705-834b-a9f3a275975e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226656279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1226656279
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1460098505
Short name T667
Test name
Test status
Simulation time 5162644132 ps
CPU time 64.7 seconds
Started May 02 01:41:48 PM PDT 24
Finished May 02 01:42:54 PM PDT 24
Peak memory 766976 kb
Host smart-19cd4297-f9f3-420b-9cdb-e45cdc6211b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460098505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1460098505
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1510542853
Short name T371
Test name
Test status
Simulation time 1833186859 ps
CPU time 18.08 seconds
Started May 02 01:41:59 PM PDT 24
Finished May 02 01:42:18 PM PDT 24
Peak memory 204116 kb
Host smart-3738885b-80b3-4135-af4d-0d8972e9cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510542853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1510542853
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.1688831070
Short name T1009
Test name
Test status
Simulation time 30705546 ps
CPU time 0.73 seconds
Started May 02 01:41:51 PM PDT 24
Finished May 02 01:41:53 PM PDT 24
Peak memory 203852 kb
Host smart-f7ec6e10-66b2-484f-9139-41fb6a666f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688831070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1688831070
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2516068126
Short name T293
Test name
Test status
Simulation time 2916350956 ps
CPU time 36.93 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:27 PM PDT 24
Peak memory 540884 kb
Host smart-5a65062a-18a1-430e-8a4d-5d36fa74759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516068126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2516068126
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3182115801
Short name T297
Test name
Test status
Simulation time 4624246862 ps
CPU time 76.14 seconds
Started May 02 01:41:50 PM PDT 24
Finished May 02 01:43:08 PM PDT 24
Peak memory 364428 kb
Host smart-517be883-f93f-4314-9ee7-ef94498f6357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182115801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3182115801
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.2815576807
Short name T832
Test name
Test status
Simulation time 6836039908 ps
CPU time 325.16 seconds
Started May 02 01:41:55 PM PDT 24
Finished May 02 01:47:21 PM PDT 24
Peak memory 1696276 kb
Host smart-1452e5a1-59d8-4b2f-b607-995454d4958e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815576807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.2815576807
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1529379115
Short name T409
Test name
Test status
Simulation time 2498212282 ps
CPU time 10.52 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:02 PM PDT 24
Peak memory 220060 kb
Host smart-0bba0d6f-813e-43d8-8e93-8b4923c9a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529379115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1529379115
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2344394957
Short name T121
Test name
Test status
Simulation time 62895495 ps
CPU time 0.98 seconds
Started May 02 01:41:59 PM PDT 24
Finished May 02 01:42:02 PM PDT 24
Peak memory 222484 kb
Host smart-17ac1511-5a37-40e7-96d8-1b526575ca37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344394957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2344394957
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3687365474
Short name T547
Test name
Test status
Simulation time 2213003579 ps
CPU time 2.81 seconds
Started May 02 01:41:56 PM PDT 24
Finished May 02 01:42:00 PM PDT 24
Peak memory 204180 kb
Host smart-f67607e7-f046-47fe-abae-d17dc445ec8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687365474 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3687365474
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2464038726
Short name T106
Test name
Test status
Simulation time 10374092228 ps
CPU time 3.73 seconds
Started May 02 01:41:57 PM PDT 24
Finished May 02 01:42:02 PM PDT 24
Peak memory 214412 kb
Host smart-db3ab9d3-07f0-49f1-9019-0dc1ad9d29fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464038726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2464038726
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1687271793
Short name T700
Test name
Test status
Simulation time 10389179128 ps
CPU time 13.31 seconds
Started May 02 01:41:58 PM PDT 24
Finished May 02 01:42:12 PM PDT 24
Peak memory 307428 kb
Host smart-f6a1b49c-6ca8-43da-a9d8-8798eefef370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687271793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1687271793
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.4034239286
Short name T1344
Test name
Test status
Simulation time 2399894878 ps
CPU time 3.13 seconds
Started May 02 01:41:56 PM PDT 24
Finished May 02 01:42:01 PM PDT 24
Peak memory 204244 kb
Host smart-2d58bb75-8ade-487c-8095-f3bb6a926a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034239286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.4034239286
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.693415273
Short name T451
Test name
Test status
Simulation time 2432163734 ps
CPU time 5.8 seconds
Started May 02 01:41:51 PM PDT 24
Finished May 02 01:41:58 PM PDT 24
Peak memory 204264 kb
Host smart-cb7524b3-60ab-42ac-8744-83c7c1397438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693415273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.693415273
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.1498423420
Short name T22
Test name
Test status
Simulation time 11712479281 ps
CPU time 10.48 seconds
Started May 02 01:41:55 PM PDT 24
Finished May 02 01:42:07 PM PDT 24
Peak memory 307324 kb
Host smart-b7ef3ebc-01fb-4fb6-bbce-ce199090c1bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498423420 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.1498423420
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.474261209
Short name T330
Test name
Test status
Simulation time 759899142 ps
CPU time 26.59 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:17 PM PDT 24
Peak memory 204124 kb
Host smart-763bdd54-1041-4d62-8e0c-beda8a33e0cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474261209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.474261209
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2889963143
Short name T1284
Test name
Test status
Simulation time 1422111012 ps
CPU time 24.02 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:42:15 PM PDT 24
Peak memory 217908 kb
Host smart-516e6419-ae94-4389-9e95-c2669b13d798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889963143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2889963143
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3484759431
Short name T1211
Test name
Test status
Simulation time 71975050612 ps
CPU time 346.23 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 01:47:38 PM PDT 24
Peak memory 3336320 kb
Host smart-03209eb0-65f7-4601-8ddf-bc2278ba6730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484759431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3484759431
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1215185093
Short name T1316
Test name
Test status
Simulation time 33538317326 ps
CPU time 1888.29 seconds
Started May 02 01:41:49 PM PDT 24
Finished May 02 02:13:20 PM PDT 24
Peak memory 3685872 kb
Host smart-5ffa73ff-0346-46f5-9b33-3ab47ef26056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215185093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1215185093
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2951494921
Short name T114
Test name
Test status
Simulation time 15536187 ps
CPU time 0.61 seconds
Started May 02 01:43:21 PM PDT 24
Finished May 02 01:43:23 PM PDT 24
Peak memory 203792 kb
Host smart-d936eb1c-22e6-47e3-bf21-08b4b95ad9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951494921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2951494921
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3388594372
Short name T418
Test name
Test status
Simulation time 289905008 ps
CPU time 1.75 seconds
Started May 02 01:43:20 PM PDT 24
Finished May 02 01:43:24 PM PDT 24
Peak memory 212456 kb
Host smart-b3218f82-7a97-4b8b-9c2f-7872a55122bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388594372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3388594372
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2488505061
Short name T706
Test name
Test status
Simulation time 752930909 ps
CPU time 8.51 seconds
Started May 02 01:43:12 PM PDT 24
Finished May 02 01:43:22 PM PDT 24
Peak memory 286600 kb
Host smart-b6e79a33-e842-4f09-b8a5-6af63cb1c13c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488505061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2488505061
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2226011068
Short name T343
Test name
Test status
Simulation time 6731047242 ps
CPU time 68.55 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:44:20 PM PDT 24
Peak memory 454488 kb
Host smart-eeb7f473-fb5d-4830-b62f-3496d6d93434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226011068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2226011068
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.2543928181
Short name T1302
Test name
Test status
Simulation time 2098378159 ps
CPU time 60.94 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:44:12 PM PDT 24
Peak memory 710764 kb
Host smart-1a64c95a-e84e-4a9b-90b2-eb59a44ad525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543928181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2543928181
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3719631923
Short name T260
Test name
Test status
Simulation time 86881461 ps
CPU time 0.85 seconds
Started May 02 01:43:11 PM PDT 24
Finished May 02 01:43:13 PM PDT 24
Peak memory 203968 kb
Host smart-f723a08c-2471-4b73-97b3-626dc448366b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719631923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3719631923
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1388550468
Short name T814
Test name
Test status
Simulation time 557108127 ps
CPU time 9.95 seconds
Started May 02 01:43:12 PM PDT 24
Finished May 02 01:43:23 PM PDT 24
Peak memory 235712 kb
Host smart-98d80f17-3ad2-4948-ab2f-81634cc7860a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388550468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1388550468
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2640700154
Short name T174
Test name
Test status
Simulation time 34500416989 ps
CPU time 63.22 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:44:14 PM PDT 24
Peak memory 889888 kb
Host smart-b8eab473-0c4f-4b98-bc44-25133d448c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640700154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2640700154
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.859033734
Short name T309
Test name
Test status
Simulation time 1122547966 ps
CPU time 5.13 seconds
Started May 02 01:43:17 PM PDT 24
Finished May 02 01:43:24 PM PDT 24
Peak memory 204124 kb
Host smart-33459ead-829d-4d16-8be7-c42fb061a4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859033734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.859033734
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2236450450
Short name T917
Test name
Test status
Simulation time 1478369736 ps
CPU time 72.71 seconds
Started May 02 01:43:19 PM PDT 24
Finished May 02 01:44:34 PM PDT 24
Peak memory 300308 kb
Host smart-8fb21d65-93af-44ec-a5db-0bb453df5d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236450450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2236450450
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3308887590
Short name T252
Test name
Test status
Simulation time 168285031 ps
CPU time 0.63 seconds
Started May 02 01:43:11 PM PDT 24
Finished May 02 01:43:13 PM PDT 24
Peak memory 203844 kb
Host smart-9725f8a0-bb0d-4052-971b-57aa42bd5ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308887590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3308887590
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3795046723
Short name T490
Test name
Test status
Simulation time 10206450518 ps
CPU time 55.37 seconds
Started May 02 01:43:09 PM PDT 24
Finished May 02 01:44:05 PM PDT 24
Peak memory 499428 kb
Host smart-c0a9350b-eba0-47cc-9149-e4bb5ad880b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795046723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3795046723
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1067525323
Short name T872
Test name
Test status
Simulation time 3152088429 ps
CPU time 75.79 seconds
Started May 02 01:43:12 PM PDT 24
Finished May 02 01:44:29 PM PDT 24
Peak memory 332504 kb
Host smart-82b0fa41-d9b5-4a89-a7d2-6c0f289eae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067525323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1067525323
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2967445545
Short name T186
Test name
Test status
Simulation time 23357964274 ps
CPU time 189.55 seconds
Started May 02 01:43:22 PM PDT 24
Finished May 02 01:46:33 PM PDT 24
Peak memory 1159872 kb
Host smart-cf464e74-2eca-471c-be09-83c8c733f6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967445545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2967445545
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.909485814
Short name T1299
Test name
Test status
Simulation time 1217226326 ps
CPU time 3.14 seconds
Started May 02 01:43:22 PM PDT 24
Finished May 02 01:43:27 PM PDT 24
Peak memory 204128 kb
Host smart-a7f8ee94-e5fa-433c-912f-26cfa78767c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909485814 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.909485814
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.252068098
Short name T1208
Test name
Test status
Simulation time 10218502230 ps
CPU time 15.24 seconds
Started May 02 01:43:18 PM PDT 24
Finished May 02 01:43:36 PM PDT 24
Peak memory 289616 kb
Host smart-34f2d74d-509a-4422-b281-f4feee3b7b09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252068098 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.252068098
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.970925019
Short name T57
Test name
Test status
Simulation time 10060433909 ps
CPU time 78.14 seconds
Started May 02 01:43:18 PM PDT 24
Finished May 02 01:44:38 PM PDT 24
Peak memory 463180 kb
Host smart-2271b69d-6207-4a8b-acf3-1b5a608e7e4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970925019 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.970925019
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1677288838
Short name T581
Test name
Test status
Simulation time 3126593839 ps
CPU time 2.49 seconds
Started May 02 01:43:18 PM PDT 24
Finished May 02 01:43:23 PM PDT 24
Peak memory 204248 kb
Host smart-06f3e4e8-0e76-45e6-a6b5-1aeffc68a275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677288838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1677288838
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.3082106052
Short name T332
Test name
Test status
Simulation time 2260781990 ps
CPU time 5.85 seconds
Started May 02 01:43:22 PM PDT 24
Finished May 02 01:43:29 PM PDT 24
Peak memory 212452 kb
Host smart-145815c4-3955-411d-965c-05a942d96182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082106052 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.3082106052
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.302553523
Short name T1031
Test name
Test status
Simulation time 11428118060 ps
CPU time 23.36 seconds
Started May 02 01:43:17 PM PDT 24
Finished May 02 01:43:43 PM PDT 24
Peak memory 610664 kb
Host smart-767115f3-8cf6-4e48-be4b-d76eb43aee69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302553523 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.302553523
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3958359451
Short name T500
Test name
Test status
Simulation time 2031996863 ps
CPU time 12.46 seconds
Started May 02 01:43:18 PM PDT 24
Finished May 02 01:43:33 PM PDT 24
Peak memory 204136 kb
Host smart-8c85121b-273e-4df4-bde6-bcf53be9d989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958359451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3958359451
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.245504620
Short name T710
Test name
Test status
Simulation time 3274113712 ps
CPU time 30.03 seconds
Started May 02 01:43:17 PM PDT 24
Finished May 02 01:43:49 PM PDT 24
Peak memory 222400 kb
Host smart-a73b3ba8-5f80-461f-be76-5ac3656f503f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245504620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.245504620
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2816804688
Short name T841
Test name
Test status
Simulation time 16842146300 ps
CPU time 16.34 seconds
Started May 02 01:43:18 PM PDT 24
Finished May 02 01:43:36 PM PDT 24
Peak memory 204104 kb
Host smart-c70e87c6-2571-4cba-80ab-8260fa0f518c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816804688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2816804688
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.4214269531
Short name T354
Test name
Test status
Simulation time 45361791915 ps
CPU time 134.37 seconds
Started May 02 01:43:19 PM PDT 24
Finished May 02 01:45:35 PM PDT 24
Peak memory 534568 kb
Host smart-5ee94e5d-19e4-4543-a419-532c26671c1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214269531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.4214269531
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2931386901
Short name T274
Test name
Test status
Simulation time 1244137850 ps
CPU time 6.53 seconds
Started May 02 01:43:21 PM PDT 24
Finished May 02 01:43:29 PM PDT 24
Peak memory 212352 kb
Host smart-c603f373-7799-4319-bc11-1afd7270862d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931386901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2931386901
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3259777562
Short name T113
Test name
Test status
Simulation time 53655965 ps
CPU time 0.59 seconds
Started May 02 01:43:24 PM PDT 24
Finished May 02 01:43:26 PM PDT 24
Peak memory 203876 kb
Host smart-a27dbba3-2a96-47cc-80f5-05792692e08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259777562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3259777562
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1573468270
Short name T808
Test name
Test status
Simulation time 186507596 ps
CPU time 1.49 seconds
Started May 02 01:43:20 PM PDT 24
Finished May 02 01:43:23 PM PDT 24
Peak memory 212448 kb
Host smart-3035bee3-6961-4eea-a569-1f2f2537aecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573468270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1573468270
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.738856076
Short name T285
Test name
Test status
Simulation time 241420395 ps
CPU time 5.24 seconds
Started May 02 01:43:21 PM PDT 24
Finished May 02 01:43:28 PM PDT 24
Peak memory 251708 kb
Host smart-5640ef3a-be4a-4173-8d01-8c9865fa7a28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738856076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.738856076
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3273299326
Short name T862
Test name
Test status
Simulation time 2274546837 ps
CPU time 80.2 seconds
Started May 02 01:43:16 PM PDT 24
Finished May 02 01:44:38 PM PDT 24
Peak memory 679816 kb
Host smart-744b86ee-563f-497c-9127-876f89b16725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273299326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3273299326
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2709157268
Short name T933
Test name
Test status
Simulation time 6973612587 ps
CPU time 67 seconds
Started May 02 01:43:20 PM PDT 24
Finished May 02 01:44:28 PM PDT 24
Peak memory 674520 kb
Host smart-18c59aff-fb29-4b7c-91da-2b4a00b2f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709157268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2709157268
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3926379298
Short name T573
Test name
Test status
Simulation time 146974619 ps
CPU time 1.05 seconds
Started May 02 01:43:19 PM PDT 24
Finished May 02 01:43:22 PM PDT 24
Peak memory 204112 kb
Host smart-b6e4f4d8-3bcf-495c-b1d9-50a12d188d74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926379298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3926379298
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3452422719
Short name T1131
Test name
Test status
Simulation time 818486031 ps
CPU time 4.17 seconds
Started May 02 01:43:21 PM PDT 24
Finished May 02 01:43:27 PM PDT 24
Peak memory 229780 kb
Host smart-f8d810fb-2b6b-44d1-93a4-c0e5bacce6f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452422719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3452422719
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.4158979610
Short name T689
Test name
Test status
Simulation time 3932639987 ps
CPU time 279.25 seconds
Started May 02 01:43:19 PM PDT 24
Finished May 02 01:48:00 PM PDT 24
Peak memory 1137692 kb
Host smart-cf17df7a-1b67-4112-8005-44e33d0f54e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158979610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.4158979610
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2878537744
Short name T830
Test name
Test status
Simulation time 239097442 ps
CPU time 8.85 seconds
Started May 02 01:43:28 PM PDT 24
Finished May 02 01:43:37 PM PDT 24
Peak memory 204232 kb
Host smart-e6f638b2-a2df-4346-9ae4-2505025b93d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878537744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2878537744
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.2669415110
Short name T541
Test name
Test status
Simulation time 9361679189 ps
CPU time 19.5 seconds
Started May 02 01:43:26 PM PDT 24
Finished May 02 01:43:46 PM PDT 24
Peak memory 319712 kb
Host smart-ef122c81-4327-4db7-852a-bee94abb24bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669415110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.2669415110
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.3191336005
Short name T1078
Test name
Test status
Simulation time 27504881 ps
CPU time 0.65 seconds
Started May 02 01:43:16 PM PDT 24
Finished May 02 01:43:19 PM PDT 24
Peak memory 203728 kb
Host smart-32bd55b1-e3cd-4953-ad5d-c53da5530491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191336005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3191336005
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2256583806
Short name T810
Test name
Test status
Simulation time 1101318565 ps
CPU time 57 seconds
Started May 02 01:43:22 PM PDT 24
Finished May 02 01:44:20 PM PDT 24
Peak memory 366260 kb
Host smart-c5d0ad26-88d1-4f2a-a30d-87303e79f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256583806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2256583806
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1039482277
Short name T983
Test name
Test status
Simulation time 26247156856 ps
CPU time 593.08 seconds
Started May 02 01:43:25 PM PDT 24
Finished May 02 01:53:19 PM PDT 24
Peak memory 1443444 kb
Host smart-2237c17d-5b26-49d0-bd95-77b9d433db87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039482277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1039482277
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1395058344
Short name T1074
Test name
Test status
Simulation time 596557713 ps
CPU time 9.98 seconds
Started May 02 01:43:17 PM PDT 24
Finished May 02 01:43:29 PM PDT 24
Peak memory 220592 kb
Host smart-60bbfd7d-380b-450f-9d2a-36292193dee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395058344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1395058344
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.4217720223
Short name T1266
Test name
Test status
Simulation time 983004248 ps
CPU time 2.66 seconds
Started May 02 01:43:26 PM PDT 24
Finished May 02 01:43:30 PM PDT 24
Peak memory 204140 kb
Host smart-ea65e0fa-d02f-4327-9d9b-b91a72528e7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217720223 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.4217720223
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.19499928
Short name T478
Test name
Test status
Simulation time 10543925301 ps
CPU time 6.33 seconds
Started May 02 01:43:25 PM PDT 24
Finished May 02 01:43:32 PM PDT 24
Peak memory 215968 kb
Host smart-c778d507-a7f9-44e1-bee8-83800a3010a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19499928 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_acq.19499928
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.59349890
Short name T229
Test name
Test status
Simulation time 10141297948 ps
CPU time 24.47 seconds
Started May 02 01:43:27 PM PDT 24
Finished May 02 01:43:52 PM PDT 24
Peak memory 332128 kb
Host smart-7a099142-9dd4-43a1-9550-60537f93459b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59349890 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_fifo_reset_tx.59349890
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1263143239
Short name T981
Test name
Test status
Simulation time 2311472165 ps
CPU time 4.14 seconds
Started May 02 01:43:25 PM PDT 24
Finished May 02 01:43:30 PM PDT 24
Peak memory 204176 kb
Host smart-27d0ab9d-8777-4822-aa05-efc049a00248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263143239 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1263143239
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.4129172038
Short name T685
Test name
Test status
Simulation time 14074468283 ps
CPU time 79.3 seconds
Started May 02 01:43:29 PM PDT 24
Finished May 02 01:44:49 PM PDT 24
Peak memory 1737580 kb
Host smart-9e0f3e3e-580a-449f-b578-8534535a2498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129172038 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.4129172038
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.407475387
Short name T953
Test name
Test status
Simulation time 3396719059 ps
CPU time 10.47 seconds
Started May 02 01:43:24 PM PDT 24
Finished May 02 01:43:35 PM PDT 24
Peak memory 204268 kb
Host smart-0947fe74-5e43-46f1-a55b-e97f97759cae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407475387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.407475387
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.699873162
Short name T925
Test name
Test status
Simulation time 1292325242 ps
CPU time 50.93 seconds
Started May 02 01:43:29 PM PDT 24
Finished May 02 01:44:21 PM PDT 24
Peak memory 204900 kb
Host smart-4c03f512-a8ac-40e6-a373-330c833c3357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699873162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.699873162
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.69112137
Short name T993
Test name
Test status
Simulation time 57770365322 ps
CPU time 553.2 seconds
Started May 02 01:43:27 PM PDT 24
Finished May 02 01:52:41 PM PDT 24
Peak memory 4708856 kb
Host smart-898c8548-e869-4736-9ecd-e396a938c9ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69112137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stress_wr.69112137
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2306533946
Short name T906
Test name
Test status
Simulation time 33462554701 ps
CPU time 561.58 seconds
Started May 02 01:43:26 PM PDT 24
Finished May 02 01:52:48 PM PDT 24
Peak memory 1732104 kb
Host smart-945d5fc0-a346-4303-a8ce-1c3cd514a3b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306533946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2306533946
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1279673197
Short name T1345
Test name
Test status
Simulation time 1251465520 ps
CPU time 6.95 seconds
Started May 02 01:43:26 PM PDT 24
Finished May 02 01:43:33 PM PDT 24
Peak memory 220480 kb
Host smart-72c76d33-35b4-4e76-af03-0475aed20052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279673197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1279673197
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.120157343
Short name T549
Test name
Test status
Simulation time 28749028 ps
CPU time 0.59 seconds
Started May 02 01:43:35 PM PDT 24
Finished May 02 01:43:37 PM PDT 24
Peak memory 203880 kb
Host smart-2c37cfe2-fa9c-4540-bcfc-e24bf6bf0272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120157343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.120157343
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2640270059
Short name T819
Test name
Test status
Simulation time 62509912 ps
CPU time 1.3 seconds
Started May 02 01:43:32 PM PDT 24
Finished May 02 01:43:34 PM PDT 24
Peak memory 220600 kb
Host smart-eefb37e8-f866-4b07-807a-d5b043506b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640270059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2640270059
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2666102228
Short name T1151
Test name
Test status
Simulation time 481892603 ps
CPU time 8.55 seconds
Started May 02 01:43:35 PM PDT 24
Finished May 02 01:43:45 PM PDT 24
Peak memory 311028 kb
Host smart-b8fa001c-8505-423a-b61b-53c9220c6132
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666102228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2666102228
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3678337677
Short name T1222
Test name
Test status
Simulation time 7146037342 ps
CPU time 78.06 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:44:53 PM PDT 24
Peak memory 430360 kb
Host smart-a2f37fd5-dda9-49d0-9016-4b374de54674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678337677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3678337677
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.4021366547
Short name T742
Test name
Test status
Simulation time 3204011037 ps
CPU time 47.06 seconds
Started May 02 01:43:33 PM PDT 24
Finished May 02 01:44:21 PM PDT 24
Peak memory 587856 kb
Host smart-2496c413-e577-462d-b4aa-117bbab3dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021366547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4021366547
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.805059098
Short name T1240
Test name
Test status
Simulation time 508947846 ps
CPU time 1.08 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:43:36 PM PDT 24
Peak memory 204104 kb
Host smart-69f93260-5717-4adb-a215-9424f60610e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805059098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.805059098
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1342818600
Short name T1162
Test name
Test status
Simulation time 958096309 ps
CPU time 5.16 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:43:41 PM PDT 24
Peak memory 234992 kb
Host smart-a8d491f7-46fd-4291-86b1-e64895ea10ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342818600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1342818600
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1797911556
Short name T367
Test name
Test status
Simulation time 7726410871 ps
CPU time 120.95 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:45:37 PM PDT 24
Peak memory 1147756 kb
Host smart-06b403a6-5669-4688-b056-10fbf7e3ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797911556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1797911556
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.578176316
Short name T741
Test name
Test status
Simulation time 346257580 ps
CPU time 4.24 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:43:39 PM PDT 24
Peak memory 204188 kb
Host smart-744b41c9-8621-4371-aa18-f984b252396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578176316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.578176316
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2791308737
Short name T213
Test name
Test status
Simulation time 2624112158 ps
CPU time 62.6 seconds
Started May 02 01:43:33 PM PDT 24
Finished May 02 01:44:37 PM PDT 24
Peak memory 315572 kb
Host smart-16583186-b51c-4d36-b56c-c2c86f0518bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791308737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2791308737
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.2877624341
Short name T1326
Test name
Test status
Simulation time 32975817 ps
CPU time 0.66 seconds
Started May 02 01:43:35 PM PDT 24
Finished May 02 01:43:37 PM PDT 24
Peak memory 203792 kb
Host smart-ed69d73e-1f4e-4353-8f26-72364d2b5415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877624341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2877624341
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3691887129
Short name T1274
Test name
Test status
Simulation time 19804595357 ps
CPU time 126.16 seconds
Started May 02 01:43:36 PM PDT 24
Finished May 02 01:45:43 PM PDT 24
Peak memory 841896 kb
Host smart-8d0d6f8c-20de-4b94-9ff7-15270a8a7b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691887129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3691887129
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.364100988
Short name T1153
Test name
Test status
Simulation time 1371912246 ps
CPU time 28.41 seconds
Started May 02 01:43:27 PM PDT 24
Finished May 02 01:43:56 PM PDT 24
Peak memory 341440 kb
Host smart-7c226ec8-d706-4f44-85e0-99208efd079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364100988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.364100988
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.3579592297
Short name T1329
Test name
Test status
Simulation time 11700565777 ps
CPU time 408.7 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:50:25 PM PDT 24
Peak memory 1702536 kb
Host smart-bc430c21-e4cf-48e8-aff5-d1d5e09afa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579592297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.3579592297
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.4289979433
Short name T709
Test name
Test status
Simulation time 1458907568 ps
CPU time 33.1 seconds
Started May 02 01:43:35 PM PDT 24
Finished May 02 01:44:10 PM PDT 24
Peak memory 212340 kb
Host smart-9ec74503-7b51-4e33-8957-7b84dd40b3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289979433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.4289979433
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1760680847
Short name T619
Test name
Test status
Simulation time 3169485805 ps
CPU time 3.53 seconds
Started May 02 01:43:35 PM PDT 24
Finished May 02 01:43:40 PM PDT 24
Peak memory 204276 kb
Host smart-ce7e5522-ae26-41cc-8f02-4b0711752556
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760680847 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1760680847
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.18958555
Short name T49
Test name
Test status
Simulation time 10088779150 ps
CPU time 63 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:44:38 PM PDT 24
Peak memory 457032 kb
Host smart-2b4fbe67-0a1f-40d6-8c5e-17f3477fef48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18958555 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_acq.18958555
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2714816290
Short name T923
Test name
Test status
Simulation time 10172048368 ps
CPU time 8.57 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:43:44 PM PDT 24
Peak memory 239200 kb
Host smart-3015e224-d0a3-4c8a-a596-f34be3ca9f41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714816290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2714816290
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.143379737
Short name T962
Test name
Test status
Simulation time 354010389 ps
CPU time 2.26 seconds
Started May 02 01:43:33 PM PDT 24
Finished May 02 01:43:36 PM PDT 24
Peak memory 204220 kb
Host smart-fa941b30-8022-4177-b492-d53d54f4ba39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143379737 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_hrst.143379737
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1185921011
Short name T282
Test name
Test status
Simulation time 3055403740 ps
CPU time 4.42 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:43:40 PM PDT 24
Peak memory 208924 kb
Host smart-8e59788e-9d53-46a5-9019-709bdb70fbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185921011 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1185921011
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3931087392
Short name T601
Test name
Test status
Simulation time 4583627566 ps
CPU time 9.55 seconds
Started May 02 01:43:35 PM PDT 24
Finished May 02 01:43:46 PM PDT 24
Peak memory 204180 kb
Host smart-74e6b3e6-17b3-46a6-b05c-9ba58995e564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931087392 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3931087392
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.4104979558
Short name T444
Test name
Test status
Simulation time 1446137466 ps
CPU time 7.61 seconds
Started May 02 01:43:33 PM PDT 24
Finished May 02 01:43:42 PM PDT 24
Peak memory 204112 kb
Host smart-b0480880-5666-4dfd-a104-2bc51a03d468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104979558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.4104979558
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.2080249225
Short name T1279
Test name
Test status
Simulation time 13175997275 ps
CPU time 28.27 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:44:03 PM PDT 24
Peak memory 218768 kb
Host smart-d67dfbb9-935b-4f63-904c-32ac008df59c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080249225 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.2080249225
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2406121833
Short name T7
Test name
Test status
Simulation time 330487380 ps
CPU time 4.93 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:43:40 PM PDT 24
Peak memory 204052 kb
Host smart-5a5ebd6a-b2af-4c54-bb70-c605d4c94595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406121833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2406121833
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.2947057928
Short name T1075
Test name
Test status
Simulation time 7419019182 ps
CPU time 245.44 seconds
Started May 02 01:43:35 PM PDT 24
Finished May 02 01:47:41 PM PDT 24
Peak memory 1968988 kb
Host smart-ead9ba2a-4231-4147-97ee-00821b43602e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947057928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.2947057928
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3465996378
Short name T654
Test name
Test status
Simulation time 1556487123 ps
CPU time 7.52 seconds
Started May 02 01:43:34 PM PDT 24
Finished May 02 01:43:43 PM PDT 24
Peak memory 220444 kb
Host smart-b8d5b130-6b53-484d-8b52-81cfde8dfa62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465996378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3465996378
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2259767999
Short name T112
Test name
Test status
Simulation time 31904446 ps
CPU time 0.6 seconds
Started May 02 01:43:49 PM PDT 24
Finished May 02 01:43:50 PM PDT 24
Peak memory 203804 kb
Host smart-33c76564-7def-4057-8506-de127c4f8ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259767999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2259767999
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.166993738
Short name T1278
Test name
Test status
Simulation time 470178579 ps
CPU time 1.66 seconds
Started May 02 01:43:47 PM PDT 24
Finished May 02 01:43:49 PM PDT 24
Peak memory 212516 kb
Host smart-d7b8a9cb-01b6-45b0-8c2f-d0fb5d015fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166993738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.166993738
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3941904800
Short name T1107
Test name
Test status
Simulation time 2350577252 ps
CPU time 8.99 seconds
Started May 02 01:43:43 PM PDT 24
Finished May 02 01:43:53 PM PDT 24
Peak memory 290024 kb
Host smart-ad76959f-d647-4630-a294-3a2fbfa5e32e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941904800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3941904800
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1326677306
Short name T997
Test name
Test status
Simulation time 5513540776 ps
CPU time 90.81 seconds
Started May 02 01:43:41 PM PDT 24
Finished May 02 01:45:13 PM PDT 24
Peak memory 548276 kb
Host smart-5fc1dd5f-9e74-4ecf-a323-a14557e7dba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326677306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1326677306
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1068030627
Short name T302
Test name
Test status
Simulation time 77509787 ps
CPU time 0.85 seconds
Started May 02 01:43:41 PM PDT 24
Finished May 02 01:43:43 PM PDT 24
Peak memory 203884 kb
Host smart-8fcf53ca-7878-4e9e-b5e5-9f61584d2c28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068030627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1068030627
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.82115787
Short name T1052
Test name
Test status
Simulation time 127403493 ps
CPU time 7.55 seconds
Started May 02 01:43:43 PM PDT 24
Finished May 02 01:43:51 PM PDT 24
Peak memory 224556 kb
Host smart-7b3ab813-d97c-4b21-97df-73b529894dce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82115787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.82115787
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1069900373
Short name T672
Test name
Test status
Simulation time 8475064204 ps
CPU time 131.92 seconds
Started May 02 01:43:43 PM PDT 24
Finished May 02 01:45:56 PM PDT 24
Peak memory 1217724 kb
Host smart-a0ba7161-8333-4722-ae50-c3ce52bd5668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069900373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1069900373
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.542818207
Short name T843
Test name
Test status
Simulation time 519717867 ps
CPU time 21.73 seconds
Started May 02 01:43:51 PM PDT 24
Finished May 02 01:44:14 PM PDT 24
Peak memory 204172 kb
Host smart-59b86957-e558-4d14-95bc-be34b7ac2070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542818207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.542818207
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2140122276
Short name T215
Test name
Test status
Simulation time 1976425445 ps
CPU time 49.38 seconds
Started May 02 01:43:56 PM PDT 24
Finished May 02 01:44:46 PM PDT 24
Peak memory 368376 kb
Host smart-2ad1ef74-6f5c-4387-b2f8-f6157d885f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140122276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2140122276
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3199244831
Short name T954
Test name
Test status
Simulation time 25142453 ps
CPU time 0.68 seconds
Started May 02 01:43:41 PM PDT 24
Finished May 02 01:43:44 PM PDT 24
Peak memory 203804 kb
Host smart-13b71b43-bf57-4dfd-8552-856f453083f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199244831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3199244831
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1773487632
Short name T602
Test name
Test status
Simulation time 305707417 ps
CPU time 7.61 seconds
Started May 02 01:43:43 PM PDT 24
Finished May 02 01:43:52 PM PDT 24
Peak memory 231740 kb
Host smart-b8c3cc03-102f-44c5-b457-b8cfe9c2d19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773487632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1773487632
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.353725010
Short name T660
Test name
Test status
Simulation time 11401661258 ps
CPU time 71.17 seconds
Started May 02 01:43:41 PM PDT 24
Finished May 02 01:44:53 PM PDT 24
Peak memory 332836 kb
Host smart-e474ac21-d778-4e34-b28d-2fcc8f3990dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353725010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.353725010
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.403566625
Short name T1336
Test name
Test status
Simulation time 1944604559 ps
CPU time 21.27 seconds
Started May 02 01:43:47 PM PDT 24
Finished May 02 01:44:09 PM PDT 24
Peak memory 212312 kb
Host smart-a7e654be-d6ed-4f2f-8ed8-2f886689bfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403566625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.403566625
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.4261039668
Short name T825
Test name
Test status
Simulation time 644802968 ps
CPU time 3.09 seconds
Started May 02 01:43:43 PM PDT 24
Finished May 02 01:43:47 PM PDT 24
Peak memory 204168 kb
Host smart-c3eebcac-7e8b-48d3-a22a-063a74ec0465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261039668 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.4261039668
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.254349262
Short name T1008
Test name
Test status
Simulation time 10104520774 ps
CPU time 57.28 seconds
Started May 02 01:43:42 PM PDT 24
Finished May 02 01:44:40 PM PDT 24
Peak memory 382024 kb
Host smart-c36a40ce-6bcd-41fe-9822-52f516a56d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254349262 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.254349262
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1220746454
Short name T48
Test name
Test status
Simulation time 10057696450 ps
CPU time 62.48 seconds
Started May 02 01:43:40 PM PDT 24
Finished May 02 01:44:43 PM PDT 24
Peak memory 562096 kb
Host smart-c0a525dc-76cc-43ae-a253-4ce7e8439fcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220746454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1220746454
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.811242575
Short name T579
Test name
Test status
Simulation time 2342365596 ps
CPU time 2.89 seconds
Started May 02 01:43:46 PM PDT 24
Finished May 02 01:43:50 PM PDT 24
Peak memory 204280 kb
Host smart-a128f25b-2d83-4d11-8176-f3dee3ee694c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811242575 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_hrst.811242575
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3450678400
Short name T513
Test name
Test status
Simulation time 2314166509 ps
CPU time 5.09 seconds
Started May 02 01:43:40 PM PDT 24
Finished May 02 01:43:46 PM PDT 24
Peak memory 212436 kb
Host smart-d98d59c5-e107-4cdb-9258-0cab33060b13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450678400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3450678400
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.503148831
Short name T563
Test name
Test status
Simulation time 19758155571 ps
CPU time 316.75 seconds
Started May 02 01:43:43 PM PDT 24
Finished May 02 01:49:01 PM PDT 24
Peak memory 3231452 kb
Host smart-f2484271-4ea1-47b2-9b8c-a900159c1fb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503148831 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.503148831
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1251973255
Short name T881
Test name
Test status
Simulation time 1501402362 ps
CPU time 28.95 seconds
Started May 02 01:43:41 PM PDT 24
Finished May 02 01:44:11 PM PDT 24
Peak memory 204164 kb
Host smart-35b7f66d-fc1e-46c5-9e0f-a27a559a359a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251973255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1251973255
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1789270172
Short name T1342
Test name
Test status
Simulation time 33057359076 ps
CPU time 310 seconds
Started May 02 01:43:41 PM PDT 24
Finished May 02 01:48:53 PM PDT 24
Peak memory 3322316 kb
Host smart-3500fb3a-96ad-4000-92d0-aecc8fd016b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789270172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1789270172
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.220611603
Short name T299
Test name
Test status
Simulation time 13396153598 ps
CPU time 241.37 seconds
Started May 02 01:43:40 PM PDT 24
Finished May 02 01:47:43 PM PDT 24
Peak memory 1030332 kb
Host smart-36f41bac-a268-45fe-9628-a41a5e0db11f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220611603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.220611603
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.665173564
Short name T1081
Test name
Test status
Simulation time 1152814060 ps
CPU time 6.01 seconds
Started May 02 01:43:42 PM PDT 24
Finished May 02 01:43:49 PM PDT 24
Peak memory 220380 kb
Host smart-8d45e898-19ff-472b-96d8-50367a9657fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665173564 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.665173564
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3927689180
Short name T1114
Test name
Test status
Simulation time 159490971 ps
CPU time 0.59 seconds
Started May 02 01:43:56 PM PDT 24
Finished May 02 01:43:57 PM PDT 24
Peak memory 203740 kb
Host smart-568bf433-e14d-44b7-9309-9f5fd9cd1f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927689180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3927689180
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.4245871592
Short name T1176
Test name
Test status
Simulation time 84534470 ps
CPU time 1.77 seconds
Started May 02 01:43:51 PM PDT 24
Finished May 02 01:43:54 PM PDT 24
Peak memory 204288 kb
Host smart-dadb4cb0-aa0e-4fd1-a37d-d388ba893902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245871592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.4245871592
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.642356989
Short name T1290
Test name
Test status
Simulation time 1264073499 ps
CPU time 16.68 seconds
Started May 02 01:43:52 PM PDT 24
Finished May 02 01:44:09 PM PDT 24
Peak memory 270584 kb
Host smart-02cf9963-c5e0-45cc-81b6-9d03e5e92e45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642356989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.642356989
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.832263509
Short name T1183
Test name
Test status
Simulation time 4760827510 ps
CPU time 73.13 seconds
Started May 02 01:43:51 PM PDT 24
Finished May 02 01:45:05 PM PDT 24
Peak memory 713164 kb
Host smart-2f7331db-fd8c-410e-ba45-d6220f2b9b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832263509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.832263509
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2451187318
Short name T1132
Test name
Test status
Simulation time 2152202848 ps
CPU time 82.84 seconds
Started May 02 01:43:54 PM PDT 24
Finished May 02 01:45:17 PM PDT 24
Peak memory 737144 kb
Host smart-f530465c-f340-4ac9-803a-ee5ea9369a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451187318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2451187318
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2613064574
Short name T676
Test name
Test status
Simulation time 565077207 ps
CPU time 1.05 seconds
Started May 02 01:43:49 PM PDT 24
Finished May 02 01:43:51 PM PDT 24
Peak memory 204136 kb
Host smart-84edb663-c554-4492-b70d-8d7b82a1b002
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613064574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2613064574
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3395178085
Short name T1054
Test name
Test status
Simulation time 225188429 ps
CPU time 6.94 seconds
Started May 02 01:43:50 PM PDT 24
Finished May 02 01:43:58 PM PDT 24
Peak memory 222832 kb
Host smart-62bde39d-e891-42c3-baa0-4113b2e63bb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395178085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3395178085
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3729074817
Short name T43
Test name
Test status
Simulation time 8572683023 ps
CPU time 325.49 seconds
Started May 02 01:43:50 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 1248188 kb
Host smart-546c4c94-eb33-4b6b-949f-1df347b4b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729074817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3729074817
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3270986977
Short name T737
Test name
Test status
Simulation time 259026170 ps
CPU time 2.69 seconds
Started May 02 01:44:00 PM PDT 24
Finished May 02 01:44:03 PM PDT 24
Peak memory 204216 kb
Host smart-6ccee945-db65-4ac7-9a68-d6f7c286bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270986977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3270986977
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.722021194
Short name T1214
Test name
Test status
Simulation time 8733291889 ps
CPU time 33.72 seconds
Started May 02 01:43:57 PM PDT 24
Finished May 02 01:44:31 PM PDT 24
Peak memory 379448 kb
Host smart-556d1ced-5e29-4dca-bd77-ba283fc02ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722021194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.722021194
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.401480653
Short name T647
Test name
Test status
Simulation time 90865521 ps
CPU time 0.71 seconds
Started May 02 01:43:52 PM PDT 24
Finished May 02 01:43:54 PM PDT 24
Peak memory 203804 kb
Host smart-a37245fb-4c63-4b88-aac5-41fd23c59790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401480653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.401480653
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1384880483
Short name T716
Test name
Test status
Simulation time 3270609711 ps
CPU time 8.54 seconds
Started May 02 01:43:53 PM PDT 24
Finished May 02 01:44:03 PM PDT 24
Peak memory 212460 kb
Host smart-c6b23755-c83c-4195-bee7-db8aea512bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384880483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1384880483
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2560410319
Short name T1137
Test name
Test status
Simulation time 5399696505 ps
CPU time 60.22 seconds
Started May 02 01:43:50 PM PDT 24
Finished May 02 01:44:52 PM PDT 24
Peak memory 315292 kb
Host smart-af981c23-2163-465c-b2bf-79aed8d9e474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560410319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2560410319
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.278291972
Short name T786
Test name
Test status
Simulation time 36259779521 ps
CPU time 694.99 seconds
Started May 02 01:43:52 PM PDT 24
Finished May 02 01:55:28 PM PDT 24
Peak memory 1496688 kb
Host smart-8f3f310e-a751-49bf-9033-24c0feb105d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278291972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.278291972
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1449300341
Short name T527
Test name
Test status
Simulation time 1162005041 ps
CPU time 26.29 seconds
Started May 02 01:43:50 PM PDT 24
Finished May 02 01:44:17 PM PDT 24
Peak memory 212256 kb
Host smart-de40a183-34c4-49ac-b229-b69e99c90ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449300341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1449300341
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3292236178
Short name T337
Test name
Test status
Simulation time 5091906809 ps
CPU time 5.16 seconds
Started May 02 01:43:58 PM PDT 24
Finished May 02 01:44:04 PM PDT 24
Peak memory 207504 kb
Host smart-827bad88-c0e7-4b38-a28a-d8150ff3fdf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292236178 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3292236178
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3834539298
Short name T920
Test name
Test status
Simulation time 10112363329 ps
CPU time 7.29 seconds
Started May 02 01:43:55 PM PDT 24
Finished May 02 01:44:03 PM PDT 24
Peak memory 230408 kb
Host smart-b1fc96e8-b11a-4fc8-bfb7-16dc7db0d9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834539298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3834539298
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1586483551
Short name T699
Test name
Test status
Simulation time 10124134549 ps
CPU time 28.04 seconds
Started May 02 01:43:57 PM PDT 24
Finished May 02 01:44:25 PM PDT 24
Peak memory 344444 kb
Host smart-b49a3c88-191c-4a22-b5cf-ee26fc0182c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586483551 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1586483551
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.550086953
Short name T583
Test name
Test status
Simulation time 402121661 ps
CPU time 2.49 seconds
Started May 02 01:44:06 PM PDT 24
Finished May 02 01:44:10 PM PDT 24
Peak memory 204220 kb
Host smart-0396c21a-daa8-4ee9-8676-8d50b9e14c2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550086953 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.550086953
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1982284046
Short name T697
Test name
Test status
Simulation time 1553983380 ps
CPU time 4.29 seconds
Started May 02 01:43:58 PM PDT 24
Finished May 02 01:44:03 PM PDT 24
Peak memory 204160 kb
Host smart-973e9245-6b3a-46be-84cc-6cb96cf48ba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982284046 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1982284046
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1531144929
Short name T1079
Test name
Test status
Simulation time 19906242438 ps
CPU time 152.62 seconds
Started May 02 01:44:01 PM PDT 24
Finished May 02 01:46:34 PM PDT 24
Peak memory 2442644 kb
Host smart-0323faaf-d734-4c65-aef7-5cb028b3c4ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531144929 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1531144929
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2954192342
Short name T588
Test name
Test status
Simulation time 1083774156 ps
CPU time 15.06 seconds
Started May 02 01:43:51 PM PDT 24
Finished May 02 01:44:07 PM PDT 24
Peak memory 204116 kb
Host smart-b78ae6a7-2587-447a-9c6c-3b4de1ce54d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954192342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2954192342
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.2633922086
Short name T918
Test name
Test status
Simulation time 643833743 ps
CPU time 12.33 seconds
Started May 02 01:43:50 PM PDT 24
Finished May 02 01:44:03 PM PDT 24
Peak memory 208076 kb
Host smart-dfc20862-0ba4-424a-87ce-afa12060b214
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633922086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.2633922086
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3081097214
Short name T1255
Test name
Test status
Simulation time 11612601164 ps
CPU time 11.94 seconds
Started May 02 01:43:49 PM PDT 24
Finished May 02 01:44:02 PM PDT 24
Peak memory 204248 kb
Host smart-afab45ef-a7f8-47a8-8eb7-6d82abf4d3d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081097214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3081097214
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2333502275
Short name T221
Test name
Test status
Simulation time 18663985690 ps
CPU time 130.32 seconds
Started May 02 01:43:57 PM PDT 24
Finished May 02 01:46:08 PM PDT 24
Peak memory 1296420 kb
Host smart-1df6ee21-2224-4070-b792-6177d5b304cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333502275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2333502275
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1413920614
Short name T12
Test name
Test status
Simulation time 3238051840 ps
CPU time 7.19 seconds
Started May 02 01:43:54 PM PDT 24
Finished May 02 01:44:02 PM PDT 24
Peak memory 220352 kb
Host smart-dbbb3834-6fdf-45d8-9f9e-d56ed6a66f56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413920614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1413920614
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1574326691
Short name T370
Test name
Test status
Simulation time 32610551 ps
CPU time 0.64 seconds
Started May 02 01:44:13 PM PDT 24
Finished May 02 01:44:14 PM PDT 24
Peak memory 203892 kb
Host smart-186efa58-b207-4076-905a-94729dfa6fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574326691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1574326691
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.889049591
Short name T377
Test name
Test status
Simulation time 404883335 ps
CPU time 1.24 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 01:44:05 PM PDT 24
Peak memory 212424 kb
Host smart-aa3782dd-aaaf-4079-b67d-91e385211c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889049591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.889049591
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1006358332
Short name T730
Test name
Test status
Simulation time 689459968 ps
CPU time 16.43 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 01:44:20 PM PDT 24
Peak memory 249004 kb
Host smart-38e4c29f-4c1b-4ee6-b3ff-9f46bc75b61c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006358332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1006358332
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3986186013
Short name T471
Test name
Test status
Simulation time 1978108684 ps
CPU time 137.08 seconds
Started May 02 01:44:06 PM PDT 24
Finished May 02 01:46:24 PM PDT 24
Peak memory 673704 kb
Host smart-8768a43a-5b9e-4121-8d8b-e17f8362c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986186013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3986186013
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.143085837
Short name T916
Test name
Test status
Simulation time 5233533096 ps
CPU time 33.79 seconds
Started May 02 01:44:01 PM PDT 24
Finished May 02 01:44:35 PM PDT 24
Peak memory 460224 kb
Host smart-8e602bc1-443d-4ee4-957a-ac90a4d32291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143085837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.143085837
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.910946605
Short name T60
Test name
Test status
Simulation time 163645422 ps
CPU time 0.9 seconds
Started May 02 01:44:07 PM PDT 24
Finished May 02 01:44:08 PM PDT 24
Peak memory 203956 kb
Host smart-0a83cd39-f55e-45ac-b6e0-4e7dee7869ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910946605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.910946605
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1110067451
Short name T661
Test name
Test status
Simulation time 192939217 ps
CPU time 2.83 seconds
Started May 02 01:44:04 PM PDT 24
Finished May 02 01:44:08 PM PDT 24
Peak memory 220904 kb
Host smart-f4c9bc56-e1fd-43d4-9b3a-8695ed23dfb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110067451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1110067451
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3319449485
Short name T735
Test name
Test status
Simulation time 14163769186 ps
CPU time 80.35 seconds
Started May 02 01:43:58 PM PDT 24
Finished May 02 01:45:19 PM PDT 24
Peak memory 1051616 kb
Host smart-d3e75fd7-ac27-47b3-8a4f-83f896e0af05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319449485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3319449485
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1269609383
Short name T442
Test name
Test status
Simulation time 1673622818 ps
CPU time 14.94 seconds
Started May 02 01:44:09 PM PDT 24
Finished May 02 01:44:25 PM PDT 24
Peak memory 204168 kb
Host smart-f2cf051a-5a1a-446c-8666-9fed31ee230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269609383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1269609383
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2037112440
Short name T1034
Test name
Test status
Simulation time 1674379770 ps
CPU time 25.2 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 01:44:29 PM PDT 24
Peak memory 328196 kb
Host smart-9577f4d2-1590-4722-9cd2-81ec0e59a2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037112440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2037112440
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1518891175
Short name T1124
Test name
Test status
Simulation time 86157214 ps
CPU time 0.6 seconds
Started May 02 01:43:55 PM PDT 24
Finished May 02 01:43:56 PM PDT 24
Peak memory 203744 kb
Host smart-278d4731-5fdd-4a28-9bbd-4a124c4b9446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518891175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1518891175
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2658656437
Short name T352
Test name
Test status
Simulation time 5558910133 ps
CPU time 16.86 seconds
Started May 02 01:44:08 PM PDT 24
Finished May 02 01:44:25 PM PDT 24
Peak memory 212416 kb
Host smart-6ab914cd-ad35-4f02-a226-7c53b2fe1f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658656437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2658656437
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1656720145
Short name T1257
Test name
Test status
Simulation time 12269999554 ps
CPU time 17.62 seconds
Started May 02 01:43:58 PM PDT 24
Finished May 02 01:44:16 PM PDT 24
Peak memory 284596 kb
Host smart-29708507-dd3e-4a63-b6af-02138b252c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656720145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1656720145
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.4108864204
Short name T125
Test name
Test status
Simulation time 1766260846 ps
CPU time 19.88 seconds
Started May 02 01:44:07 PM PDT 24
Finished May 02 01:44:27 PM PDT 24
Peak memory 212324 kb
Host smart-f54d9a0a-feea-47e4-a772-91059d2c6f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108864204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.4108864204
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3309349530
Short name T264
Test name
Test status
Simulation time 717763614 ps
CPU time 3.62 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 01:44:08 PM PDT 24
Peak memory 204172 kb
Host smart-007960fd-24f7-41c9-9ef6-b52ae4eba2c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309349530 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3309349530
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2285869078
Short name T913
Test name
Test status
Simulation time 10117108426 ps
CPU time 66.83 seconds
Started May 02 01:44:04 PM PDT 24
Finished May 02 01:45:11 PM PDT 24
Peak memory 430440 kb
Host smart-627f797b-36b9-46ec-bd2b-fc5d56d4820c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285869078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2285869078
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4293268088
Short name T1197
Test name
Test status
Simulation time 10272859050 ps
CPU time 16.98 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 01:44:21 PM PDT 24
Peak memory 305140 kb
Host smart-c8c4626f-1177-45c4-9900-84ae0926c884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293268088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4293268088
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2804456174
Short name T864
Test name
Test status
Simulation time 366021957 ps
CPU time 2.2 seconds
Started May 02 01:44:04 PM PDT 24
Finished May 02 01:44:07 PM PDT 24
Peak memory 204216 kb
Host smart-98ef92eb-3c21-4a00-96d0-d6dc0e0214b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804456174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2804456174
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.453335251
Short name T5
Test name
Test status
Simulation time 2036362041 ps
CPU time 5.84 seconds
Started May 02 01:44:01 PM PDT 24
Finished May 02 01:44:08 PM PDT 24
Peak memory 216980 kb
Host smart-d52c3a59-6cba-4105-a512-9e76668d20ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453335251 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.453335251
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.4180008419
Short name T474
Test name
Test status
Simulation time 19480005657 ps
CPU time 315.19 seconds
Started May 02 01:44:04 PM PDT 24
Finished May 02 01:49:20 PM PDT 24
Peak memory 3146388 kb
Host smart-08dd2093-36e0-4e3e-8c07-8a949db313aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180008419 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.4180008419
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.849074218
Short name T852
Test name
Test status
Simulation time 619855939 ps
CPU time 9.71 seconds
Started May 02 01:44:02 PM PDT 24
Finished May 02 01:44:13 PM PDT 24
Peak memory 204076 kb
Host smart-1625cafb-bbf4-4b35-b460-d14b739508ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849074218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.849074218
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.1714205182
Short name T1351
Test name
Test status
Simulation time 97840050059 ps
CPU time 60.06 seconds
Started May 02 01:44:02 PM PDT 24
Finished May 02 01:45:03 PM PDT 24
Peak memory 424012 kb
Host smart-6279370e-a8d1-4153-8fa8-943e2f1f90b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714205182 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.1714205182
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2283575537
Short name T342
Test name
Test status
Simulation time 4776259251 ps
CPU time 50.89 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 01:44:55 PM PDT 24
Peak memory 206044 kb
Host smart-33aabe8a-cbde-42a8-8882-a90321b1cec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283575537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2283575537
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2782055801
Short name T893
Test name
Test status
Simulation time 36899678729 ps
CPU time 424.72 seconds
Started May 02 01:44:05 PM PDT 24
Finished May 02 01:51:11 PM PDT 24
Peak memory 4066188 kb
Host smart-56016f54-99d6-402c-9858-ae7d652fca36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782055801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2782055801
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2810057299
Short name T1287
Test name
Test status
Simulation time 20284178649 ps
CPU time 2988.66 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 02:33:53 PM PDT 24
Peak memory 4032768 kb
Host smart-43c3a75a-29a6-436e-9c10-cfeb7d9bf704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810057299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2810057299
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.307346888
Short name T407
Test name
Test status
Simulation time 1395589587 ps
CPU time 6.74 seconds
Started May 02 01:44:03 PM PDT 24
Finished May 02 01:44:11 PM PDT 24
Peak memory 212316 kb
Host smart-7da24ff9-a4a3-4152-b116-f136aba90dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307346888 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.307346888
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.4153696384
Short name T1230
Test name
Test status
Simulation time 43413109 ps
CPU time 0.63 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:44:25 PM PDT 24
Peak memory 203856 kb
Host smart-0da925f4-1f94-45a6-a0ad-982df3713228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153696384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.4153696384
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2716797479
Short name T767
Test name
Test status
Simulation time 568036337 ps
CPU time 1.48 seconds
Started May 02 01:44:12 PM PDT 24
Finished May 02 01:44:14 PM PDT 24
Peak memory 212484 kb
Host smart-1bc10d5d-e242-458d-a6de-a654d60544b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716797479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2716797479
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.903576992
Short name T1069
Test name
Test status
Simulation time 307239271 ps
CPU time 5.55 seconds
Started May 02 01:44:14 PM PDT 24
Finished May 02 01:44:20 PM PDT 24
Peak memory 266460 kb
Host smart-c4190f56-f6c7-4cff-b3ee-890ac7986756
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903576992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.903576992
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2825700527
Short name T607
Test name
Test status
Simulation time 1394904026 ps
CPU time 40.98 seconds
Started May 02 01:44:12 PM PDT 24
Finished May 02 01:44:54 PM PDT 24
Peak memory 548028 kb
Host smart-528d5d1d-e890-4ab1-90e9-9136fd023d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825700527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2825700527
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.803948979
Short name T1064
Test name
Test status
Simulation time 1194830786 ps
CPU time 29.84 seconds
Started May 02 01:44:11 PM PDT 24
Finished May 02 01:44:42 PM PDT 24
Peak memory 484936 kb
Host smart-8c4ee4d2-9fef-4d75-84eb-c91d620fc9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803948979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.803948979
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3240844769
Short name T931
Test name
Test status
Simulation time 115157232 ps
CPU time 1.03 seconds
Started May 02 01:44:11 PM PDT 24
Finished May 02 01:44:13 PM PDT 24
Peak memory 204112 kb
Host smart-59e35bac-fdeb-425e-a479-2401a6b5d78b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240844769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3240844769
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3685945279
Short name T1068
Test name
Test status
Simulation time 502539534 ps
CPU time 6.85 seconds
Started May 02 01:44:12 PM PDT 24
Finished May 02 01:44:19 PM PDT 24
Peak memory 223824 kb
Host smart-18c92f62-dc17-46ab-b9fb-35c66cca8cce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685945279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3685945279
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3969380263
Short name T639
Test name
Test status
Simulation time 4344373722 ps
CPU time 130.41 seconds
Started May 02 01:44:12 PM PDT 24
Finished May 02 01:46:23 PM PDT 24
Peak memory 1227976 kb
Host smart-0179fae4-e3c4-46a4-9a0b-b560d6c71db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969380263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3969380263
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.300706859
Short name T1019
Test name
Test status
Simulation time 896813524 ps
CPU time 5.33 seconds
Started May 02 01:44:21 PM PDT 24
Finished May 02 01:44:27 PM PDT 24
Peak memory 204100 kb
Host smart-dd3ab1c2-566a-4166-984b-418c882f863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300706859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.300706859
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.986103986
Short name T1082
Test name
Test status
Simulation time 3003463775 ps
CPU time 68.62 seconds
Started May 02 01:44:22 PM PDT 24
Finished May 02 01:45:31 PM PDT 24
Peak memory 374468 kb
Host smart-3c4bc9b5-3f19-4e7f-8212-27a2041b950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986103986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.986103986
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.148944752
Short name T195
Test name
Test status
Simulation time 20696535 ps
CPU time 0.68 seconds
Started May 02 01:44:14 PM PDT 24
Finished May 02 01:44:15 PM PDT 24
Peak memory 203892 kb
Host smart-32b27bd4-4ef1-4b57-aae7-cd69e898a681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148944752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.148944752
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1828981874
Short name T578
Test name
Test status
Simulation time 7618305465 ps
CPU time 26.89 seconds
Started May 02 01:44:10 PM PDT 24
Finished May 02 01:44:38 PM PDT 24
Peak memory 271944 kb
Host smart-97d3f01f-40fc-4bcf-afa4-f3fd0da1ec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828981874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1828981874
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1984551930
Short name T1061
Test name
Test status
Simulation time 1463674996 ps
CPU time 22.39 seconds
Started May 02 01:44:10 PM PDT 24
Finished May 02 01:44:33 PM PDT 24
Peak memory 335444 kb
Host smart-96bb2b52-03b1-484b-ba8a-86c9abd2f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984551930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1984551930
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.3246484286
Short name T305
Test name
Test status
Simulation time 1729667594 ps
CPU time 20.95 seconds
Started May 02 01:44:10 PM PDT 24
Finished May 02 01:44:32 PM PDT 24
Peak memory 212400 kb
Host smart-3576f8cf-d30f-4973-9354-d8db2fed00fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246484286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3246484286
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2477855249
Short name T1157
Test name
Test status
Simulation time 4230649440 ps
CPU time 4.43 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:44:29 PM PDT 24
Peak memory 204284 kb
Host smart-afed4d73-b611-4631-bf95-658321c6fb02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477855249 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2477855249
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.4156735253
Short name T740
Test name
Test status
Simulation time 10274839164 ps
CPU time 16.95 seconds
Started May 02 01:44:12 PM PDT 24
Finished May 02 01:44:30 PM PDT 24
Peak memory 288236 kb
Host smart-fac59741-5e10-44ec-b4fc-3d5d4d42c0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156735253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.4156735253
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2551698738
Short name T702
Test name
Test status
Simulation time 1573669891 ps
CPU time 2.77 seconds
Started May 02 01:44:22 PM PDT 24
Finished May 02 01:44:26 PM PDT 24
Peak memory 204152 kb
Host smart-0da57a9d-dfac-480a-a5e5-15ec7b228894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551698738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2551698738
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3222988328
Short name T868
Test name
Test status
Simulation time 3441749719 ps
CPU time 7.34 seconds
Started May 02 01:44:10 PM PDT 24
Finished May 02 01:44:19 PM PDT 24
Peak memory 212440 kb
Host smart-04cbb55d-104e-40e0-945a-1f41f1b57f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222988328 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3222988328
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2886425477
Short name T1021
Test name
Test status
Simulation time 12816804220 ps
CPU time 15.14 seconds
Started May 02 01:44:11 PM PDT 24
Finished May 02 01:44:27 PM PDT 24
Peak memory 424760 kb
Host smart-6e86ba18-debf-47fb-8650-3761f799e03f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886425477 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2886425477
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3387659538
Short name T384
Test name
Test status
Simulation time 466225290 ps
CPU time 6.3 seconds
Started May 02 01:44:11 PM PDT 24
Finished May 02 01:44:18 PM PDT 24
Peak memory 204132 kb
Host smart-fb45d972-85c0-4caa-95f6-d901bd8f3baf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387659538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3387659538
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3283085532
Short name T763
Test name
Test status
Simulation time 6557389844 ps
CPU time 72.34 seconds
Started May 02 01:44:16 PM PDT 24
Finished May 02 01:45:29 PM PDT 24
Peak memory 207984 kb
Host smart-36730913-2e94-4ab1-a1e9-5a3e96676f0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283085532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3283085532
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2918068557
Short name T576
Test name
Test status
Simulation time 30943405027 ps
CPU time 33.18 seconds
Started May 02 01:44:12 PM PDT 24
Finished May 02 01:44:46 PM PDT 24
Peak memory 729064 kb
Host smart-6b89da31-e940-40ee-a279-d9a92f74e6d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918068557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2918068557
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3881376234
Short name T432
Test name
Test status
Simulation time 22098143767 ps
CPU time 156.03 seconds
Started May 02 01:44:10 PM PDT 24
Finished May 02 01:46:47 PM PDT 24
Peak memory 1252688 kb
Host smart-2f34cba3-1a7b-469a-8cc0-3b38ddb7c766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881376234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3881376234
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1058703601
Short name T224
Test name
Test status
Simulation time 1418745177 ps
CPU time 6.88 seconds
Started May 02 01:44:10 PM PDT 24
Finished May 02 01:44:18 PM PDT 24
Peak memory 211224 kb
Host smart-f7fe9182-2398-4fd0-b6a3-30fabeef06a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058703601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1058703601
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2884887117
Short name T1324
Test name
Test status
Simulation time 25308726 ps
CPU time 0.62 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:44:31 PM PDT 24
Peak memory 203872 kb
Host smart-76bd152b-1023-4aa4-9465-6f4574d60388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884887117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2884887117
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.352866410
Short name T630
Test name
Test status
Simulation time 73415572 ps
CPU time 1.56 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:44:26 PM PDT 24
Peak memory 212472 kb
Host smart-4993729c-5b8f-4320-9b29-b87dd61e29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352866410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.352866410
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2199151869
Short name T521
Test name
Test status
Simulation time 236887928 ps
CPU time 5.07 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:44:29 PM PDT 24
Peak memory 239348 kb
Host smart-bec70843-ef80-4c41-9f3e-2a90581b9ea4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199151869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2199151869
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.368758946
Short name T944
Test name
Test status
Simulation time 4669604896 ps
CPU time 49.75 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:45:14 PM PDT 24
Peak memory 589380 kb
Host smart-1ec63733-904e-414a-ab98-f6a7ae067cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368758946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.368758946
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3688377434
Short name T92
Test name
Test status
Simulation time 4131645515 ps
CPU time 43.88 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:45:08 PM PDT 24
Peak memory 528972 kb
Host smart-3827db78-08db-4ad6-9bbd-6189d18a93d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688377434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3688377434
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2587573270
Short name T254
Test name
Test status
Simulation time 1378315082 ps
CPU time 0.91 seconds
Started May 02 01:44:22 PM PDT 24
Finished May 02 01:44:25 PM PDT 24
Peak memory 203972 kb
Host smart-ec0f684f-9d66-40dc-baf8-9f317f4d291f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587573270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2587573270
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1569596288
Short name T1014
Test name
Test status
Simulation time 192415016 ps
CPU time 3.96 seconds
Started May 02 01:44:22 PM PDT 24
Finished May 02 01:44:27 PM PDT 24
Peak memory 204088 kb
Host smart-8694775e-1775-4331-b276-1f0c4555462e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569596288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1569596288
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1804041537
Short name T1246
Test name
Test status
Simulation time 3287494068 ps
CPU time 92.65 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:45:57 PM PDT 24
Peak memory 936348 kb
Host smart-babefb72-81b8-40bb-a5ad-92906447bd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804041537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1804041537
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.4261660567
Short name T894
Test name
Test status
Simulation time 1413996575 ps
CPU time 14.54 seconds
Started May 02 01:44:31 PM PDT 24
Finished May 02 01:44:47 PM PDT 24
Peak memory 204160 kb
Host smart-bb6b3097-9c88-4ee5-a08c-22ac91cf9e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261660567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.4261660567
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.1449833502
Short name T1158
Test name
Test status
Simulation time 16924038987 ps
CPU time 18.56 seconds
Started May 02 01:44:33 PM PDT 24
Finished May 02 01:44:52 PM PDT 24
Peak memory 278484 kb
Host smart-25cdf70d-dd33-468e-9a96-2f4047730fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449833502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.1449833502
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.4253593837
Short name T723
Test name
Test status
Simulation time 26100004 ps
CPU time 0.63 seconds
Started May 02 01:44:21 PM PDT 24
Finished May 02 01:44:23 PM PDT 24
Peak memory 203788 kb
Host smart-5f54cfe3-a660-463b-a551-03a3b3e95566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253593837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.4253593837
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1589010878
Short name T1025
Test name
Test status
Simulation time 6423792677 ps
CPU time 68.01 seconds
Started May 02 01:44:22 PM PDT 24
Finished May 02 01:45:31 PM PDT 24
Peak memory 213056 kb
Host smart-52dfee17-29b7-4a7a-85c8-2f32fb7ff370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589010878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1589010878
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.2256137682
Short name T620
Test name
Test status
Simulation time 915322353 ps
CPU time 14.56 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:44:39 PM PDT 24
Peak memory 258772 kb
Host smart-a8a11660-eb72-4cc4-886b-a33c0762aae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256137682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2256137682
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1036385534
Short name T437
Test name
Test status
Simulation time 2171257563 ps
CPU time 9.52 seconds
Started May 02 01:44:23 PM PDT 24
Finished May 02 01:44:34 PM PDT 24
Peak memory 215668 kb
Host smart-5161bf1f-303d-4516-b278-e330e2d31c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036385534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1036385534
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1035415797
Short name T1015
Test name
Test status
Simulation time 4463831425 ps
CPU time 2.65 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:44:32 PM PDT 24
Peak memory 204208 kb
Host smart-4ea1891d-b6d2-4f12-bf81-e2999cbb4748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035415797 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1035415797
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.601855996
Short name T557
Test name
Test status
Simulation time 10068761212 ps
CPU time 65.97 seconds
Started May 02 01:44:30 PM PDT 24
Finished May 02 01:45:37 PM PDT 24
Peak memory 513596 kb
Host smart-d0857b05-d72c-4028-ad3d-b37e35ca5d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601855996 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.601855996
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1475756567
Short name T670
Test name
Test status
Simulation time 10055784909 ps
CPU time 68.69 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:45:38 PM PDT 24
Peak memory 552720 kb
Host smart-89ee656e-6361-4fce-920a-07d551a6bb80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475756567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1475756567
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1459577756
Short name T957
Test name
Test status
Simulation time 2551168773 ps
CPU time 3.45 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:44:34 PM PDT 24
Peak memory 204184 kb
Host smart-0702463e-e98e-4ec9-ad49-c21bf4496045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459577756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1459577756
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3888562805
Short name T1005
Test name
Test status
Simulation time 978789913 ps
CPU time 4.63 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:44:34 PM PDT 24
Peak memory 206272 kb
Host smart-fe18479b-a65c-45ca-9256-78a3d622fef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888562805 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3888562805
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.885271992
Short name T454
Test name
Test status
Simulation time 3067467923 ps
CPU time 7.01 seconds
Started May 02 01:44:31 PM PDT 24
Finished May 02 01:44:39 PM PDT 24
Peak memory 204184 kb
Host smart-539894a7-48af-49a4-8e35-8eda895946f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885271992 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.885271992
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2966735458
Short name T876
Test name
Test status
Simulation time 906542846 ps
CPU time 11.39 seconds
Started May 02 01:44:22 PM PDT 24
Finished May 02 01:44:35 PM PDT 24
Peak memory 204184 kb
Host smart-bea1cdc9-22d6-4827-a219-7ecc72164cb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966735458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2966735458
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.416660225
Short name T837
Test name
Test status
Simulation time 1140870556 ps
CPU time 45.83 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:45:16 PM PDT 24
Peak memory 205592 kb
Host smart-d4bba4bf-121a-42db-b3fa-4d236e47691a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416660225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.416660225
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2853373841
Short name T275
Test name
Test status
Simulation time 22217108835 ps
CPU time 8.5 seconds
Started May 02 01:44:22 PM PDT 24
Finished May 02 01:44:32 PM PDT 24
Peak memory 204292 kb
Host smart-01edabe3-61fe-428d-a0ea-d37bc765da36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853373841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2853373841
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1048159194
Short name T701
Test name
Test status
Simulation time 13903703007 ps
CPU time 456.41 seconds
Started May 02 01:44:28 PM PDT 24
Finished May 02 01:52:06 PM PDT 24
Peak memory 2963008 kb
Host smart-a8fd0ff2-9d01-408f-b4df-db49f64fdf84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048159194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1048159194
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.4037202851
Short name T484
Test name
Test status
Simulation time 1111433643 ps
CPU time 6.17 seconds
Started May 02 01:44:28 PM PDT 24
Finished May 02 01:44:35 PM PDT 24
Peak memory 204240 kb
Host smart-c54305c2-45e3-4773-8f06-42cea40d82f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037202851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.4037202851
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3008897269
Short name T550
Test name
Test status
Simulation time 19227096 ps
CPU time 0.66 seconds
Started May 02 01:44:45 PM PDT 24
Finished May 02 01:44:47 PM PDT 24
Peak memory 203900 kb
Host smart-c3d3491d-ee5d-4b5f-a1ef-bf613490bb5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008897269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3008897269
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1201347151
Short name T873
Test name
Test status
Simulation time 523033572 ps
CPU time 1.57 seconds
Started May 02 01:44:30 PM PDT 24
Finished May 02 01:44:33 PM PDT 24
Peak memory 212396 kb
Host smart-21b31b5f-ae0a-4316-82f5-9ffd36f4cab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201347151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1201347151
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.801254462
Short name T866
Test name
Test status
Simulation time 527513692 ps
CPU time 6.01 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:44:36 PM PDT 24
Peak memory 254984 kb
Host smart-e1891c9a-e50c-4bb5-9ac4-e8ff46547a0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801254462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.801254462
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1676697795
Short name T363
Test name
Test status
Simulation time 5801164646 ps
CPU time 97.3 seconds
Started May 02 01:44:31 PM PDT 24
Finished May 02 01:46:09 PM PDT 24
Peak memory 552372 kb
Host smart-6eaa49e1-b4a2-4278-b940-75205383c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676697795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1676697795
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3692650690
Short name T552
Test name
Test status
Simulation time 2109428248 ps
CPU time 152.98 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:47:03 PM PDT 24
Peak memory 644176 kb
Host smart-c667ea10-dfe9-4536-92bd-a4f2a4322fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692650690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3692650690
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3257225568
Short name T570
Test name
Test status
Simulation time 361024800 ps
CPU time 0.9 seconds
Started May 02 01:44:31 PM PDT 24
Finished May 02 01:44:33 PM PDT 24
Peak memory 203888 kb
Host smart-2f94faf0-0be8-47a1-adf0-966ad187a37f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257225568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3257225568
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1565654871
Short name T842
Test name
Test status
Simulation time 718802672 ps
CPU time 5.01 seconds
Started May 02 01:44:30 PM PDT 24
Finished May 02 01:44:36 PM PDT 24
Peak memory 237024 kb
Host smart-17417cbe-bd94-4669-9de2-2200c0c3b5ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565654871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1565654871
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1230386196
Short name T754
Test name
Test status
Simulation time 3991898064 ps
CPU time 285.36 seconds
Started May 02 01:44:28 PM PDT 24
Finished May 02 01:49:14 PM PDT 24
Peak memory 1129480 kb
Host smart-095ca15d-2f2d-434d-84a9-1498dbc7b62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230386196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1230386196
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2783249794
Short name T1000
Test name
Test status
Simulation time 381295840 ps
CPU time 5.08 seconds
Started May 02 01:44:45 PM PDT 24
Finished May 02 01:44:51 PM PDT 24
Peak memory 204196 kb
Host smart-8231ed39-a140-458b-aa59-a251efd7606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783249794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2783249794
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2265676416
Short name T533
Test name
Test status
Simulation time 1607802460 ps
CPU time 23.53 seconds
Started May 02 01:44:40 PM PDT 24
Finished May 02 01:45:05 PM PDT 24
Peak memory 310240 kb
Host smart-5c0ed030-7aa1-47b1-a650-538cbc1cd499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265676416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2265676416
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1661068293
Short name T341
Test name
Test status
Simulation time 68247872 ps
CPU time 0.61 seconds
Started May 02 01:44:43 PM PDT 24
Finished May 02 01:44:45 PM PDT 24
Peak memory 203824 kb
Host smart-b58ea78f-61dd-4c65-95e3-615692c93516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661068293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1661068293
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.181922828
Short name T464
Test name
Test status
Simulation time 3137042391 ps
CPU time 122.01 seconds
Started May 02 01:44:28 PM PDT 24
Finished May 02 01:46:31 PM PDT 24
Peak memory 228672 kb
Host smart-1bfb5f9d-cd79-4064-bfa8-d2316a639b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181922828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.181922828
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1997657365
Short name T271
Test name
Test status
Simulation time 31224533855 ps
CPU time 75.18 seconds
Started May 02 01:44:27 PM PDT 24
Finished May 02 01:45:43 PM PDT 24
Peak memory 380136 kb
Host smart-10442aea-4545-4189-9117-9715e7dbc41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997657365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1997657365
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.697761416
Short name T94
Test name
Test status
Simulation time 9343601380 ps
CPU time 777.85 seconds
Started May 02 01:44:31 PM PDT 24
Finished May 02 01:57:30 PM PDT 24
Peak memory 1230988 kb
Host smart-dc6f07c5-1f2c-44fc-88e7-a70477d22903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697761416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.697761416
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3058683771
Short name T629
Test name
Test status
Simulation time 364684382 ps
CPU time 16.19 seconds
Started May 02 01:44:33 PM PDT 24
Finished May 02 01:44:50 PM PDT 24
Peak memory 212364 kb
Host smart-4289e017-c431-4621-96ff-e230af2ebf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058683771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3058683771
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.743438687
Short name T502
Test name
Test status
Simulation time 711897479 ps
CPU time 3.67 seconds
Started May 02 01:44:34 PM PDT 24
Finished May 02 01:44:38 PM PDT 24
Peak memory 212372 kb
Host smart-ad91dbac-aff2-4776-ab5c-3b3284c022b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743438687 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.743438687
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3040447029
Short name T1307
Test name
Test status
Simulation time 10068207222 ps
CPU time 62.11 seconds
Started May 02 01:44:35 PM PDT 24
Finished May 02 01:45:38 PM PDT 24
Peak memory 466444 kb
Host smart-6946293d-fd13-483b-93f8-a98483de1c5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040447029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3040447029
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.351809237
Short name T414
Test name
Test status
Simulation time 10045761966 ps
CPU time 68.93 seconds
Started May 02 01:44:35 PM PDT 24
Finished May 02 01:45:45 PM PDT 24
Peak memory 547980 kb
Host smart-f533e286-b705-4baf-8c2f-3ef6aaf08e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351809237 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_tx.351809237
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.173713974
Short name T459
Test name
Test status
Simulation time 573919541 ps
CPU time 1.89 seconds
Started May 02 01:44:34 PM PDT 24
Finished May 02 01:44:37 PM PDT 24
Peak memory 204108 kb
Host smart-b507f0b1-5ef8-41ba-9142-663fb89fc4b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173713974 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.173713974
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3417260042
Short name T398
Test name
Test status
Simulation time 2974549409 ps
CPU time 7.22 seconds
Started May 02 01:44:29 PM PDT 24
Finished May 02 01:44:37 PM PDT 24
Peak memory 204224 kb
Host smart-5d7715ed-8ec2-4ff7-85bf-aa4c7e2976cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417260042 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3417260042
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.4152787967
Short name T1306
Test name
Test status
Simulation time 3197041044 ps
CPU time 6.87 seconds
Started May 02 01:44:34 PM PDT 24
Finished May 02 01:44:42 PM PDT 24
Peak memory 204228 kb
Host smart-45cac8c0-3e59-49a3-83fc-237697203815
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152787967 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.4152787967
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1576225375
Short name T403
Test name
Test status
Simulation time 980396205 ps
CPU time 13.8 seconds
Started May 02 01:44:32 PM PDT 24
Finished May 02 01:44:47 PM PDT 24
Peak memory 204152 kb
Host smart-e4d1dbab-4b69-45f2-9ee0-3286b3822506
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576225375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1576225375
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.56648219
Short name T1165
Test name
Test status
Simulation time 618882826 ps
CPU time 11.12 seconds
Started May 02 01:44:31 PM PDT 24
Finished May 02 01:44:43 PM PDT 24
Peak memory 206528 kb
Host smart-42ad77a9-1712-4a15-94c5-85e6587a6f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56648219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_rd.56648219
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1491815905
Short name T222
Test name
Test status
Simulation time 37290289559 ps
CPU time 359.91 seconds
Started May 02 01:44:28 PM PDT 24
Finished May 02 01:50:29 PM PDT 24
Peak memory 3749652 kb
Host smart-b282d7ac-524d-4163-9939-1afceb07ceb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491815905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1491815905
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.4125963258
Short name T634
Test name
Test status
Simulation time 23156640802 ps
CPU time 1590.64 seconds
Started May 02 01:44:30 PM PDT 24
Finished May 02 02:11:03 PM PDT 24
Peak memory 5656360 kb
Host smart-bbd58650-ec04-4b51-8776-7406d32f407b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125963258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.4125963258
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.2938903003
Short name T412
Test name
Test status
Simulation time 6753675508 ps
CPU time 7.2 seconds
Started May 02 01:44:36 PM PDT 24
Finished May 02 01:44:44 PM PDT 24
Peak memory 220396 kb
Host smart-0abccec6-a618-4701-ac87-55e3eba8a56a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938903003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.2938903003
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2086254270
Short name T960
Test name
Test status
Simulation time 48339465 ps
CPU time 0.64 seconds
Started May 02 01:44:51 PM PDT 24
Finished May 02 01:44:52 PM PDT 24
Peak memory 203892 kb
Host smart-dfe1c41d-fa44-48cb-b9f0-2dd5205a746a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086254270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2086254270
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3445543564
Short name T934
Test name
Test status
Simulation time 236278545 ps
CPU time 1.26 seconds
Started May 02 01:44:41 PM PDT 24
Finished May 02 01:44:43 PM PDT 24
Peak memory 204128 kb
Host smart-31f33a06-b58f-4211-b90e-c8b9eb0947ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445543564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3445543564
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.795343568
Short name T851
Test name
Test status
Simulation time 852077924 ps
CPU time 11.49 seconds
Started May 02 01:44:45 PM PDT 24
Finished May 02 01:44:58 PM PDT 24
Peak memory 235828 kb
Host smart-ee1ea420-de30-4511-a47a-5c9d4913bece
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795343568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.795343568
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2474892508
Short name T900
Test name
Test status
Simulation time 2419871794 ps
CPU time 39.18 seconds
Started May 02 01:44:44 PM PDT 24
Finished May 02 01:45:24 PM PDT 24
Peak memory 499136 kb
Host smart-007601d3-1a0e-4544-a755-715abc2f9c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474892508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2474892508
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1160096877
Short name T690
Test name
Test status
Simulation time 25619191280 ps
CPU time 113.02 seconds
Started May 02 01:44:42 PM PDT 24
Finished May 02 01:46:35 PM PDT 24
Peak memory 588776 kb
Host smart-a3c09a6f-d0cc-41b8-9f0c-264f19a47061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160096877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1160096877
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1000799694
Short name T1215
Test name
Test status
Simulation time 1292443703 ps
CPU time 1.01 seconds
Started May 02 01:44:43 PM PDT 24
Finished May 02 01:44:45 PM PDT 24
Peak memory 204116 kb
Host smart-1d646907-eb17-41bc-a982-6e255b0f9c9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000799694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1000799694
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4120108475
Short name T38
Test name
Test status
Simulation time 1492397242 ps
CPU time 5.86 seconds
Started May 02 01:44:45 PM PDT 24
Finished May 02 01:44:52 PM PDT 24
Peak memory 204208 kb
Host smart-8890be10-d686-435c-b38b-737bd37283b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120108475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4120108475
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3903652149
Short name T1261
Test name
Test status
Simulation time 3635870761 ps
CPU time 71.13 seconds
Started May 02 01:44:43 PM PDT 24
Finished May 02 01:45:55 PM PDT 24
Peak memory 835008 kb
Host smart-70528eee-64bc-4202-bcef-db1fb9fe5dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903652149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3903652149
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.96598540
Short name T911
Test name
Test status
Simulation time 791388859 ps
CPU time 21.6 seconds
Started May 02 01:44:49 PM PDT 24
Finished May 02 01:45:11 PM PDT 24
Peak memory 204136 kb
Host smart-8ee03722-64c7-4953-af31-ea4ec98b34a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96598540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.96598540
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.628592280
Short name T1268
Test name
Test status
Simulation time 1992508514 ps
CPU time 23.7 seconds
Started May 02 01:44:51 PM PDT 24
Finished May 02 01:45:16 PM PDT 24
Peak memory 333584 kb
Host smart-5d7e3b28-6bb8-4d19-b5fa-217370df29bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628592280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.628592280
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2558128142
Short name T196
Test name
Test status
Simulation time 93146932 ps
CPU time 0.68 seconds
Started May 02 01:44:42 PM PDT 24
Finished May 02 01:44:44 PM PDT 24
Peak memory 203804 kb
Host smart-c0594766-d207-4176-aaa7-04deccb4dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558128142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2558128142
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1481290079
Short name T783
Test name
Test status
Simulation time 6950475953 ps
CPU time 136.31 seconds
Started May 02 01:44:44 PM PDT 24
Finished May 02 01:47:01 PM PDT 24
Peak memory 212436 kb
Host smart-88594910-e5b0-4d7b-8f0f-316ce9a76c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481290079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1481290079
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2205962166
Short name T531
Test name
Test status
Simulation time 6140311474 ps
CPU time 27.79 seconds
Started May 02 01:44:45 PM PDT 24
Finished May 02 01:45:14 PM PDT 24
Peak memory 361272 kb
Host smart-80f847c4-842d-4a3a-bf42-d181aee42b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205962166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2205962166
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2208225242
Short name T796
Test name
Test status
Simulation time 20257247202 ps
CPU time 226.35 seconds
Started May 02 01:44:44 PM PDT 24
Finished May 02 01:48:31 PM PDT 24
Peak memory 1183996 kb
Host smart-079f6696-5f58-4d73-9345-e3b58589e04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208225242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2208225242
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2078401033
Short name T968
Test name
Test status
Simulation time 6355782665 ps
CPU time 8.41 seconds
Started May 02 01:44:43 PM PDT 24
Finished May 02 01:44:52 PM PDT 24
Peak memory 228744 kb
Host smart-13d57e4a-e089-47ad-9520-45b23495b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078401033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2078401033
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3321009806
Short name T1102
Test name
Test status
Simulation time 813575351 ps
CPU time 3.89 seconds
Started May 02 01:44:49 PM PDT 24
Finished May 02 01:44:53 PM PDT 24
Peak memory 204120 kb
Host smart-e4410c2a-3006-4b93-8407-41835c86c5b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321009806 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3321009806
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1055667257
Short name T674
Test name
Test status
Simulation time 10075026198 ps
CPU time 67.29 seconds
Started May 02 01:44:42 PM PDT 24
Finished May 02 01:45:50 PM PDT 24
Peak memory 511952 kb
Host smart-c1b6e49b-038e-4c3a-8e63-f1fcef5d69be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055667257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1055667257
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2886633936
Short name T1150
Test name
Test status
Simulation time 10103725228 ps
CPU time 72.62 seconds
Started May 02 01:44:49 PM PDT 24
Finished May 02 01:46:02 PM PDT 24
Peak memory 480456 kb
Host smart-5ce00cf5-0f4f-4ba8-8094-fc0e9a1ee19d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886633936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2886633936
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.4114827609
Short name T15
Test name
Test status
Simulation time 2627370350 ps
CPU time 2.64 seconds
Started May 02 01:44:50 PM PDT 24
Finished May 02 01:44:53 PM PDT 24
Peak memory 204192 kb
Host smart-b5d2802f-ef7d-49b1-8272-88c92599fd4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114827609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.4114827609
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2974984120
Short name T657
Test name
Test status
Simulation time 757288999 ps
CPU time 4.15 seconds
Started May 02 01:44:42 PM PDT 24
Finished May 02 01:44:47 PM PDT 24
Peak memory 204200 kb
Host smart-847a1ee1-d7ec-4b15-a2f5-557d5eafc9ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974984120 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2974984120
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.4247797015
Short name T107
Test name
Test status
Simulation time 5565080115 ps
CPU time 14.31 seconds
Started May 02 01:44:42 PM PDT 24
Finished May 02 01:44:58 PM PDT 24
Peak memory 204192 kb
Host smart-40774373-29a1-4587-94dc-9d9fbbacb79c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247797015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.4247797015
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.4097285453
Short name T577
Test name
Test status
Simulation time 2664450846 ps
CPU time 11.16 seconds
Started May 02 01:44:45 PM PDT 24
Finished May 02 01:44:57 PM PDT 24
Peak memory 208020 kb
Host smart-10948ba9-dada-4343-b97c-c1aa97dff5d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097285453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.4097285453
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1771731675
Short name T1353
Test name
Test status
Simulation time 43806202117 ps
CPU time 253.41 seconds
Started May 02 01:44:42 PM PDT 24
Finished May 02 01:48:56 PM PDT 24
Peak memory 3056924 kb
Host smart-9630db07-d3ac-4065-8bf5-9550139299e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771731675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1771731675
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3875916624
Short name T592
Test name
Test status
Simulation time 9323944324 ps
CPU time 325.56 seconds
Started May 02 01:44:43 PM PDT 24
Finished May 02 01:50:10 PM PDT 24
Peak memory 2382472 kb
Host smart-5fd41481-a216-4cbb-9be9-f169ec64dd9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875916624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3875916624
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2785856899
Short name T1144
Test name
Test status
Simulation time 12088501125 ps
CPU time 8.06 seconds
Started May 02 01:44:43 PM PDT 24
Finished May 02 01:44:52 PM PDT 24
Peak memory 220516 kb
Host smart-af8b322a-954b-48f6-a4cb-ca0d5c8a46a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785856899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2785856899
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.70387167
Short name T345
Test name
Test status
Simulation time 24043635 ps
CPU time 0.62 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:42:06 PM PDT 24
Peak memory 203840 kb
Host smart-eb30b8a5-c8b7-4c48-a7f6-55aac34f72b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70387167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.70387167
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.4215613068
Short name T248
Test name
Test status
Simulation time 259395698 ps
CPU time 1.75 seconds
Started May 02 01:41:56 PM PDT 24
Finished May 02 01:41:58 PM PDT 24
Peak memory 212428 kb
Host smart-457ce6d8-0232-4957-a157-f67c9bb571fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215613068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.4215613068
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1433325629
Short name T956
Test name
Test status
Simulation time 3816443888 ps
CPU time 16.95 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:26 PM PDT 24
Peak memory 272512 kb
Host smart-ff8b187f-679c-442b-abb1-9d09d8efe038
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433325629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1433325629
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.303297312
Short name T526
Test name
Test status
Simulation time 4181870071 ps
CPU time 59.91 seconds
Started May 02 01:41:57 PM PDT 24
Finished May 02 01:42:58 PM PDT 24
Peak memory 647752 kb
Host smart-b1fd3de9-8b5c-4535-98ed-d185538eddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303297312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.303297312
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.354503008
Short name T655
Test name
Test status
Simulation time 4351597888 ps
CPU time 75.44 seconds
Started May 02 01:41:59 PM PDT 24
Finished May 02 01:43:16 PM PDT 24
Peak memory 474820 kb
Host smart-a95ec350-e9ab-44ad-94a2-b8e2979ed8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354503008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.354503008
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3380999546
Short name T1323
Test name
Test status
Simulation time 461353807 ps
CPU time 1.01 seconds
Started May 02 01:41:58 PM PDT 24
Finished May 02 01:42:01 PM PDT 24
Peak memory 204156 kb
Host smart-580a3298-67ac-4a69-bc67-31380252c485
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380999546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3380999546
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2939736779
Short name T98
Test name
Test status
Simulation time 155657022 ps
CPU time 6.62 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:16 PM PDT 24
Peak memory 204152 kb
Host smart-f0fe9c3f-73a2-4896-b5f4-dcced3e528e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939736779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2939736779
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.480016803
Short name T231
Test name
Test status
Simulation time 5010535935 ps
CPU time 68.17 seconds
Started May 02 01:41:56 PM PDT 24
Finished May 02 01:43:06 PM PDT 24
Peak memory 800404 kb
Host smart-8aec104a-0439-48ba-848b-63edcde6f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480016803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.480016803
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.981007093
Short name T691
Test name
Test status
Simulation time 1102902070 ps
CPU time 6.47 seconds
Started May 02 01:42:06 PM PDT 24
Finished May 02 01:42:13 PM PDT 24
Peak memory 204108 kb
Host smart-236ed353-8f6f-4322-9b12-9547e3c9f21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981007093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.981007093
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3801271955
Short name T1314
Test name
Test status
Simulation time 4614001428 ps
CPU time 23.19 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:42:29 PM PDT 24
Peak memory 293712 kb
Host smart-7d26c02c-706b-436d-a45a-0ccb0778e733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801271955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3801271955
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.2224454487
Short name T846
Test name
Test status
Simulation time 58308621 ps
CPU time 0.67 seconds
Started May 02 01:41:59 PM PDT 24
Finished May 02 01:42:01 PM PDT 24
Peak memory 203828 kb
Host smart-223e31a4-8166-4deb-b6d5-a9300bee3abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224454487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2224454487
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2731458275
Short name T6
Test name
Test status
Simulation time 622049901 ps
CPU time 6.08 seconds
Started May 02 01:41:58 PM PDT 24
Finished May 02 01:42:06 PM PDT 24
Peak memory 250060 kb
Host smart-a3e8d16d-7eb7-448c-a2d6-55ea103ce7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731458275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2731458275
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2896366173
Short name T1170
Test name
Test status
Simulation time 7593154477 ps
CPU time 30.83 seconds
Started May 02 01:41:58 PM PDT 24
Finished May 02 01:42:30 PM PDT 24
Peak memory 315568 kb
Host smart-d5a6d466-0f56-4963-a78b-f675f6c21a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896366173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2896366173
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1449756899
Short name T422
Test name
Test status
Simulation time 743845932 ps
CPU time 35.21 seconds
Started May 02 01:41:57 PM PDT 24
Finished May 02 01:42:34 PM PDT 24
Peak memory 212424 kb
Host smart-2786b3a0-2c01-4503-8060-737a32752cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449756899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1449756899
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.4092119172
Short name T1225
Test name
Test status
Simulation time 9988542407 ps
CPU time 5.62 seconds
Started May 02 01:41:57 PM PDT 24
Finished May 02 01:42:04 PM PDT 24
Peak memory 212636 kb
Host smart-f5b748cf-53f6-4f53-978a-af5a98e3cf6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092119172 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.4092119172
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.805588558
Short name T1134
Test name
Test status
Simulation time 10220770680 ps
CPU time 11.94 seconds
Started May 02 01:41:55 PM PDT 24
Finished May 02 01:42:09 PM PDT 24
Peak memory 245568 kb
Host smart-1b291fe2-b3af-4951-9ebd-b8dcc1c58e22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805588558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.805588558
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3702875379
Short name T839
Test name
Test status
Simulation time 10216837205 ps
CPU time 35.24 seconds
Started May 02 01:41:58 PM PDT 24
Finished May 02 01:42:35 PM PDT 24
Peak memory 354604 kb
Host smart-5c287a6b-7004-4aea-beaa-c0107cda705f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702875379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3702875379
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3505288558
Short name T815
Test name
Test status
Simulation time 2809184198 ps
CPU time 2.58 seconds
Started May 02 01:41:55 PM PDT 24
Finished May 02 01:41:59 PM PDT 24
Peak memory 204188 kb
Host smart-adb110c9-e566-4aa1-bc45-25ab3abd70df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505288558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3505288558
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3865840342
Short name T645
Test name
Test status
Simulation time 3938912327 ps
CPU time 5.07 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:14 PM PDT 24
Peak memory 212300 kb
Host smart-ad4bdaa4-da12-4004-8a0b-bac7f1516eed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865840342 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3865840342
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.888514110
Short name T721
Test name
Test status
Simulation time 11797592837 ps
CPU time 53.3 seconds
Started May 02 01:41:57 PM PDT 24
Finished May 02 01:42:52 PM PDT 24
Peak memory 1239444 kb
Host smart-5e5673db-aa69-49ae-9b3e-4458184e1550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888514110 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.888514110
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.4063160491
Short name T892
Test name
Test status
Simulation time 1428430354 ps
CPU time 5.09 seconds
Started May 02 01:41:58 PM PDT 24
Finished May 02 01:42:05 PM PDT 24
Peak memory 204180 kb
Host smart-1c5d44d6-a61b-4eb4-a8a9-93995c964015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063160491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.4063160491
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.2944287006
Short name T288
Test name
Test status
Simulation time 1277790638 ps
CPU time 18.72 seconds
Started May 02 01:41:59 PM PDT 24
Finished May 02 01:42:19 PM PDT 24
Peak memory 218120 kb
Host smart-74efc027-a628-4f2a-aec4-f27a369d3b31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944287006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.2944287006
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2077043369
Short name T313
Test name
Test status
Simulation time 29672504603 ps
CPU time 26.33 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:35 PM PDT 24
Peak memory 581288 kb
Host smart-746585ef-fcde-4b03-b90d-a33c9371fc06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077043369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2077043369
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1003466762
Short name T477
Test name
Test status
Simulation time 6467106238 ps
CPU time 5.81 seconds
Started May 02 01:41:59 PM PDT 24
Finished May 02 01:42:06 PM PDT 24
Peak memory 204284 kb
Host smart-4e29a79c-42c5-45c2-986f-f1be857dc7f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003466762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1003466762
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3849674211
Short name T623
Test name
Test status
Simulation time 21602285 ps
CPU time 0.58 seconds
Started May 02 01:45:03 PM PDT 24
Finished May 02 01:45:04 PM PDT 24
Peak memory 203844 kb
Host smart-3e3a6b36-ddbb-4b02-a25c-f3430f78a23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849674211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3849674211
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3093079105
Short name T1089
Test name
Test status
Simulation time 230835075 ps
CPU time 1.47 seconds
Started May 02 01:44:57 PM PDT 24
Finished May 02 01:45:00 PM PDT 24
Peak memory 212468 kb
Host smart-6f09483e-8b8b-4fd1-b1b8-cda488f7347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093079105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3093079105
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1339613203
Short name T415
Test name
Test status
Simulation time 2281433799 ps
CPU time 7.04 seconds
Started May 02 01:44:49 PM PDT 24
Finished May 02 01:44:56 PM PDT 24
Peak memory 266752 kb
Host smart-4e31f2fe-7805-490a-b958-b1a83b1fcee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339613203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1339613203
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1662386887
Short name T849
Test name
Test status
Simulation time 9258729893 ps
CPU time 175.06 seconds
Started May 02 01:44:58 PM PDT 24
Finished May 02 01:47:55 PM PDT 24
Peak memory 779920 kb
Host smart-63a6d44a-129b-489e-8e92-3598ce132a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662386887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1662386887
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.527035841
Short name T608
Test name
Test status
Simulation time 5588490199 ps
CPU time 93.03 seconds
Started May 02 01:44:49 PM PDT 24
Finished May 02 01:46:22 PM PDT 24
Peak memory 467200 kb
Host smart-bd14edc3-c14a-4d96-b607-2627227bbb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527035841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.527035841
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2944012505
Short name T1002
Test name
Test status
Simulation time 479776953 ps
CPU time 2.94 seconds
Started May 02 01:44:50 PM PDT 24
Finished May 02 01:44:54 PM PDT 24
Peak memory 204236 kb
Host smart-b20bf061-4227-4a44-a485-27dbea6ee90c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944012505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2944012505
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3321688149
Short name T1091
Test name
Test status
Simulation time 10472937318 ps
CPU time 72.07 seconds
Started May 02 01:44:50 PM PDT 24
Finished May 02 01:46:03 PM PDT 24
Peak memory 854584 kb
Host smart-1ce86c12-c12d-4e70-a09b-7cc2dd814ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321688149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3321688149
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.1953212712
Short name T935
Test name
Test status
Simulation time 460820645 ps
CPU time 7.17 seconds
Started May 02 01:45:05 PM PDT 24
Finished May 02 01:45:13 PM PDT 24
Peak memory 204200 kb
Host smart-c11326c2-515c-4f06-b4bc-6f44b6a69e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953212712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1953212712
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2719299804
Short name T369
Test name
Test status
Simulation time 5268020389 ps
CPU time 67.94 seconds
Started May 02 01:45:05 PM PDT 24
Finished May 02 01:46:14 PM PDT 24
Peak memory 346388 kb
Host smart-1631e4e5-85c7-4e51-8212-29941a7cfdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719299804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2719299804
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.560766011
Short name T551
Test name
Test status
Simulation time 20959342 ps
CPU time 0.67 seconds
Started May 02 01:44:52 PM PDT 24
Finished May 02 01:44:53 PM PDT 24
Peak memory 203748 kb
Host smart-cac1f7a3-72fc-4ed3-895a-edf2affb9db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560766011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.560766011
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.567880746
Short name T1294
Test name
Test status
Simulation time 5126931228 ps
CPU time 58.07 seconds
Started May 02 01:44:57 PM PDT 24
Finished May 02 01:45:57 PM PDT 24
Peak memory 204248 kb
Host smart-a50ca2a6-38b9-4622-9272-f57e82a645e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567880746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.567880746
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.904372352
Short name T824
Test name
Test status
Simulation time 2761694692 ps
CPU time 28.33 seconds
Started May 02 01:44:50 PM PDT 24
Finished May 02 01:45:19 PM PDT 24
Peak memory 365112 kb
Host smart-f2af8dc8-e133-417c-a5d2-5cb9e3ef9bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904372352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.904372352
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1483483336
Short name T243
Test name
Test status
Simulation time 41086271611 ps
CPU time 2312.38 seconds
Started May 02 01:44:58 PM PDT 24
Finished May 02 02:23:32 PM PDT 24
Peak memory 2759208 kb
Host smart-ff1dac92-b639-4bdc-b677-e6873f562a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483483336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1483483336
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3430224936
Short name T1122
Test name
Test status
Simulation time 1307688481 ps
CPU time 29.23 seconds
Started May 02 01:44:58 PM PDT 24
Finished May 02 01:45:28 PM PDT 24
Peak memory 212256 kb
Host smart-d2dd170a-b823-41f7-93d3-05735281e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430224936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3430224936
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.4078161115
Short name T677
Test name
Test status
Simulation time 1140860485 ps
CPU time 2.83 seconds
Started May 02 01:44:56 PM PDT 24
Finished May 02 01:45:00 PM PDT 24
Peak memory 204184 kb
Host smart-1a51456e-130f-47d2-861b-e8f6d62ccbd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078161115 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.4078161115
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2931093097
Short name T809
Test name
Test status
Simulation time 10312512755 ps
CPU time 14.8 seconds
Started May 02 01:44:59 PM PDT 24
Finished May 02 01:45:15 PM PDT 24
Peak memory 258276 kb
Host smart-8e8eaeef-b7fa-4c61-b6ca-1bfd2f29cc2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931093097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2931093097
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.216161017
Short name T1303
Test name
Test status
Simulation time 10053066111 ps
CPU time 66.4 seconds
Started May 02 01:44:58 PM PDT 24
Finished May 02 01:46:06 PM PDT 24
Peak memory 475712 kb
Host smart-645553c2-2c4f-487a-8fa1-0f8c6e3d3676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216161017 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.216161017
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3566721910
Short name T1012
Test name
Test status
Simulation time 393287931 ps
CPU time 2.52 seconds
Started May 02 01:44:58 PM PDT 24
Finished May 02 01:45:02 PM PDT 24
Peak memory 204216 kb
Host smart-56988696-0fc4-45e5-bae6-ebacbdb8fdc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566721910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3566721910
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2073674061
Short name T558
Test name
Test status
Simulation time 3329452619 ps
CPU time 4.68 seconds
Started May 02 01:44:59 PM PDT 24
Finished May 02 01:45:05 PM PDT 24
Peak memory 212476 kb
Host smart-516e5b6e-9e0b-4391-afa1-d3591cbfdb8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073674061 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2073674061
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.1866816306
Short name T1259
Test name
Test status
Simulation time 17533591201 ps
CPU time 231.01 seconds
Started May 02 01:44:58 PM PDT 24
Finished May 02 01:48:50 PM PDT 24
Peak memory 2761740 kb
Host smart-99e71287-0cd0-423f-8ff3-3ad3419c3901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866816306 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.1866816306
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3769880598
Short name T100
Test name
Test status
Simulation time 867265581 ps
CPU time 12.72 seconds
Started May 02 01:44:59 PM PDT 24
Finished May 02 01:45:13 PM PDT 24
Peak memory 204100 kb
Host smart-61d8dd98-06d8-4959-8f7d-6a9e4cf80fb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769880598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3769880598
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1259003996
Short name T1135
Test name
Test status
Simulation time 2903272113 ps
CPU time 11.4 seconds
Started May 02 01:45:00 PM PDT 24
Finished May 02 01:45:12 PM PDT 24
Peak memory 212364 kb
Host smart-2b86357d-6837-41e9-a5a5-951b5978512e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259003996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1259003996
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2336073603
Short name T1094
Test name
Test status
Simulation time 61288047009 ps
CPU time 607.11 seconds
Started May 02 01:44:57 PM PDT 24
Finished May 02 01:55:06 PM PDT 24
Peak memory 5042792 kb
Host smart-1ead5dc0-5cb6-4d07-9688-7bd30eca7c5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336073603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2336073603
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3462464765
Short name T1092
Test name
Test status
Simulation time 22306871098 ps
CPU time 509.6 seconds
Started May 02 01:44:57 PM PDT 24
Finished May 02 01:53:28 PM PDT 24
Peak memory 2728932 kb
Host smart-ec1f02e4-7d59-4ed2-b66b-b3c4f5a74eab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462464765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3462464765
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.418965867
Short name T1043
Test name
Test status
Simulation time 1595571836 ps
CPU time 6.84 seconds
Started May 02 01:45:00 PM PDT 24
Finished May 02 01:45:08 PM PDT 24
Peak memory 218976 kb
Host smart-144665c4-bd4c-4e14-904d-f1a0c809a434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418965867 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.418965867
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3071924749
Short name T1232
Test name
Test status
Simulation time 16141229 ps
CPU time 0.62 seconds
Started May 02 01:45:14 PM PDT 24
Finished May 02 01:45:16 PM PDT 24
Peak memory 203876 kb
Host smart-8f764a18-8389-475e-8de7-1d4ff1646266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071924749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3071924749
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1651025086
Short name T692
Test name
Test status
Simulation time 75149297 ps
CPU time 1.59 seconds
Started May 02 01:45:07 PM PDT 24
Finished May 02 01:45:10 PM PDT 24
Peak memory 212460 kb
Host smart-1ff49f6f-e5fc-4952-a64e-2d3555574154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651025086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1651025086
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2972360076
Short name T886
Test name
Test status
Simulation time 1200820512 ps
CPU time 6.24 seconds
Started May 02 01:45:06 PM PDT 24
Finished May 02 01:45:14 PM PDT 24
Peak memory 257588 kb
Host smart-2f8134be-9985-4159-9234-1ddcf11d96a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972360076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2972360076
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1863286835
Short name T656
Test name
Test status
Simulation time 1494979073 ps
CPU time 98.27 seconds
Started May 02 01:45:05 PM PDT 24
Finished May 02 01:46:44 PM PDT 24
Peak memory 568284 kb
Host smart-580f2765-affa-417c-977d-460eaaf605e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863286835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1863286835
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3748129566
Short name T1226
Test name
Test status
Simulation time 1467355485 ps
CPU time 97.98 seconds
Started May 02 01:45:06 PM PDT 24
Finished May 02 01:46:45 PM PDT 24
Peak memory 525212 kb
Host smart-e6fd3d8b-8da8-4383-8473-91dc3a7a9972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748129566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3748129566
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1385560531
Short name T1147
Test name
Test status
Simulation time 83518976 ps
CPU time 0.85 seconds
Started May 02 01:45:06 PM PDT 24
Finished May 02 01:45:08 PM PDT 24
Peak memory 203996 kb
Host smart-c401f182-33df-4cd8-9b9f-73415409f4b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385560531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1385560531
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3119951369
Short name T1282
Test name
Test status
Simulation time 486659615 ps
CPU time 6.88 seconds
Started May 02 01:45:06 PM PDT 24
Finished May 02 01:45:14 PM PDT 24
Peak memory 204108 kb
Host smart-4fc7c1a6-dc99-4e40-9507-d1798632e9e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119951369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3119951369
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2221899671
Short name T1346
Test name
Test status
Simulation time 19129695438 ps
CPU time 133.24 seconds
Started May 02 01:45:07 PM PDT 24
Finished May 02 01:47:22 PM PDT 24
Peak memory 1393980 kb
Host smart-1ac875d7-3495-4725-a0a3-1f429e016172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221899671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2221899671
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2291294522
Short name T896
Test name
Test status
Simulation time 2518603000 ps
CPU time 12.51 seconds
Started May 02 01:45:11 PM PDT 24
Finished May 02 01:45:25 PM PDT 24
Peak memory 204228 kb
Host smart-54ba191d-2891-44b2-99d9-e5dbdde99eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291294522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2291294522
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.327436721
Short name T439
Test name
Test status
Simulation time 4783681763 ps
CPU time 25.09 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:45:39 PM PDT 24
Peak memory 360448 kb
Host smart-f6c289b8-7e7a-46de-b6f6-bb6fc281d874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327436721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.327436721
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1860812226
Short name T882
Test name
Test status
Simulation time 113115435 ps
CPU time 0.68 seconds
Started May 02 01:45:07 PM PDT 24
Finished May 02 01:45:09 PM PDT 24
Peak memory 203832 kb
Host smart-692a3c4b-b863-4de5-8851-c351c4039e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860812226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1860812226
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3099613977
Short name T642
Test name
Test status
Simulation time 1278034349 ps
CPU time 23.06 seconds
Started May 02 01:45:06 PM PDT 24
Finished May 02 01:45:30 PM PDT 24
Peak memory 333844 kb
Host smart-4f60c75d-e474-4c62-8602-3d5f3ed48481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099613977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3099613977
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2045078664
Short name T722
Test name
Test status
Simulation time 933723029 ps
CPU time 21.06 seconds
Started May 02 01:45:16 PM PDT 24
Finished May 02 01:45:37 PM PDT 24
Peak memory 212360 kb
Host smart-f30517c2-b551-457d-a111-cd3913a84f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045078664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2045078664
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2157525322
Short name T1042
Test name
Test status
Simulation time 1010027463 ps
CPU time 4.77 seconds
Started May 02 01:45:17 PM PDT 24
Finished May 02 01:45:22 PM PDT 24
Peak memory 212360 kb
Host smart-c83939af-7ad1-43c7-87d3-1e99aeedf77a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157525322 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2157525322
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1460649926
Short name T54
Test name
Test status
Simulation time 10204116262 ps
CPU time 21.51 seconds
Started May 02 01:45:11 PM PDT 24
Finished May 02 01:45:34 PM PDT 24
Peak memory 307144 kb
Host smart-23137b9b-d72e-49c7-88df-48f6cfe57bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460649926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1460649926
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1041498962
Short name T664
Test name
Test status
Simulation time 10202414811 ps
CPU time 13.57 seconds
Started May 02 01:45:12 PM PDT 24
Finished May 02 01:45:26 PM PDT 24
Peak memory 281140 kb
Host smart-6ee13f0d-b6d9-42f6-9042-f780f93a8d40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041498962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1041498962
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.680121114
Short name T278
Test name
Test status
Simulation time 682097895 ps
CPU time 2.08 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:45:17 PM PDT 24
Peak memory 204160 kb
Host smart-8b0a3a6b-280c-4363-a79a-84981cb5654c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680121114 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.680121114
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.486591583
Short name T829
Test name
Test status
Simulation time 2457802651 ps
CPU time 5.57 seconds
Started May 02 01:45:05 PM PDT 24
Finished May 02 01:45:11 PM PDT 24
Peak memory 218116 kb
Host smart-7558ee4c-6db4-4e27-a721-d2e014f82d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486591583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.486591583
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1486018968
Short name T708
Test name
Test status
Simulation time 10903349721 ps
CPU time 25.16 seconds
Started May 02 01:45:07 PM PDT 24
Finished May 02 01:45:34 PM PDT 24
Peak memory 584800 kb
Host smart-b0b87949-f3ea-4990-ba47-93736cbecf98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486018968 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1486018968
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3594362395
Short name T528
Test name
Test status
Simulation time 1466840114 ps
CPU time 14.87 seconds
Started May 02 01:45:06 PM PDT 24
Finished May 02 01:45:22 PM PDT 24
Peak memory 204212 kb
Host smart-474147bf-7774-4de8-9394-1810c60d3d1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594362395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3594362395
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.815759231
Short name T1154
Test name
Test status
Simulation time 1487460054 ps
CPU time 21.81 seconds
Started May 02 01:45:08 PM PDT 24
Finished May 02 01:45:31 PM PDT 24
Peak memory 231372 kb
Host smart-8409ec0b-d9fa-4be3-87d8-a2680bad9fc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815759231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.815759231
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3027610676
Short name T1231
Test name
Test status
Simulation time 15176767041 ps
CPU time 28.7 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:45:42 PM PDT 24
Peak memory 204208 kb
Host smart-0297e0fd-5b5f-4c8a-a481-9768b8c3ded1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027610676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3027610676
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2761872532
Short name T466
Test name
Test status
Simulation time 26749607578 ps
CPU time 480.53 seconds
Started May 02 01:45:05 PM PDT 24
Finished May 02 01:53:06 PM PDT 24
Peak memory 3155600 kb
Host smart-55b0aaa4-1123-44b3-8f9b-a9dd6224cd04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761872532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2761872532
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.752983952
Short name T569
Test name
Test status
Simulation time 6224695860 ps
CPU time 7.88 seconds
Started May 02 01:45:08 PM PDT 24
Finished May 02 01:45:17 PM PDT 24
Peak memory 219564 kb
Host smart-4f7a72cd-9cd8-4816-b954-42d6e740254c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752983952 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.752983952
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.122089517
Short name T1331
Test name
Test status
Simulation time 20871344 ps
CPU time 0.64 seconds
Started May 02 01:45:25 PM PDT 24
Finished May 02 01:45:26 PM PDT 24
Peak memory 203900 kb
Host smart-7293f258-2c55-426e-9466-766cae8ec64f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122089517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.122089517
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1690899056
Short name T524
Test name
Test status
Simulation time 386231166 ps
CPU time 2.07 seconds
Started May 02 01:45:14 PM PDT 24
Finished May 02 01:45:17 PM PDT 24
Peak memory 212452 kb
Host smart-189497b1-1e01-49f5-ac9d-d523f3dce960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690899056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1690899056
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1798272702
Short name T565
Test name
Test status
Simulation time 1863857590 ps
CPU time 8.27 seconds
Started May 02 01:45:12 PM PDT 24
Finished May 02 01:45:21 PM PDT 24
Peak memory 281480 kb
Host smart-414b8868-ef37-4efd-bd8f-da4878a0f317
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798272702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1798272702
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3199758634
Short name T797
Test name
Test status
Simulation time 1845460079 ps
CPU time 125.36 seconds
Started May 02 01:45:18 PM PDT 24
Finished May 02 01:47:24 PM PDT 24
Peak memory 648796 kb
Host smart-db154c1e-5f33-4bb0-b214-1e2b2c55710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199758634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3199758634
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1283507409
Short name T878
Test name
Test status
Simulation time 7845246509 ps
CPU time 127.77 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:47:21 PM PDT 24
Peak memory 632816 kb
Host smart-fbaa1dff-08ee-486f-992d-c94fabbd868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283507409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1283507409
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3428375725
Short name T987
Test name
Test status
Simulation time 547616794 ps
CPU time 0.99 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:45:15 PM PDT 24
Peak memory 203980 kb
Host smart-d6963bdc-249a-450c-83fe-734e53a8bb45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428375725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3428375725
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3491556033
Short name T1035
Test name
Test status
Simulation time 180319578 ps
CPU time 5.27 seconds
Started May 02 01:45:11 PM PDT 24
Finished May 02 01:45:17 PM PDT 24
Peak memory 235812 kb
Host smart-d9b33584-c77d-450d-99fa-41d8d3ad70cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491556033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3491556033
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1172474937
Short name T713
Test name
Test status
Simulation time 6223191757 ps
CPU time 147.45 seconds
Started May 02 01:45:17 PM PDT 24
Finished May 02 01:47:46 PM PDT 24
Peak memory 1304344 kb
Host smart-a349e3ef-4719-470b-8af0-4c83ea94c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172474937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1172474937
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.183299071
Short name T1024
Test name
Test status
Simulation time 4795574413 ps
CPU time 3.97 seconds
Started May 02 01:45:22 PM PDT 24
Finished May 02 01:45:27 PM PDT 24
Peak memory 204272 kb
Host smart-4a448932-d9e2-4f3b-b68e-601778ac321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183299071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.183299071
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.629731483
Short name T684
Test name
Test status
Simulation time 1343444279 ps
CPU time 27.74 seconds
Started May 02 01:45:20 PM PDT 24
Finished May 02 01:45:48 PM PDT 24
Peak memory 346288 kb
Host smart-6fc27f45-6a71-4799-80e0-1519267ae3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629731483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.629731483
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1569959402
Short name T1322
Test name
Test status
Simulation time 112389580 ps
CPU time 0.67 seconds
Started May 02 01:45:16 PM PDT 24
Finished May 02 01:45:18 PM PDT 24
Peak memory 203864 kb
Host smart-2c7bf563-0658-4c53-8f08-77d0d7af2489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569959402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1569959402
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.280348332
Short name T75
Test name
Test status
Simulation time 2924389232 ps
CPU time 32.19 seconds
Started May 02 01:45:14 PM PDT 24
Finished May 02 01:45:47 PM PDT 24
Peak memory 228688 kb
Host smart-be4bb301-a117-416f-b4f6-f985da0d601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280348332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.280348332
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1741179837
Short name T249
Test name
Test status
Simulation time 2701466991 ps
CPU time 64.21 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:46:19 PM PDT 24
Peak memory 332372 kb
Host smart-bbddeb02-47fa-4df1-8382-7a56a318e125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741179837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1741179837
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1961971025
Short name T184
Test name
Test status
Simulation time 5699034695 ps
CPU time 208.67 seconds
Started May 02 01:45:14 PM PDT 24
Finished May 02 01:48:43 PM PDT 24
Peak memory 1169352 kb
Host smart-1d944891-7b31-4c22-8f13-21dd141ff188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961971025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1961971025
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3333373586
Short name T232
Test name
Test status
Simulation time 649714896 ps
CPU time 28.59 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:45:43 PM PDT 24
Peak memory 212304 kb
Host smart-fd4628ac-9524-4ff6-a038-b25fe42ad072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333373586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3333373586
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.4201967815
Short name T1096
Test name
Test status
Simulation time 2096058677 ps
CPU time 3.54 seconds
Started May 02 01:45:12 PM PDT 24
Finished May 02 01:45:17 PM PDT 24
Peak memory 212408 kb
Host smart-3677d713-f0dc-4c32-bb96-5638c54f9a9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201967815 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.4201967815
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1640673864
Short name T632
Test name
Test status
Simulation time 10035024278 ps
CPU time 72.58 seconds
Started May 02 01:45:17 PM PDT 24
Finished May 02 01:46:30 PM PDT 24
Peak memory 410644 kb
Host smart-9d1ae2f2-0185-462c-8705-3c70ea519c3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640673864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1640673864
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1632979616
Short name T1269
Test name
Test status
Simulation time 10139534623 ps
CPU time 68.12 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:46:22 PM PDT 24
Peak memory 468780 kb
Host smart-21f4bb4c-1a09-4949-9bb9-ebb5cfbd548c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632979616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1632979616
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2741715777
Short name T491
Test name
Test status
Simulation time 1663127802 ps
CPU time 2.56 seconds
Started May 02 01:45:14 PM PDT 24
Finished May 02 01:45:18 PM PDT 24
Peak memory 204136 kb
Host smart-cc43a09c-806b-4c22-b526-9c63bc66f3c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741715777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2741715777
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3125120184
Short name T941
Test name
Test status
Simulation time 940201393 ps
CPU time 4.45 seconds
Started May 02 01:45:14 PM PDT 24
Finished May 02 01:45:20 PM PDT 24
Peak memory 205976 kb
Host smart-7a889f16-3059-4f75-8ee0-2f3bf993947d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125120184 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3125120184
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2954095093
Short name T413
Test name
Test status
Simulation time 20207450849 ps
CPU time 57.05 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:46:12 PM PDT 24
Peak memory 1342616 kb
Host smart-4253f52d-c17d-4ab2-a47e-d9135a7b7c0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954095093 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2954095093
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.2438727533
Short name T1020
Test name
Test status
Simulation time 1529806181 ps
CPU time 10.05 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:45:24 PM PDT 24
Peak memory 204108 kb
Host smart-b913f82b-698b-471a-a844-70b78e867a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438727533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.2438727533
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1490082095
Short name T1125
Test name
Test status
Simulation time 4145592950 ps
CPU time 37.94 seconds
Started May 02 01:45:12 PM PDT 24
Finished May 02 01:45:51 PM PDT 24
Peak memory 204160 kb
Host smart-8abcff2b-3e3d-408e-b9d4-e93b042a21b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490082095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1490082095
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2579810250
Short name T776
Test name
Test status
Simulation time 38326928531 ps
CPU time 160.29 seconds
Started May 02 01:45:14 PM PDT 24
Finished May 02 01:47:55 PM PDT 24
Peak memory 2151996 kb
Host smart-63de819a-e619-465b-a963-b9c7a119d558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579810250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2579810250
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1114805477
Short name T465
Test name
Test status
Simulation time 30251385130 ps
CPU time 201.01 seconds
Started May 02 01:45:12 PM PDT 24
Finished May 02 01:48:33 PM PDT 24
Peak memory 1749600 kb
Host smart-614d993b-92b4-4f55-bb52-82a60214bffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114805477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1114805477
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.4130049635
Short name T835
Test name
Test status
Simulation time 1518788290 ps
CPU time 6.96 seconds
Started May 02 01:45:13 PM PDT 24
Finished May 02 01:45:21 PM PDT 24
Peak memory 217352 kb
Host smart-a1f05735-db17-4abe-9a90-ec40774c6689
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130049635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.4130049635
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2816860513
Short name T921
Test name
Test status
Simulation time 62905885 ps
CPU time 0.6 seconds
Started May 02 01:45:31 PM PDT 24
Finished May 02 01:45:32 PM PDT 24
Peak memory 203880 kb
Host smart-59ed927e-5d68-46f0-9815-4a28dc8e550d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816860513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2816860513
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.3153495298
Short name T1341
Test name
Test status
Simulation time 463378944 ps
CPU time 1.28 seconds
Started May 02 01:45:25 PM PDT 24
Finished May 02 01:45:27 PM PDT 24
Peak memory 212448 kb
Host smart-bcfea1ce-e633-4b78-94a7-91364c9ed449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153495298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3153495298
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2306998302
Short name T781
Test name
Test status
Simulation time 907153589 ps
CPU time 4.27 seconds
Started May 02 01:45:22 PM PDT 24
Finished May 02 01:45:27 PM PDT 24
Peak memory 238272 kb
Host smart-3c158c58-0d87-4f33-ba61-fd1eeb2338f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306998302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2306998302
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3015873559
Short name T1206
Test name
Test status
Simulation time 6539617095 ps
CPU time 140.46 seconds
Started May 02 01:45:21 PM PDT 24
Finished May 02 01:47:43 PM PDT 24
Peak memory 678032 kb
Host smart-408bddfc-54e3-4533-8d91-51b6ebdd1b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015873559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3015873559
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.421277104
Short name T529
Test name
Test status
Simulation time 6648360789 ps
CPU time 37.1 seconds
Started May 02 01:45:19 PM PDT 24
Finished May 02 01:45:57 PM PDT 24
Peak memory 503068 kb
Host smart-8bfa08ce-fbe6-405e-b4fd-05ece420b9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421277104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.421277104
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.762289114
Short name T1028
Test name
Test status
Simulation time 129083290 ps
CPU time 2.69 seconds
Started May 02 01:45:21 PM PDT 24
Finished May 02 01:45:24 PM PDT 24
Peak memory 204156 kb
Host smart-0881ddc1-a8ef-4f0c-867d-e612c668459d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762289114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
762289114
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3391858909
Short name T287
Test name
Test status
Simulation time 5261842551 ps
CPU time 245.72 seconds
Started May 02 01:45:20 PM PDT 24
Finished May 02 01:49:27 PM PDT 24
Peak memory 1042408 kb
Host smart-6571ed7b-6dda-4100-a915-d04f18f53e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391858909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3391858909
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.12881234
Short name T1196
Test name
Test status
Simulation time 997605880 ps
CPU time 3.59 seconds
Started May 02 01:45:30 PM PDT 24
Finished May 02 01:45:35 PM PDT 24
Peak memory 204064 kb
Host smart-beb37c22-05ea-4112-876a-0904e403bce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12881234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.12881234
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2347755867
Short name T511
Test name
Test status
Simulation time 914106295 ps
CPU time 13.71 seconds
Started May 02 01:45:29 PM PDT 24
Finished May 02 01:45:43 PM PDT 24
Peak memory 281256 kb
Host smart-8f6e132b-1db5-4b36-aace-8abb920c7629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347755867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2347755867
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.268896571
Short name T193
Test name
Test status
Simulation time 32036088 ps
CPU time 0.63 seconds
Started May 02 01:45:19 PM PDT 24
Finished May 02 01:45:20 PM PDT 24
Peak memory 203728 kb
Host smart-5881a04e-4845-4216-974a-21dec18c28cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268896571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.268896571
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3486696704
Short name T693
Test name
Test status
Simulation time 13106125013 ps
CPU time 93.09 seconds
Started May 02 01:45:21 PM PDT 24
Finished May 02 01:46:55 PM PDT 24
Peak memory 696748 kb
Host smart-0de39eed-eedc-4391-ae3d-4f260b6c1bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486696704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3486696704
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.726899638
Short name T1298
Test name
Test status
Simulation time 3936579264 ps
CPU time 28.06 seconds
Started May 02 01:45:22 PM PDT 24
Finished May 02 01:45:51 PM PDT 24
Peak memory 366644 kb
Host smart-21a9c6f7-c8f1-4695-b0ab-59b485b4bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726899638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.726899638
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.619204128
Short name T416
Test name
Test status
Simulation time 55502889153 ps
CPU time 617.23 seconds
Started May 02 01:45:22 PM PDT 24
Finished May 02 01:55:40 PM PDT 24
Peak memory 1978940 kb
Host smart-05139aea-2c05-4933-abb6-81c43cda2690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619204128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.619204128
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2017376886
Short name T489
Test name
Test status
Simulation time 2078588146 ps
CPU time 22.63 seconds
Started May 02 01:45:22 PM PDT 24
Finished May 02 01:45:46 PM PDT 24
Peak memory 212348 kb
Host smart-e632c1f6-0997-4798-8d8b-ca3fe1b8ea1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017376886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2017376886
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2382065006
Short name T374
Test name
Test status
Simulation time 2855342623 ps
CPU time 3.44 seconds
Started May 02 01:45:27 PM PDT 24
Finished May 02 01:45:31 PM PDT 24
Peak memory 212380 kb
Host smart-bce1b042-0b5a-4a6d-8ec5-1bed3a94e187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382065006 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2382065006
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2678360966
Short name T514
Test name
Test status
Simulation time 10193818479 ps
CPU time 12.64 seconds
Started May 02 01:45:28 PM PDT 24
Finished May 02 01:45:41 PM PDT 24
Peak memory 280052 kb
Host smart-78a38246-09bd-426e-8476-53cc5028eb4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678360966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2678360966
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.773394787
Short name T989
Test name
Test status
Simulation time 10270088851 ps
CPU time 32.46 seconds
Started May 02 01:45:28 PM PDT 24
Finished May 02 01:46:02 PM PDT 24
Peak memory 334476 kb
Host smart-2171873e-a81f-4ab9-b6f7-f57f7b55e247
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773394787 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.773394787
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1030554984
Short name T393
Test name
Test status
Simulation time 1779672613 ps
CPU time 2.42 seconds
Started May 02 01:45:30 PM PDT 24
Finished May 02 01:45:33 PM PDT 24
Peak memory 204200 kb
Host smart-20b76f96-759e-40c0-be14-5ddd32a78b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030554984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1030554984
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.738948703
Short name T427
Test name
Test status
Simulation time 21826872357 ps
CPU time 5.35 seconds
Started May 02 01:45:27 PM PDT 24
Finished May 02 01:45:34 PM PDT 24
Peak memory 220144 kb
Host smart-27a35778-1bbe-46d6-ad7c-b6889b616d97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738948703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.738948703
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3222541318
Short name T59
Test name
Test status
Simulation time 7078916368 ps
CPU time 14.66 seconds
Started May 02 01:45:30 PM PDT 24
Finished May 02 01:45:45 PM PDT 24
Peak memory 623080 kb
Host smart-eea61882-aaf1-4a12-8a86-9534f53c61ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222541318 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3222541318
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1829703222
Short name T1118
Test name
Test status
Simulation time 742706230 ps
CPU time 28.51 seconds
Started May 02 01:45:23 PM PDT 24
Finished May 02 01:45:53 PM PDT 24
Peak memory 204156 kb
Host smart-1baada29-71db-44b7-92b4-82ebb43092f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829703222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1829703222
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2104735778
Short name T219
Test name
Test status
Simulation time 7873079139 ps
CPU time 49.19 seconds
Started May 02 01:45:21 PM PDT 24
Finished May 02 01:46:12 PM PDT 24
Peak memory 204560 kb
Host smart-8fe7d4fc-c6d7-406b-bb44-6b77cf1deff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104735778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2104735778
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1612804392
Short name T974
Test name
Test status
Simulation time 35854707812 ps
CPU time 394.75 seconds
Started May 02 01:45:22 PM PDT 24
Finished May 02 01:51:58 PM PDT 24
Peak memory 4008080 kb
Host smart-748bb94b-3354-4d8c-a1ca-e671854850bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612804392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1612804392
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1942273188
Short name T290
Test name
Test status
Simulation time 4469560416 ps
CPU time 98.51 seconds
Started May 02 01:45:20 PM PDT 24
Finished May 02 01:47:00 PM PDT 24
Peak memory 579848 kb
Host smart-416b69b1-d323-494c-be75-0bf3d8712251
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942273188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1942273188
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3974719466
Short name T838
Test name
Test status
Simulation time 6099675225 ps
CPU time 6.97 seconds
Started May 02 01:45:28 PM PDT 24
Finished May 02 01:45:36 PM PDT 24
Peak memory 214732 kb
Host smart-ee660e24-2514-4cc0-a7d3-c1d44be64090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974719466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3974719466
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3688019013
Short name T869
Test name
Test status
Simulation time 39764296 ps
CPU time 0.63 seconds
Started May 02 01:45:42 PM PDT 24
Finished May 02 01:45:45 PM PDT 24
Peak memory 203868 kb
Host smart-54dc641f-449e-4975-a57d-adf537a9fb84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688019013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3688019013
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.1007901506
Short name T875
Test name
Test status
Simulation time 123860012 ps
CPU time 1.13 seconds
Started May 02 01:45:33 PM PDT 24
Finished May 02 01:45:35 PM PDT 24
Peak memory 212476 kb
Host smart-91663d99-36ae-4d2e-b8bd-9af6dc58967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007901506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.1007901506
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.643300241
Short name T1080
Test name
Test status
Simulation time 1796390974 ps
CPU time 8.35 seconds
Started May 02 01:45:29 PM PDT 24
Finished May 02 01:45:38 PM PDT 24
Peak memory 299112 kb
Host smart-bbaa50fe-f535-4dc4-b7ba-42285ed57f36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643300241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.643300241
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1958135987
Short name T1300
Test name
Test status
Simulation time 8100976931 ps
CPU time 45.4 seconds
Started May 02 01:45:30 PM PDT 24
Finished May 02 01:46:17 PM PDT 24
Peak memory 548496 kb
Host smart-71b45ab0-92ff-46ea-9530-6a27fc3b8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958135987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1958135987
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2128951899
Short name T1239
Test name
Test status
Simulation time 7972138915 ps
CPU time 73.75 seconds
Started May 02 01:45:30 PM PDT 24
Finished May 02 01:46:45 PM PDT 24
Peak memory 691444 kb
Host smart-8d171e8c-35ba-4192-9686-e0d1d1041e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128951899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2128951899
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3788428689
Short name T686
Test name
Test status
Simulation time 752390751 ps
CPU time 1.07 seconds
Started May 02 01:45:29 PM PDT 24
Finished May 02 01:45:31 PM PDT 24
Peak memory 204148 kb
Host smart-36a04120-5d8b-4992-98aa-e0e267da3e58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788428689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3788428689
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3805931213
Short name T795
Test name
Test status
Simulation time 195882228 ps
CPU time 4.04 seconds
Started May 02 01:45:30 PM PDT 24
Finished May 02 01:45:35 PM PDT 24
Peak memory 204204 kb
Host smart-fe4f2859-22c3-4f26-bf04-df4d02f7448f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805931213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3805931213
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1748704104
Short name T178
Test name
Test status
Simulation time 3166054045 ps
CPU time 72.01 seconds
Started May 02 01:45:32 PM PDT 24
Finished May 02 01:46:44 PM PDT 24
Peak memory 932320 kb
Host smart-56fe4da6-5b19-4dd7-a2f6-1aa599c48d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748704104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1748704104
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.811325713
Short name T972
Test name
Test status
Simulation time 970679259 ps
CPU time 3.97 seconds
Started May 02 01:45:35 PM PDT 24
Finished May 02 01:45:40 PM PDT 24
Peak memory 204172 kb
Host smart-5fa0f662-b2b0-45fb-9197-dd5548718f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811325713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.811325713
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3364526023
Short name T519
Test name
Test status
Simulation time 6477942680 ps
CPU time 25.15 seconds
Started May 02 01:45:40 PM PDT 24
Finished May 02 01:46:07 PM PDT 24
Peak memory 334140 kb
Host smart-1487d29c-7953-4a55-b44e-32ca8f5f1026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364526023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3364526023
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1341635988
Short name T192
Test name
Test status
Simulation time 28501398 ps
CPU time 0.68 seconds
Started May 02 01:45:35 PM PDT 24
Finished May 02 01:45:38 PM PDT 24
Peak memory 203840 kb
Host smart-1e8cc635-5817-4b1c-952c-e89d1825e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341635988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1341635988
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1379903037
Short name T1281
Test name
Test status
Simulation time 7651879890 ps
CPU time 109.83 seconds
Started May 02 01:45:32 PM PDT 24
Finished May 02 01:47:23 PM PDT 24
Peak memory 294228 kb
Host smart-a25c56c5-add4-4201-ba07-c6c96fe448dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379903037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1379903037
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.393874094
Short name T671
Test name
Test status
Simulation time 1823556275 ps
CPU time 38.68 seconds
Started May 02 01:45:29 PM PDT 24
Finished May 02 01:46:09 PM PDT 24
Peak memory 430068 kb
Host smart-61c81f3d-80a6-44b5-8b85-b782551dc09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393874094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.393874094
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.1922051296
Short name T244
Test name
Test status
Simulation time 19768501361 ps
CPU time 337.69 seconds
Started May 02 01:45:33 PM PDT 24
Finished May 02 01:51:12 PM PDT 24
Peak memory 828904 kb
Host smart-86214546-9f37-4377-b9eb-1dbb57579ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922051296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1922051296
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.81954934
Short name T1099
Test name
Test status
Simulation time 965364213 ps
CPU time 22.03 seconds
Started May 02 01:45:29 PM PDT 24
Finished May 02 01:45:52 PM PDT 24
Peak memory 212368 kb
Host smart-58f66f1f-a504-4c78-b946-6d78e43390e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81954934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.81954934
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.643559144
Short name T975
Test name
Test status
Simulation time 1309653501 ps
CPU time 3.45 seconds
Started May 02 01:45:39 PM PDT 24
Finished May 02 01:45:45 PM PDT 24
Peak memory 204204 kb
Host smart-e98a1934-7b1f-41df-b627-3b17990873e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643559144 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.643559144
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3720822770
Short name T497
Test name
Test status
Simulation time 10084123392 ps
CPU time 9.46 seconds
Started May 02 01:45:37 PM PDT 24
Finished May 02 01:45:49 PM PDT 24
Peak memory 250472 kb
Host smart-677c36e8-6933-419d-9cc8-4e62a8dad9c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720822770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3720822770
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3106147959
Short name T424
Test name
Test status
Simulation time 10403546822 ps
CPU time 14.46 seconds
Started May 02 01:45:40 PM PDT 24
Finished May 02 01:45:57 PM PDT 24
Peak memory 268676 kb
Host smart-78e1e30a-a5f5-419f-b16f-14e5373a6b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106147959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3106147959
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.3698969554
Short name T1022
Test name
Test status
Simulation time 1128899598 ps
CPU time 1.94 seconds
Started May 02 01:45:38 PM PDT 24
Finished May 02 01:45:42 PM PDT 24
Peak memory 204196 kb
Host smart-0a61c283-17ee-4662-82f5-9b179c9818de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698969554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.3698969554
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2178104259
Short name T612
Test name
Test status
Simulation time 818924257 ps
CPU time 4.16 seconds
Started May 02 01:45:37 PM PDT 24
Finished May 02 01:45:43 PM PDT 24
Peak memory 204180 kb
Host smart-43e16145-16e4-4461-8fca-5056ba364503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178104259 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2178104259
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2613089750
Short name T725
Test name
Test status
Simulation time 19758375000 ps
CPU time 4.58 seconds
Started May 02 01:45:37 PM PDT 24
Finished May 02 01:45:44 PM PDT 24
Peak memory 204220 kb
Host smart-4e7ccb91-d5df-489f-a3b7-02af6fa24bbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613089750 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2613089750
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.214798564
Short name T605
Test name
Test status
Simulation time 24971311552 ps
CPU time 25.27 seconds
Started May 02 01:45:44 PM PDT 24
Finished May 02 01:46:11 PM PDT 24
Peak memory 204200 kb
Host smart-769973b2-9b05-421f-8f5d-b34a86eb351a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214798564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.214798564
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.903102802
Short name T1149
Test name
Test status
Simulation time 22605316152 ps
CPU time 21.98 seconds
Started May 02 01:45:37 PM PDT 24
Finished May 02 01:46:01 PM PDT 24
Peak memory 218612 kb
Host smart-f10c434d-7aea-4e3c-b5da-179966d97544
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903102802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.903102802
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.2457468210
Short name T537
Test name
Test status
Simulation time 54580864554 ps
CPU time 1499.86 seconds
Started May 02 01:45:37 PM PDT 24
Finished May 02 02:10:39 PM PDT 24
Peak memory 8814952 kb
Host smart-247d05d3-4c88-4b1e-b525-78c9bef4476e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457468210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.2457468210
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.898615844
Short name T1243
Test name
Test status
Simulation time 1391035169 ps
CPU time 6.95 seconds
Started May 02 01:45:35 PM PDT 24
Finished May 02 01:45:43 PM PDT 24
Peak memory 220448 kb
Host smart-b1a681ca-4a86-4995-9613-36af1fe0eb1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898615844 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.898615844
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.742747720
Short name T1127
Test name
Test status
Simulation time 22712103 ps
CPU time 0.63 seconds
Started May 02 01:45:56 PM PDT 24
Finished May 02 01:45:58 PM PDT 24
Peak memory 203744 kb
Host smart-036ba7f9-447d-4076-89be-35221635e5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742747720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.742747720
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1788795772
Short name T1184
Test name
Test status
Simulation time 87482583 ps
CPU time 1.59 seconds
Started May 02 01:45:44 PM PDT 24
Finished May 02 01:45:47 PM PDT 24
Peak memory 212424 kb
Host smart-a5364398-cb95-414a-a72f-3b524dd43814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788795772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1788795772
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2269216538
Short name T1142
Test name
Test status
Simulation time 405724487 ps
CPU time 6.93 seconds
Started May 02 01:45:41 PM PDT 24
Finished May 02 01:45:50 PM PDT 24
Peak memory 279192 kb
Host smart-8e38ee6c-74cd-4ee5-a60e-3ecb1d8b89ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269216538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2269216538
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1781995340
Short name T1219
Test name
Test status
Simulation time 2618057065 ps
CPU time 132.01 seconds
Started May 02 01:45:42 PM PDT 24
Finished May 02 01:47:56 PM PDT 24
Peak memory 654084 kb
Host smart-68a1d314-beea-412d-a605-932948cc87e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781995340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1781995340
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2138010156
Short name T1267
Test name
Test status
Simulation time 6374175356 ps
CPU time 103.54 seconds
Started May 02 01:45:43 PM PDT 24
Finished May 02 01:47:28 PM PDT 24
Peak memory 554116 kb
Host smart-ae98d336-0bf1-4c87-bdfa-a55201690d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138010156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2138010156
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.786310027
Short name T326
Test name
Test status
Simulation time 88784482 ps
CPU time 0.9 seconds
Started May 02 01:45:46 PM PDT 24
Finished May 02 01:45:48 PM PDT 24
Peak memory 203956 kb
Host smart-bfaf5446-5035-4b20-aec5-a042d88c3732
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786310027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fm
t.786310027
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.177658623
Short name T1276
Test name
Test status
Simulation time 371258771 ps
CPU time 8.91 seconds
Started May 02 01:45:41 PM PDT 24
Finished May 02 01:45:52 PM PDT 24
Peak memory 204172 kb
Host smart-30c93c7c-982c-4533-86e2-32b9b3208746
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177658623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
177658623
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3214586044
Short name T310
Test name
Test status
Simulation time 3535619859 ps
CPU time 237.11 seconds
Started May 02 01:45:40 PM PDT 24
Finished May 02 01:49:40 PM PDT 24
Peak memory 997648 kb
Host smart-f94d52c3-634e-492f-a91d-f8c781f65870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214586044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3214586044
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.719637575
Short name T441
Test name
Test status
Simulation time 680304311 ps
CPU time 4.34 seconds
Started May 02 01:45:51 PM PDT 24
Finished May 02 01:45:56 PM PDT 24
Peak memory 204136 kb
Host smart-b2d33a79-b663-4e95-8f55-0e00a64f11c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719637575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.719637575
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2746065739
Short name T1291
Test name
Test status
Simulation time 7684551787 ps
CPU time 34.12 seconds
Started May 02 01:45:48 PM PDT 24
Finished May 02 01:46:24 PM PDT 24
Peak memory 342000 kb
Host smart-6ba5dedc-d126-426a-93ae-e366197c4af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746065739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2746065739
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.3609314953
Short name T217
Test name
Test status
Simulation time 17297928 ps
CPU time 0.61 seconds
Started May 02 01:45:39 PM PDT 24
Finished May 02 01:45:42 PM PDT 24
Peak memory 203788 kb
Host smart-14ce6812-49ac-4c1a-b4c7-2026354a2f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609314953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3609314953
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2913396207
Short name T199
Test name
Test status
Simulation time 49228883204 ps
CPU time 2010.93 seconds
Started May 02 01:45:41 PM PDT 24
Finished May 02 02:19:14 PM PDT 24
Peak memory 204272 kb
Host smart-31c3b7fb-95d3-45b9-a4fa-fa3512a96d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913396207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2913396207
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2686989095
Short name T475
Test name
Test status
Simulation time 1325073085 ps
CPU time 24.98 seconds
Started May 02 01:45:42 PM PDT 24
Finished May 02 01:46:09 PM PDT 24
Peak memory 299144 kb
Host smart-2d65efb7-11df-47e0-b1de-f5f16a44aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686989095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2686989095
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1379989309
Short name T1105
Test name
Test status
Simulation time 18224864308 ps
CPU time 323.76 seconds
Started May 02 01:45:43 PM PDT 24
Finished May 02 01:51:09 PM PDT 24
Peak memory 760100 kb
Host smart-ebfc001a-5f12-4fa0-bdc4-adde3de2cd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379989309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1379989309
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.109769825
Short name T594
Test name
Test status
Simulation time 728160530 ps
CPU time 6.09 seconds
Started May 02 01:45:41 PM PDT 24
Finished May 02 01:45:49 PM PDT 24
Peak memory 212300 kb
Host smart-a93e690b-0cd6-43a5-a5f4-0ac613c6f6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109769825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.109769825
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1231783068
Short name T1
Test name
Test status
Simulation time 795678482 ps
CPU time 3.47 seconds
Started May 02 01:45:56 PM PDT 24
Finished May 02 01:46:01 PM PDT 24
Peak memory 204172 kb
Host smart-663fede3-b8cb-4a73-9616-8483793ede8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231783068 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1231783068
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2823047423
Short name T314
Test name
Test status
Simulation time 10144395410 ps
CPU time 6.07 seconds
Started May 02 01:45:53 PM PDT 24
Finished May 02 01:46:00 PM PDT 24
Peak memory 244208 kb
Host smart-cfe23cd9-cf17-4bc8-abe5-13976d27b560
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823047423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2823047423
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.4020067245
Short name T688
Test name
Test status
Simulation time 593334044 ps
CPU time 2.02 seconds
Started May 02 01:45:49 PM PDT 24
Finished May 02 01:45:52 PM PDT 24
Peak memory 204120 kb
Host smart-4ba6a92f-cd74-430c-8176-8bcb95ca9319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020067245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.4020067245
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1921903015
Short name T739
Test name
Test status
Simulation time 3767019769 ps
CPU time 3.95 seconds
Started May 02 01:45:54 PM PDT 24
Finished May 02 01:45:59 PM PDT 24
Peak memory 204188 kb
Host smart-77b989d0-e1a0-44ef-a01c-b730716c4602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921903015 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1921903015
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.244824834
Short name T262
Test name
Test status
Simulation time 15569574549 ps
CPU time 7.98 seconds
Started May 02 01:45:48 PM PDT 24
Finished May 02 01:45:57 PM PDT 24
Peak memory 256112 kb
Host smart-6ef660fd-ef4c-48e8-92f6-b4468056f487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244824834 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.244824834
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2788817913
Short name T1138
Test name
Test status
Simulation time 1683207667 ps
CPU time 29.98 seconds
Started May 02 01:45:43 PM PDT 24
Finished May 02 01:46:15 PM PDT 24
Peak memory 204140 kb
Host smart-842a4365-acc9-4313-aedc-ab52b9b748a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788817913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2788817913
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2000588086
Short name T1171
Test name
Test status
Simulation time 5357625939 ps
CPU time 32.3 seconds
Started May 02 01:45:49 PM PDT 24
Finished May 02 01:46:22 PM PDT 24
Peak memory 204244 kb
Host smart-9e0f5ba1-498b-4189-8b1f-39b0082439d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000588086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2000588086
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.1240833469
Short name T423
Test name
Test status
Simulation time 47505264104 ps
CPU time 131.99 seconds
Started May 02 01:45:49 PM PDT 24
Finished May 02 01:48:02 PM PDT 24
Peak memory 1775364 kb
Host smart-e5618f05-a7e9-40a8-b3fd-c443b6f8bc7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240833469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.1240833469
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2336601388
Short name T406
Test name
Test status
Simulation time 24605697410 ps
CPU time 149.38 seconds
Started May 02 01:45:56 PM PDT 24
Finished May 02 01:48:27 PM PDT 24
Peak memory 1460244 kb
Host smart-4d192be4-0826-44f4-8d1e-7c055bb65fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336601388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2336601388
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2082288944
Short name T1283
Test name
Test status
Simulation time 4701756338 ps
CPU time 6.12 seconds
Started May 02 01:45:49 PM PDT 24
Finished May 02 01:45:56 PM PDT 24
Peak memory 212476 kb
Host smart-3ad4c368-8bfc-4503-9700-4a839e70c8c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082288944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2082288944
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3107960372
Short name T1249
Test name
Test status
Simulation time 29469237 ps
CPU time 0.59 seconds
Started May 02 01:46:10 PM PDT 24
Finished May 02 01:46:12 PM PDT 24
Peak memory 203884 kb
Host smart-6e51bf22-27a9-49f9-92fc-ff344b3306b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107960372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3107960372
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1899458956
Short name T1236
Test name
Test status
Simulation time 128540156 ps
CPU time 1.63 seconds
Started May 02 01:45:57 PM PDT 24
Finished May 02 01:46:00 PM PDT 24
Peak memory 212432 kb
Host smart-f72dd819-37f8-4273-a9d5-b30bc5771a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899458956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1899458956
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.4280852782
Short name T1286
Test name
Test status
Simulation time 165878168 ps
CPU time 2.17 seconds
Started May 02 01:45:57 PM PDT 24
Finished May 02 01:46:01 PM PDT 24
Peak memory 210100 kb
Host smart-e2a1772e-5e12-4e32-a8fb-c907edbd13cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280852782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.4280852782
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1742526097
Short name T463
Test name
Test status
Simulation time 2258224773 ps
CPU time 68.14 seconds
Started May 02 01:45:57 PM PDT 24
Finished May 02 01:47:07 PM PDT 24
Peak memory 676128 kb
Host smart-a20c29fe-dc8e-4d97-aa80-b36cb0ae2113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742526097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1742526097
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.565996870
Short name T1110
Test name
Test status
Simulation time 5856066881 ps
CPU time 98.82 seconds
Started May 02 01:46:00 PM PDT 24
Finished May 02 01:47:40 PM PDT 24
Peak memory 552308 kb
Host smart-9d0ae76b-13aa-4550-a69e-ab989b042bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565996870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.565996870
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2995852166
Short name T973
Test name
Test status
Simulation time 2295445849 ps
CPU time 0.97 seconds
Started May 02 01:45:59 PM PDT 24
Finished May 02 01:46:01 PM PDT 24
Peak memory 204036 kb
Host smart-c02b48d4-5596-4bf5-a07f-5bc3ac5e9115
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995852166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2995852166
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2356127589
Short name T611
Test name
Test status
Simulation time 516519719 ps
CPU time 3.93 seconds
Started May 02 01:46:00 PM PDT 24
Finished May 02 01:46:05 PM PDT 24
Peak memory 204092 kb
Host smart-b7b76df0-0d14-4e19-973c-b70b3cca0717
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356127589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2356127589
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2582445848
Short name T180
Test name
Test status
Simulation time 4620054448 ps
CPU time 114.5 seconds
Started May 02 01:45:59 PM PDT 24
Finished May 02 01:47:55 PM PDT 24
Peak memory 1233644 kb
Host smart-cb8faf8d-da27-4557-b79c-a985e6bbba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582445848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2582445848
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3095491951
Short name T823
Test name
Test status
Simulation time 2074146104 ps
CPU time 17.58 seconds
Started May 02 01:46:06 PM PDT 24
Finished May 02 01:46:24 PM PDT 24
Peak memory 204200 kb
Host smart-d63430a6-076a-482b-9df9-5c1c96029683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095491951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3095491951
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.670939798
Short name T1007
Test name
Test status
Simulation time 3560958888 ps
CPU time 86.71 seconds
Started May 02 01:46:05 PM PDT 24
Finished May 02 01:47:32 PM PDT 24
Peak memory 313224 kb
Host smart-bb68c590-5ec1-4275-9591-14816bbe7d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670939798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.670939798
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2779726029
Short name T1174
Test name
Test status
Simulation time 26185515 ps
CPU time 0.66 seconds
Started May 02 01:45:56 PM PDT 24
Finished May 02 01:45:59 PM PDT 24
Peak memory 203816 kb
Host smart-df9f47ff-6475-4c99-8590-6d6bb522372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779726029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2779726029
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1715434090
Short name T1198
Test name
Test status
Simulation time 685281912 ps
CPU time 7.88 seconds
Started May 02 01:45:58 PM PDT 24
Finished May 02 01:46:07 PM PDT 24
Peak memory 212296 kb
Host smart-1efa7844-22b6-4bf2-a7e1-23dddfdbdc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715434090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1715434090
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.374380707
Short name T636
Test name
Test status
Simulation time 2747966353 ps
CPU time 22.16 seconds
Started May 02 01:45:49 PM PDT 24
Finished May 02 01:46:12 PM PDT 24
Peak memory 330332 kb
Host smart-f6d789b0-098e-4dd9-9bd9-03b6c2b5e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374380707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.374380707
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1624458518
Short name T622
Test name
Test status
Simulation time 291040384 ps
CPU time 12.9 seconds
Started May 02 01:45:56 PM PDT 24
Finished May 02 01:46:10 PM PDT 24
Peak memory 212284 kb
Host smart-4d2ab39f-81d0-4e37-8d17-70e358223f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624458518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1624458518
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4262475428
Short name T483
Test name
Test status
Simulation time 1452324397 ps
CPU time 3.64 seconds
Started May 02 01:46:10 PM PDT 24
Finished May 02 01:46:15 PM PDT 24
Peak memory 212368 kb
Host smart-3cfa6c95-cb79-4e9d-9150-6721e024abe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262475428 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4262475428
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2735023437
Short name T545
Test name
Test status
Simulation time 10022691539 ps
CPU time 67.6 seconds
Started May 02 01:45:58 PM PDT 24
Finished May 02 01:47:07 PM PDT 24
Peak memory 439172 kb
Host smart-bdecff1f-1887-49cc-acc6-38c1616e63b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735023437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2735023437
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.803875345
Short name T482
Test name
Test status
Simulation time 10202476924 ps
CPU time 30.27 seconds
Started May 02 01:45:58 PM PDT 24
Finished May 02 01:46:29 PM PDT 24
Peak memory 376232 kb
Host smart-4cadc375-3993-4e72-9d30-efe0765dd4a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803875345 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.803875345
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2729711708
Short name T1349
Test name
Test status
Simulation time 467670010 ps
CPU time 1.66 seconds
Started May 02 01:46:06 PM PDT 24
Finished May 02 01:46:09 PM PDT 24
Peak memory 204200 kb
Host smart-b308b2ef-1c25-4d91-9688-e4ff9b445bbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729711708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2729711708
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3631155353
Short name T1023
Test name
Test status
Simulation time 4251296804 ps
CPU time 5.06 seconds
Started May 02 01:45:57 PM PDT 24
Finished May 02 01:46:04 PM PDT 24
Peak memory 214908 kb
Host smart-c6110cd4-af1c-4b95-9546-478c4d904690
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631155353 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3631155353
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.4095654452
Short name T950
Test name
Test status
Simulation time 13710320976 ps
CPU time 10.27 seconds
Started May 02 01:45:56 PM PDT 24
Finished May 02 01:46:08 PM PDT 24
Peak memory 346484 kb
Host smart-894b2d69-0840-4b48-a139-4ee6b1a1ff3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095654452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.4095654452
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.51626940
Short name T1004
Test name
Test status
Simulation time 1179208592 ps
CPU time 47.67 seconds
Started May 02 01:45:59 PM PDT 24
Finished May 02 01:46:48 PM PDT 24
Peak memory 204108 kb
Host smart-e6b6ef38-b9fd-47c1-9da9-d7bc631d7d71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51626940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_targ
et_smoke.51626940
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.473680776
Short name T256
Test name
Test status
Simulation time 893380952 ps
CPU time 39.17 seconds
Started May 02 01:45:58 PM PDT 24
Finished May 02 01:46:39 PM PDT 24
Peak memory 204176 kb
Host smart-099fd50f-42ad-492c-86d7-ceee71c15283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473680776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_rd.473680776
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.4166220467
Short name T1248
Test name
Test status
Simulation time 34933545502 ps
CPU time 140.87 seconds
Started May 02 01:45:58 PM PDT 24
Finished May 02 01:48:20 PM PDT 24
Peak memory 1971296 kb
Host smart-6045a023-ad1c-410e-b697-483f0a90995f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166220467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.4166220467
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.766342942
Short name T538
Test name
Test status
Simulation time 26156277208 ps
CPU time 591.7 seconds
Started May 02 01:46:13 PM PDT 24
Finished May 02 01:56:06 PM PDT 24
Peak memory 1643796 kb
Host smart-995ec144-cb98-427b-a0ac-46a5f405aa68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766342942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stretch.766342942
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2136936076
Short name T1106
Test name
Test status
Simulation time 5404980206 ps
CPU time 7.53 seconds
Started May 02 01:45:58 PM PDT 24
Finished May 02 01:46:07 PM PDT 24
Peak memory 220520 kb
Host smart-64965e7e-5707-41ff-ac1b-71293dd96980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136936076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2136936076
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.4153996100
Short name T508
Test name
Test status
Simulation time 42537854 ps
CPU time 0.61 seconds
Started May 02 01:46:16 PM PDT 24
Finished May 02 01:46:18 PM PDT 24
Peak memory 203916 kb
Host smart-2003d91b-ec0c-4fb9-9e27-d10bd0f5334f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153996100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.4153996100
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3869697343
Short name T410
Test name
Test status
Simulation time 443133021 ps
CPU time 1.69 seconds
Started May 02 01:46:08 PM PDT 24
Finished May 02 01:46:11 PM PDT 24
Peak memory 204160 kb
Host smart-b16fd01b-8821-4224-8435-7c75fa3aa72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869697343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3869697343
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2074304556
Short name T1001
Test name
Test status
Simulation time 1346126019 ps
CPU time 5.23 seconds
Started May 02 01:46:09 PM PDT 24
Finished May 02 01:46:15 PM PDT 24
Peak memory 241296 kb
Host smart-a72dcf08-7290-4a4d-bb9f-c950529d8ef1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074304556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2074304556
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3691939871
Short name T1218
Test name
Test status
Simulation time 5560259078 ps
CPU time 91.43 seconds
Started May 02 01:46:08 PM PDT 24
Finished May 02 01:47:41 PM PDT 24
Peak memory 535312 kb
Host smart-52abb0a5-4214-44e6-b265-ba816bf10d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691939871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3691939871
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3939109305
Short name T961
Test name
Test status
Simulation time 2042902962 ps
CPU time 143.48 seconds
Started May 02 01:46:08 PM PDT 24
Finished May 02 01:48:32 PM PDT 24
Peak memory 624528 kb
Host smart-3f8cdf11-55ce-41bc-8461-2931544198f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939109305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3939109305
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3972472267
Short name T1160
Test name
Test status
Simulation time 408301467 ps
CPU time 0.96 seconds
Started May 02 01:46:09 PM PDT 24
Finished May 02 01:46:11 PM PDT 24
Peak memory 203968 kb
Host smart-ed6d6a62-47ef-4cae-ad3c-5ff819c0b9c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972472267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3972472267
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3037302004
Short name T949
Test name
Test status
Simulation time 1474365532 ps
CPU time 5.05 seconds
Started May 02 01:46:07 PM PDT 24
Finished May 02 01:46:13 PM PDT 24
Peak memory 236936 kb
Host smart-a155bef1-aac9-4da3-87d5-447e30086cf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037302004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3037302004
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2406796665
Short name T1076
Test name
Test status
Simulation time 8920737039 ps
CPU time 75.26 seconds
Started May 02 01:46:09 PM PDT 24
Finished May 02 01:47:25 PM PDT 24
Peak memory 995036 kb
Host smart-a29a2a71-c6c9-4f3d-8a91-2a173472ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406796665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2406796665
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.751225292
Short name T212
Test name
Test status
Simulation time 717318914 ps
CPU time 5.86 seconds
Started May 02 01:46:18 PM PDT 24
Finished May 02 01:46:25 PM PDT 24
Peak memory 204080 kb
Host smart-979e6384-4a4c-4a20-95d9-dff0fbecb932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751225292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.751225292
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2981135224
Short name T347
Test name
Test status
Simulation time 8121906063 ps
CPU time 42 seconds
Started May 02 01:46:16 PM PDT 24
Finished May 02 01:46:59 PM PDT 24
Peak memory 404836 kb
Host smart-98533ff0-03bb-4867-978e-0da2f618cf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981135224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2981135224
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.911334709
Short name T1119
Test name
Test status
Simulation time 121894033 ps
CPU time 0.64 seconds
Started May 02 01:46:07 PM PDT 24
Finished May 02 01:46:08 PM PDT 24
Peak memory 203848 kb
Host smart-214f7d43-606b-451a-8d5f-55cd95eae51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911334709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.911334709
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.681180655
Short name T553
Test name
Test status
Simulation time 27678065152 ps
CPU time 399.99 seconds
Started May 02 01:46:08 PM PDT 24
Finished May 02 01:52:49 PM PDT 24
Peak memory 757152 kb
Host smart-56aa58df-c642-4c09-84a3-f91a736fbb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681180655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.681180655
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.273553807
Short name T1179
Test name
Test status
Simulation time 1754678800 ps
CPU time 31.8 seconds
Started May 02 01:46:06 PM PDT 24
Finished May 02 01:46:39 PM PDT 24
Peak memory 370132 kb
Host smart-b6df31fb-a491-437a-9521-bb4457290602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273553807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.273553807
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2192004096
Short name T237
Test name
Test status
Simulation time 488575683 ps
CPU time 9.35 seconds
Started May 02 01:46:08 PM PDT 24
Finished May 02 01:46:18 PM PDT 24
Peak memory 220400 kb
Host smart-0b8bbf9d-0fd3-47c2-88b6-353a2fa530e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192004096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2192004096
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3232208622
Short name T1247
Test name
Test status
Simulation time 1610522652 ps
CPU time 3.55 seconds
Started May 02 01:46:29 PM PDT 24
Finished May 02 01:46:33 PM PDT 24
Peak memory 212352 kb
Host smart-e2df8d62-67fb-4878-a92d-b46223de2e6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232208622 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3232208622
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2223114370
Short name T883
Test name
Test status
Simulation time 10066026205 ps
CPU time 61.96 seconds
Started May 02 01:46:15 PM PDT 24
Finished May 02 01:47:18 PM PDT 24
Peak memory 497052 kb
Host smart-6c2a3a98-1fbd-446d-917f-3b01d0c024c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223114370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2223114370
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2167377792
Short name T50
Test name
Test status
Simulation time 10334504535 ps
CPU time 8.01 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:46:26 PM PDT 24
Peak memory 246220 kb
Host smart-4c265e3c-17f1-4fb9-ba05-1b22dff4d913
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167377792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2167377792
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.4106951386
Short name T817
Test name
Test status
Simulation time 1672973607 ps
CPU time 3.24 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:46:21 PM PDT 24
Peak memory 204148 kb
Host smart-e47cd7ba-0e0a-4320-9b49-20f69e5c0a85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106951386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.4106951386
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2775946188
Short name T1305
Test name
Test status
Simulation time 6118781747 ps
CPU time 5.83 seconds
Started May 02 01:46:15 PM PDT 24
Finished May 02 01:46:21 PM PDT 24
Peak memory 212352 kb
Host smart-e8981ddb-4b18-4a0a-9d57-a96c237f508c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775946188 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2775946188
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3754835157
Short name T21
Test name
Test status
Simulation time 20164748657 ps
CPU time 403.61 seconds
Started May 02 01:46:16 PM PDT 24
Finished May 02 01:53:01 PM PDT 24
Peak memory 3433312 kb
Host smart-a592c59d-43da-4ffc-b948-c4f136ef6a6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754835157 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3754835157
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2964003636
Short name T1190
Test name
Test status
Simulation time 4618091476 ps
CPU time 12.32 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:46:30 PM PDT 24
Peak memory 204164 kb
Host smart-e15fd71e-423c-4be5-8efd-58935a6a4647
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964003636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2964003636
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.847905409
Short name T126
Test name
Test status
Simulation time 1440243200 ps
CPU time 57.16 seconds
Started May 02 01:46:16 PM PDT 24
Finished May 02 01:47:15 PM PDT 24
Peak memory 206824 kb
Host smart-670d412a-fd20-4918-b7ba-04f928b0685e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847905409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.847905409
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.297905626
Short name T635
Test name
Test status
Simulation time 47506500380 ps
CPU time 325.84 seconds
Started May 02 01:46:39 PM PDT 24
Finished May 02 01:52:05 PM PDT 24
Peak memory 3424500 kb
Host smart-3ad4aea1-89c9-4a68-9402-2bab466d37ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297905626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_wr.297905626
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3256911944
Short name T877
Test name
Test status
Simulation time 1226252756 ps
CPU time 6.58 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:46:25 PM PDT 24
Peak memory 217892 kb
Host smart-eb36bee9-069e-47ee-b921-6f3bb9f44d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256911944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3256911944
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1594475343
Short name T641
Test name
Test status
Simulation time 42271824 ps
CPU time 0.6 seconds
Started May 02 01:46:25 PM PDT 24
Finished May 02 01:46:27 PM PDT 24
Peak memory 203868 kb
Host smart-007d08d7-ce81-4673-be2e-e35043326dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594475343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1594475343
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2332021696
Short name T1060
Test name
Test status
Simulation time 70598650 ps
CPU time 1.54 seconds
Started May 02 01:46:26 PM PDT 24
Finished May 02 01:46:28 PM PDT 24
Peak memory 212532 kb
Host smart-ba95c7b6-3e33-4a12-aaf4-619f94a3a814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332021696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2332021696
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3587293794
Short name T1221
Test name
Test status
Simulation time 472612566 ps
CPU time 6.42 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:46:25 PM PDT 24
Peak memory 270100 kb
Host smart-90b7f811-6d5a-4d91-9444-eeec1d18b694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587293794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3587293794
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.1855243186
Short name T542
Test name
Test status
Simulation time 1786575076 ps
CPU time 56.81 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:47:15 PM PDT 24
Peak memory 598692 kb
Host smart-ec3d8e64-7f54-4c40-98f0-1c3fdb7af1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855243186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.1855243186
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3494612703
Short name T820
Test name
Test status
Simulation time 1069874837 ps
CPU time 70.62 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:47:28 PM PDT 24
Peak memory 461344 kb
Host smart-59cc4b2c-2304-4b31-b1e6-27ffe9a2088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494612703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3494612703
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.680248581
Short name T646
Test name
Test status
Simulation time 240344328 ps
CPU time 0.81 seconds
Started May 02 01:46:15 PM PDT 24
Finished May 02 01:46:17 PM PDT 24
Peak memory 203972 kb
Host smart-e11149ae-5609-4830-b647-54032f754be8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680248581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.680248581
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2280682763
Short name T912
Test name
Test status
Simulation time 128167117 ps
CPU time 6.47 seconds
Started May 02 01:46:17 PM PDT 24
Finished May 02 01:46:24 PM PDT 24
Peak memory 204144 kb
Host smart-711e4dc4-9dd9-4509-a765-981812c86d55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280682763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2280682763
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3577129978
Short name T236
Test name
Test status
Simulation time 4210462611 ps
CPU time 116.66 seconds
Started May 02 01:46:28 PM PDT 24
Finished May 02 01:48:26 PM PDT 24
Peak memory 1252044 kb
Host smart-0f6d07f3-b88b-4ff4-820b-35e43b94551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577129978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3577129978
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2979082751
Short name T1273
Test name
Test status
Simulation time 1045367172 ps
CPU time 10.51 seconds
Started May 02 01:46:25 PM PDT 24
Finished May 02 01:46:37 PM PDT 24
Peak memory 204164 kb
Host smart-c8ada07c-f0ee-447d-b196-020c750993ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979082751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2979082751
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.891142185
Short name T76
Test name
Test status
Simulation time 6284015826 ps
CPU time 22.97 seconds
Started May 02 01:46:29 PM PDT 24
Finished May 02 01:46:53 PM PDT 24
Peak memory 317912 kb
Host smart-e6d4079f-f315-41f7-b019-859f342f7699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891142185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.891142185
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1907865292
Short name T450
Test name
Test status
Simulation time 78290614 ps
CPU time 0.64 seconds
Started May 02 01:46:16 PM PDT 24
Finished May 02 01:46:18 PM PDT 24
Peak memory 203800 kb
Host smart-12bdfa05-ac99-4339-8707-fe0ee732388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907865292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1907865292
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2016394857
Short name T924
Test name
Test status
Simulation time 3358800893 ps
CPU time 15.1 seconds
Started May 02 01:46:18 PM PDT 24
Finished May 02 01:46:34 PM PDT 24
Peak memory 227512 kb
Host smart-4ae8199d-c82b-420c-8d37-a356ce7c16a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016394857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2016394857
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1594256800
Short name T361
Test name
Test status
Simulation time 4806036868 ps
CPU time 25.38 seconds
Started May 02 01:46:16 PM PDT 24
Finished May 02 01:46:42 PM PDT 24
Peak memory 364308 kb
Host smart-988e463f-143c-423b-99e9-34ce78644074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594256800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1594256800
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3832103206
Short name T1301
Test name
Test status
Simulation time 93476125414 ps
CPU time 154.73 seconds
Started May 02 01:46:26 PM PDT 24
Finished May 02 01:49:02 PM PDT 24
Peak memory 710308 kb
Host smart-8ce843ea-7908-4a25-9723-81f9efca04c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832103206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3832103206
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3531665177
Short name T1063
Test name
Test status
Simulation time 1492727527 ps
CPU time 26.12 seconds
Started May 02 01:46:18 PM PDT 24
Finished May 02 01:46:45 PM PDT 24
Peak memory 212324 kb
Host smart-28f52d4d-75e0-4895-89ac-71c886eab6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531665177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3531665177
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.4094508584
Short name T802
Test name
Test status
Simulation time 467361057 ps
CPU time 2.61 seconds
Started May 02 01:46:27 PM PDT 24
Finished May 02 01:46:31 PM PDT 24
Peak memory 204192 kb
Host smart-09868cc1-98e1-47e0-9d0c-a50da7f6693f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094508584 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.4094508584
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3225530128
Short name T714
Test name
Test status
Simulation time 10299180206 ps
CPU time 12.71 seconds
Started May 02 01:46:28 PM PDT 24
Finished May 02 01:46:42 PM PDT 24
Peak memory 253728 kb
Host smart-ae7b5f1c-a9d2-4892-964a-e4c8eb1320eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225530128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3225530128
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1779096908
Short name T1313
Test name
Test status
Simulation time 10474977902 ps
CPU time 13.56 seconds
Started May 02 01:46:28 PM PDT 24
Finished May 02 01:46:43 PM PDT 24
Peak memory 264600 kb
Host smart-0efe0eec-20ac-455f-8ee0-31e4845b8b22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779096908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1779096908
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.677779492
Short name T1130
Test name
Test status
Simulation time 379131646 ps
CPU time 2.35 seconds
Started May 02 01:46:27 PM PDT 24
Finished May 02 01:46:31 PM PDT 24
Peak memory 204196 kb
Host smart-305c650a-be34-43ce-911d-b26c0fd1a5b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677779492 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_hrst.677779492
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1044928281
Short name T760
Test name
Test status
Simulation time 1160769401 ps
CPU time 5.43 seconds
Started May 02 01:46:26 PM PDT 24
Finished May 02 01:46:32 PM PDT 24
Peak memory 204160 kb
Host smart-55136394-9bd3-412e-998d-00f22dc245bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044928281 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1044928281
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2490914503
Short name T681
Test name
Test status
Simulation time 16605307594 ps
CPU time 167.84 seconds
Started May 02 01:46:26 PM PDT 24
Finished May 02 01:49:14 PM PDT 24
Peak memory 2448556 kb
Host smart-49df2f8c-6142-4a06-87f1-5d01ed787ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490914503 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2490914503
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.602491156
Short name T643
Test name
Test status
Simulation time 4769206083 ps
CPU time 15.43 seconds
Started May 02 01:46:27 PM PDT 24
Finished May 02 01:46:44 PM PDT 24
Peak memory 204224 kb
Host smart-b97d894b-36b1-4d95-a14c-5947da3993bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602491156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.602491156
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.4192650147
Short name T1310
Test name
Test status
Simulation time 3914404929 ps
CPU time 11.41 seconds
Started May 02 01:46:25 PM PDT 24
Finished May 02 01:46:37 PM PDT 24
Peak memory 209108 kb
Host smart-4ae220c4-20a7-4d5f-9c4d-89fd12777ee7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192650147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.4192650147
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.331999327
Short name T732
Test name
Test status
Simulation time 22794502831 ps
CPU time 12.31 seconds
Started May 02 01:46:27 PM PDT 24
Finished May 02 01:46:40 PM PDT 24
Peak memory 204192 kb
Host smart-3c235a8d-8c40-40db-8116-c59c96b920b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331999327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_wr.331999327
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3875131466
Short name T914
Test name
Test status
Simulation time 7696205092 ps
CPU time 39.13 seconds
Started May 02 01:46:27 PM PDT 24
Finished May 02 01:47:08 PM PDT 24
Peak memory 601424 kb
Host smart-92c49be5-efbe-44bc-b0fd-26c768e31883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875131466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3875131466
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.839936434
Short name T1037
Test name
Test status
Simulation time 1250480049 ps
CPU time 6.77 seconds
Started May 02 01:46:27 PM PDT 24
Finished May 02 01:46:35 PM PDT 24
Peak memory 220468 kb
Host smart-b4f417ea-94bd-430f-b32b-73c5fc793828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839936434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.839936434
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3787879054
Short name T356
Test name
Test status
Simulation time 28207616 ps
CPU time 0.63 seconds
Started May 02 01:46:46 PM PDT 24
Finished May 02 01:46:47 PM PDT 24
Peak memory 203916 kb
Host smart-645e4288-fb47-4abf-aad2-dceaf8178aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787879054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3787879054
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3411764083
Short name T1056
Test name
Test status
Simulation time 92149076 ps
CPU time 1.37 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:46:38 PM PDT 24
Peak memory 212504 kb
Host smart-cae53a20-0404-4c39-915e-5f51d66568ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411764083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3411764083
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3243554255
Short name T253
Test name
Test status
Simulation time 806205135 ps
CPU time 10.55 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:46:48 PM PDT 24
Peak memory 245556 kb
Host smart-d107ac7f-5b14-4077-a501-1a4a98182fb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243554255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3243554255
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2744350608
Short name T430
Test name
Test status
Simulation time 7078969872 ps
CPU time 30.5 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:47:07 PM PDT 24
Peak memory 361944 kb
Host smart-53260447-6336-4474-ad39-1127f6d64a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744350608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2744350608
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2043169936
Short name T520
Test name
Test status
Simulation time 4966098798 ps
CPU time 98.7 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:48:16 PM PDT 24
Peak memory 519480 kb
Host smart-9ca5374d-adba-4a2e-b37d-837307cd8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043169936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2043169936
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.80622880
Short name T932
Test name
Test status
Simulation time 207878157 ps
CPU time 0.89 seconds
Started May 02 01:46:35 PM PDT 24
Finished May 02 01:46:37 PM PDT 24
Peak memory 203968 kb
Host smart-f76c9f06-5916-423a-b837-e03532bb732c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80622880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt
.80622880
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2447375742
Short name T766
Test name
Test status
Simulation time 374981934 ps
CPU time 5.22 seconds
Started May 02 01:46:35 PM PDT 24
Finished May 02 01:46:40 PM PDT 24
Peak memory 217676 kb
Host smart-4da381ea-f50a-4c34-add3-b8d4071eb071
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447375742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2447375742
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.221740615
Short name T779
Test name
Test status
Simulation time 2355989028 ps
CPU time 124.64 seconds
Started May 02 01:46:38 PM PDT 24
Finished May 02 01:48:43 PM PDT 24
Peak memory 663648 kb
Host smart-78ff0143-1dcc-407d-a6f1-76111f1bfecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221740615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.221740615
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.4216077587
Short name T1265
Test name
Test status
Simulation time 1062021599 ps
CPU time 22.05 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:46:59 PM PDT 24
Peak memory 204188 kb
Host smart-ca5f7da0-4a38-423c-9aab-3025b0aaff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216077587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.4216077587
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2977087781
Short name T800
Test name
Test status
Simulation time 1092122025 ps
CPU time 18.93 seconds
Started May 02 01:46:37 PM PDT 24
Finished May 02 01:46:57 PM PDT 24
Peak memory 294312 kb
Host smart-54f1477e-b319-42e7-b1c9-af5e3ef03f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977087781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2977087781
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1101172682
Short name T1242
Test name
Test status
Simulation time 87633989 ps
CPU time 0.65 seconds
Started May 02 01:46:27 PM PDT 24
Finished May 02 01:46:29 PM PDT 24
Peak memory 203840 kb
Host smart-1ebbd254-9933-47d8-bacb-e9ba97c484c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101172682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1101172682
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.647464672
Short name T425
Test name
Test status
Simulation time 12581560636 ps
CPU time 479.5 seconds
Started May 02 01:46:37 PM PDT 24
Finished May 02 01:54:38 PM PDT 24
Peak memory 971236 kb
Host smart-3e0fa24f-d838-4e69-a20e-331722252980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647464672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.647464672
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3675791051
Short name T1340
Test name
Test status
Simulation time 1073975409 ps
CPU time 20.61 seconds
Started May 02 01:46:26 PM PDT 24
Finished May 02 01:46:47 PM PDT 24
Peak memory 293524 kb
Host smart-640bfd28-13b0-4573-8393-4aeb8e3f5490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675791051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3675791051
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2259126683
Short name T185
Test name
Test status
Simulation time 14999221504 ps
CPU time 482.86 seconds
Started May 02 01:46:35 PM PDT 24
Finished May 02 01:54:38 PM PDT 24
Peak memory 1730192 kb
Host smart-ed68af24-bdd7-4cfe-b7d1-6feda375bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259126683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2259126683
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.4243689803
Short name T572
Test name
Test status
Simulation time 578554302 ps
CPU time 25.26 seconds
Started May 02 01:46:35 PM PDT 24
Finished May 02 01:47:01 PM PDT 24
Peak memory 212364 kb
Host smart-5b332ef6-290d-4ccf-91c7-90629f877e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243689803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.4243689803
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3717413224
Short name T259
Test name
Test status
Simulation time 649246526 ps
CPU time 3.64 seconds
Started May 02 01:46:37 PM PDT 24
Finished May 02 01:46:41 PM PDT 24
Peak memory 212372 kb
Host smart-929cba8f-2a96-407f-84ed-6bc70ff2d70c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717413224 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3717413224
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3593064706
Short name T597
Test name
Test status
Simulation time 10107797900 ps
CPU time 66.36 seconds
Started May 02 01:46:37 PM PDT 24
Finished May 02 01:47:44 PM PDT 24
Peak memory 449128 kb
Host smart-7b436467-461f-426a-a9d9-1d737894c7b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593064706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3593064706
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.909349894
Short name T1193
Test name
Test status
Simulation time 10040619622 ps
CPU time 90.43 seconds
Started May 02 01:46:38 PM PDT 24
Finished May 02 01:48:09 PM PDT 24
Peak memory 541024 kb
Host smart-6c8a00ea-0e64-4280-9c0a-cc1438b22717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909349894 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.909349894
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.422524583
Short name T362
Test name
Test status
Simulation time 903698541 ps
CPU time 2.18 seconds
Started May 02 01:46:34 PM PDT 24
Finished May 02 01:46:37 PM PDT 24
Peak memory 204088 kb
Host smart-ebf1a6a5-d6c8-4d39-8e3f-89fd43095b25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422524583 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.422524583
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3781834844
Short name T395
Test name
Test status
Simulation time 1241314712 ps
CPU time 5.77 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:46:42 PM PDT 24
Peak memory 217292 kb
Host smart-764f0fc6-4cb3-4f89-8bbb-64f03576f85e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781834844 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3781834844
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3220294232
Short name T1044
Test name
Test status
Simulation time 17762235309 ps
CPU time 32.55 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:47:10 PM PDT 24
Peak memory 673032 kb
Host smart-94403d3e-3c4f-4653-a175-cf51e4e3d58d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220294232 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3220294232
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.836798329
Short name T1195
Test name
Test status
Simulation time 1090855458 ps
CPU time 18.47 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:46:56 PM PDT 24
Peak memory 204108 kb
Host smart-a0d004af-6242-43b7-889b-e1cf46a6eeb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836798329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.836798329
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1011286407
Short name T431
Test name
Test status
Simulation time 1567496442 ps
CPU time 31.3 seconds
Started May 02 01:46:36 PM PDT 24
Finished May 02 01:47:08 PM PDT 24
Peak memory 204036 kb
Host smart-5549c297-838f-4eb2-9619-c81201d3f1f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011286407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1011286407
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2604807411
Short name T357
Test name
Test status
Simulation time 50179143459 ps
CPU time 155.21 seconds
Started May 02 01:46:38 PM PDT 24
Finished May 02 01:49:14 PM PDT 24
Peak memory 1863564 kb
Host smart-e00aaaaf-f012-4b12-8cc5-fda21da70e46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604807411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2604807411
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.22149846
Short name T279
Test name
Test status
Simulation time 9244058718 ps
CPU time 275.82 seconds
Started May 02 01:46:37 PM PDT 24
Finished May 02 01:51:14 PM PDT 24
Peak memory 2000136 kb
Host smart-0e4b1040-773d-4222-acb7-b27f7b059e6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22149846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_stretch.22149846
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3672096030
Short name T339
Test name
Test status
Simulation time 1931458842 ps
CPU time 6.88 seconds
Started May 02 01:46:35 PM PDT 24
Finished May 02 01:46:43 PM PDT 24
Peak memory 220464 kb
Host smart-6697d978-bd40-4cee-813a-debf1d6b6436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672096030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3672096030
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2151739881
Short name T969
Test name
Test status
Simulation time 41323729 ps
CPU time 0.6 seconds
Started May 02 01:42:16 PM PDT 24
Finished May 02 01:42:17 PM PDT 24
Peak memory 203876 kb
Host smart-1157e858-cfc8-46da-919e-5916796379eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151739881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2151739881
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3325474672
Short name T62
Test name
Test status
Simulation time 245464521 ps
CPU time 1.28 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:10 PM PDT 24
Peak memory 212388 kb
Host smart-ffec2c1e-b604-4e2b-a7b2-a4c9a89914a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325474672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3325474672
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.677800612
Short name T447
Test name
Test status
Simulation time 558905371 ps
CPU time 5.67 seconds
Started May 02 01:42:03 PM PDT 24
Finished May 02 01:42:10 PM PDT 24
Peak memory 264948 kb
Host smart-b6f497ab-48f5-47a5-8ebe-884db9562cc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677800612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.677800612
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2430983269
Short name T44
Test name
Test status
Simulation time 10402497750 ps
CPU time 131.01 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:44:17 PM PDT 24
Peak memory 643344 kb
Host smart-4c53599c-11cc-43df-b15b-41906f205d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430983269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2430983269
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.188488334
Short name T613
Test name
Test status
Simulation time 5103216014 ps
CPU time 45.19 seconds
Started May 02 01:42:07 PM PDT 24
Finished May 02 01:42:53 PM PDT 24
Peak memory 545684 kb
Host smart-d88d65bb-fd87-460f-b18e-0696cb0883f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188488334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.188488334
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3272944480
Short name T79
Test name
Test status
Simulation time 138555597 ps
CPU time 1.01 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:42:07 PM PDT 24
Peak memory 203984 kb
Host smart-a4913cb6-cdf3-4c67-b57c-578277053061
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272944480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3272944480
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3618777582
Short name T204
Test name
Test status
Simulation time 570285960 ps
CPU time 7.88 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:42:13 PM PDT 24
Peak memory 204184 kb
Host smart-16c2b3e4-5aa5-40b1-8b3f-c238f3cd082e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618777582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3618777582
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.3667364639
Short name T1188
Test name
Test status
Simulation time 10882583850 ps
CPU time 95.96 seconds
Started May 02 01:42:09 PM PDT 24
Finished May 02 01:43:46 PM PDT 24
Peak memory 1118944 kb
Host smart-490106b8-8c1e-406d-85c6-39bcf38278ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667364639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3667364639
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.1675370820
Short name T375
Test name
Test status
Simulation time 218852887 ps
CPU time 2.53 seconds
Started May 02 01:42:23 PM PDT 24
Finished May 02 01:42:26 PM PDT 24
Peak memory 204184 kb
Host smart-4029e786-48e9-43ac-b259-c1dad47fffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675370820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1675370820
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.4026466020
Short name T769
Test name
Test status
Simulation time 7189312216 ps
CPU time 86.57 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:43:36 PM PDT 24
Peak memory 365304 kb
Host smart-088d7c6f-4246-45b0-bc38-92827c26b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026466020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.4026466020
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.4174034983
Short name T948
Test name
Test status
Simulation time 115808306 ps
CPU time 0.65 seconds
Started May 02 01:42:07 PM PDT 24
Finished May 02 01:42:09 PM PDT 24
Peak memory 203804 kb
Host smart-8310c9af-5998-4738-b3ed-082a41ca15ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174034983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.4174034983
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3953497551
Short name T785
Test name
Test status
Simulation time 6800626035 ps
CPU time 30.8 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:40 PM PDT 24
Peak memory 252712 kb
Host smart-3f8bf566-a762-46b4-952f-b19f3072e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953497551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3953497551
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2848319997
Short name T567
Test name
Test status
Simulation time 4798799130 ps
CPU time 16.16 seconds
Started May 02 01:42:03 PM PDT 24
Finished May 02 01:42:20 PM PDT 24
Peak memory 296764 kb
Host smart-3b930212-f2db-44c0-87e0-c351f5bd559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848319997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2848319997
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3275022736
Short name T768
Test name
Test status
Simulation time 7520160043 ps
CPU time 256.53 seconds
Started May 02 01:42:04 PM PDT 24
Finished May 02 01:46:22 PM PDT 24
Peak memory 1154064 kb
Host smart-eb66fb9b-17d0-4c2a-82b6-54b1eeff30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275022736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3275022736
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1864969000
Short name T1101
Test name
Test status
Simulation time 2231257028 ps
CPU time 7.26 seconds
Started May 02 01:42:06 PM PDT 24
Finished May 02 01:42:14 PM PDT 24
Peak memory 212416 kb
Host smart-c7c2f1a0-19d1-438e-a012-b224d279da66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864969000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1864969000
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1472819823
Short name T119
Test name
Test status
Simulation time 144969022 ps
CPU time 0.83 seconds
Started May 02 01:42:20 PM PDT 24
Finished May 02 01:42:21 PM PDT 24
Peak memory 221444 kb
Host smart-aee209a4-52c1-4c65-b77b-827074d74435
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472819823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1472819823
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3596084650
Short name T801
Test name
Test status
Simulation time 3054767817 ps
CPU time 3.77 seconds
Started May 02 01:42:08 PM PDT 24
Finished May 02 01:42:13 PM PDT 24
Peak memory 212464 kb
Host smart-3afb5d5b-fd1c-40db-bc41-9fb4bcae0752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596084650 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3596084650
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2143723320
Short name T55
Test name
Test status
Simulation time 10397142737 ps
CPU time 14.53 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:42:21 PM PDT 24
Peak memory 282600 kb
Host smart-38b0b8e1-4aab-4d72-8bbe-d087ddca52f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143723320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2143723320
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1308808236
Short name T504
Test name
Test status
Simulation time 514428261 ps
CPU time 2.49 seconds
Started May 02 01:42:11 PM PDT 24
Finished May 02 01:42:14 PM PDT 24
Peak memory 204120 kb
Host smart-1837d993-40bc-49c0-98bb-90e40a4c6150
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308808236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1308808236
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3969708703
Short name T1212
Test name
Test status
Simulation time 1389298716 ps
CPU time 6.84 seconds
Started May 02 01:42:04 PM PDT 24
Finished May 02 01:42:12 PM PDT 24
Peak memory 213476 kb
Host smart-6837e16a-2d2e-4cbe-b660-4e0dc1fbd51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969708703 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3969708703
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3841302191
Short name T651
Test name
Test status
Simulation time 23511349890 ps
CPU time 77.91 seconds
Started May 02 01:42:04 PM PDT 24
Finished May 02 01:43:23 PM PDT 24
Peak memory 1585552 kb
Host smart-b4aac0a2-e8c0-4ecd-908f-75c711edfdc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841302191 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3841302191
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1001361462
Short name T458
Test name
Test status
Simulation time 1217578728 ps
CPU time 15.14 seconds
Started May 02 01:42:06 PM PDT 24
Finished May 02 01:42:22 PM PDT 24
Peak memory 204152 kb
Host smart-3814ddf8-875e-4b08-87d4-02e1a95c19fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001361462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1001361462
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.585016656
Short name T1350
Test name
Test status
Simulation time 32917186546 ps
CPU time 1055.2 seconds
Started May 02 01:42:06 PM PDT 24
Finished May 02 01:59:43 PM PDT 24
Peak memory 5224016 kb
Host smart-b0e67726-bc05-45b8-8286-ba001114a4ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585016656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.i2c_target_stress_all.585016656
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2260549221
Short name T1133
Test name
Test status
Simulation time 800168231 ps
CPU time 11.18 seconds
Started May 02 01:42:05 PM PDT 24
Finished May 02 01:42:17 PM PDT 24
Peak memory 204148 kb
Host smart-f05bc827-9c23-4ec7-bcd7-6e20dd8685e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260549221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2260549221
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2545952919
Short name T1186
Test name
Test status
Simulation time 13767844777 ps
CPU time 26.23 seconds
Started May 02 01:42:09 PM PDT 24
Finished May 02 01:42:36 PM PDT 24
Peak memory 204116 kb
Host smart-a290dc87-2d8c-40c7-822d-66a31f2bab9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545952919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2545952919
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3152716417
Short name T1006
Test name
Test status
Simulation time 12059473034 ps
CPU time 366.43 seconds
Started May 02 01:42:06 PM PDT 24
Finished May 02 01:48:13 PM PDT 24
Peak memory 1184080 kb
Host smart-782ecdae-de43-4794-b1c6-56eda23bc3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152716417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3152716417
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3006438801
Short name T1046
Test name
Test status
Simulation time 10540478634 ps
CPU time 7.25 seconds
Started May 02 01:42:07 PM PDT 24
Finished May 02 01:42:15 PM PDT 24
Peak memory 220528 kb
Host smart-23da906f-9fbe-4c8d-a58a-e9599815cb6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006438801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3006438801
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.3414703447
Short name T744
Test name
Test status
Simulation time 2038855389 ps
CPU time 6.57 seconds
Started May 02 01:42:02 PM PDT 24
Finished May 02 01:42:09 PM PDT 24
Peak memory 204092 kb
Host smart-0c725537-731d-4cf7-8b98-5d60b02d6e2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414703447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.3414703447
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3383332775
Short name T556
Test name
Test status
Simulation time 22680530 ps
CPU time 0.62 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:46:56 PM PDT 24
Peak memory 203892 kb
Host smart-31468617-7663-4231-920d-2b1ed47acf50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383332775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3383332775
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2188612345
Short name T907
Test name
Test status
Simulation time 151861627 ps
CPU time 1.28 seconds
Started May 02 01:46:45 PM PDT 24
Finished May 02 01:46:47 PM PDT 24
Peak memory 216000 kb
Host smart-abbb299f-4732-4088-ba49-ffb7f3fec0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188612345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2188612345
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2440457467
Short name T401
Test name
Test status
Simulation time 1180704705 ps
CPU time 10.87 seconds
Started May 02 01:46:47 PM PDT 24
Finished May 02 01:46:59 PM PDT 24
Peak memory 239268 kb
Host smart-5ab8296c-e330-4192-90b4-1d2aa83d536d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440457467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2440457467
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1134706458
Short name T1071
Test name
Test status
Simulation time 1338236600 ps
CPU time 86.7 seconds
Started May 02 01:46:44 PM PDT 24
Finished May 02 01:48:12 PM PDT 24
Peak memory 482092 kb
Host smart-b3cf867f-5603-4f76-b985-49a24c38a64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134706458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1134706458
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.22573018
Short name T940
Test name
Test status
Simulation time 17043354939 ps
CPU time 25.97 seconds
Started May 02 01:46:45 PM PDT 24
Finished May 02 01:47:12 PM PDT 24
Peak memory 369344 kb
Host smart-082d6479-8f07-4a79-a6d4-2d86a4d80794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22573018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.22573018
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2520684836
Short name T207
Test name
Test status
Simulation time 484388809 ps
CPU time 1.02 seconds
Started May 02 01:46:47 PM PDT 24
Finished May 02 01:46:50 PM PDT 24
Peak memory 203956 kb
Host smart-a2f0b31e-28a5-4769-b752-6f5ce7337a89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520684836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2520684836
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.121636357
Short name T93
Test name
Test status
Simulation time 658685493 ps
CPU time 3.56 seconds
Started May 02 01:46:46 PM PDT 24
Finished May 02 01:46:51 PM PDT 24
Peak memory 204144 kb
Host smart-e6ac0e02-04ee-487f-a03b-2215e3f3ff2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121636357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
121636357
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2378012449
Short name T1253
Test name
Test status
Simulation time 15931006921 ps
CPU time 122.79 seconds
Started May 02 01:46:45 PM PDT 24
Finished May 02 01:48:49 PM PDT 24
Peak memory 1157248 kb
Host smart-ae0f64dc-0d2d-4f22-bcd5-bbf6007f9167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378012449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2378012449
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.450568515
Short name T1295
Test name
Test status
Simulation time 1670712709 ps
CPU time 6.58 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:47:01 PM PDT 24
Peak memory 204132 kb
Host smart-fa807522-4cbe-4046-b47a-61c6ac83c5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450568515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.450568515
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1340363183
Short name T694
Test name
Test status
Simulation time 6504763077 ps
CPU time 34.62 seconds
Started May 02 01:46:55 PM PDT 24
Finished May 02 01:47:30 PM PDT 24
Peak memory 341052 kb
Host smart-6499d533-bfb0-4675-b9f2-ab1fe73dc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340363183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1340363183
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1377596279
Short name T1139
Test name
Test status
Simulation time 81267438 ps
CPU time 0.65 seconds
Started May 02 01:46:46 PM PDT 24
Finished May 02 01:46:47 PM PDT 24
Peak memory 203800 kb
Host smart-8e6766f9-45f7-4cd1-b719-794811c893c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377596279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1377596279
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2879960663
Short name T1163
Test name
Test status
Simulation time 372104651 ps
CPU time 11.98 seconds
Started May 02 01:46:45 PM PDT 24
Finished May 02 01:46:57 PM PDT 24
Peak memory 204180 kb
Host smart-557736d3-dd5e-4b71-beba-b24480bb8ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879960663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2879960663
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3944433355
Short name T1220
Test name
Test status
Simulation time 11090050575 ps
CPU time 24.67 seconds
Started May 02 01:46:45 PM PDT 24
Finished May 02 01:47:11 PM PDT 24
Peak memory 353736 kb
Host smart-23ef7489-04e5-40a4-9ece-684f24a15311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944433355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3944433355
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.123105913
Short name T198
Test name
Test status
Simulation time 50478195251 ps
CPU time 880.34 seconds
Started May 02 01:46:48 PM PDT 24
Finished May 02 02:01:29 PM PDT 24
Peak memory 1429016 kb
Host smart-c3db294a-d5b9-499f-9d5c-ff5c0cd1fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123105913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.123105913
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3470140066
Short name T614
Test name
Test status
Simulation time 778680406 ps
CPU time 18.55 seconds
Started May 02 01:46:44 PM PDT 24
Finished May 02 01:47:03 PM PDT 24
Peak memory 212368 kb
Host smart-84e8107e-0b89-41d2-abe2-04618a5aba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470140066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3470140066
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.162021536
Short name T27
Test name
Test status
Simulation time 3768536658 ps
CPU time 3.93 seconds
Started May 02 01:46:48 PM PDT 24
Finished May 02 01:46:53 PM PDT 24
Peak memory 212428 kb
Host smart-b871ca0a-56bd-46f1-968d-6ed30787b3e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162021536 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.162021536
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.616072196
Short name T990
Test name
Test status
Simulation time 10079230500 ps
CPU time 26.64 seconds
Started May 02 01:46:44 PM PDT 24
Finished May 02 01:47:12 PM PDT 24
Peak memory 298500 kb
Host smart-809afbe3-1a49-49c4-89e7-d237d22ce857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616072196 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.616072196
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.589837275
Short name T1041
Test name
Test status
Simulation time 11105805415 ps
CPU time 3.87 seconds
Started May 02 01:46:46 PM PDT 24
Finished May 02 01:46:51 PM PDT 24
Peak memory 239472 kb
Host smart-df4bd16d-09b5-4071-b313-6819a209948d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589837275 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.589837275
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.1616411784
Short name T662
Test name
Test status
Simulation time 929821604 ps
CPU time 2.67 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:46:57 PM PDT 24
Peak memory 204156 kb
Host smart-87d90dd3-a65b-4e3b-86c7-5787768bc7e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616411784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.1616411784
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2765128480
Short name T1146
Test name
Test status
Simulation time 1012119344 ps
CPU time 5.71 seconds
Started May 02 01:46:46 PM PDT 24
Finished May 02 01:46:52 PM PDT 24
Peak memory 218360 kb
Host smart-bf04d8ec-dc21-4489-8025-4a41e0dd62ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765128480 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2765128480
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3613348890
Short name T813
Test name
Test status
Simulation time 7306977699 ps
CPU time 5.32 seconds
Started May 02 01:46:44 PM PDT 24
Finished May 02 01:46:50 PM PDT 24
Peak memory 204232 kb
Host smart-1032ce1e-8c72-4995-bb9d-d879f0c40339
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613348890 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3613348890
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.367285895
Short name T1223
Test name
Test status
Simulation time 566414682 ps
CPU time 6.81 seconds
Started May 02 01:46:44 PM PDT 24
Finished May 02 01:46:51 PM PDT 24
Peak memory 204172 kb
Host smart-93b35607-9305-4209-9820-6ef09283b871
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367285895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.367285895
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.4235944731
Short name T486
Test name
Test status
Simulation time 6676147708 ps
CPU time 30.03 seconds
Started May 02 01:46:46 PM PDT 24
Finished May 02 01:47:18 PM PDT 24
Peak memory 226072 kb
Host smart-4e6cb390-8652-4a94-b2ad-c3142c46e2d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235944731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.4235944731
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1232841921
Short name T1172
Test name
Test status
Simulation time 16552257822 ps
CPU time 16.76 seconds
Started May 02 01:46:47 PM PDT 24
Finished May 02 01:47:05 PM PDT 24
Peak memory 204180 kb
Host smart-7ad234ce-b4be-4d45-81a8-d21a41637c89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232841921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1232841921
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2291686872
Short name T678
Test name
Test status
Simulation time 6036445626 ps
CPU time 120.34 seconds
Started May 02 01:46:46 PM PDT 24
Finished May 02 01:48:47 PM PDT 24
Peak memory 1451504 kb
Host smart-6497a8ff-dcce-4419-987b-c11ad93920cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291686872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2291686872
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3091986304
Short name T1320
Test name
Test status
Simulation time 5398672529 ps
CPU time 6.87 seconds
Started May 02 01:46:47 PM PDT 24
Finished May 02 01:46:55 PM PDT 24
Peak memory 220444 kb
Host smart-2ae0c8e6-9316-40ce-a438-2e4113b5b1c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091986304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3091986304
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.2619989358
Short name T28
Test name
Test status
Simulation time 4148262030 ps
CPU time 5.26 seconds
Started May 02 01:46:49 PM PDT 24
Finished May 02 01:46:55 PM PDT 24
Peak memory 207884 kb
Host smart-4d6c128c-657d-4bba-a846-520e7a96db58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619989358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.2619989358
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2824275298
Short name T445
Test name
Test status
Simulation time 16125188 ps
CPU time 0.61 seconds
Started May 02 01:47:01 PM PDT 24
Finished May 02 01:47:03 PM PDT 24
Peak memory 203900 kb
Host smart-27085d42-1c62-49e4-a2d2-f8e46889f383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824275298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2824275298
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1584450180
Short name T1095
Test name
Test status
Simulation time 159252546 ps
CPU time 1.55 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:46:56 PM PDT 24
Peak memory 212448 kb
Host smart-30c177ec-ace2-400e-8001-16accb027666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584450180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1584450180
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1145572265
Short name T1049
Test name
Test status
Simulation time 1124640933 ps
CPU time 4.88 seconds
Started May 02 01:46:53 PM PDT 24
Finished May 02 01:46:59 PM PDT 24
Peak memory 246184 kb
Host smart-f770188b-605c-4741-8940-66e90fb4c7bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145572265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1145572265
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.554176597
Short name T233
Test name
Test status
Simulation time 2175471973 ps
CPU time 62.91 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:47:57 PM PDT 24
Peak memory 688956 kb
Host smart-e42bccde-ab79-4ead-b4c7-3e2ad7d6e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554176597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.554176597
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3834719035
Short name T476
Test name
Test status
Simulation time 1497284850 ps
CPU time 104.97 seconds
Started May 02 01:46:52 PM PDT 24
Finished May 02 01:48:38 PM PDT 24
Peak memory 564724 kb
Host smart-a1684160-95a0-458e-809d-99b0f79db167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834719035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3834719035
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1234470799
Short name T208
Test name
Test status
Simulation time 224046456 ps
CPU time 0.87 seconds
Started May 02 01:46:53 PM PDT 24
Finished May 02 01:46:55 PM PDT 24
Peak memory 203924 kb
Host smart-ff7b4d22-b9ad-4a2b-b769-94cded8a9624
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234470799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1234470799
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.337451441
Short name T1040
Test name
Test status
Simulation time 592947081 ps
CPU time 7.61 seconds
Started May 02 01:46:53 PM PDT 24
Finished May 02 01:47:01 PM PDT 24
Peak memory 226684 kb
Host smart-5877fdff-2486-439a-a215-efb81574ebf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337451441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
337451441
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.818921475
Short name T1233
Test name
Test status
Simulation time 4942264283 ps
CPU time 50.29 seconds
Started May 02 01:46:53 PM PDT 24
Finished May 02 01:47:44 PM PDT 24
Peak memory 804244 kb
Host smart-aed739c8-82a1-47a8-94b0-f9bb58ca3e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818921475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.818921475
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2661450313
Short name T71
Test name
Test status
Simulation time 8640343516 ps
CPU time 29.12 seconds
Started May 02 01:47:01 PM PDT 24
Finished May 02 01:47:32 PM PDT 24
Peak memory 204152 kb
Host smart-9282a79e-30dc-47ce-8147-949e548ab752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661450313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2661450313
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.371921728
Short name T1338
Test name
Test status
Simulation time 5184866954 ps
CPU time 18.91 seconds
Started May 02 01:47:00 PM PDT 24
Finished May 02 01:47:19 PM PDT 24
Peak memory 305076 kb
Host smart-30e951ab-f48d-45e4-a772-0da642b87471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371921728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.371921728
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2461099151
Short name T818
Test name
Test status
Simulation time 74892640 ps
CPU time 0.67 seconds
Started May 02 01:46:57 PM PDT 24
Finished May 02 01:46:58 PM PDT 24
Peak memory 203836 kb
Host smart-453b204d-5bf0-4912-9e54-acca62fe4196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461099151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2461099151
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1152001816
Short name T1129
Test name
Test status
Simulation time 5420745785 ps
CPU time 73.2 seconds
Started May 02 01:46:53 PM PDT 24
Finished May 02 01:48:07 PM PDT 24
Peak memory 400376 kb
Host smart-6c136850-8cd1-4782-8391-648bb88d1487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152001816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1152001816
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.48578106
Short name T668
Test name
Test status
Simulation time 4130919575 ps
CPU time 49.22 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:47:44 PM PDT 24
Peak memory 313284 kb
Host smart-781820f2-a226-4178-a8ff-893e5073fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48578106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.48578106
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.95308315
Short name T176
Test name
Test status
Simulation time 9560237980 ps
CPU time 243.53 seconds
Started May 02 01:46:52 PM PDT 24
Finished May 02 01:50:57 PM PDT 24
Peak memory 1739852 kb
Host smart-6ea18a0c-a15d-4039-ace1-54f73bfb9aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95308315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.95308315
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.2513855395
Short name T1280
Test name
Test status
Simulation time 2828106251 ps
CPU time 28.81 seconds
Started May 02 01:46:52 PM PDT 24
Finished May 02 01:47:21 PM PDT 24
Peak memory 212348 kb
Host smart-bc53deee-bc48-4947-9ff4-7b344c34fdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513855395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.2513855395
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.4093182544
Short name T554
Test name
Test status
Simulation time 10436443764 ps
CPU time 12.59 seconds
Started May 02 01:47:03 PM PDT 24
Finished May 02 01:47:17 PM PDT 24
Peak memory 265188 kb
Host smart-13ebd260-4f62-4e29-84fe-97c19aa6f904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093182544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.4093182544
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1387391322
Short name T562
Test name
Test status
Simulation time 10065814625 ps
CPU time 63.71 seconds
Started May 02 01:47:02 PM PDT 24
Finished May 02 01:48:07 PM PDT 24
Peak memory 442464 kb
Host smart-7ca459c7-e33b-4558-857a-3aae0ef10eea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387391322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1387391322
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2887014960
Short name T1288
Test name
Test status
Simulation time 1413544282 ps
CPU time 2.43 seconds
Started May 02 01:47:02 PM PDT 24
Finished May 02 01:47:06 PM PDT 24
Peak memory 204176 kb
Host smart-fc8a2090-962d-488c-a3e2-fd84e7672515
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887014960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2887014960
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3588633683
Short name T1057
Test name
Test status
Simulation time 3881640432 ps
CPU time 5.55 seconds
Started May 02 01:46:52 PM PDT 24
Finished May 02 01:46:59 PM PDT 24
Peak memory 212412 kb
Host smart-19ee828e-248c-48da-b176-32382467ceba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588633683 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3588633683
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.432219093
Short name T228
Test name
Test status
Simulation time 16838920934 ps
CPU time 8.03 seconds
Started May 02 01:46:57 PM PDT 24
Finished May 02 01:47:05 PM PDT 24
Peak memory 338836 kb
Host smart-6a108728-52ab-4760-b6ed-caa6b20a1906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432219093 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.432219093
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3067921065
Short name T683
Test name
Test status
Simulation time 2693482673 ps
CPU time 9.25 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:47:04 PM PDT 24
Peak memory 204132 kb
Host smart-150e1e57-3190-4c2c-ba14-f3d5a20c4705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067921065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3067921065
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.4154391792
Short name T372
Test name
Test status
Simulation time 4687100237 ps
CPU time 20.96 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 01:47:16 PM PDT 24
Peak memory 220284 kb
Host smart-95c5bcff-edaf-4a5f-9f9b-871a95392a7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154391792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.4154391792
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3186054928
Short name T995
Test name
Test status
Simulation time 34344002634 ps
CPU time 129.16 seconds
Started May 02 01:46:55 PM PDT 24
Finished May 02 01:49:05 PM PDT 24
Peak memory 1901536 kb
Host smart-351e1eaa-d989-4a83-b3e6-c971e69dd687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186054928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3186054928
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.3240992857
Short name T470
Test name
Test status
Simulation time 41269245577 ps
CPU time 829.49 seconds
Started May 02 01:46:54 PM PDT 24
Finished May 02 02:00:44 PM PDT 24
Peak memory 4232984 kb
Host smart-a7711df7-0538-40e8-8922-db987934b919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240992857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.3240992857
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.933973281
Short name T595
Test name
Test status
Simulation time 2638406453 ps
CPU time 5.89 seconds
Started May 02 01:46:52 PM PDT 24
Finished May 02 01:46:58 PM PDT 24
Peak memory 212456 kb
Host smart-0c1f9671-7a74-4b8a-85b8-e12825c5e3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933973281 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.933973281
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2694421038
Short name T1178
Test name
Test status
Simulation time 42820234 ps
CPU time 0.6 seconds
Started May 02 01:47:16 PM PDT 24
Finished May 02 01:47:17 PM PDT 24
Peak memory 203904 kb
Host smart-9a0bd97c-57d0-4729-9c3f-ee07c26baa79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694421038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2694421038
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1303382839
Short name T1100
Test name
Test status
Simulation time 112137392 ps
CPU time 1.54 seconds
Started May 02 01:47:03 PM PDT 24
Finished May 02 01:47:05 PM PDT 24
Peak memory 215448 kb
Host smart-d83685af-10aa-419b-86c0-0a4167cedcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303382839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1303382839
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.4099891277
Short name T364
Test name
Test status
Simulation time 357706907 ps
CPU time 9.63 seconds
Started May 02 01:47:01 PM PDT 24
Finished May 02 01:47:11 PM PDT 24
Peak memory 234844 kb
Host smart-d9a4bd44-7e0c-4599-a3dd-104cc8082dea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099891277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.4099891277
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2775060110
Short name T95
Test name
Test status
Simulation time 1989313141 ps
CPU time 55.91 seconds
Started May 02 01:47:02 PM PDT 24
Finished May 02 01:47:59 PM PDT 24
Peak memory 551396 kb
Host smart-e62a533b-34bf-4a26-a794-78f672ebf6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775060110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2775060110
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3406191502
Short name T435
Test name
Test status
Simulation time 1577636793 ps
CPU time 104.76 seconds
Started May 02 01:47:02 PM PDT 24
Finished May 02 01:48:47 PM PDT 24
Peak memory 562676 kb
Host smart-9f2d74c0-9fc1-41cc-aaaf-245afc8529a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406191502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3406191502
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3173680775
Short name T1098
Test name
Test status
Simulation time 415102644 ps
CPU time 1.15 seconds
Started May 02 01:47:01 PM PDT 24
Finished May 02 01:47:03 PM PDT 24
Peak memory 204136 kb
Host smart-c9996ad9-e5fa-45dd-b09f-4868a2148e10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173680775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3173680775
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.580637128
Short name T455
Test name
Test status
Simulation time 259258341 ps
CPU time 2.71 seconds
Started May 02 01:47:01 PM PDT 24
Finished May 02 01:47:05 PM PDT 24
Peak memory 204144 kb
Host smart-c38214cf-8207-4d7b-81cf-27ed892edf23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580637128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
580637128
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2186294916
Short name T1090
Test name
Test status
Simulation time 14404118285 ps
CPU time 67.48 seconds
Started May 02 01:47:02 PM PDT 24
Finished May 02 01:48:10 PM PDT 24
Peak memory 923792 kb
Host smart-b8ad7a5f-8366-47d1-984c-16f3e9e12f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186294916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2186294916
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1175242461
Short name T599
Test name
Test status
Simulation time 1658463295 ps
CPU time 16.46 seconds
Started May 02 01:47:09 PM PDT 24
Finished May 02 01:47:27 PM PDT 24
Peak memory 204112 kb
Host smart-812c0ee5-e004-4201-802a-71d7e664fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175242461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1175242461
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.1873475358
Short name T39
Test name
Test status
Simulation time 7281866686 ps
CPU time 78.35 seconds
Started May 02 01:47:09 PM PDT 24
Finished May 02 01:48:29 PM PDT 24
Peak memory 349676 kb
Host smart-b852dd63-158d-4973-8daa-597d38857efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873475358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.1873475358
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.4045460230
Short name T349
Test name
Test status
Simulation time 152426670 ps
CPU time 0.63 seconds
Started May 02 01:47:02 PM PDT 24
Finished May 02 01:47:04 PM PDT 24
Peak memory 203824 kb
Host smart-d8db43e6-bef9-4282-ba60-042256155f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045460230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.4045460230
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1138806880
Short name T200
Test name
Test status
Simulation time 14795008418 ps
CPU time 13.1 seconds
Started May 02 01:47:00 PM PDT 24
Finished May 02 01:47:14 PM PDT 24
Peak memory 301344 kb
Host smart-5ea6ecb7-5d65-4404-9329-3534e018d057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138806880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1138806880
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1406770688
Short name T988
Test name
Test status
Simulation time 1561948170 ps
CPU time 14.03 seconds
Started May 02 01:47:01 PM PDT 24
Finished May 02 01:47:16 PM PDT 24
Peak memory 301508 kb
Host smart-b3554d6a-fe85-4ed1-b2b4-242dd89d31ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406770688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1406770688
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.3687877425
Short name T238
Test name
Test status
Simulation time 17886188378 ps
CPU time 1339.11 seconds
Started May 02 01:47:09 PM PDT 24
Finished May 02 02:09:29 PM PDT 24
Peak memory 3702572 kb
Host smart-83838db5-9246-4aa2-81b9-c1ab17e3159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687877425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3687877425
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3365656381
Short name T1062
Test name
Test status
Simulation time 886964315 ps
CPU time 20.44 seconds
Started May 02 01:47:03 PM PDT 24
Finished May 02 01:47:24 PM PDT 24
Peak memory 212336 kb
Host smart-78f29dc2-86e1-4ff0-97e3-3ec113bd186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365656381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3365656381
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2294318298
Short name T621
Test name
Test status
Simulation time 7253250610 ps
CPU time 5.73 seconds
Started May 02 01:47:11 PM PDT 24
Finished May 02 01:47:18 PM PDT 24
Peak memory 211236 kb
Host smart-4dd5ea5a-daa4-41a1-909d-dc2c56635aa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294318298 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2294318298
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.39299782
Short name T951
Test name
Test status
Simulation time 10277072761 ps
CPU time 4.97 seconds
Started May 02 01:47:09 PM PDT 24
Finished May 02 01:47:15 PM PDT 24
Peak memory 220540 kb
Host smart-1ca4f9e7-7f9f-4ad8-badc-d94bd2618a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39299782 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_acq.39299782
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1865407126
Short name T860
Test name
Test status
Simulation time 10078342055 ps
CPU time 80.64 seconds
Started May 02 01:47:10 PM PDT 24
Finished May 02 01:48:32 PM PDT 24
Peak memory 550784 kb
Host smart-bab92558-0ac1-477f-9ddf-2af6e0dd6686
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865407126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1865407126
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3124468306
Short name T757
Test name
Test status
Simulation time 1232816577 ps
CPU time 2.22 seconds
Started May 02 01:47:12 PM PDT 24
Finished May 02 01:47:15 PM PDT 24
Peak memory 204132 kb
Host smart-058080e6-5bfc-44b1-bb67-7adc297452dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124468306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3124468306
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.631469543
Short name T758
Test name
Test status
Simulation time 806717205 ps
CPU time 4.05 seconds
Started May 02 01:47:10 PM PDT 24
Finished May 02 01:47:16 PM PDT 24
Peak memory 204896 kb
Host smart-e991e480-67fa-49e1-97a3-66484a96b7c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631469543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.631469543
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2114420269
Short name T736
Test name
Test status
Simulation time 18981935214 ps
CPU time 398.32 seconds
Started May 02 01:47:10 PM PDT 24
Finished May 02 01:53:49 PM PDT 24
Peak memory 4590256 kb
Host smart-bae4666b-2762-4312-84b1-c0bb582952b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114420269 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2114420269
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2644333417
Short name T624
Test name
Test status
Simulation time 3489027843 ps
CPU time 11.13 seconds
Started May 02 01:47:09 PM PDT 24
Finished May 02 01:47:21 PM PDT 24
Peak memory 204244 kb
Host smart-b3e51017-928b-4db5-97fc-e849186491cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644333417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2644333417
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2840510107
Short name T390
Test name
Test status
Simulation time 4719691067 ps
CPU time 19.94 seconds
Started May 02 01:47:11 PM PDT 24
Finished May 02 01:47:32 PM PDT 24
Peak memory 204260 kb
Host smart-41a0cc2e-64da-459b-ae43-16d6aff133de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840510107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2840510107
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.4255177729
Short name T446
Test name
Test status
Simulation time 55702511313 ps
CPU time 1491.84 seconds
Started May 02 01:47:11 PM PDT 24
Finished May 02 02:12:04 PM PDT 24
Peak memory 9125032 kb
Host smart-f32d8a9e-3a35-4bb2-800b-bb047d76ec38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255177729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.4255177729
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.673011004
Short name T1252
Test name
Test status
Simulation time 15782391813 ps
CPU time 185.56 seconds
Started May 02 01:47:10 PM PDT 24
Finished May 02 01:50:17 PM PDT 24
Peak memory 748164 kb
Host smart-eb9542d7-bef5-4de5-92c5-ff9d8e12c3a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673011004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.673011004
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3262247863
Short name T13
Test name
Test status
Simulation time 4998613094 ps
CPU time 6.76 seconds
Started May 02 01:47:10 PM PDT 24
Finished May 02 01:47:18 PM PDT 24
Peak memory 212444 kb
Host smart-dcc1d9e9-5293-4808-8a6d-b34ccd5e280f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262247863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3262247863
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.752302356
Short name T568
Test name
Test status
Simulation time 28950714 ps
CPU time 0.59 seconds
Started May 02 01:47:24 PM PDT 24
Finished May 02 01:47:26 PM PDT 24
Peak memory 203896 kb
Host smart-5c1fdc9b-559e-4d05-a059-9df7746b99f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752302356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.752302356
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3017032878
Short name T501
Test name
Test status
Simulation time 266704258 ps
CPU time 1.2 seconds
Started May 02 01:47:17 PM PDT 24
Finished May 02 01:47:20 PM PDT 24
Peak memory 212480 kb
Host smart-01aadc83-aeeb-43aa-bdc4-0637c61c7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017032878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3017032878
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1671052433
Short name T617
Test name
Test status
Simulation time 325578487 ps
CPU time 6.15 seconds
Started May 02 01:47:17 PM PDT 24
Finished May 02 01:47:24 PM PDT 24
Peak memory 272828 kb
Host smart-66b1363e-9ee7-4fb6-a8db-87733fbda038
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671052433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1671052433
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1695650000
Short name T503
Test name
Test status
Simulation time 21125253168 ps
CPU time 70.54 seconds
Started May 02 01:47:18 PM PDT 24
Finished May 02 01:48:29 PM PDT 24
Peak memory 729996 kb
Host smart-40e04ffb-ba3c-49d9-b96e-a924cd6a9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695650000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1695650000
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.232353316
Short name T319
Test name
Test status
Simulation time 1727010129 ps
CPU time 49.7 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:48:17 PM PDT 24
Peak memory 501756 kb
Host smart-93e19832-bd9c-41ac-b4ef-981d19b88b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232353316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.232353316
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2184240426
Short name T748
Test name
Test status
Simulation time 578430344 ps
CPU time 1.11 seconds
Started May 02 01:47:16 PM PDT 24
Finished May 02 01:47:18 PM PDT 24
Peak memory 204140 kb
Host smart-e02d14df-59bd-4d36-ac76-f48f10d5fba2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184240426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2184240426
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3611109675
Short name T1297
Test name
Test status
Simulation time 111048955 ps
CPU time 2.8 seconds
Started May 02 01:47:17 PM PDT 24
Finished May 02 01:47:21 PM PDT 24
Peak memory 204120 kb
Host smart-a7a00476-b7f6-4f72-8dce-91031c5ea38b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611109675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3611109675
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1741538254
Short name T175
Test name
Test status
Simulation time 16655268007 ps
CPU time 108.18 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:49:15 PM PDT 24
Peak memory 1241972 kb
Host smart-9153debf-fec6-4014-89ef-b4bc5f8b6806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741538254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1741538254
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.4049303441
Short name T1011
Test name
Test status
Simulation time 3173644055 ps
CPU time 13.64 seconds
Started May 02 01:47:26 PM PDT 24
Finished May 02 01:47:41 PM PDT 24
Peak memory 245904 kb
Host smart-fd431d59-5587-4fd5-92f4-21eeb7c6eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049303441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.4049303441
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.4146019940
Short name T408
Test name
Test status
Simulation time 88425833 ps
CPU time 0.67 seconds
Started May 02 01:47:19 PM PDT 24
Finished May 02 01:47:20 PM PDT 24
Peak memory 203844 kb
Host smart-66794733-2c53-48e7-b939-9df0a66970e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146019940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.4146019940
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.1063369960
Short name T420
Test name
Test status
Simulation time 3550335635 ps
CPU time 69.45 seconds
Started May 02 01:47:17 PM PDT 24
Finished May 02 01:48:28 PM PDT 24
Peak memory 311920 kb
Host smart-4b254c02-742f-490d-b328-547f8352ef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063369960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1063369960
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.1326749283
Short name T187
Test name
Test status
Simulation time 9870467072 ps
CPU time 265.82 seconds
Started May 02 01:47:17 PM PDT 24
Finished May 02 01:51:44 PM PDT 24
Peak memory 1015736 kb
Host smart-24aebacc-d5eb-45cc-891f-7abc194d416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326749283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.1326749283
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1604387781
Short name T1013
Test name
Test status
Simulation time 1081165694 ps
CPU time 24.75 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:47:52 PM PDT 24
Peak memory 212344 kb
Host smart-f753770c-384d-4387-a945-cfb7ffedd8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604387781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1604387781
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3563419504
Short name T301
Test name
Test status
Simulation time 514854040 ps
CPU time 2.67 seconds
Started May 02 01:47:26 PM PDT 24
Finished May 02 01:47:31 PM PDT 24
Peak memory 204136 kb
Host smart-86dfd9d7-a369-476c-9ad9-9db25797e67e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563419504 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3563419504
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2370662996
Short name T485
Test name
Test status
Simulation time 10713481288 ps
CPU time 5.64 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:47:32 PM PDT 24
Peak memory 228060 kb
Host smart-60c23258-dbbc-4ddb-9c71-1483f057e258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370662996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2370662996
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2095545634
Short name T922
Test name
Test status
Simulation time 10050206755 ps
CPU time 68.25 seconds
Started May 02 01:47:24 PM PDT 24
Finished May 02 01:48:34 PM PDT 24
Peak memory 560600 kb
Host smart-9282f374-c7e7-4748-b938-ba7097a511b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095545634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2095545634
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2753076469
Short name T788
Test name
Test status
Simulation time 513424805 ps
CPU time 2.74 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:47:30 PM PDT 24
Peak memory 204176 kb
Host smart-3a521f82-3071-4669-922e-efc58bcba695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753076469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2753076469
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3652130625
Short name T631
Test name
Test status
Simulation time 7675415030 ps
CPU time 4.68 seconds
Started May 02 01:47:26 PM PDT 24
Finished May 02 01:47:33 PM PDT 24
Peak memory 207120 kb
Host smart-5df40356-1bb3-48ac-86b9-77b028ad1736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652130625 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3652130625
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3687468497
Short name T518
Test name
Test status
Simulation time 8571119273 ps
CPU time 23.16 seconds
Started May 02 01:47:18 PM PDT 24
Finished May 02 01:47:42 PM PDT 24
Peak memory 415108 kb
Host smart-e0d52be0-9f6b-4bbd-913b-73fee107e40d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687468497 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3687468497
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3807221850
Short name T308
Test name
Test status
Simulation time 726199088 ps
CPU time 25.58 seconds
Started May 02 01:47:16 PM PDT 24
Finished May 02 01:47:43 PM PDT 24
Peak memory 204068 kb
Host smart-54d1c577-e4fe-47f4-ab7d-9d9873e8d444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807221850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3807221850
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.447816573
Short name T1332
Test name
Test status
Simulation time 28966475443 ps
CPU time 67.49 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:48:34 PM PDT 24
Peak memory 609040 kb
Host smart-2d456baf-8cf2-4963-bc93-487e0f1c6134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447816573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_target_stress_all.447816573
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.504026324
Short name T365
Test name
Test status
Simulation time 5231341017 ps
CPU time 12.78 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:47:40 PM PDT 24
Peak memory 213216 kb
Host smart-17243a85-0da9-475a-9840-7aa9a072ddb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504026324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.504026324
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1434638066
Short name T507
Test name
Test status
Simulation time 49182838490 ps
CPU time 57.79 seconds
Started May 02 01:47:20 PM PDT 24
Finished May 02 01:48:18 PM PDT 24
Peak memory 1022288 kb
Host smart-cf192579-b13e-4927-b225-aae5b4eb8034
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434638066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1434638066
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1286386996
Short name T833
Test name
Test status
Simulation time 40664986340 ps
CPU time 2874.17 seconds
Started May 02 01:47:17 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 9952168 kb
Host smart-497f3d48-782c-4966-9814-10b0c991539c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286386996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1286386996
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2551229622
Short name T291
Test name
Test status
Simulation time 8138662132 ps
CPU time 7.21 seconds
Started May 02 01:47:18 PM PDT 24
Finished May 02 01:47:26 PM PDT 24
Peak memory 219000 kb
Host smart-77763f14-b48f-47b7-a0b7-adb2c2d5ec9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551229622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2551229622
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2773948406
Short name T879
Test name
Test status
Simulation time 17132691 ps
CPU time 0.63 seconds
Started May 02 01:47:41 PM PDT 24
Finished May 02 01:47:43 PM PDT 24
Peak memory 203904 kb
Host smart-702df01d-d2e5-4a5b-98af-3e215fb5de1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773948406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2773948406
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2012094406
Short name T919
Test name
Test status
Simulation time 303179831 ps
CPU time 1.49 seconds
Started May 02 01:47:26 PM PDT 24
Finished May 02 01:47:30 PM PDT 24
Peak memory 212508 kb
Host smart-9c50f099-5763-4fbf-8c11-014c5451bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012094406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2012094406
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3952519152
Short name T663
Test name
Test status
Simulation time 194316569 ps
CPU time 4.09 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:47:31 PM PDT 24
Peak memory 228768 kb
Host smart-c816f1e4-9f39-42a6-8ec4-37a200a75c19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952519152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3952519152
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2422477624
Short name T751
Test name
Test status
Simulation time 1972002324 ps
CPU time 56.11 seconds
Started May 02 01:47:24 PM PDT 24
Finished May 02 01:48:22 PM PDT 24
Peak memory 510880 kb
Host smart-94b6fd9a-4a01-4f0e-8e84-bd3f9657c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422477624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2422477624
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.649903808
Short name T1055
Test name
Test status
Simulation time 1622348478 ps
CPU time 46.37 seconds
Started May 02 01:47:24 PM PDT 24
Finished May 02 01:48:11 PM PDT 24
Peak memory 604664 kb
Host smart-88b221fc-cb00-4221-9aae-3402d1de174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649903808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.649903808
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.590772209
Short name T210
Test name
Test status
Simulation time 125073276 ps
CPU time 1.13 seconds
Started May 02 01:47:28 PM PDT 24
Finished May 02 01:47:30 PM PDT 24
Peak memory 204152 kb
Host smart-23b321ee-0a3d-45d9-aced-554eb32506fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590772209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.590772209
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3566383679
Short name T871
Test name
Test status
Simulation time 435380464 ps
CPU time 3.64 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:47:31 PM PDT 24
Peak memory 221724 kb
Host smart-59d4c8bf-5dd3-485f-a2de-26316a42e807
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566383679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3566383679
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.246328259
Short name T790
Test name
Test status
Simulation time 2295553016 ps
CPU time 147.68 seconds
Started May 02 01:47:23 PM PDT 24
Finished May 02 01:49:52 PM PDT 24
Peak memory 771624 kb
Host smart-4b63e216-b212-4cca-bdd5-67046da39452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246328259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.246328259
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.3768642431
Short name T658
Test name
Test status
Simulation time 1619520840 ps
CPU time 2.99 seconds
Started May 02 01:47:32 PM PDT 24
Finished May 02 01:47:37 PM PDT 24
Peak memory 204140 kb
Host smart-8614b7ab-c7d8-4710-8133-9a8b260b9012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768642431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3768642431
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.236159670
Short name T992
Test name
Test status
Simulation time 6497022117 ps
CPU time 29.89 seconds
Started May 02 01:47:33 PM PDT 24
Finished May 02 01:48:04 PM PDT 24
Peak memory 306936 kb
Host smart-5659ca5c-a2f5-4373-b315-d6d35a414749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236159670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.236159670
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.4225115010
Short name T609
Test name
Test status
Simulation time 45501038 ps
CPU time 0.65 seconds
Started May 02 01:47:26 PM PDT 24
Finished May 02 01:47:28 PM PDT 24
Peak memory 203772 kb
Host smart-7c5e4932-7de3-4cdf-9b08-dcba60ad24bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225115010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.4225115010
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3449432849
Short name T718
Test name
Test status
Simulation time 6586290279 ps
CPU time 64.51 seconds
Started May 02 01:47:25 PM PDT 24
Finished May 02 01:48:32 PM PDT 24
Peak memory 204292 kb
Host smart-b768e9d1-a605-48e5-9bc7-668c7acf0204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449432849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3449432849
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2350442105
Short name T1036
Test name
Test status
Simulation time 7380058142 ps
CPU time 95.92 seconds
Started May 02 01:47:28 PM PDT 24
Finished May 02 01:49:05 PM PDT 24
Peak memory 366572 kb
Host smart-d4289cae-0f35-45aa-bfd8-1efbcbb0eddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350442105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2350442105
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2281737497
Short name T383
Test name
Test status
Simulation time 1432556006 ps
CPU time 33.66 seconds
Started May 02 01:47:24 PM PDT 24
Finished May 02 01:48:00 PM PDT 24
Peak memory 213668 kb
Host smart-13a2f682-a45e-4b5d-b924-3fc2524baef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281737497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2281737497
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1941461587
Short name T350
Test name
Test status
Simulation time 4305021294 ps
CPU time 3.7 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:47:49 PM PDT 24
Peak memory 204304 kb
Host smart-86d03abf-827d-42f4-a510-245d783315e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941461587 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1941461587
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1817295581
Short name T52
Test name
Test status
Simulation time 10208662487 ps
CPU time 14 seconds
Started May 02 01:47:32 PM PDT 24
Finished May 02 01:47:47 PM PDT 24
Peak memory 268284 kb
Host smart-998a855b-ae79-4c45-afed-c6c1b720c335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817295581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1817295581
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2008552215
Short name T791
Test name
Test status
Simulation time 10470566444 ps
CPU time 15.54 seconds
Started May 02 01:47:31 PM PDT 24
Finished May 02 01:47:48 PM PDT 24
Peak memory 297348 kb
Host smart-d4143cdf-c0fb-4513-b76d-b1d848701687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008552215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2008552215
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.84124724
Short name T469
Test name
Test status
Simulation time 371613393 ps
CPU time 2.27 seconds
Started May 02 01:47:33 PM PDT 24
Finished May 02 01:47:36 PM PDT 24
Peak memory 204200 kb
Host smart-741d7d2a-a216-4b87-ba9e-d2d727cdebaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84124724 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.i2c_target_hrst.84124724
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1372358904
Short name T379
Test name
Test status
Simulation time 4710483075 ps
CPU time 5.08 seconds
Started May 02 01:47:33 PM PDT 24
Finished May 02 01:47:39 PM PDT 24
Peak memory 204228 kb
Host smart-0d698fe5-4fef-489b-ae26-10bc7352ec9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372358904 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1372358904
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2224181252
Short name T724
Test name
Test status
Simulation time 33123020088 ps
CPU time 12.58 seconds
Started May 02 01:47:33 PM PDT 24
Finished May 02 01:47:48 PM PDT 24
Peak memory 414276 kb
Host smart-3a3f8f1d-3e64-4578-a95c-cd25e51b548d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224181252 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2224181252
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2555940911
Short name T675
Test name
Test status
Simulation time 2728543059 ps
CPU time 19.84 seconds
Started May 02 01:47:26 PM PDT 24
Finished May 02 01:47:48 PM PDT 24
Peak memory 204212 kb
Host smart-d0690aa0-a032-4713-8672-52603a1e0ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555940911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2555940911
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2831800600
Short name T762
Test name
Test status
Simulation time 18216040069 ps
CPU time 83.9 seconds
Started May 02 01:47:32 PM PDT 24
Finished May 02 01:48:57 PM PDT 24
Peak memory 212732 kb
Host smart-65945b7d-c053-4ca0-b922-a19aa0e87288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831800600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2831800600
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2253383662
Short name T555
Test name
Test status
Simulation time 56526572895 ps
CPU time 68.91 seconds
Started May 02 01:47:45 PM PDT 24
Finished May 02 01:48:55 PM PDT 24
Peak memory 1034632 kb
Host smart-931008f5-1818-4284-90b0-3ad02f938dd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253383662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2253383662
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.161634909
Short name T978
Test name
Test status
Simulation time 29856465339 ps
CPU time 249.61 seconds
Started May 02 01:47:33 PM PDT 24
Finished May 02 01:51:44 PM PDT 24
Peak memory 1769356 kb
Host smart-bd4489d3-ff99-486c-b06f-0066dcf1ee8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161634909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.161634909
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2735864706
Short name T11
Test name
Test status
Simulation time 5666532182 ps
CPU time 7.12 seconds
Started May 02 01:47:33 PM PDT 24
Finished May 02 01:47:42 PM PDT 24
Peak memory 220476 kb
Host smart-1c9d4ff0-91a3-464f-9e46-5581eb64f7a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735864706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2735864706
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.1393571193
Short name T1077
Test name
Test status
Simulation time 18049369 ps
CPU time 0.6 seconds
Started May 02 01:47:47 PM PDT 24
Finished May 02 01:47:48 PM PDT 24
Peak memory 203880 kb
Host smart-40a6001f-fdfd-4d09-bb4b-24bb878cd58f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393571193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1393571193
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.892456772
Short name T947
Test name
Test status
Simulation time 145171987 ps
CPU time 1.68 seconds
Started May 02 01:47:42 PM PDT 24
Finished May 02 01:47:45 PM PDT 24
Peak memory 212460 kb
Host smart-eb6a86c6-53fe-4543-b66b-9a67d5036146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892456772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.892456772
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3015993987
Short name T729
Test name
Test status
Simulation time 206055739 ps
CPU time 10.19 seconds
Started May 02 01:47:41 PM PDT 24
Finished May 02 01:47:53 PM PDT 24
Peak memory 242772 kb
Host smart-d49cb180-9b03-4cbe-a02b-ee5bef0f7af3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015993987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3015993987
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1117615809
Short name T1292
Test name
Test status
Simulation time 1247012024 ps
CPU time 39.56 seconds
Started May 02 01:47:43 PM PDT 24
Finished May 02 01:48:24 PM PDT 24
Peak memory 500704 kb
Host smart-e734c8da-11b5-4688-856a-00b00b32194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117615809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1117615809
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2090216820
Short name T945
Test name
Test status
Simulation time 8240129623 ps
CPU time 155.85 seconds
Started May 02 01:47:35 PM PDT 24
Finished May 02 01:50:12 PM PDT 24
Peak memory 697336 kb
Host smart-ba3f67b5-3548-4fa6-9458-bc9c870ce300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090216820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2090216820
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.84885774
Short name T764
Test name
Test status
Simulation time 94568586 ps
CPU time 0.89 seconds
Started May 02 01:47:42 PM PDT 24
Finished May 02 01:47:44 PM PDT 24
Peak memory 203968 kb
Host smart-73362d24-bee8-4f90-8122-f24804c9229d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84885774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt
.84885774
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1903042164
Short name T727
Test name
Test status
Simulation time 590990653 ps
CPU time 9.03 seconds
Started May 02 01:47:43 PM PDT 24
Finished May 02 01:47:53 PM PDT 24
Peak memory 231200 kb
Host smart-a0a81680-7050-4c2c-ba7c-f26ca93b9258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903042164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1903042164
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3384279890
Short name T177
Test name
Test status
Simulation time 20633962789 ps
CPU time 80.12 seconds
Started May 02 01:47:33 PM PDT 24
Finished May 02 01:48:54 PM PDT 24
Peak memory 986148 kb
Host smart-2bb1828d-e063-4108-bc75-c9d58d664ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384279890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3384279890
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.551908831
Short name T659
Test name
Test status
Simulation time 580960102 ps
CPU time 23.64 seconds
Started May 02 01:47:43 PM PDT 24
Finished May 02 01:48:08 PM PDT 24
Peak memory 204196 kb
Host smart-0a5ec2ca-fc4d-4aba-a6ba-39af5fd034e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551908831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.551908831
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2845698058
Short name T908
Test name
Test status
Simulation time 7664708239 ps
CPU time 28.53 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:48:14 PM PDT 24
Peak memory 317984 kb
Host smart-32820517-a31f-4ed2-aa9e-4a01560435fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845698058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2845698058
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.874010945
Short name T191
Test name
Test status
Simulation time 55172677 ps
CPU time 0.66 seconds
Started May 02 01:47:32 PM PDT 24
Finished May 02 01:47:34 PM PDT 24
Peak memory 203804 kb
Host smart-c442d17f-473f-4ee1-a994-f40c16a833d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874010945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.874010945
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2579554640
Short name T300
Test name
Test status
Simulation time 2556264427 ps
CPU time 170.43 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:50:36 PM PDT 24
Peak memory 790012 kb
Host smart-82e89147-a78f-41eb-9ee6-059d4a801f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579554640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2579554640
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3992474322
Short name T793
Test name
Test status
Simulation time 1019999176 ps
CPU time 19.13 seconds
Started May 02 01:47:32 PM PDT 24
Finished May 02 01:47:53 PM PDT 24
Peak memory 282932 kb
Host smart-c27d343e-2aa9-4727-acfb-9c00f5b229ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992474322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3992474322
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.782336404
Short name T902
Test name
Test status
Simulation time 5393837393 ps
CPU time 219.53 seconds
Started May 02 01:47:42 PM PDT 24
Finished May 02 01:51:23 PM PDT 24
Peak memory 597804 kb
Host smart-6eddeb17-9548-465f-80a0-3142a974d580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782336404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.782336404
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.240761541
Short name T85
Test name
Test status
Simulation time 1403015605 ps
CPU time 15.77 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:48:01 PM PDT 24
Peak memory 212324 kb
Host smart-133cad82-18ca-4a1c-9b1d-5fb93407d917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240761541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.240761541
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3932176857
Short name T323
Test name
Test status
Simulation time 1129518414 ps
CPU time 2.94 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:47:48 PM PDT 24
Peak memory 204168 kb
Host smart-ce5552ee-0ee2-44c6-a931-301ef92738fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932176857 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3932176857
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3785458184
Short name T1309
Test name
Test status
Simulation time 10070976643 ps
CPU time 68.31 seconds
Started May 02 01:47:41 PM PDT 24
Finished May 02 01:48:50 PM PDT 24
Peak memory 474120 kb
Host smart-35f20f33-b2ec-47c4-8804-63edc15ca1fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785458184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3785458184
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3251294409
Short name T816
Test name
Test status
Simulation time 763274898 ps
CPU time 2.48 seconds
Started May 02 01:47:42 PM PDT 24
Finished May 02 01:47:46 PM PDT 24
Peak memory 204152 kb
Host smart-a512803d-a9da-41a7-9c60-afb3ca297421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251294409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3251294409
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.4161947070
Short name T1293
Test name
Test status
Simulation time 4270441684 ps
CPU time 5.28 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:47:51 PM PDT 24
Peak memory 217276 kb
Host smart-603c8db9-21cc-4d5b-bc1e-8614bd6adf08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161947070 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.4161947070
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.4129948553
Short name T926
Test name
Test status
Simulation time 11052297854 ps
CPU time 11.6 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:47:56 PM PDT 24
Peak memory 333980 kb
Host smart-555e0c66-9c37-4c30-add0-e3a146872d45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129948553 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.4129948553
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2223317009
Short name T1161
Test name
Test status
Simulation time 926025560 ps
CPU time 11.14 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:47:56 PM PDT 24
Peak memory 204100 kb
Host smart-9eb221fa-eb2e-4fd2-8a69-7e7375e7066f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223317009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2223317009
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3936222907
Short name T836
Test name
Test status
Simulation time 296426377 ps
CPU time 5.45 seconds
Started May 02 01:47:44 PM PDT 24
Finished May 02 01:47:50 PM PDT 24
Peak memory 204092 kb
Host smart-70e8493b-27ed-44d0-9572-0e89874d73e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936222907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3936222907
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1656414064
Short name T720
Test name
Test status
Simulation time 47220879891 ps
CPU time 302.21 seconds
Started May 02 01:47:41 PM PDT 24
Finished May 02 01:52:44 PM PDT 24
Peak memory 3376504 kb
Host smart-a9933503-f47e-4e57-80b9-7c2619285f38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656414064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1656414064
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2137908373
Short name T1155
Test name
Test status
Simulation time 8039423928 ps
CPU time 212.26 seconds
Started May 02 01:47:43 PM PDT 24
Finished May 02 01:51:16 PM PDT 24
Peak memory 1923948 kb
Host smart-ec21b156-88d3-466b-b22f-89d1401ee415
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137908373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2137908373
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3407054175
Short name T865
Test name
Test status
Simulation time 1272742716 ps
CPU time 5.9 seconds
Started May 02 01:47:41 PM PDT 24
Finished May 02 01:47:48 PM PDT 24
Peak memory 204100 kb
Host smart-4d17d0c0-1693-4ec1-8762-f25c2c01bef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407054175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3407054175
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.190148738
Short name T606
Test name
Test status
Simulation time 59648572 ps
CPU time 0.61 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 01:47:59 PM PDT 24
Peak memory 203904 kb
Host smart-a09673ca-9f60-4de9-b9d0-82dc35ce7922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190148738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.190148738
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2844277443
Short name T1352
Test name
Test status
Simulation time 914125851 ps
CPU time 1.44 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 01:48:00 PM PDT 24
Peak memory 204280 kb
Host smart-d5077373-c708-4cb5-b907-d2df0761aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844277443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2844277443
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1355830595
Short name T559
Test name
Test status
Simulation time 352872536 ps
CPU time 8.14 seconds
Started May 02 01:47:46 PM PDT 24
Finished May 02 01:47:55 PM PDT 24
Peak memory 281828 kb
Host smart-d9a40fac-0f7d-4dcf-84e4-1339dc4b0d45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355830595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1355830595
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2295827265
Short name T386
Test name
Test status
Simulation time 4333170133 ps
CPU time 157.67 seconds
Started May 02 01:47:45 PM PDT 24
Finished May 02 01:50:24 PM PDT 24
Peak memory 720664 kb
Host smart-0c56c428-5f23-4e22-a812-61eee387b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295827265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2295827265
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3061003902
Short name T560
Test name
Test status
Simulation time 7714924040 ps
CPU time 76.48 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 01:49:15 PM PDT 24
Peak memory 675468 kb
Host smart-22b252a8-9a78-415b-98db-7eb2c4573eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061003902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3061003902
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2879737696
Short name T498
Test name
Test status
Simulation time 252375803 ps
CPU time 0.79 seconds
Started May 02 01:47:47 PM PDT 24
Finished May 02 01:47:49 PM PDT 24
Peak memory 203984 kb
Host smart-72358a47-879e-45a5-a17c-3fba781bf21c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879737696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2879737696
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3042981593
Short name T320
Test name
Test status
Simulation time 1489220346 ps
CPU time 10.68 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 01:48:10 PM PDT 24
Peak memory 240400 kb
Host smart-e4ca0d61-2d64-4877-adbc-b5ba7bdc317e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042981593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3042981593
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.421152065
Short name T861
Test name
Test status
Simulation time 2568037943 ps
CPU time 69.02 seconds
Started May 02 01:47:50 PM PDT 24
Finished May 02 01:49:00 PM PDT 24
Peak memory 827184 kb
Host smart-51ee5e9f-7ba0-4c79-8eb3-12bf5459da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421152065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.421152065
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.436977547
Short name T977
Test name
Test status
Simulation time 1131778084 ps
CPU time 5.05 seconds
Started May 02 01:47:56 PM PDT 24
Finished May 02 01:48:02 PM PDT 24
Peak memory 204172 kb
Host smart-f3264e1c-f06b-4ac1-976c-405057dd5cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436977547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.436977547
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3127797864
Short name T122
Test name
Test status
Simulation time 1455727594 ps
CPU time 32.03 seconds
Started May 02 01:47:55 PM PDT 24
Finished May 02 01:48:28 PM PDT 24
Peak memory 413860 kb
Host smart-88a0542b-aa14-4bc5-82d9-2a5a88ea4fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127797864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3127797864
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2995974371
Short name T335
Test name
Test status
Simulation time 53485246 ps
CPU time 0.67 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 01:48:00 PM PDT 24
Peak memory 203872 kb
Host smart-e3241d1d-b76c-4e62-9190-d3ee1ac86eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995974371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2995974371
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3030237794
Short name T1180
Test name
Test status
Simulation time 2746833018 ps
CPU time 28.2 seconds
Started May 02 01:47:46 PM PDT 24
Finished May 02 01:48:15 PM PDT 24
Peak memory 269316 kb
Host smart-65cf6ea5-f675-4718-b997-12d33d36ffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030237794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3030237794
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.4252013400
Short name T755
Test name
Test status
Simulation time 3268720714 ps
CPU time 77.19 seconds
Started May 02 01:47:49 PM PDT 24
Finished May 02 01:49:06 PM PDT 24
Peak memory 361212 kb
Host smart-7432b90f-aafb-4bb0-8401-3316c57b668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252013400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.4252013400
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.540744750
Short name T561
Test name
Test status
Simulation time 16959959618 ps
CPU time 725.22 seconds
Started May 02 01:47:48 PM PDT 24
Finished May 02 01:59:54 PM PDT 24
Peak memory 2376476 kb
Host smart-0864000b-5b15-4b80-9e43-907045ac05f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540744750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.540744750
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.4269299807
Short name T324
Test name
Test status
Simulation time 2630861051 ps
CPU time 9.08 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 01:48:08 PM PDT 24
Peak memory 219760 kb
Host smart-3c23e73e-2d08-4cdf-91ca-6a5e39c8bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269299807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.4269299807
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2438794356
Short name T1083
Test name
Test status
Simulation time 476271330 ps
CPU time 2.4 seconds
Started May 02 01:47:56 PM PDT 24
Finished May 02 01:48:00 PM PDT 24
Peak memory 204156 kb
Host smart-4aa65967-116f-4b9a-bd3c-bc9179ea4d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438794356 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2438794356
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1435602866
Short name T891
Test name
Test status
Simulation time 10024869033 ps
CPU time 73.51 seconds
Started May 02 01:47:55 PM PDT 24
Finished May 02 01:49:09 PM PDT 24
Peak memory 448584 kb
Host smart-02d4811f-7e2f-4d83-a7e5-5e8ebb72946f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435602866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1435602866
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.4134411595
Short name T411
Test name
Test status
Simulation time 10066957236 ps
CPU time 26.13 seconds
Started May 02 01:47:56 PM PDT 24
Finished May 02 01:48:23 PM PDT 24
Peak memory 345636 kb
Host smart-6013ab8d-a09b-4d3b-904f-713d40fb12a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134411595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.4134411595
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3325349131
Short name T580
Test name
Test status
Simulation time 472798140 ps
CPU time 1.99 seconds
Started May 02 01:47:57 PM PDT 24
Finished May 02 01:48:00 PM PDT 24
Peak memory 204196 kb
Host smart-00cd1748-b86b-47ea-ba2a-a1e8a7cf0f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325349131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3325349131
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2167075477
Short name T979
Test name
Test status
Simulation time 789904052 ps
CPU time 4.41 seconds
Started May 02 01:47:57 PM PDT 24
Finished May 02 01:48:02 PM PDT 24
Peak memory 205460 kb
Host smart-82487f07-b6e6-436d-9202-c09229ac8591
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167075477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2167075477
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1211908330
Short name T831
Test name
Test status
Simulation time 12852561371 ps
CPU time 78.86 seconds
Started May 02 01:47:56 PM PDT 24
Finished May 02 01:49:15 PM PDT 24
Peak memory 1642844 kb
Host smart-0fa01d1a-e10b-4e25-86ac-94735d9d95a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211908330 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1211908330
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.4143498141
Short name T34
Test name
Test status
Simulation time 1281327085 ps
CPU time 34.74 seconds
Started May 02 01:47:49 PM PDT 24
Finished May 02 01:48:24 PM PDT 24
Peak memory 204192 kb
Host smart-e1ec9b08-982d-40ab-bdba-474c9b2b391b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143498141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.4143498141
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1000879626
Short name T65
Test name
Test status
Simulation time 6956421522 ps
CPU time 16.84 seconds
Started May 02 01:47:48 PM PDT 24
Finished May 02 01:48:05 PM PDT 24
Peak memory 204160 kb
Host smart-dc63d670-42b3-43bd-a726-c2326d9ee9ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000879626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1000879626
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2597773869
Short name T283
Test name
Test status
Simulation time 35426473827 ps
CPU time 132.8 seconds
Started May 02 01:47:50 PM PDT 24
Finished May 02 01:50:03 PM PDT 24
Peak memory 1918864 kb
Host smart-82c61b93-b6fe-435d-9f99-ac71b73ad838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597773869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2597773869
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3620691466
Short name T1070
Test name
Test status
Simulation time 36028958019 ps
CPU time 936.65 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 02:03:36 PM PDT 24
Peak memory 4436712 kb
Host smart-5580238b-c4cc-48e0-a995-84795dde6408
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620691466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3620691466
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1208248251
Short name T494
Test name
Test status
Simulation time 2626198433 ps
CPU time 6.34 seconds
Started May 02 01:47:55 PM PDT 24
Finished May 02 01:48:02 PM PDT 24
Peak memory 211924 kb
Host smart-e713e45b-ae06-4200-90c6-8ba6b873a510
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208248251 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1208248251
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.511810937
Short name T1251
Test name
Test status
Simulation time 39609098 ps
CPU time 0.6 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:48:13 PM PDT 24
Peak memory 203904 kb
Host smart-3fa55b28-9926-419e-996c-79a26362be44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511810937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.511810937
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2998273455
Short name T1027
Test name
Test status
Simulation time 48110027 ps
CPU time 1.41 seconds
Started May 02 01:48:06 PM PDT 24
Finished May 02 01:48:08 PM PDT 24
Peak memory 204260 kb
Host smart-304df4b8-59a2-416b-a644-20363b2aa1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998273455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2998273455
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.129468907
Short name T628
Test name
Test status
Simulation time 1204400276 ps
CPU time 5.75 seconds
Started May 02 01:47:56 PM PDT 24
Finished May 02 01:48:03 PM PDT 24
Peak memory 264688 kb
Host smart-92f708c1-936c-4e5b-a269-e31e7564d94e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129468907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.129468907
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.676220027
Short name T999
Test name
Test status
Simulation time 6779358681 ps
CPU time 41.2 seconds
Started May 02 01:48:03 PM PDT 24
Finished May 02 01:48:45 PM PDT 24
Peak memory 360708 kb
Host smart-9cd2af23-2f67-4ca4-84d4-931ab21396e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676220027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.676220027
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1292650255
Short name T966
Test name
Test status
Simulation time 5830054275 ps
CPU time 47.17 seconds
Started May 02 01:47:55 PM PDT 24
Finished May 02 01:48:43 PM PDT 24
Peak memory 582288 kb
Host smart-8a5ddae6-d571-4e60-8b23-22061eee43d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292650255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1292650255
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.212396888
Short name T340
Test name
Test status
Simulation time 528093449 ps
CPU time 1.1 seconds
Started May 02 01:47:57 PM PDT 24
Finished May 02 01:47:59 PM PDT 24
Peak memory 204132 kb
Host smart-ccea951f-d0a4-4d0b-9001-b2d3b52de42f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212396888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.212396888
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2762169403
Short name T909
Test name
Test status
Simulation time 296638813 ps
CPU time 3.94 seconds
Started May 02 01:48:08 PM PDT 24
Finished May 02 01:48:13 PM PDT 24
Peak memory 204100 kb
Host smart-f955646d-ce50-4599-865f-5877bfe8903e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762169403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2762169403
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2270336513
Short name T593
Test name
Test status
Simulation time 27160495557 ps
CPU time 199.92 seconds
Started May 02 01:47:58 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 870684 kb
Host smart-0f101c24-e944-4a1c-9487-b6178f7fd871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270336513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2270336513
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3392302979
Short name T855
Test name
Test status
Simulation time 286058767 ps
CPU time 7.6 seconds
Started May 02 01:48:12 PM PDT 24
Finished May 02 01:48:21 PM PDT 24
Peak memory 204076 kb
Host smart-7af7819f-026d-45db-895e-2c7b940cc5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392302979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3392302979
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1827442639
Short name T1205
Test name
Test status
Simulation time 8097317882 ps
CPU time 35.41 seconds
Started May 02 01:48:15 PM PDT 24
Finished May 02 01:48:51 PM PDT 24
Peak memory 358192 kb
Host smart-90295293-fa8e-4dcb-9865-9892356b1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827442639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1827442639
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_perf.4009187618
Short name T292
Test name
Test status
Simulation time 3013766112 ps
CPU time 17.38 seconds
Started May 02 01:48:04 PM PDT 24
Finished May 02 01:48:22 PM PDT 24
Peak memory 212668 kb
Host smart-27827d65-588f-4bb7-a63d-8df92328d3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009187618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.4009187618
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2890414983
Short name T1234
Test name
Test status
Simulation time 4984400486 ps
CPU time 21.64 seconds
Started May 02 01:47:57 PM PDT 24
Finished May 02 01:48:20 PM PDT 24
Peak memory 298148 kb
Host smart-c5f0a82c-8116-432c-94bc-65afe4137ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890414983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2890414983
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.120105481
Short name T63
Test name
Test status
Simulation time 344083584 ps
CPU time 7.12 seconds
Started May 02 01:48:05 PM PDT 24
Finished May 02 01:48:13 PM PDT 24
Peak memory 212336 kb
Host smart-d2a0292c-5d3b-49ac-9dfc-aa106998cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120105481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.120105481
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1993362742
Short name T1182
Test name
Test status
Simulation time 683551757 ps
CPU time 3.29 seconds
Started May 02 01:48:05 PM PDT 24
Finished May 02 01:48:09 PM PDT 24
Peak memory 204120 kb
Host smart-a70bd287-51ef-45ec-939a-1143b4cb78ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993362742 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1993362742
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2580741224
Short name T649
Test name
Test status
Simulation time 10056483670 ps
CPU time 73.76 seconds
Started May 02 01:48:06 PM PDT 24
Finished May 02 01:49:20 PM PDT 24
Peak memory 469268 kb
Host smart-a687afb6-6733-4da0-a857-b9d65a17d016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580741224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2580741224
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2244937776
Short name T1050
Test name
Test status
Simulation time 10334176328 ps
CPU time 31.29 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:48:43 PM PDT 24
Peak memory 351496 kb
Host smart-093098a7-0786-4d67-9450-5bdce2bb74ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244937776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2244937776
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1893054590
Short name T1275
Test name
Test status
Simulation time 429232134 ps
CPU time 2.48 seconds
Started May 02 01:48:04 PM PDT 24
Finished May 02 01:48:07 PM PDT 24
Peak memory 204208 kb
Host smart-05adab6d-2dd0-441a-9b30-f1fe13a089e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893054590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1893054590
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1290382651
Short name T31
Test name
Test status
Simulation time 937289968 ps
CPU time 5.01 seconds
Started May 02 01:48:05 PM PDT 24
Finished May 02 01:48:10 PM PDT 24
Peak memory 212412 kb
Host smart-e4014a73-4b26-41d7-b1de-c817eefd5d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290382651 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1290382651
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2999836261
Short name T994
Test name
Test status
Simulation time 6628770376 ps
CPU time 7.88 seconds
Started May 02 01:48:04 PM PDT 24
Finished May 02 01:48:12 PM PDT 24
Peak memory 204248 kb
Host smart-98d1aacd-6574-4f6c-b45d-f132311afe8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999836261 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2999836261
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2335455219
Short name T346
Test name
Test status
Simulation time 696248366 ps
CPU time 9.41 seconds
Started May 02 01:48:03 PM PDT 24
Finished May 02 01:48:13 PM PDT 24
Peak memory 204212 kb
Host smart-02703e2d-9770-4c14-9f70-45ad64d72292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335455219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2335455219
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1736884760
Short name T295
Test name
Test status
Simulation time 380461363 ps
CPU time 5.88 seconds
Started May 02 01:48:10 PM PDT 24
Finished May 02 01:48:17 PM PDT 24
Peak memory 204176 kb
Host smart-991f0254-c450-4f36-b7cc-3c0bd9b42440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736884760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1736884760
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3578642684
Short name T506
Test name
Test status
Simulation time 58130977676 ps
CPU time 1099.62 seconds
Started May 02 01:48:07 PM PDT 24
Finished May 02 02:06:28 PM PDT 24
Peak memory 7760668 kb
Host smart-a2f7eb1f-cfc3-4fc0-8372-74e0324a3181
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578642684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3578642684
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3669313962
Short name T338
Test name
Test status
Simulation time 26136598125 ps
CPU time 1683.06 seconds
Started May 02 01:48:04 PM PDT 24
Finished May 02 02:16:08 PM PDT 24
Peak memory 6337432 kb
Host smart-27243648-84f1-49de-ac71-d1e790397aa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669313962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3669313962
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.972915894
Short name T1148
Test name
Test status
Simulation time 2729273247 ps
CPU time 6.48 seconds
Started May 02 01:48:03 PM PDT 24
Finished May 02 01:48:10 PM PDT 24
Peak memory 204208 kb
Host smart-a1abcc2d-d534-4eb3-b8fd-60d0afa41aa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972915894 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.972915894
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3386890639
Short name T938
Test name
Test status
Simulation time 46259041 ps
CPU time 0.61 seconds
Started May 02 01:48:20 PM PDT 24
Finished May 02 01:48:22 PM PDT 24
Peak memory 203900 kb
Host smart-158d5020-b0cb-4f9f-9970-66ef2be512dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386890639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3386890639
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2975113619
Short name T333
Test name
Test status
Simulation time 315224679 ps
CPU time 1.4 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:48:14 PM PDT 24
Peak memory 212480 kb
Host smart-34c35e3b-6004-4bca-adea-ca047bb34e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975113619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2975113619
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2991369988
Short name T854
Test name
Test status
Simulation time 315689384 ps
CPU time 6.93 seconds
Started May 02 01:48:13 PM PDT 24
Finished May 02 01:48:20 PM PDT 24
Peak memory 265756 kb
Host smart-503ac127-0736-4427-b251-2d18e267ce85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991369988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2991369988
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1586387703
Short name T637
Test name
Test status
Simulation time 7323956574 ps
CPU time 45.28 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:48:57 PM PDT 24
Peak memory 471596 kb
Host smart-606653b1-ac0d-45d4-8aad-d1e4168ae59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586387703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1586387703
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2505983673
Short name T460
Test name
Test status
Simulation time 1253564421 ps
CPU time 29.16 seconds
Started May 02 01:48:14 PM PDT 24
Finished May 02 01:48:44 PM PDT 24
Peak memory 331244 kb
Host smart-c53c4545-7760-49de-a84f-93483a8f580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505983673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2505983673
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2967888945
Short name T78
Test name
Test status
Simulation time 103592214 ps
CPU time 0.96 seconds
Started May 02 01:48:21 PM PDT 24
Finished May 02 01:48:24 PM PDT 24
Peak memory 203984 kb
Host smart-a6c0ff0c-e2b6-437e-9f29-efa2889c498e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967888945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2967888945
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4165612274
Short name T433
Test name
Test status
Simulation time 529426027 ps
CPU time 3.4 seconds
Started May 02 01:48:12 PM PDT 24
Finished May 02 01:48:17 PM PDT 24
Peak memory 224212 kb
Host smart-d64ea8ec-10dc-4d21-b235-69f515d1d6ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165612274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4165612274
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.681918420
Short name T1152
Test name
Test status
Simulation time 2617594455 ps
CPU time 59.11 seconds
Started May 02 01:48:10 PM PDT 24
Finished May 02 01:49:10 PM PDT 24
Peak memory 852268 kb
Host smart-9c13742c-b6d7-48bf-b842-cbaea3a2333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681918420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.681918420
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.4261741981
Short name T626
Test name
Test status
Simulation time 290259382 ps
CPU time 4.76 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:48:25 PM PDT 24
Peak memory 204132 kb
Host smart-7aa7b0be-0336-4069-94f0-869711584eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261741981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.4261741981
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.4071813509
Short name T74
Test name
Test status
Simulation time 1211149903 ps
CPU time 18.72 seconds
Started May 02 01:48:21 PM PDT 24
Finished May 02 01:48:41 PM PDT 24
Peak memory 306152 kb
Host smart-dba4e8c0-9117-409c-abcd-fce5411cdf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071813509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.4071813509
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2831237963
Short name T35
Test name
Test status
Simulation time 89140296 ps
CPU time 0.65 seconds
Started May 02 01:48:37 PM PDT 24
Finished May 02 01:48:38 PM PDT 24
Peak memory 203784 kb
Host smart-214b5606-2915-497c-be08-134f2fc68ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831237963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2831237963
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1034724196
Short name T509
Test name
Test status
Simulation time 2772916141 ps
CPU time 9 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:48:21 PM PDT 24
Peak memory 221184 kb
Host smart-025e3e00-ee8f-4321-9657-a004785a7395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034724196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1034724196
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3458837364
Short name T246
Test name
Test status
Simulation time 3009540428 ps
CPU time 66.24 seconds
Started May 02 01:48:12 PM PDT 24
Finished May 02 01:49:19 PM PDT 24
Peak memory 302516 kb
Host smart-44d6c2b0-538c-495c-9961-9d08be27c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458837364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3458837364
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.2888108152
Short name T58
Test name
Test status
Simulation time 44687108591 ps
CPU time 1012.05 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 02:05:04 PM PDT 24
Peak memory 1991584 kb
Host smart-6d87ed58-cc32-46a2-b9ca-480c37e01fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888108152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2888108152
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3269329479
Short name T307
Test name
Test status
Simulation time 1304889134 ps
CPU time 9.4 seconds
Started May 02 01:48:17 PM PDT 24
Finished May 02 01:48:28 PM PDT 24
Peak memory 220524 kb
Host smart-736124e3-f509-4119-a684-6920639fe73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269329479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3269329479
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2529113512
Short name T980
Test name
Test status
Simulation time 1029752810 ps
CPU time 2.04 seconds
Started May 02 01:48:20 PM PDT 24
Finished May 02 01:48:24 PM PDT 24
Peak memory 204036 kb
Host smart-a3eb28fb-3b8b-419c-89b0-39ee078be914
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529113512 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2529113512
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2496848700
Short name T1136
Test name
Test status
Simulation time 10092450048 ps
CPU time 57.64 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:49:19 PM PDT 24
Peak memory 518236 kb
Host smart-32d8b8e8-b80c-4268-b9f1-d734855ad67c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496848700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2496848700
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1242196948
Short name T958
Test name
Test status
Simulation time 10261821708 ps
CPU time 10.5 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:48:31 PM PDT 24
Peak memory 247564 kb
Host smart-697c48d2-a516-47a5-a29f-f26a8a772245
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242196948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1242196948
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.808176588
Short name T1258
Test name
Test status
Simulation time 1418287926 ps
CPU time 1.9 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:48:23 PM PDT 24
Peak memory 204184 kb
Host smart-2f5d2c46-150a-4edd-b028-d16087c9ae35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808176588 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_hrst.808176588
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3877671379
Short name T312
Test name
Test status
Simulation time 5292694742 ps
CPU time 7.13 seconds
Started May 02 01:48:20 PM PDT 24
Finished May 02 01:48:29 PM PDT 24
Peak memory 218968 kb
Host smart-d124743d-c10b-4e6a-b438-cfe014a48cc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877671379 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3877671379
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2942435248
Short name T534
Test name
Test status
Simulation time 10028803368 ps
CPU time 40.53 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:49:01 PM PDT 24
Peak memory 817720 kb
Host smart-cccb9826-a338-4e06-96f2-8749da836baa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942435248 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2942435248
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2533421886
Short name T1017
Test name
Test status
Simulation time 9944556599 ps
CPU time 9.32 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:48:21 PM PDT 24
Peak memory 204160 kb
Host smart-3c50fdf0-24d4-446d-bbb1-32062ad650f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533421886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2533421886
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2265763891
Short name T32
Test name
Test status
Simulation time 487018793 ps
CPU time 8.72 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:48:21 PM PDT 24
Peak memory 205908 kb
Host smart-3e69db92-411a-4381-97d4-2ba7627835bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265763891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2265763891
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.4144352437
Short name T473
Test name
Test status
Simulation time 46448936642 ps
CPU time 119.09 seconds
Started May 02 01:48:11 PM PDT 24
Finished May 02 01:50:10 PM PDT 24
Peak memory 1689152 kb
Host smart-af65ef66-c277-4a3c-af23-3b4c14642be1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144352437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.4144352437
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.2081599217
Short name T392
Test name
Test status
Simulation time 27331353095 ps
CPU time 1997.74 seconds
Started May 02 01:48:12 PM PDT 24
Finished May 02 02:21:30 PM PDT 24
Peak memory 3359316 kb
Host smart-760d5971-8b0f-46dc-b895-b43ec7df7785
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081599217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.2081599217
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.599814518
Short name T496
Test name
Test status
Simulation time 1539623673 ps
CPU time 7.17 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:48:28 PM PDT 24
Peak memory 220396 kb
Host smart-3e310f5c-0f72-4536-ac14-df0a67628e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599814518 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.599814518
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.585244650
Short name T991
Test name
Test status
Simulation time 28681463 ps
CPU time 0.6 seconds
Started May 02 01:48:46 PM PDT 24
Finished May 02 01:48:47 PM PDT 24
Peak memory 203860 kb
Host smart-46111d9f-71b7-4d1e-809f-08b5dcb11d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585244650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.585244650
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2762302831
Short name T102
Test name
Test status
Simulation time 439412529 ps
CPU time 1.49 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:48:32 PM PDT 24
Peak memory 212452 kb
Host smart-9f97e7d5-98a3-4489-a7d0-1dfb932b2ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762302831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2762302831
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3096393036
Short name T268
Test name
Test status
Simulation time 375293297 ps
CPU time 6.92 seconds
Started May 02 01:48:32 PM PDT 24
Finished May 02 01:48:39 PM PDT 24
Peak memory 282216 kb
Host smart-292a5261-f0c8-4f05-9cfe-4dfd4dab36ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096393036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.3096393036
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.1705607863
Short name T42
Test name
Test status
Simulation time 15719467209 ps
CPU time 147.04 seconds
Started May 02 01:48:29 PM PDT 24
Finished May 02 01:50:57 PM PDT 24
Peak memory 684708 kb
Host smart-3d61a29a-99d6-44d0-9402-36a834a801e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705607863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1705607863
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1774217886
Short name T443
Test name
Test status
Simulation time 6199459853 ps
CPU time 106.14 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:50:07 PM PDT 24
Peak memory 576064 kb
Host smart-d66e73b7-74e8-4b5f-b429-5d282eacf96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774217886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1774217886
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3452978298
Short name T711
Test name
Test status
Simulation time 136123830 ps
CPU time 1 seconds
Started May 02 01:48:18 PM PDT 24
Finished May 02 01:48:21 PM PDT 24
Peak memory 203980 kb
Host smart-e80f33c2-1712-4329-9ed6-9313623127ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452978298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3452978298
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1841437678
Short name T798
Test name
Test status
Simulation time 103006083 ps
CPU time 2.42 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:48:33 PM PDT 24
Peak memory 204212 kb
Host smart-505707a7-725a-4124-8fe0-aa8e94ac755e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841437678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1841437678
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3927849953
Short name T1010
Test name
Test status
Simulation time 4516532295 ps
CPU time 140.81 seconds
Started May 02 01:48:18 PM PDT 24
Finished May 02 01:50:41 PM PDT 24
Peak memory 1302348 kb
Host smart-ff3b090a-7780-4141-9585-6806b668fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927849953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3927849953
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2476609787
Short name T880
Test name
Test status
Simulation time 840782830 ps
CPU time 17.12 seconds
Started May 02 01:48:46 PM PDT 24
Finished May 02 01:49:04 PM PDT 24
Peak memory 204152 kb
Host smart-0f14d0f1-6efb-4e36-8d6c-3c8d44331a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476609787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2476609787
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3945872417
Short name T348
Test name
Test status
Simulation time 6430324048 ps
CPU time 25.88 seconds
Started May 02 01:48:45 PM PDT 24
Finished May 02 01:49:12 PM PDT 24
Peak memory 342536 kb
Host smart-38fe7027-739d-43ee-9b5e-90401ddf1126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945872417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3945872417
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1855744516
Short name T96
Test name
Test status
Simulation time 110050536 ps
CPU time 0.63 seconds
Started May 02 01:48:19 PM PDT 24
Finished May 02 01:48:21 PM PDT 24
Peak memory 203752 kb
Host smart-5283c980-62e5-4995-ba2e-808cf34ab394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855744516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1855744516
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.944571136
Short name T984
Test name
Test status
Simulation time 51903391372 ps
CPU time 152.07 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 220612 kb
Host smart-29698554-b892-4642-b146-a8119a78ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944571136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.944571136
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.974639857
Short name T286
Test name
Test status
Simulation time 5442762504 ps
CPU time 23.68 seconds
Started May 02 01:48:20 PM PDT 24
Finished May 02 01:48:45 PM PDT 24
Peak memory 280276 kb
Host smart-bf902554-f1c7-495a-97e5-c38b54bd1b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974639857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.974639857
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.174069498
Short name T939
Test name
Test status
Simulation time 4637504389 ps
CPU time 7.02 seconds
Started May 02 01:48:31 PM PDT 24
Finished May 02 01:48:39 PM PDT 24
Peak memory 212392 kb
Host smart-71d6a4bd-fc79-402e-904a-a421055de172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174069498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.174069498
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2085827725
Short name T255
Test name
Test status
Simulation time 1019652067 ps
CPU time 4.75 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:48:35 PM PDT 24
Peak memory 212392 kb
Host smart-ac3a3d8f-68da-4ecb-94a8-3db35714b03e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085827725 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2085827725
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1988765074
Short name T1073
Test name
Test status
Simulation time 10062447047 ps
CPU time 60.01 seconds
Started May 02 01:48:29 PM PDT 24
Finished May 02 01:49:29 PM PDT 24
Peak memory 472256 kb
Host smart-d16e1f8e-58f4-47a7-b3b4-d716d6dcc94a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988765074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1988765074
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.909175039
Short name T124
Test name
Test status
Simulation time 10421674645 ps
CPU time 14.56 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:48:46 PM PDT 24
Peak memory 286804 kb
Host smart-226bbdbc-6887-4207-8f58-fc6addb0f220
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909175039 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.909175039
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.4021813584
Short name T25
Test name
Test status
Simulation time 710011356 ps
CPU time 2.24 seconds
Started May 02 01:48:29 PM PDT 24
Finished May 02 01:48:32 PM PDT 24
Peak memory 204180 kb
Host smart-b1b6782d-e215-48b8-bfa2-983529db8aba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021813584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.4021813584
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.352957410
Short name T745
Test name
Test status
Simulation time 4484785125 ps
CPU time 5.3 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:48:36 PM PDT 24
Peak memory 212832 kb
Host smart-0d60a4c5-97e4-4587-b8dc-1cb7d5fe687b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352957410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.352957410
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1957454248
Short name T306
Test name
Test status
Simulation time 7173635663 ps
CPU time 14.02 seconds
Started May 02 01:48:31 PM PDT 24
Finished May 02 01:48:46 PM PDT 24
Peak memory 227064 kb
Host smart-60bdaa34-a0c6-4f7e-bf1a-ba6819488d14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957454248 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1957454248
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3020496893
Short name T752
Test name
Test status
Simulation time 2124746761 ps
CPU time 19.85 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:48:51 PM PDT 24
Peak memory 204148 kb
Host smart-29b3d4a4-11f0-4728-bd52-a4ba11272785
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020496893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3020496893
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.238435562
Short name T1016
Test name
Test status
Simulation time 7942423078 ps
CPU time 28.22 seconds
Started May 02 01:48:31 PM PDT 24
Finished May 02 01:49:01 PM PDT 24
Peak memory 236228 kb
Host smart-a8f9dcba-e11b-4bd4-b1d9-4e22bb540392
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238435562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.238435562
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2561054768
Short name T61
Test name
Test status
Simulation time 10644151373 ps
CPU time 10.91 seconds
Started May 02 01:48:29 PM PDT 24
Finished May 02 01:48:41 PM PDT 24
Peak memory 204224 kb
Host smart-eb806aba-409b-4ea8-80f0-c14b72221051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561054768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2561054768
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.869383126
Short name T985
Test name
Test status
Simulation time 1070617122 ps
CPU time 5.95 seconds
Started May 02 01:48:30 PM PDT 24
Finished May 02 01:48:37 PM PDT 24
Peak memory 211124 kb
Host smart-78ae21e3-6bd7-4b6f-b65b-731884b91551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869383126 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.869383126
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2446378005
Short name T355
Test name
Test status
Simulation time 17961116 ps
CPU time 0.65 seconds
Started May 02 01:42:28 PM PDT 24
Finished May 02 01:42:30 PM PDT 24
Peak memory 203896 kb
Host smart-d1493593-6fc0-4529-bc6a-709865b9d148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446378005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2446378005
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.46683931
Short name T448
Test name
Test status
Simulation time 271012041 ps
CPU time 1.32 seconds
Started May 02 01:42:19 PM PDT 24
Finished May 02 01:42:21 PM PDT 24
Peak memory 220660 kb
Host smart-232a9755-d7a0-473e-ad2a-d24888e553cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46683931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.46683931
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1436754265
Short name T717
Test name
Test status
Simulation time 698732878 ps
CPU time 7.08 seconds
Started May 02 01:42:17 PM PDT 24
Finished May 02 01:42:25 PM PDT 24
Peak memory 280180 kb
Host smart-0c6b6b1f-cf9e-4f44-a98f-bfe863958233
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436754265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1436754265
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.852270148
Short name T1169
Test name
Test status
Simulation time 4554819826 ps
CPU time 38.2 seconds
Started May 02 01:42:17 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 477572 kb
Host smart-5a12308d-b189-4ded-88ff-990dd3abbd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852270148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.852270148
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.253376973
Short name T499
Test name
Test status
Simulation time 1373600957 ps
CPU time 87.35 seconds
Started May 02 01:42:16 PM PDT 24
Finished May 02 01:43:45 PM PDT 24
Peak memory 510544 kb
Host smart-a44f74e5-f86f-4c24-a309-9311367b4d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253376973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.253376973
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1828810073
Short name T946
Test name
Test status
Simulation time 101413549 ps
CPU time 1.06 seconds
Started May 02 01:42:22 PM PDT 24
Finished May 02 01:42:24 PM PDT 24
Peak memory 204092 kb
Host smart-8325e7e1-0a52-4244-ba40-1f292ec92a5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828810073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1828810073
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3645979594
Short name T591
Test name
Test status
Simulation time 174906649 ps
CPU time 10.26 seconds
Started May 02 01:42:17 PM PDT 24
Finished May 02 01:42:28 PM PDT 24
Peak memory 237472 kb
Host smart-5ab9ce0f-f700-4167-a4ab-b8173e7845fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645979594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3645979594
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2586972119
Short name T733
Test name
Test status
Simulation time 44795577277 ps
CPU time 279.7 seconds
Started May 02 01:42:23 PM PDT 24
Finished May 02 01:47:03 PM PDT 24
Peak memory 1067304 kb
Host smart-ff0203b1-592b-4daf-93a6-9ca6a694524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586972119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2586972119
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.1203631779
Short name T480
Test name
Test status
Simulation time 267537540 ps
CPU time 3.46 seconds
Started May 02 01:42:28 PM PDT 24
Finished May 02 01:42:33 PM PDT 24
Peak memory 204172 kb
Host smart-bbca64a9-c80d-455a-bce6-50649eb1b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203631779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.1203631779
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3145996855
Short name T1229
Test name
Test status
Simulation time 1355968149 ps
CPU time 61.04 seconds
Started May 02 01:42:28 PM PDT 24
Finished May 02 01:43:30 PM PDT 24
Peak memory 326080 kb
Host smart-57e303d6-0820-498e-a726-e9510b03b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145996855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3145996855
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3355688523
Short name T189
Test name
Test status
Simulation time 47255257 ps
CPU time 0.68 seconds
Started May 02 01:42:18 PM PDT 24
Finished May 02 01:42:20 PM PDT 24
Peak memory 203848 kb
Host smart-0bdc68ee-774a-49f5-a2d7-4ce0f5c9cee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355688523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3355688523
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1962571722
Short name T80
Test name
Test status
Simulation time 3811851631 ps
CPU time 19.91 seconds
Started May 02 01:42:16 PM PDT 24
Finished May 02 01:42:36 PM PDT 24
Peak memory 374508 kb
Host smart-7d1bce95-ea95-4726-a633-fc983b58560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962571722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1962571722
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3775106414
Short name T848
Test name
Test status
Simulation time 5833051496 ps
CPU time 21.01 seconds
Started May 02 01:42:16 PM PDT 24
Finished May 02 01:42:38 PM PDT 24
Peak memory 298148 kb
Host smart-5989be5a-3954-4bfb-b263-652154408d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775106414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3775106414
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3278694392
Short name T183
Test name
Test status
Simulation time 117205635318 ps
CPU time 926.43 seconds
Started May 02 01:42:22 PM PDT 24
Finished May 02 01:57:49 PM PDT 24
Peak memory 2566600 kb
Host smart-6303b0c1-b76b-4d1e-a316-905eb99c5a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278694392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3278694392
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2177291177
Short name T1262
Test name
Test status
Simulation time 1774611235 ps
CPU time 20.19 seconds
Started May 02 01:42:24 PM PDT 24
Finished May 02 01:42:45 PM PDT 24
Peak memory 212372 kb
Host smart-21924d89-5032-4afb-9f2c-3caf8492cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177291177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2177291177
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1022521392
Short name T118
Test name
Test status
Simulation time 36516172 ps
CPU time 0.83 seconds
Started May 02 01:42:25 PM PDT 24
Finished May 02 01:42:27 PM PDT 24
Peak memory 221456 kb
Host smart-6ba8a85d-0f79-402c-ad0d-18fa2b6d1846
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022521392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1022521392
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3020710138
Short name T625
Test name
Test status
Simulation time 7711632111 ps
CPU time 4.19 seconds
Started May 02 01:42:27 PM PDT 24
Finished May 02 01:42:32 PM PDT 24
Peak memory 204248 kb
Host smart-d8dbe7ed-c3c8-44e6-a35d-f3bd8bcdc6fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020710138 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3020710138
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1219715979
Short name T1254
Test name
Test status
Simulation time 10145436471 ps
CPU time 14.26 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:45 PM PDT 24
Peak memory 290608 kb
Host smart-310bc3a2-82a7-4dcd-99a4-f43f6328f92b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219715979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1219715979
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3312106095
Short name T1337
Test name
Test status
Simulation time 10078714057 ps
CPU time 40.44 seconds
Started May 02 01:42:28 PM PDT 24
Finished May 02 01:43:09 PM PDT 24
Peak memory 368256 kb
Host smart-6c8d570b-bd1f-49c3-959f-f91693039203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312106095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3312106095
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3885494167
Short name T1285
Test name
Test status
Simulation time 466656280 ps
CPU time 2.8 seconds
Started May 02 01:42:25 PM PDT 24
Finished May 02 01:42:29 PM PDT 24
Peak memory 204064 kb
Host smart-e05a39c8-2263-4ac2-a12d-6038e7e5754e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885494167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3885494167
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1591867889
Short name T525
Test name
Test status
Simulation time 1254748305 ps
CPU time 6.07 seconds
Started May 02 01:42:20 PM PDT 24
Finished May 02 01:42:26 PM PDT 24
Peak memory 217552 kb
Host smart-2a04ee6e-d674-4e2f-9f1d-4835f5cc4015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591867889 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1591867889
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.712590306
Short name T462
Test name
Test status
Simulation time 22687735145 ps
CPU time 460.25 seconds
Started May 02 01:42:17 PM PDT 24
Finished May 02 01:49:58 PM PDT 24
Peak memory 4060964 kb
Host smart-364e1fce-9764-4be9-9903-3efc0ec4fa2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712590306 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.712590306
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3015089603
Short name T1304
Test name
Test status
Simulation time 1786153759 ps
CPU time 26.82 seconds
Started May 02 01:42:47 PM PDT 24
Finished May 02 01:43:14 PM PDT 24
Peak memory 204144 kb
Host smart-c39c99a8-ead9-4d3c-bfd7-d0f85388f750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015089603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3015089603
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1679684489
Short name T955
Test name
Test status
Simulation time 13149236144 ps
CPU time 12.29 seconds
Started May 02 01:42:16 PM PDT 24
Finished May 02 01:42:30 PM PDT 24
Peak memory 211248 kb
Host smart-db3a91fd-787a-4cbf-869a-f4133ba64c8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679684489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1679684489
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2516886226
Short name T1103
Test name
Test status
Simulation time 24084152210 ps
CPU time 72.03 seconds
Started May 02 01:42:21 PM PDT 24
Finished May 02 01:43:34 PM PDT 24
Peak memory 1142244 kb
Host smart-4c30c281-12b2-4a18-bbad-430f52379c03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516886226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2516886226
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3277941121
Short name T1204
Test name
Test status
Simulation time 8628901967 ps
CPU time 13.57 seconds
Started May 02 01:42:18 PM PDT 24
Finished May 02 01:42:32 PM PDT 24
Peak memory 221880 kb
Host smart-d34d2d0f-7704-48e8-845b-99a1dff8bd3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277941121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3277941121
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1517867326
Short name T452
Test name
Test status
Simulation time 5784825821 ps
CPU time 6.12 seconds
Started May 02 01:42:26 PM PDT 24
Finished May 02 01:42:34 PM PDT 24
Peak memory 212416 kb
Host smart-0992dd96-402c-434f-b9f3-e244676382f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517867326 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1517867326
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1825146472
Short name T1245
Test name
Test status
Simulation time 18487287 ps
CPU time 0.62 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:48:57 PM PDT 24
Peak memory 203800 kb
Host smart-13ff8f86-2970-43ac-98fa-31954205cc0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825146472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1825146472
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2185755273
Short name T419
Test name
Test status
Simulation time 218337586 ps
CPU time 1.64 seconds
Started May 02 01:48:48 PM PDT 24
Finished May 02 01:48:51 PM PDT 24
Peak memory 215536 kb
Host smart-579b6548-3f9a-4fe0-a2d7-5a6e8aadbc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185755273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2185755273
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1776376105
Short name T481
Test name
Test status
Simulation time 1085435531 ps
CPU time 10.11 seconds
Started May 02 01:48:49 PM PDT 24
Finished May 02 01:48:59 PM PDT 24
Peak memory 322560 kb
Host smart-785b6ac0-4977-436e-99b6-792c87a7b34e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776376105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1776376105
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2438628525
Short name T86
Test name
Test status
Simulation time 3479248284 ps
CPU time 62.88 seconds
Started May 02 01:48:47 PM PDT 24
Finished May 02 01:49:51 PM PDT 24
Peak memory 620248 kb
Host smart-f7a12dcb-0f44-4088-b56b-d659918334fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438628525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2438628525
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2626373671
Short name T826
Test name
Test status
Simulation time 12949306875 ps
CPU time 35.21 seconds
Started May 02 01:48:48 PM PDT 24
Finished May 02 01:49:24 PM PDT 24
Peak memory 524604 kb
Host smart-e4ad73dc-4726-45ac-b3fd-4d4d02fca87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626373671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2626373671
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1105576737
Short name T543
Test name
Test status
Simulation time 363772409 ps
CPU time 0.94 seconds
Started May 02 01:48:46 PM PDT 24
Finished May 02 01:48:48 PM PDT 24
Peak memory 203980 kb
Host smart-3082c7c4-ec4c-4472-8e04-336f51bda7c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105576737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1105576737
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.649864711
Short name T564
Test name
Test status
Simulation time 1005069686 ps
CPU time 2.71 seconds
Started May 02 01:48:47 PM PDT 24
Finished May 02 01:48:51 PM PDT 24
Peak memory 204192 kb
Host smart-a11da840-29ca-4fc6-9844-198f826d957c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649864711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
649864711
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3803327505
Short name T759
Test name
Test status
Simulation time 2649167771 ps
CPU time 61.55 seconds
Started May 02 01:48:47 PM PDT 24
Finished May 02 01:49:50 PM PDT 24
Peak memory 833784 kb
Host smart-4879cfb1-8b51-4753-9782-87b35f663d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803327505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3803327505
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1642792095
Short name T895
Test name
Test status
Simulation time 1146640378 ps
CPU time 8.73 seconds
Started May 02 01:48:57 PM PDT 24
Finished May 02 01:49:07 PM PDT 24
Peak memory 204152 kb
Host smart-9aa78545-27aa-4d7a-9dd5-1de1e04e2e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642792095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1642792095
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1832601287
Short name T1168
Test name
Test status
Simulation time 2778809503 ps
CPU time 28.52 seconds
Started May 02 01:48:48 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 366440 kb
Host smart-59730cdf-1470-4ceb-9349-9ba61ef72aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832601287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1832601287
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3991268462
Short name T1347
Test name
Test status
Simulation time 45076510 ps
CPU time 0.64 seconds
Started May 02 01:48:46 PM PDT 24
Finished May 02 01:48:48 PM PDT 24
Peak memory 203848 kb
Host smart-21f23f0d-910b-4b18-89e4-5a0f64ac67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991268462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3991268462
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.4128438302
Short name T1200
Test name
Test status
Simulation time 12800711643 ps
CPU time 66.26 seconds
Started May 02 01:48:46 PM PDT 24
Finished May 02 01:49:53 PM PDT 24
Peak memory 581544 kb
Host smart-374d34b3-8899-49bc-8e5f-a99adef6a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128438302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.4128438302
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2292808282
Short name T417
Test name
Test status
Simulation time 3436488805 ps
CPU time 43.06 seconds
Started May 02 01:48:45 PM PDT 24
Finished May 02 01:49:30 PM PDT 24
Peak memory 304792 kb
Host smart-f7097db2-dda2-4c23-908e-862b5cd2e166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292808282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2292808282
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.405967849
Short name T241
Test name
Test status
Simulation time 32330510701 ps
CPU time 955.01 seconds
Started May 02 01:48:45 PM PDT 24
Finished May 02 02:04:41 PM PDT 24
Peak memory 1294668 kb
Host smart-ac7791da-47da-403f-a811-a6121fe5467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405967849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.405967849
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.202170710
Short name T239
Test name
Test status
Simulation time 687947234 ps
CPU time 11.64 seconds
Started May 02 01:48:46 PM PDT 24
Finished May 02 01:48:59 PM PDT 24
Peak memory 228648 kb
Host smart-7355b7b8-29bb-4a73-83a2-b970cebbdd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202170710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.202170710
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3063156123
Short name T261
Test name
Test status
Simulation time 5078497702 ps
CPU time 5.8 seconds
Started May 02 01:48:49 PM PDT 24
Finished May 02 01:48:55 PM PDT 24
Peak memory 212480 kb
Host smart-b743023a-fa14-4668-9dd1-339426ac7573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063156123 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3063156123
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.36633869
Short name T665
Test name
Test status
Simulation time 10037883798 ps
CPU time 30.92 seconds
Started May 02 01:48:47 PM PDT 24
Finished May 02 01:49:20 PM PDT 24
Peak memory 313828 kb
Host smart-ece0d27e-d29f-4a5c-a9d6-3112d079fce4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36633869 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_acq.36633869
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2774155773
Short name T203
Test name
Test status
Simulation time 10125203015 ps
CPU time 88.69 seconds
Started May 02 01:48:48 PM PDT 24
Finished May 02 01:50:17 PM PDT 24
Peak memory 578124 kb
Host smart-937cea74-4f01-4583-8527-971e2fea1b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774155773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2774155773
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1614191571
Short name T633
Test name
Test status
Simulation time 423756283 ps
CPU time 2.52 seconds
Started May 02 01:48:44 PM PDT 24
Finished May 02 01:48:48 PM PDT 24
Peak memory 204180 kb
Host smart-8ab26b31-d558-4336-a747-957a8a0527f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614191571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1614191571
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2644999696
Short name T294
Test name
Test status
Simulation time 670010988 ps
CPU time 3.69 seconds
Started May 02 01:48:47 PM PDT 24
Finished May 02 01:48:52 PM PDT 24
Peak memory 204080 kb
Host smart-78d57143-2251-4994-ad4c-09068ec74d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644999696 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2644999696
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2306561496
Short name T265
Test name
Test status
Simulation time 28522478037 ps
CPU time 77.1 seconds
Started May 02 01:48:46 PM PDT 24
Finished May 02 01:50:05 PM PDT 24
Peak memory 1546204 kb
Host smart-a804dd41-cd12-457e-8ba1-9eb82c6c8067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306561496 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2306561496
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.132762716
Short name T1235
Test name
Test status
Simulation time 4038945980 ps
CPU time 35.77 seconds
Started May 02 01:48:49 PM PDT 24
Finished May 02 01:49:26 PM PDT 24
Peak memory 204252 kb
Host smart-bc1985c5-f0ac-42c4-9d0c-d8adb95c0b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132762716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.132762716
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2106569893
Short name T885
Test name
Test status
Simulation time 292260021 ps
CPU time 11.53 seconds
Started May 02 01:48:48 PM PDT 24
Finished May 02 01:49:00 PM PDT 24
Peak memory 204152 kb
Host smart-fe4aa9b7-f5a1-4e60-8762-00efe6268f61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106569893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2106569893
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2024142847
Short name T687
Test name
Test status
Simulation time 53313799799 ps
CPU time 1242.61 seconds
Started May 02 01:48:49 PM PDT 24
Finished May 02 02:09:33 PM PDT 24
Peak memory 7817768 kb
Host smart-2bdc3982-fdca-4150-9d55-83b886cc4836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024142847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2024142847
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.954513848
Short name T803
Test name
Test status
Simulation time 1601109940 ps
CPU time 7.26 seconds
Started May 02 01:48:47 PM PDT 24
Finished May 02 01:48:56 PM PDT 24
Peak memory 219548 kb
Host smart-e2fe5231-3b2b-4146-8b1c-9321e793dac7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954513848 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.954513848
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3509565479
Short name T303
Test name
Test status
Simulation time 18470272 ps
CPU time 0.62 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:48:56 PM PDT 24
Peak memory 203884 kb
Host smart-f3bc4c54-d198-4d27-a46c-abaa48b76d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509565479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3509565479
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.4064932753
Short name T479
Test name
Test status
Simulation time 108720590 ps
CPU time 1.65 seconds
Started May 02 01:48:56 PM PDT 24
Finished May 02 01:48:58 PM PDT 24
Peak memory 212432 kb
Host smart-214e42f2-131d-45a7-a617-f9859aa3cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064932753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.4064932753
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.752904123
Short name T296
Test name
Test status
Simulation time 1150814474 ps
CPU time 7.59 seconds
Started May 02 01:48:54 PM PDT 24
Finished May 02 01:49:03 PM PDT 24
Peak memory 221636 kb
Host smart-ae1b285d-1164-42f2-9566-c190d6aa5450
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752904123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.752904123
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1877242594
Short name T589
Test name
Test status
Simulation time 2086970768 ps
CPU time 68.19 seconds
Started May 02 01:48:58 PM PDT 24
Finished May 02 01:50:07 PM PDT 24
Peak memory 708040 kb
Host smart-57fb8626-1219-4c9b-89ec-609673daed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877242594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1877242594
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1721805712
Short name T1263
Test name
Test status
Simulation time 1673427263 ps
CPU time 109.79 seconds
Started May 02 01:48:58 PM PDT 24
Finished May 02 01:50:48 PM PDT 24
Peak memory 566656 kb
Host smart-ce1fda4b-3781-4b81-96d9-4f19551a6a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721805712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1721805712
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2958307234
Short name T263
Test name
Test status
Simulation time 851975364 ps
CPU time 0.8 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:48:57 PM PDT 24
Peak memory 203976 kb
Host smart-0d775dcc-1083-4328-b0ad-4082c220a51b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958307234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2958307234
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2429999845
Short name T574
Test name
Test status
Simulation time 111420062 ps
CPU time 2.72 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:48:59 PM PDT 24
Peak memory 219732 kb
Host smart-71cf5a12-e966-4c26-990b-2a4e2b092134
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429999845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2429999845
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.617710834
Short name T712
Test name
Test status
Simulation time 44932016580 ps
CPU time 265.15 seconds
Started May 02 01:48:57 PM PDT 24
Finished May 02 01:53:23 PM PDT 24
Peak memory 1098172 kb
Host smart-fd42528e-fba3-483d-a47a-34e93ae51ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617710834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.617710834
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3290259569
Short name T216
Test name
Test status
Simulation time 1707478080 ps
CPU time 15.64 seconds
Started May 02 01:48:57 PM PDT 24
Finished May 02 01:49:13 PM PDT 24
Peak memory 204132 kb
Host smart-e04044d1-fff7-4ebf-8a57-8f12a59ac05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290259569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3290259569
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.3662348455
Short name T1093
Test name
Test status
Simulation time 1089945339 ps
CPU time 18.45 seconds
Started May 02 01:48:58 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 247036 kb
Host smart-4f08a6e8-4055-4a8c-83fb-b73d5b0b9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662348455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.3662348455
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.926139232
Short name T959
Test name
Test status
Simulation time 76561549 ps
CPU time 0.63 seconds
Started May 02 01:48:56 PM PDT 24
Finished May 02 01:48:57 PM PDT 24
Peak memory 203872 kb
Host smart-56142ef1-6d75-4e21-ae36-a0342ed02234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926139232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.926139232
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.658820034
Short name T856
Test name
Test status
Simulation time 51428996864 ps
CPU time 220.31 seconds
Started May 02 01:48:58 PM PDT 24
Finished May 02 01:52:40 PM PDT 24
Peak memory 204224 kb
Host smart-d8253660-b4c8-4a55-8c4b-1afdfc7d775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658820034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.658820034
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2275619403
Short name T270
Test name
Test status
Simulation time 7243856443 ps
CPU time 34.78 seconds
Started May 02 01:48:57 PM PDT 24
Finished May 02 01:49:33 PM PDT 24
Peak memory 361164 kb
Host smart-f7653bf1-dc8e-42f5-ad15-2afed381efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275619403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2275619403
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2777222898
Short name T434
Test name
Test status
Simulation time 4571408406 ps
CPU time 18.7 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:49:14 PM PDT 24
Peak memory 212360 kb
Host smart-0d717dc4-1025-45ae-a375-b2ef9ee21f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777222898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2777222898
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.4153993021
Short name T1111
Test name
Test status
Simulation time 5921523447 ps
CPU time 3.36 seconds
Started May 02 01:48:59 PM PDT 24
Finished May 02 01:49:03 PM PDT 24
Peak memory 204228 kb
Host smart-48ae72aa-74a7-424e-b312-ae86cd098d90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153993021 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.4153993021
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.411989766
Short name T359
Test name
Test status
Simulation time 10065864507 ps
CPU time 80.46 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:50:16 PM PDT 24
Peak memory 435160 kb
Host smart-711f4b27-7d70-4d22-80f3-ba36a666d99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411989766 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.411989766
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2971447525
Short name T1335
Test name
Test status
Simulation time 10034334195 ps
CPU time 71.33 seconds
Started May 02 01:48:58 PM PDT 24
Finished May 02 01:50:10 PM PDT 24
Peak memory 488856 kb
Host smart-81db49a2-d63a-47c8-9ca1-c16f3dfa1a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971447525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2971447525
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.4151442061
Short name T598
Test name
Test status
Simulation time 449394385 ps
CPU time 2.53 seconds
Started May 02 01:48:57 PM PDT 24
Finished May 02 01:49:00 PM PDT 24
Peak memory 204180 kb
Host smart-3ca2a0e1-9a03-4308-b479-528467712b5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151442061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.4151442061
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2333024267
Short name T1120
Test name
Test status
Simulation time 1722890036 ps
CPU time 4.55 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:49:00 PM PDT 24
Peak memory 204084 kb
Host smart-ac27a4c0-1c7d-4647-a529-9df8e491959e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333024267 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2333024267
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.1853280214
Short name T915
Test name
Test status
Simulation time 12029316897 ps
CPU time 215.62 seconds
Started May 02 01:48:59 PM PDT 24
Finished May 02 01:52:36 PM PDT 24
Peak memory 3053712 kb
Host smart-2ce36d4d-fe28-4491-add2-5e3867d3cccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853280214 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1853280214
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2750034089
Short name T1029
Test name
Test status
Simulation time 1239462678 ps
CPU time 9.8 seconds
Started May 02 01:48:54 PM PDT 24
Finished May 02 01:49:05 PM PDT 24
Peak memory 204120 kb
Host smart-feacf1ec-e679-4c8f-981e-d8a23220c449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750034089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2750034089
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2078257061
Short name T1117
Test name
Test status
Simulation time 1571309774 ps
CPU time 6.22 seconds
Started May 02 01:48:59 PM PDT 24
Finished May 02 01:49:06 PM PDT 24
Peak memory 204576 kb
Host smart-826ac09d-bfae-4bc4-8202-b524b1035767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078257061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2078257061
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1080875126
Short name T943
Test name
Test status
Simulation time 50504530185 ps
CPU time 361.2 seconds
Started May 02 01:48:55 PM PDT 24
Finished May 02 01:54:57 PM PDT 24
Peak memory 3517064 kb
Host smart-ff23a285-1664-4eb7-aec6-594e431b09fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080875126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1080875126
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.472072412
Short name T257
Test name
Test status
Simulation time 30228291162 ps
CPU time 602.72 seconds
Started May 02 01:49:00 PM PDT 24
Finished May 02 01:59:03 PM PDT 24
Peak memory 1729812 kb
Host smart-c087a1da-66c3-4730-b992-529025a64dc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472072412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.472072412
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2399796093
Short name T867
Test name
Test status
Simulation time 6445018610 ps
CPU time 6.29 seconds
Started May 02 01:48:57 PM PDT 24
Finished May 02 01:49:04 PM PDT 24
Peak memory 204212 kb
Host smart-9996b96e-60bb-406b-9269-bab1455ffef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399796093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2399796093
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.755259091
Short name T834
Test name
Test status
Simulation time 18354515 ps
CPU time 0.6 seconds
Started May 02 01:49:10 PM PDT 24
Finished May 02 01:49:12 PM PDT 24
Peak memory 203880 kb
Host smart-be5c1d22-6582-437b-8413-47c574ab9875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755259091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.755259091
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3943344450
Short name T397
Test name
Test status
Simulation time 279018377 ps
CPU time 1.84 seconds
Started May 02 01:49:04 PM PDT 24
Finished May 02 01:49:07 PM PDT 24
Peak memory 212464 kb
Host smart-cbfc1416-0841-450c-8979-3f0f0e13cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943344450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3943344450
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3204004015
Short name T1319
Test name
Test status
Simulation time 433591513 ps
CPU time 9.07 seconds
Started May 02 01:49:04 PM PDT 24
Finished May 02 01:49:14 PM PDT 24
Peak memory 287236 kb
Host smart-a90eea4d-5d47-4183-8a24-1d485c8a48cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204004015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3204004015
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3632439749
Short name T318
Test name
Test status
Simulation time 1452955494 ps
CPU time 78.13 seconds
Started May 02 01:49:04 PM PDT 24
Finished May 02 01:50:23 PM PDT 24
Peak memory 346872 kb
Host smart-4b5883cd-c8f2-4d29-be2a-9cf93e672c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632439749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3632439749
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1639874087
Short name T1140
Test name
Test status
Simulation time 1747178668 ps
CPU time 81.1 seconds
Started May 02 01:48:59 PM PDT 24
Finished May 02 01:50:21 PM PDT 24
Peak memory 482004 kb
Host smart-94daf313-47f2-4b26-86c6-4a890d9a4fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639874087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1639874087
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3995137037
Short name T845
Test name
Test status
Simulation time 142355207 ps
CPU time 0.81 seconds
Started May 02 01:49:04 PM PDT 24
Finished May 02 01:49:06 PM PDT 24
Peak memory 203944 kb
Host smart-23ba499b-6e06-4d93-be48-0e07b7319899
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995137037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3995137037
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.2238400213
Short name T380
Test name
Test status
Simulation time 698829639 ps
CPU time 5.21 seconds
Started May 02 01:49:02 PM PDT 24
Finished May 02 01:49:09 PM PDT 24
Peak memory 239044 kb
Host smart-d58ea13a-fcbb-4ce9-8417-e3015c405c47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238400213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.2238400213
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1872205779
Short name T1048
Test name
Test status
Simulation time 3710845913 ps
CPU time 280.6 seconds
Started May 02 01:48:56 PM PDT 24
Finished May 02 01:53:37 PM PDT 24
Peak memory 1090548 kb
Host smart-f05301ab-11ed-4c51-b06d-ddf361864c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872205779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1872205779
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2535435944
Short name T1112
Test name
Test status
Simulation time 229747369 ps
CPU time 3.08 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 204156 kb
Host smart-4562a5ef-a923-41c6-b334-075c166d35fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535435944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2535435944
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.676873973
Short name T1003
Test name
Test status
Simulation time 1706754488 ps
CPU time 84.63 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:50:39 PM PDT 24
Peak memory 365580 kb
Host smart-5168973e-6700-4146-961e-784c31455a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676873973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.676873973
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.122391238
Short name T190
Test name
Test status
Simulation time 53998237 ps
CPU time 0.61 seconds
Started May 02 01:48:58 PM PDT 24
Finished May 02 01:49:00 PM PDT 24
Peak memory 203808 kb
Host smart-afc1c754-3489-421b-826a-51e6b8826a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122391238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.122391238
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2708578437
Short name T970
Test name
Test status
Simulation time 5310789155 ps
CPU time 104.34 seconds
Started May 02 01:49:03 PM PDT 24
Finished May 02 01:50:48 PM PDT 24
Peak memory 1000796 kb
Host smart-ea22ac29-9b9d-490c-adcb-d65f665d6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708578437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2708578437
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3004427141
Short name T910
Test name
Test status
Simulation time 1491182233 ps
CPU time 31.21 seconds
Started May 02 01:48:59 PM PDT 24
Finished May 02 01:49:31 PM PDT 24
Peak memory 345592 kb
Host smart-ee1d796c-8052-49cf-98b4-1b838c039efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004427141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3004427141
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3822098338
Short name T245
Test name
Test status
Simulation time 44931635706 ps
CPU time 316.1 seconds
Started May 02 01:49:05 PM PDT 24
Finished May 02 01:54:22 PM PDT 24
Peak memory 1082484 kb
Host smart-8c9f6f4d-11f7-451b-be8f-2de0bc25a171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822098338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3822098338
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3219010474
Short name T976
Test name
Test status
Simulation time 636927886 ps
CPU time 11.99 seconds
Started May 02 01:49:06 PM PDT 24
Finished May 02 01:49:19 PM PDT 24
Peak memory 220532 kb
Host smart-f823530f-8372-401a-9448-9d3a3368b4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219010474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3219010474
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1046012928
Short name T805
Test name
Test status
Simulation time 2176113878 ps
CPU time 2.69 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 204296 kb
Host smart-e27d388a-8517-4d54-beeb-a7dc255fef13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046012928 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1046012928
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3629449117
Short name T618
Test name
Test status
Simulation time 10090837005 ps
CPU time 9.31 seconds
Started May 02 01:49:05 PM PDT 24
Finished May 02 01:49:16 PM PDT 24
Peak memory 246116 kb
Host smart-b0cac639-c1b7-450d-81fa-612a723617b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629449117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3629449117
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.353188542
Short name T698
Test name
Test status
Simulation time 10059558021 ps
CPU time 65.78 seconds
Started May 02 01:49:06 PM PDT 24
Finished May 02 01:50:12 PM PDT 24
Peak memory 441200 kb
Host smart-e5cf7b37-f5f7-4b60-85d4-1026d63b322e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353188542 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.353188542
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.4218127878
Short name T897
Test name
Test status
Simulation time 644223358 ps
CPU time 2.34 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 204236 kb
Host smart-7139c2cc-153c-460d-ac4b-03fdca2bcabc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218127878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.4218127878
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.878523020
Short name T64
Test name
Test status
Simulation time 2695761870 ps
CPU time 6.94 seconds
Started May 02 01:49:03 PM PDT 24
Finished May 02 01:49:10 PM PDT 24
Peak memory 220504 kb
Host smart-e2f8c68c-8e97-4470-aa1a-22769ccb3bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878523020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.878523020
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2412340582
Short name T1108
Test name
Test status
Simulation time 6452603623 ps
CPU time 10.24 seconds
Started May 02 01:49:05 PM PDT 24
Finished May 02 01:49:16 PM PDT 24
Peak memory 489276 kb
Host smart-56223320-0895-405d-9505-bf65cebfc6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412340582 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2412340582
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1193899985
Short name T226
Test name
Test status
Simulation time 472200064 ps
CPU time 7.68 seconds
Started May 02 01:49:03 PM PDT 24
Finished May 02 01:49:11 PM PDT 24
Peak memory 204076 kb
Host smart-85ddb0b9-5aa0-44d3-9d02-811aabcbded0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193899985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1193899985
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.4284380035
Short name T1189
Test name
Test status
Simulation time 1182426276 ps
CPU time 18.72 seconds
Started May 02 01:49:05 PM PDT 24
Finished May 02 01:49:25 PM PDT 24
Peak memory 224096 kb
Host smart-9518bae5-d41c-45e1-ad5d-3c8ef6c2b05e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284380035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.4284380035
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2447169074
Short name T784
Test name
Test status
Simulation time 16156285907 ps
CPU time 9.14 seconds
Started May 02 01:49:03 PM PDT 24
Finished May 02 01:49:13 PM PDT 24
Peak memory 204184 kb
Host smart-f6b44938-050d-4dfd-a5a9-0944df3095d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447169074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2447169074
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1055320982
Short name T227
Test name
Test status
Simulation time 40228756523 ps
CPU time 308.08 seconds
Started May 02 01:49:04 PM PDT 24
Finished May 02 01:54:13 PM PDT 24
Peak memory 2311272 kb
Host smart-1b19110f-087e-4f59-83b0-5b3aa22ed3ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055320982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1055320982
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.301727851
Short name T761
Test name
Test status
Simulation time 10113939900 ps
CPU time 6.32 seconds
Started May 02 01:49:05 PM PDT 24
Finished May 02 01:49:12 PM PDT 24
Peak memory 218204 kb
Host smart-c8243a35-f79e-4fc2-92e6-7f50967eb880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301727851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.301727851
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1726086835
Short name T1087
Test name
Test status
Simulation time 40020876 ps
CPU time 0.64 seconds
Started May 02 01:49:22 PM PDT 24
Finished May 02 01:49:23 PM PDT 24
Peak memory 203872 kb
Host smart-558e03c3-ddf2-4f9c-aee8-becf5615efd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726086835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1726086835
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.528861613
Short name T807
Test name
Test status
Simulation time 114666773 ps
CPU time 1.52 seconds
Started May 02 01:49:14 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 212456 kb
Host smart-057e7507-1070-4020-bf87-69b0edd95d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528861613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.528861613
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1833936796
Short name T1210
Test name
Test status
Simulation time 1052432382 ps
CPU time 5.57 seconds
Started May 02 01:49:07 PM PDT 24
Finished May 02 01:49:13 PM PDT 24
Peak memory 237888 kb
Host smart-bfd20145-a418-4249-931e-0bbd26868478
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833936796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1833936796
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1624746155
Short name T1067
Test name
Test status
Simulation time 4645972708 ps
CPU time 78.13 seconds
Started May 02 01:49:08 PM PDT 24
Finished May 02 01:50:27 PM PDT 24
Peak memory 504008 kb
Host smart-486ed87f-6cbd-4957-8436-3ad86172b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624746155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1624746155
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.4096425516
Short name T1217
Test name
Test status
Simulation time 8958609271 ps
CPU time 64.32 seconds
Started May 02 01:49:08 PM PDT 24
Finished May 02 01:50:13 PM PDT 24
Peak memory 739052 kb
Host smart-49606ea7-8fbb-48eb-adab-c33e62f51cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096425516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.4096425516
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.819461249
Short name T404
Test name
Test status
Simulation time 130616672 ps
CPU time 1.08 seconds
Started May 02 01:49:08 PM PDT 24
Finished May 02 01:49:10 PM PDT 24
Peak memory 204060 kb
Host smart-531edc3b-6a3a-4755-b356-c32b32fa073b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819461249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.819461249
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.495411104
Short name T388
Test name
Test status
Simulation time 374046213 ps
CPU time 9.12 seconds
Started May 02 01:49:08 PM PDT 24
Finished May 02 01:49:18 PM PDT 24
Peak memory 204184 kb
Host smart-93c30936-930e-4840-af53-e07aed603e16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495411104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
495411104
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2059317973
Short name T179
Test name
Test status
Simulation time 16968690472 ps
CPU time 105.54 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:51:00 PM PDT 24
Peak memory 1216672 kb
Host smart-cac29d50-2873-4e54-9b6a-e21ae1b96250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059317973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2059317973
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1350247860
Short name T1199
Test name
Test status
Simulation time 472324421 ps
CPU time 6.7 seconds
Started May 02 01:49:22 PM PDT 24
Finished May 02 01:49:30 PM PDT 24
Peak memory 204068 kb
Host smart-7d264072-b523-4b70-aab5-b4c5aef7eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350247860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1350247860
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2703207724
Short name T468
Test name
Test status
Simulation time 1318225445 ps
CPU time 24.14 seconds
Started May 02 01:49:23 PM PDT 24
Finished May 02 01:49:48 PM PDT 24
Peak memory 348464 kb
Host smart-d2c5db61-cf60-450b-8e39-436d20b8ab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703207724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2703207724
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1384524573
Short name T194
Test name
Test status
Simulation time 31370040 ps
CPU time 0.67 seconds
Started May 02 01:49:05 PM PDT 24
Finished May 02 01:49:07 PM PDT 24
Peak memory 203824 kb
Host smart-110a5797-0d30-47ad-a435-e0e9b148adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384524573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1384524573
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.275229984
Short name T870
Test name
Test status
Simulation time 411989805 ps
CPU time 3.72 seconds
Started May 02 01:49:12 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 236928 kb
Host smart-cfd0ed74-44c4-4362-a895-059f93158b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275229984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.275229984
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1661425183
Short name T1264
Test name
Test status
Simulation time 4709133052 ps
CPU time 18.89 seconds
Started May 02 01:49:07 PM PDT 24
Finished May 02 01:49:26 PM PDT 24
Peak memory 324256 kb
Host smart-cec9fd0f-50f6-488e-bb63-69f3dc4e600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661425183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1661425183
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.682081304
Short name T235
Test name
Test status
Simulation time 33457926723 ps
CPU time 1077.22 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 02:07:12 PM PDT 24
Peak memory 3371404 kb
Host smart-aec2fcb3-a524-49f4-a432-eeb36a30d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682081304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.682081304
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2755418898
Short name T899
Test name
Test status
Simulation time 2230741843 ps
CPU time 26 seconds
Started May 02 01:49:14 PM PDT 24
Finished May 02 01:49:41 PM PDT 24
Peak memory 212416 kb
Host smart-b0cd2a6d-c9a0-4624-a6d1-ee978fd44c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755418898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2755418898
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1550994366
Short name T787
Test name
Test status
Simulation time 831640975 ps
CPU time 3.73 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:49:18 PM PDT 24
Peak memory 212436 kb
Host smart-79804ea3-3d32-4ebc-8d8a-bf2f468306d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550994366 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1550994366
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1034100437
Short name T109
Test name
Test status
Simulation time 10139201213 ps
CPU time 13.66 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:49:28 PM PDT 24
Peak memory 257096 kb
Host smart-b153d4cf-f9be-468d-bc3c-2bca2dbbb3c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034100437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1034100437
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1262907371
Short name T648
Test name
Test status
Simulation time 10085127066 ps
CPU time 75.41 seconds
Started May 02 01:49:14 PM PDT 24
Finished May 02 01:50:31 PM PDT 24
Peak memory 500812 kb
Host smart-1ebb4b5f-195f-4361-8279-95ed2e9e6efe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262907371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1262907371
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3440393268
Short name T1066
Test name
Test status
Simulation time 976484952 ps
CPU time 1.95 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:49:17 PM PDT 24
Peak memory 204120 kb
Host smart-ec2fb7b6-fe8f-45ff-8c3d-673aa365d599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440393268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3440393268
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1045819985
Short name T1333
Test name
Test status
Simulation time 754169544 ps
CPU time 3.9 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:49:18 PM PDT 24
Peak memory 204220 kb
Host smart-f75156ff-ada8-470e-abc4-c856399779d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045819985 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1045819985
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2158137453
Short name T1181
Test name
Test status
Simulation time 19761835774 ps
CPU time 47.48 seconds
Started May 02 01:49:13 PM PDT 24
Finished May 02 01:50:02 PM PDT 24
Peak memory 821980 kb
Host smart-33d1e800-720b-4144-a4d8-a32cdda60849
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158137453 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2158137453
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1730534457
Short name T615
Test name
Test status
Simulation time 724508610 ps
CPU time 24.65 seconds
Started May 02 01:49:14 PM PDT 24
Finished May 02 01:49:40 PM PDT 24
Peak memory 204028 kb
Host smart-274901ba-a994-4fdd-b8f2-3c144a1ca958
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730534457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1730534457
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2870424871
Short name T747
Test name
Test status
Simulation time 2131934678 ps
CPU time 22.96 seconds
Started May 02 01:49:12 PM PDT 24
Finished May 02 01:49:37 PM PDT 24
Peak memory 204124 kb
Host smart-2c27e66d-c982-4820-b889-4a27da294e63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870424871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2870424871
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3784057662
Short name T382
Test name
Test status
Simulation time 51828689372 ps
CPU time 1132.17 seconds
Started May 02 01:49:11 PM PDT 24
Finished May 02 02:08:04 PM PDT 24
Peak memory 7620460 kb
Host smart-54c17748-6288-4864-9028-a81981ead6cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784057662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3784057662
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2902475116
Short name T1113
Test name
Test status
Simulation time 17102729625 ps
CPU time 55.49 seconds
Started May 02 01:49:14 PM PDT 24
Finished May 02 01:50:11 PM PDT 24
Peak memory 311140 kb
Host smart-028d1b03-cb16-49bb-8cdc-bf0f670d4ce3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902475116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2902475116
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2093293568
Short name T780
Test name
Test status
Simulation time 1198054164 ps
CPU time 6.54 seconds
Started May 02 01:49:12 PM PDT 24
Finished May 02 01:49:20 PM PDT 24
Peak memory 220428 kb
Host smart-25524021-0c06-407e-9b19-3bce04156e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093293568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2093293568
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.317689054
Short name T1260
Test name
Test status
Simulation time 27439709 ps
CPU time 0.62 seconds
Started May 02 01:49:32 PM PDT 24
Finished May 02 01:49:34 PM PDT 24
Peak memory 203800 kb
Host smart-bf21581e-bda5-46c2-a400-87a077860107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317689054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.317689054
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2198875855
Short name T123
Test name
Test status
Simulation time 227195135 ps
CPU time 1.52 seconds
Started May 02 01:49:24 PM PDT 24
Finished May 02 01:49:26 PM PDT 24
Peak memory 212416 kb
Host smart-3e0a3831-b765-4932-bc7d-ad545e4db3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198875855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2198875855
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3579206946
Short name T600
Test name
Test status
Simulation time 717065863 ps
CPU time 18.85 seconds
Started May 02 01:49:24 PM PDT 24
Finished May 02 01:49:44 PM PDT 24
Peak memory 282220 kb
Host smart-b2e5ba1f-823e-42ce-b146-ca0a26317524
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579206946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3579206946
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1772401028
Short name T1272
Test name
Test status
Simulation time 9710957320 ps
CPU time 71.65 seconds
Started May 02 01:49:26 PM PDT 24
Finished May 02 01:50:39 PM PDT 24
Peak memory 638952 kb
Host smart-5022114a-00d4-450a-9849-2f926aec62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772401028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1772401028
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2846044643
Short name T804
Test name
Test status
Simulation time 1278776614 ps
CPU time 37.58 seconds
Started May 02 01:49:23 PM PDT 24
Finished May 02 01:50:01 PM PDT 24
Peak memory 485292 kb
Host smart-e644f4e7-c8df-43c1-b634-7327d4ef38d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846044643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2846044643
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2551256327
Short name T1348
Test name
Test status
Simulation time 489080711 ps
CPU time 0.98 seconds
Started May 02 01:49:24 PM PDT 24
Finished May 02 01:49:25 PM PDT 24
Peak memory 203988 kb
Host smart-91fe316b-3f20-421a-8ac2-b242bd2ee4ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551256327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2551256327
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1169862323
Short name T812
Test name
Test status
Simulation time 640707289 ps
CPU time 5.7 seconds
Started May 02 01:49:23 PM PDT 24
Finished May 02 01:49:30 PM PDT 24
Peak memory 204116 kb
Host smart-7f28dd8d-c056-40a5-a975-428b5e453eb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169862323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1169862323
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2509743002
Short name T510
Test name
Test status
Simulation time 6288297396 ps
CPU time 93.64 seconds
Started May 02 01:49:27 PM PDT 24
Finished May 02 01:51:02 PM PDT 24
Peak memory 955936 kb
Host smart-63c0c168-ad6c-4d93-93f5-ff5df10dfdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509743002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2509743002
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3450731370
Short name T1241
Test name
Test status
Simulation time 513972138 ps
CPU time 6.44 seconds
Started May 02 01:49:31 PM PDT 24
Finished May 02 01:49:38 PM PDT 24
Peak memory 204148 kb
Host smart-95f670d9-7d46-410f-bd1e-1262fd9fb4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450731370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3450731370
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.733259339
Short name T627
Test name
Test status
Simulation time 1436292352 ps
CPU time 29.54 seconds
Started May 02 01:49:31 PM PDT 24
Finished May 02 01:50:02 PM PDT 24
Peak memory 342344 kb
Host smart-24bfa073-8a8c-4081-8531-fc4a4c79de47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733259339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.733259339
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.566174290
Short name T197
Test name
Test status
Simulation time 32008789 ps
CPU time 0.66 seconds
Started May 02 01:49:22 PM PDT 24
Finished May 02 01:49:23 PM PDT 24
Peak memory 203816 kb
Host smart-5e1d3dc4-a7ab-40aa-8071-31e5061acee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566174290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.566174290
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2349111775
Short name T1327
Test name
Test status
Simulation time 1360716794 ps
CPU time 19.54 seconds
Started May 02 01:49:25 PM PDT 24
Finished May 02 01:49:45 PM PDT 24
Peak memory 231320 kb
Host smart-daaa5978-fc5e-4534-8169-369c9020069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349111775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2349111775
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3004306035
Short name T426
Test name
Test status
Simulation time 5865466294 ps
CPU time 77.37 seconds
Started May 02 01:49:24 PM PDT 24
Finished May 02 01:50:42 PM PDT 24
Peak memory 301124 kb
Host smart-2d60c8a8-9fe5-4d57-b52d-86d445d871c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004306035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3004306035
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.772745458
Short name T472
Test name
Test status
Simulation time 552814639 ps
CPU time 9.74 seconds
Started May 02 01:49:24 PM PDT 24
Finished May 02 01:49:34 PM PDT 24
Peak memory 212360 kb
Host smart-b57280d0-c930-4aea-b396-6ceb30e8be2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772745458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.772745458
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3602973008
Short name T863
Test name
Test status
Simulation time 500426403 ps
CPU time 2.76 seconds
Started May 02 01:49:31 PM PDT 24
Finished May 02 01:49:35 PM PDT 24
Peak memory 204084 kb
Host smart-194892aa-ee97-4336-b71d-6394a76cc8dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602973008 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3602973008
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.149296511
Short name T1088
Test name
Test status
Simulation time 10031666809 ps
CPU time 55.94 seconds
Started May 02 01:49:31 PM PDT 24
Finished May 02 01:50:28 PM PDT 24
Peak memory 384212 kb
Host smart-a1a5bcd0-40dd-4421-a5a4-1fac1a85ceb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149296511 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.149296511
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.959968810
Short name T272
Test name
Test status
Simulation time 10364598262 ps
CPU time 9.05 seconds
Started May 02 01:49:32 PM PDT 24
Finished May 02 01:49:42 PM PDT 24
Peak memory 241844 kb
Host smart-707c70ec-c609-4182-b92e-2baeaaf9f8a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959968810 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.959968810
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1783838171
Short name T24
Test name
Test status
Simulation time 414100727 ps
CPU time 2.31 seconds
Started May 02 01:49:32 PM PDT 24
Finished May 02 01:49:35 PM PDT 24
Peak memory 204196 kb
Host smart-c60dea51-7ff2-4016-88f6-329362210880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783838171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1783838171
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1549312149
Short name T666
Test name
Test status
Simulation time 1815970762 ps
CPU time 6.31 seconds
Started May 02 01:49:32 PM PDT 24
Finished May 02 01:49:39 PM PDT 24
Peak memory 218696 kb
Host smart-ee3d91c8-c5be-4473-80a6-47e9d58763ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549312149 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1549312149
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.219770918
Short name T289
Test name
Test status
Simulation time 20889257032 ps
CPU time 67.94 seconds
Started May 02 01:49:31 PM PDT 24
Finished May 02 01:50:39 PM PDT 24
Peak memory 1406828 kb
Host smart-23ced8c0-bb65-4474-8526-971e6c8df619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219770918 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.219770918
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.4294523523
Short name T317
Test name
Test status
Simulation time 1175511241 ps
CPU time 9.12 seconds
Started May 02 01:49:24 PM PDT 24
Finished May 02 01:49:33 PM PDT 24
Peak memory 204124 kb
Host smart-0ffa55c7-4ede-45b5-b218-ff2207910e99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294523523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.4294523523
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1709435531
Short name T749
Test name
Test status
Simulation time 2725086054 ps
CPU time 58.99 seconds
Started May 02 01:49:31 PM PDT 24
Finished May 02 01:50:30 PM PDT 24
Peak memory 205104 kb
Host smart-16652b87-069a-4e15-8b2d-9befd8afc97e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709435531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1709435531
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2719281021
Short name T794
Test name
Test status
Simulation time 24235396078 ps
CPU time 73.27 seconds
Started May 02 01:49:22 PM PDT 24
Finished May 02 01:50:36 PM PDT 24
Peak memory 1054696 kb
Host smart-690da386-bfd8-46d0-8746-f00e9894a508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719281021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2719281021
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3589252041
Short name T360
Test name
Test status
Simulation time 1094815677 ps
CPU time 6.43 seconds
Started May 02 01:49:32 PM PDT 24
Finished May 02 01:49:39 PM PDT 24
Peak memory 212336 kb
Host smart-21d21c91-9792-453d-bed8-20e185c09484
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589252041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3589252041
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.2401973011
Short name T214
Test name
Test status
Simulation time 17985651901 ps
CPU time 7.47 seconds
Started May 02 01:49:31 PM PDT 24
Finished May 02 01:49:39 PM PDT 24
Peak memory 215016 kb
Host smart-0dcee68c-03e9-4a86-a10c-6de139a3fa8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401973011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.2401973011
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1925854051
Short name T998
Test name
Test status
Simulation time 103069172 ps
CPU time 0.58 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:49:44 PM PDT 24
Peak memory 203896 kb
Host smart-63bce31a-1c56-4359-a338-b09b38e4a325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925854051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1925854051
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.446320124
Short name T750
Test name
Test status
Simulation time 93826297 ps
CPU time 1.47 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:49:44 PM PDT 24
Peak memory 215788 kb
Host smart-a31d362d-5e60-4e09-a0a7-81c373a77bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446320124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.446320124
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1205180310
Short name T1216
Test name
Test status
Simulation time 273948661 ps
CPU time 5.63 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:49:49 PM PDT 24
Peak memory 252496 kb
Host smart-c72c7fc6-a2c0-4c53-860a-fcf9a9c11910
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205180310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1205180310
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3053651887
Short name T1026
Test name
Test status
Simulation time 13626202271 ps
CPU time 49.68 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:50:32 PM PDT 24
Peak memory 613024 kb
Host smart-f28416b3-5974-4550-b8a5-2e8198ae7a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053651887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3053651887
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2703459638
Short name T40
Test name
Test status
Simulation time 1781905706 ps
CPU time 51.15 seconds
Started May 02 01:49:33 PM PDT 24
Finished May 02 01:50:25 PM PDT 24
Peak memory 646912 kb
Host smart-179ee664-7fcb-460c-b022-c3bae252e985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703459638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2703459638
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2682856131
Short name T281
Test name
Test status
Simulation time 105596869 ps
CPU time 0.84 seconds
Started May 02 01:49:43 PM PDT 24
Finished May 02 01:49:45 PM PDT 24
Peak memory 203972 kb
Host smart-74904842-37cc-4675-a461-902125d43ebd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682856131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2682856131
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.490530658
Short name T205
Test name
Test status
Simulation time 545273173 ps
CPU time 2.94 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:49:45 PM PDT 24
Peak memory 204148 kb
Host smart-3b82d266-737f-4ae3-ad2f-085fdf01d000
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490530658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
490530658
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2819348590
Short name T173
Test name
Test status
Simulation time 14587519068 ps
CPU time 84.61 seconds
Started May 02 01:49:33 PM PDT 24
Finished May 02 01:50:58 PM PDT 24
Peak memory 1051132 kb
Host smart-46cd528f-5efe-432a-a6d6-b307e8dc6bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819348590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2819348590
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3836174611
Short name T996
Test name
Test status
Simulation time 5595838079 ps
CPU time 18.68 seconds
Started May 02 01:49:39 PM PDT 24
Finished May 02 01:49:58 PM PDT 24
Peak memory 204156 kb
Host smart-af24e398-f7df-4f57-a61c-20dbdc8a5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836174611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3836174611
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3785778656
Short name T859
Test name
Test status
Simulation time 4945827258 ps
CPU time 56.54 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:50:40 PM PDT 24
Peak memory 299616 kb
Host smart-b8d38987-c90d-4e02-be40-7842b0a58c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785778656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3785778656
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1879717210
Short name T298
Test name
Test status
Simulation time 16230165 ps
CPU time 0.62 seconds
Started May 02 01:49:32 PM PDT 24
Finished May 02 01:49:33 PM PDT 24
Peak memory 203812 kb
Host smart-6329c4a6-ef93-4fe5-8be9-f740faa302ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879717210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1879717210
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1352134486
Short name T822
Test name
Test status
Simulation time 4985800057 ps
CPU time 18.28 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:50:01 PM PDT 24
Peak memory 220972 kb
Host smart-4115df6a-7126-45a4-b219-0803a0f66e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352134486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1352134486
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1458087443
Short name T376
Test name
Test status
Simulation time 7580074548 ps
CPU time 88.19 seconds
Started May 02 01:49:33 PM PDT 24
Finished May 02 01:51:02 PM PDT 24
Peak memory 323564 kb
Host smart-19e18732-9fb2-4544-9b15-bfa33bb31349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458087443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1458087443
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.2885099320
Short name T218
Test name
Test status
Simulation time 29024138328 ps
CPU time 281 seconds
Started May 02 01:49:43 PM PDT 24
Finished May 02 01:54:26 PM PDT 24
Peak memory 1563800 kb
Host smart-01b6a1d1-1f8a-42a1-ac80-76d5877b07b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885099320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.2885099320
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.384359581
Short name T1018
Test name
Test status
Simulation time 3770389986 ps
CPU time 9.18 seconds
Started May 02 01:49:38 PM PDT 24
Finished May 02 01:49:48 PM PDT 24
Peak memory 220560 kb
Host smart-9435f704-ca26-4e09-adfc-cf734f846942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384359581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.384359581
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3260974730
Short name T982
Test name
Test status
Simulation time 2349039191 ps
CPU time 3.2 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:49:45 PM PDT 24
Peak memory 204224 kb
Host smart-141093dd-2ec3-4b13-b0da-93b5c91e5369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260974730 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3260974730
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.4075721825
Short name T964
Test name
Test status
Simulation time 10076310930 ps
CPU time 64.37 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:50:48 PM PDT 24
Peak memory 482884 kb
Host smart-1b84cbd3-18dc-455d-b596-a139b79cbc6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075721825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.4075721825
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3365943237
Short name T1325
Test name
Test status
Simulation time 10159991765 ps
CPU time 10.41 seconds
Started May 02 01:49:41 PM PDT 24
Finished May 02 01:49:53 PM PDT 24
Peak memory 265836 kb
Host smart-a0d4a50b-0e45-4194-8d38-37ef1d482d80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365943237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3365943237
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1654360016
Short name T682
Test name
Test status
Simulation time 1066347951 ps
CPU time 5.09 seconds
Started May 02 01:49:39 PM PDT 24
Finished May 02 01:49:45 PM PDT 24
Peak memory 216200 kb
Host smart-b4ddeeef-08c2-4cd3-8b04-977a8d43bc88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654360016 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1654360016
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.4160973184
Short name T103
Test name
Test status
Simulation time 5663473582 ps
CPU time 9.27 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:49:53 PM PDT 24
Peak memory 456992 kb
Host smart-81ecac58-c4dd-4382-9cb0-6c477b1ac196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160973184 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.4160973184
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.3332339572
Short name T33
Test name
Test status
Simulation time 2465270564 ps
CPU time 9.54 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:49:53 PM PDT 24
Peak memory 204208 kb
Host smart-1eefad53-2650-49b4-b028-7ba0e85dae21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332339572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.3332339572
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2446867560
Short name T952
Test name
Test status
Simulation time 6335059924 ps
CPU time 28.75 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:50:12 PM PDT 24
Peak memory 224444 kb
Host smart-faad79a3-24d2-4d06-9304-131e9369cde2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446867560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2446867560
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.973169615
Short name T705
Test name
Test status
Simulation time 9840698978 ps
CPU time 3.95 seconds
Started May 02 01:49:43 PM PDT 24
Finished May 02 01:49:48 PM PDT 24
Peak memory 204176 kb
Host smart-0c3cd8f8-4a91-4186-ab0b-b8b2b4532147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973169615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.973169615
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.4047483989
Short name T1126
Test name
Test status
Simulation time 2483186694 ps
CPU time 7.2 seconds
Started May 02 01:49:42 PM PDT 24
Finished May 02 01:49:51 PM PDT 24
Peak memory 220532 kb
Host smart-c08e8f74-1280-4068-ba76-c4913bfcf27a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047483989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.4047483989
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.270665552
Short name T402
Test name
Test status
Simulation time 39261825 ps
CPU time 0.61 seconds
Started May 02 01:49:58 PM PDT 24
Finished May 02 01:50:00 PM PDT 24
Peak memory 203900 kb
Host smart-51ab8810-025b-4bd0-8e3a-d13ec342d42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270665552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.270665552
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3997145528
Short name T1224
Test name
Test status
Simulation time 426899339 ps
CPU time 1.39 seconds
Started May 02 01:49:47 PM PDT 24
Finished May 02 01:49:49 PM PDT 24
Peak memory 212472 kb
Host smart-4046062d-68ce-4db7-a690-c371d10facef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997145528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3997145528
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.537557849
Short name T1296
Test name
Test status
Simulation time 461624654 ps
CPU time 22.97 seconds
Started May 02 01:49:41 PM PDT 24
Finished May 02 01:50:05 PM PDT 24
Peak memory 264208 kb
Host smart-142b8889-5ee5-4a9a-9752-efae6583bab1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537557849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.537557849
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1995020192
Short name T1164
Test name
Test status
Simulation time 10798093582 ps
CPU time 183.82 seconds
Started May 02 01:49:50 PM PDT 24
Finished May 02 01:52:54 PM PDT 24
Peak memory 794608 kb
Host smart-3bb2ae92-554d-4cf5-8a41-b28dff5c5310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995020192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1995020192
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2302971891
Short name T936
Test name
Test status
Simulation time 2799490673 ps
CPU time 38.43 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:50:21 PM PDT 24
Peak memory 504072 kb
Host smart-2b784c65-292d-4013-b449-168189b2f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302971891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2302971891
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.867979767
Short name T540
Test name
Test status
Simulation time 511188518 ps
CPU time 1.09 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:49:43 PM PDT 24
Peak memory 204020 kb
Host smart-8f1859db-48ec-4a22-bc9f-7b393b80bd11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867979767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.867979767
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1665344740
Short name T351
Test name
Test status
Simulation time 133033284 ps
CPU time 3.55 seconds
Started May 02 01:49:40 PM PDT 24
Finished May 02 01:49:46 PM PDT 24
Peak memory 225656 kb
Host smart-db537a18-00f7-4c86-8c32-e34dcb128ba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665344740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1665344740
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.4222577190
Short name T467
Test name
Test status
Simulation time 3642570698 ps
CPU time 96.52 seconds
Started May 02 01:49:41 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 949172 kb
Host smart-5fd4132d-1c37-4d89-bb1f-a0dd074f6ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222577190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4222577190
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.31409203
Short name T72
Test name
Test status
Simulation time 1358640366 ps
CPU time 5.36 seconds
Started May 02 01:49:48 PM PDT 24
Finished May 02 01:49:55 PM PDT 24
Peak memory 204212 kb
Host smart-770ff4fb-38ca-4291-897e-a5e60df29928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31409203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.31409203
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3959156238
Short name T1039
Test name
Test status
Simulation time 1117149181 ps
CPU time 22.34 seconds
Started May 02 01:49:47 PM PDT 24
Finished May 02 01:50:11 PM PDT 24
Peak memory 341908 kb
Host smart-83d1984d-ac68-4fc3-acab-9fbf6d3e4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959156238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3959156238
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2504716468
Short name T743
Test name
Test status
Simulation time 49315477 ps
CPU time 0.69 seconds
Started May 02 01:49:41 PM PDT 24
Finished May 02 01:49:43 PM PDT 24
Peak memory 203816 kb
Host smart-b7d08c92-e1cc-49f4-94fd-bab5f10eda70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504716468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2504716468
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3398486988
Short name T858
Test name
Test status
Simulation time 5228865257 ps
CPU time 209.2 seconds
Started May 02 01:49:48 PM PDT 24
Finished May 02 01:53:18 PM PDT 24
Peak memory 227800 kb
Host smart-34029be4-22e9-4990-ac64-04183f91fec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398486988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3398486988
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2377701181
Short name T753
Test name
Test status
Simulation time 1619051925 ps
CPU time 15.19 seconds
Started May 02 01:49:39 PM PDT 24
Finished May 02 01:49:55 PM PDT 24
Peak memory 276036 kb
Host smart-5db6e806-7683-495a-86c3-cc4a3425316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377701181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2377701181
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2642775901
Short name T1192
Test name
Test status
Simulation time 6597132529 ps
CPU time 589.96 seconds
Started May 02 01:49:55 PM PDT 24
Finished May 02 01:59:46 PM PDT 24
Peak memory 1272360 kb
Host smart-67c6d6e3-16c6-418b-a1c1-5b6527c823b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642775901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2642775901
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1893063284
Short name T640
Test name
Test status
Simulation time 442023989 ps
CPU time 8.88 seconds
Started May 02 01:49:49 PM PDT 24
Finished May 02 01:49:59 PM PDT 24
Peak memory 212288 kb
Host smart-aa12ad14-81a0-41f6-9ca2-552059a693b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893063284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1893063284
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1281679966
Short name T546
Test name
Test status
Simulation time 1474084154 ps
CPU time 3.48 seconds
Started May 02 01:49:55 PM PDT 24
Finished May 02 01:50:00 PM PDT 24
Peak memory 212332 kb
Host smart-bde6be61-4da0-42db-b56a-d19f3d549b88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281679966 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1281679966
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2086791414
Short name T56
Test name
Test status
Simulation time 11480543413 ps
CPU time 3.64 seconds
Started May 02 01:49:48 PM PDT 24
Finished May 02 01:49:53 PM PDT 24
Peak memory 225432 kb
Host smart-494293d9-e795-4a23-8c74-1bd915f4eda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086791414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2086791414
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2034021243
Short name T53
Test name
Test status
Simulation time 10041672306 ps
CPU time 67.55 seconds
Started May 02 01:49:48 PM PDT 24
Finished May 02 01:50:57 PM PDT 24
Peak memory 454024 kb
Host smart-67610a5f-e67e-40f3-9a19-669ae1918893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034021243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2034021243
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3200695397
Short name T16
Test name
Test status
Simulation time 591806386 ps
CPU time 1.9 seconds
Started May 02 01:49:49 PM PDT 24
Finished May 02 01:49:52 PM PDT 24
Peak memory 204140 kb
Host smart-7dd76813-19f8-4bfa-9049-1054c5b60f22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200695397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3200695397
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2209471700
Short name T596
Test name
Test status
Simulation time 1388384599 ps
CPU time 3.33 seconds
Started May 02 01:49:55 PM PDT 24
Finished May 02 01:49:59 PM PDT 24
Peak memory 204136 kb
Host smart-44b01906-5986-44de-8147-12eca63bae0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209471700 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2209471700
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1200388359
Short name T673
Test name
Test status
Simulation time 15749826652 ps
CPU time 188 seconds
Started May 02 01:49:48 PM PDT 24
Finished May 02 01:52:57 PM PDT 24
Peak memory 2279492 kb
Host smart-37fd80d2-68d2-45e0-b288-792b484e01e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200388359 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1200388359
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1596729737
Short name T429
Test name
Test status
Simulation time 781229974 ps
CPU time 12.39 seconds
Started May 02 01:49:56 PM PDT 24
Finished May 02 01:50:09 PM PDT 24
Peak memory 204132 kb
Host smart-3697717e-57a6-49c8-beea-e1333a435b0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596729737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1596729737
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3450028178
Short name T1317
Test name
Test status
Simulation time 2920635837 ps
CPU time 28.79 seconds
Started May 02 01:49:47 PM PDT 24
Finished May 02 01:50:17 PM PDT 24
Peak memory 224748 kb
Host smart-ce33e626-45b3-47e2-943b-6606fa2b8449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450028178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3450028178
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1500020041
Short name T1343
Test name
Test status
Simulation time 58021126942 ps
CPU time 1697.02 seconds
Started May 02 01:49:46 PM PDT 24
Finished May 02 02:18:05 PM PDT 24
Peak memory 9807068 kb
Host smart-09f7d972-e030-466c-b3aa-9fc4d682bd7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500020041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1500020041
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2134587425
Short name T1185
Test name
Test status
Simulation time 37176853763 ps
CPU time 49.89 seconds
Started May 02 01:49:55 PM PDT 24
Finished May 02 01:50:45 PM PDT 24
Peak memory 576452 kb
Host smart-e8ca95a4-1e29-439c-96c3-e0601b724d54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134587425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2134587425
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3567133239
Short name T391
Test name
Test status
Simulation time 4694209767 ps
CPU time 5.99 seconds
Started May 02 01:49:48 PM PDT 24
Finished May 02 01:49:55 PM PDT 24
Peak memory 212424 kb
Host smart-4c1189eb-3ab4-44c2-ad3a-37965d0391bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567133239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3567133239
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2466172491
Short name T267
Test name
Test status
Simulation time 16827415 ps
CPU time 0.62 seconds
Started May 02 01:50:01 PM PDT 24
Finished May 02 01:50:03 PM PDT 24
Peak memory 203960 kb
Host smart-191a8e6c-e637-4468-85bd-d254ace14035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466172491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2466172491
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.4196193693
Short name T1207
Test name
Test status
Simulation time 363354123 ps
CPU time 1.53 seconds
Started May 02 01:49:57 PM PDT 24
Finished May 02 01:49:59 PM PDT 24
Peak memory 212500 kb
Host smart-44f6c07b-92ab-4b98-a0fb-6b13881857fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196193693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.4196193693
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2552362181
Short name T850
Test name
Test status
Simulation time 285123160 ps
CPU time 14.26 seconds
Started May 02 01:50:01 PM PDT 24
Finished May 02 01:50:16 PM PDT 24
Peak memory 245324 kb
Host smart-fa88d211-ae53-408e-a91c-fb427c86de1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552362181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2552362181
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3209540711
Short name T1256
Test name
Test status
Simulation time 2209503148 ps
CPU time 83.21 seconds
Started May 02 01:49:57 PM PDT 24
Finished May 02 01:51:22 PM PDT 24
Peak memory 693920 kb
Host smart-58b1e35c-b2ad-42df-8296-2d1f932fb6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209540711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3209540711
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3382802316
Short name T378
Test name
Test status
Simulation time 40405757069 ps
CPU time 61.78 seconds
Started May 02 01:49:57 PM PDT 24
Finished May 02 01:51:00 PM PDT 24
Peak memory 648332 kb
Host smart-c2cfaa0e-4e9c-4dba-aea0-7f1b03e06521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382802316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3382802316
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3516265048
Short name T492
Test name
Test status
Simulation time 589774442 ps
CPU time 1.17 seconds
Started May 02 01:49:56 PM PDT 24
Finished May 02 01:49:58 PM PDT 24
Peak memory 204156 kb
Host smart-e9a26066-2138-4135-b975-78fbb15867f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516265048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3516265048
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3743545693
Short name T715
Test name
Test status
Simulation time 249640389 ps
CPU time 3.2 seconds
Started May 02 01:49:59 PM PDT 24
Finished May 02 01:50:03 PM PDT 24
Peak memory 204184 kb
Host smart-12975c0e-5511-4b82-bb83-30ca0c8d319b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743545693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3743545693
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1748072289
Short name T778
Test name
Test status
Simulation time 16067548535 ps
CPU time 331.08 seconds
Started May 02 01:49:59 PM PDT 24
Finished May 02 01:55:31 PM PDT 24
Peak memory 1217408 kb
Host smart-0bb43215-acb7-41d9-93a3-563d615d52a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748072289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1748072289
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2089333178
Short name T844
Test name
Test status
Simulation time 927251126 ps
CPU time 3.25 seconds
Started May 02 01:49:59 PM PDT 24
Finished May 02 01:50:04 PM PDT 24
Peak memory 204176 kb
Host smart-aa069c2f-dc16-49ea-af91-732a6349e243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089333178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2089333178
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.558836254
Short name T898
Test name
Test status
Simulation time 12404712365 ps
CPU time 32.21 seconds
Started May 02 01:49:57 PM PDT 24
Finished May 02 01:50:30 PM PDT 24
Peak memory 307980 kb
Host smart-300b498e-7ada-43a4-bab0-b1b34d4ca147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558836254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.558836254
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2504024316
Short name T653
Test name
Test status
Simulation time 35701269 ps
CPU time 0.7 seconds
Started May 02 01:49:58 PM PDT 24
Finished May 02 01:49:59 PM PDT 24
Peak memory 203808 kb
Host smart-13e2ce90-aef9-4565-b758-4ffe8c3132a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504024316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2504024316
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1323827419
Short name T927
Test name
Test status
Simulation time 24572862545 ps
CPU time 2432.91 seconds
Started May 02 01:49:56 PM PDT 24
Finished May 02 02:30:30 PM PDT 24
Peak memory 2199548 kb
Host smart-e30d63ef-0c02-4617-bc8c-22ffcad75e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323827419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1323827419
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3981497867
Short name T1321
Test name
Test status
Simulation time 1040654261 ps
CPU time 15.1 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:17 PM PDT 24
Peak memory 265360 kb
Host smart-16f6c6bc-680b-4a85-9a7b-825fb25ff9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981497867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3981497867
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.407640112
Short name T169
Test name
Test status
Simulation time 20008977559 ps
CPU time 201.27 seconds
Started May 02 01:49:56 PM PDT 24
Finished May 02 01:53:18 PM PDT 24
Peak memory 1011112 kb
Host smart-d659090f-7fc8-442c-8405-0c608d5fc724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407640112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.407640112
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3668207594
Short name T1033
Test name
Test status
Simulation time 2354595322 ps
CPU time 11.16 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:12 PM PDT 24
Peak memory 214616 kb
Host smart-c9e6c841-b23a-4e82-aee6-1887302b1309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668207594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3668207594
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.4107121376
Short name T587
Test name
Test status
Simulation time 932793104 ps
CPU time 4.58 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:06 PM PDT 24
Peak memory 212352 kb
Host smart-59699a70-d846-4f82-bee5-cb68587586ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107121376 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.4107121376
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1517222368
Short name T1145
Test name
Test status
Simulation time 10097091101 ps
CPU time 13.23 seconds
Started May 02 01:49:58 PM PDT 24
Finished May 02 01:50:12 PM PDT 24
Peak memory 248888 kb
Host smart-1d9c3499-fccc-4477-bb90-59ba06b6a877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517222368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1517222368
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1391010948
Short name T695
Test name
Test status
Simulation time 10071925766 ps
CPU time 58.93 seconds
Started May 02 01:49:56 PM PDT 24
Finished May 02 01:50:56 PM PDT 24
Peak memory 444376 kb
Host smart-a3237f8c-b9d6-4ec3-98a5-8310be6f16c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391010948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1391010948
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.911791806
Short name T901
Test name
Test status
Simulation time 5941669206 ps
CPU time 2.79 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:04 PM PDT 24
Peak memory 204280 kb
Host smart-eb412c02-75cf-46f1-9944-72291c685db5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911791806 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.911791806
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2528862685
Short name T840
Test name
Test status
Simulation time 3595600660 ps
CPU time 4.55 seconds
Started May 02 01:49:57 PM PDT 24
Finished May 02 01:50:02 PM PDT 24
Peak memory 204152 kb
Host smart-0e483926-839e-49df-aa15-c38ac529844d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528862685 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2528862685
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1222550112
Short name T967
Test name
Test status
Simulation time 7531080132 ps
CPU time 17.33 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:19 PM PDT 24
Peak memory 291876 kb
Host smart-6e369aa8-c251-4792-9dca-e79c5f67be26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222550112 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1222550112
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.500047011
Short name T1194
Test name
Test status
Simulation time 1017625305 ps
CPU time 13.25 seconds
Started May 02 01:49:56 PM PDT 24
Finished May 02 01:50:10 PM PDT 24
Peak memory 204068 kb
Host smart-4e60b2cf-7ff9-4ce8-90e1-1d79116f1861
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500047011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.500047011
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.3469529114
Short name T704
Test name
Test status
Simulation time 1962301326 ps
CPU time 16.82 seconds
Started May 02 01:49:58 PM PDT 24
Finished May 02 01:50:16 PM PDT 24
Peak memory 204128 kb
Host smart-96408c1b-2db5-416c-a658-bd1ce162a317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469529114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.3469529114
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2265830455
Short name T29
Test name
Test status
Simulation time 56971888163 ps
CPU time 66.25 seconds
Started May 02 01:49:55 PM PDT 24
Finished May 02 01:51:03 PM PDT 24
Peak memory 1057068 kb
Host smart-073b17f6-ccd0-4e8a-872e-fa334876547b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265830455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2265830455
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1111644200
Short name T304
Test name
Test status
Simulation time 40532490980 ps
CPU time 128.16 seconds
Started May 02 01:49:57 PM PDT 24
Finished May 02 01:52:06 PM PDT 24
Peak memory 1135048 kb
Host smart-a04f896b-4c7b-4df8-a207-cae6b1870076
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111644200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1111644200
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2948493484
Short name T334
Test name
Test status
Simulation time 6563079189 ps
CPU time 7.17 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:08 PM PDT 24
Peak memory 215292 kb
Host smart-8e282765-1593-416e-8533-46b9902b0d71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948493484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2948493484
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.930650615
Short name T327
Test name
Test status
Simulation time 17227470 ps
CPU time 0.61 seconds
Started May 02 01:50:15 PM PDT 24
Finished May 02 01:50:17 PM PDT 24
Peak memory 203756 kb
Host smart-0f5cf009-257d-4db2-b634-63eab9ae1131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930650615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.930650615
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1474260578
Short name T461
Test name
Test status
Simulation time 79211163 ps
CPU time 1.24 seconds
Started May 02 01:50:08 PM PDT 24
Finished May 02 01:50:10 PM PDT 24
Peak memory 212404 kb
Host smart-7a0d438c-b0e3-4ce2-a441-01bb15e63de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474260578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1474260578
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3905802703
Short name T806
Test name
Test status
Simulation time 229738905 ps
CPU time 12.42 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:14 PM PDT 24
Peak memory 251340 kb
Host smart-501ad281-7ef1-435f-a284-2865fbdcbaf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905802703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3905802703
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1407799465
Short name T1159
Test name
Test status
Simulation time 6770187362 ps
CPU time 104.56 seconds
Started May 02 01:49:58 PM PDT 24
Finished May 02 01:51:43 PM PDT 24
Peak memory 517932 kb
Host smart-67540cf3-5cc3-4cde-a5a4-6f8c3c6226fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407799465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1407799465
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.68976353
Short name T315
Test name
Test status
Simulation time 9209760801 ps
CPU time 82.55 seconds
Started May 02 01:49:58 PM PDT 24
Finished May 02 01:51:22 PM PDT 24
Peak memory 754172 kb
Host smart-afbd17ba-c951-4adc-b842-0f418dd7abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68976353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.68976353
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2712421515
Short name T571
Test name
Test status
Simulation time 393170622 ps
CPU time 0.97 seconds
Started May 02 01:49:59 PM PDT 24
Finished May 02 01:50:02 PM PDT 24
Peak memory 204180 kb
Host smart-3508c732-ca5e-4cc6-ac55-0bce375c69bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712421515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2712421515
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.493275627
Short name T515
Test name
Test status
Simulation time 131339293 ps
CPU time 3.07 seconds
Started May 02 01:50:00 PM PDT 24
Finished May 02 01:50:04 PM PDT 24
Peak memory 204184 kb
Host smart-10444daa-ad61-4a49-920a-c3ef86f0553b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493275627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
493275627
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1601628934
Short name T799
Test name
Test status
Simulation time 3578391183 ps
CPU time 82.69 seconds
Started May 02 01:49:59 PM PDT 24
Finished May 02 01:51:24 PM PDT 24
Peak memory 999236 kb
Host smart-4abc6ad9-f56f-4798-9961-9d22fe442e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601628934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1601628934
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3813224504
Short name T488
Test name
Test status
Simulation time 2127010757 ps
CPU time 6.27 seconds
Started May 02 01:50:14 PM PDT 24
Finished May 02 01:50:21 PM PDT 24
Peak memory 204144 kb
Host smart-e58d3d58-507c-46c6-a060-cfde19d5b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813224504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3813224504
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.4043409219
Short name T904
Test name
Test status
Simulation time 2376216551 ps
CPU time 21.21 seconds
Started May 02 01:50:16 PM PDT 24
Finished May 02 01:50:38 PM PDT 24
Peak memory 294848 kb
Host smart-fef1c397-6d49-4606-9446-2fe4685a2fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043409219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.4043409219
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2992013239
Short name T1045
Test name
Test status
Simulation time 16922677 ps
CPU time 0.65 seconds
Started May 02 01:49:59 PM PDT 24
Finished May 02 01:50:01 PM PDT 24
Peak memory 203840 kb
Host smart-f9e4c00c-a8bb-4774-b1c4-ffed6f8cbc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992013239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2992013239
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2713713049
Short name T1038
Test name
Test status
Simulation time 1099678127 ps
CPU time 12.34 seconds
Started May 02 01:50:05 PM PDT 24
Finished May 02 01:50:18 PM PDT 24
Peak memory 242872 kb
Host smart-f131e982-e900-42b0-af84-458d83782382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713713049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2713713049
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.213836560
Short name T516
Test name
Test status
Simulation time 7090852792 ps
CPU time 35.56 seconds
Started May 02 01:49:58 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 374792 kb
Host smart-e0015801-efaf-47ec-b58a-0880be4866db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213836560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.213836560
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3407230644
Short name T857
Test name
Test status
Simulation time 1180049054 ps
CPU time 11.48 seconds
Started May 02 01:50:08 PM PDT 24
Finished May 02 01:50:20 PM PDT 24
Peak memory 217024 kb
Host smart-2f4ed72f-94b9-43df-b0b8-bd2bb68446ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407230644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3407230644
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2939772440
Short name T777
Test name
Test status
Simulation time 3169900734 ps
CPU time 3.71 seconds
Started May 02 01:50:06 PM PDT 24
Finished May 02 01:50:10 PM PDT 24
Peak memory 204256 kb
Host smart-5abdefe2-35f0-4c62-a736-6eef534e848e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939772440 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2939772440
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3675006344
Short name T644
Test name
Test status
Simulation time 10454412107 ps
CPU time 14.73 seconds
Started May 02 01:50:05 PM PDT 24
Finished May 02 01:50:21 PM PDT 24
Peak memory 278356 kb
Host smart-15c9f978-61f5-48a6-8ae0-aa109c60b41c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675006344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3675006344
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2691044279
Short name T548
Test name
Test status
Simulation time 10031714709 ps
CPU time 65.19 seconds
Started May 02 01:50:07 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 606712 kb
Host smart-180cbf95-2642-442b-8359-cedbda14c013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691044279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2691044279
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.2235776826
Short name T26
Test name
Test status
Simulation time 1867480073 ps
CPU time 2.77 seconds
Started May 02 01:50:15 PM PDT 24
Finished May 02 01:50:19 PM PDT 24
Peak memory 204156 kb
Host smart-e7477ee5-47b5-41b5-8b87-8459739dcd58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235776826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.2235776826
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.994657011
Short name T400
Test name
Test status
Simulation time 1067679823 ps
CPU time 5.21 seconds
Started May 02 01:50:05 PM PDT 24
Finished May 02 01:50:11 PM PDT 24
Peak memory 205356 kb
Host smart-5ae2d325-ff07-418f-9aa4-49f6d1de2de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994657011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.994657011
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.3396041140
Short name T1237
Test name
Test status
Simulation time 20659360298 ps
CPU time 445.02 seconds
Started May 02 01:50:04 PM PDT 24
Finished May 02 01:57:30 PM PDT 24
Peak memory 5000200 kb
Host smart-a8f5bdbc-97dc-4517-b768-6cf6762353f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396041140 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.3396041140
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.3544510943
Short name T1244
Test name
Test status
Simulation time 848046101 ps
CPU time 10.62 seconds
Started May 02 01:50:07 PM PDT 24
Finished May 02 01:50:18 PM PDT 24
Peak memory 204056 kb
Host smart-d85cf5e7-f465-4485-96af-fce7971f80aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544510943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.3544510943
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2547481394
Short name T773
Test name
Test status
Simulation time 1321750800 ps
CPU time 12.29 seconds
Started May 02 01:50:04 PM PDT 24
Finished May 02 01:50:18 PM PDT 24
Peak memory 207396 kb
Host smart-73993df4-59da-4b90-bbc1-fc04e5316ffa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547481394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2547481394
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3028769048
Short name T517
Test name
Test status
Simulation time 42415293301 ps
CPU time 57.45 seconds
Started May 02 01:50:06 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 997564 kb
Host smart-95258419-4c49-4552-ba21-e7ca9e90a4ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028769048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3028769048
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2223705009
Short name T1175
Test name
Test status
Simulation time 4999678757 ps
CPU time 87.05 seconds
Started May 02 01:50:08 PM PDT 24
Finished May 02 01:51:36 PM PDT 24
Peak memory 1131588 kb
Host smart-ae18bc7e-54df-4598-bad3-cbcb8da58fae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223705009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2223705009
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3537294045
Short name T890
Test name
Test status
Simulation time 1391558276 ps
CPU time 6.72 seconds
Started May 02 01:50:04 PM PDT 24
Finished May 02 01:50:12 PM PDT 24
Peak memory 219144 kb
Host smart-b61940a0-67a6-457e-bda5-5d036999d7e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537294045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3537294045
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.689843700
Short name T532
Test name
Test status
Simulation time 34497872 ps
CPU time 0.64 seconds
Started May 02 01:50:25 PM PDT 24
Finished May 02 01:50:27 PM PDT 24
Peak memory 203884 kb
Host smart-d6293dff-5e0a-4f58-afb6-b73797cd9d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689843700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.689843700
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3603334964
Short name T1334
Test name
Test status
Simulation time 313295889 ps
CPU time 1.23 seconds
Started May 02 01:50:21 PM PDT 24
Finished May 02 01:50:24 PM PDT 24
Peak memory 212456 kb
Host smart-3734d0f8-0448-405e-b664-f36dc72b9692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603334964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3603334964
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3447348446
Short name T353
Test name
Test status
Simulation time 394961543 ps
CPU time 3.7 seconds
Started May 02 01:50:14 PM PDT 24
Finished May 02 01:50:19 PM PDT 24
Peak memory 239336 kb
Host smart-94288157-a784-4921-949b-f2fb19c07928
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447348446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3447348446
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.79188598
Short name T1227
Test name
Test status
Simulation time 10225723956 ps
CPU time 88.06 seconds
Started May 02 01:50:22 PM PDT 24
Finished May 02 01:51:51 PM PDT 24
Peak memory 842908 kb
Host smart-4c7c11cb-8618-4d26-a406-77f83354a6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79188598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.79188598
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1499979720
Short name T321
Test name
Test status
Simulation time 4537046907 ps
CPU time 71.43 seconds
Started May 02 01:50:15 PM PDT 24
Finished May 02 01:51:28 PM PDT 24
Peak memory 768120 kb
Host smart-3494681a-086d-4c0d-89fa-d91e4586f9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499979720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1499979720
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.4179180786
Short name T209
Test name
Test status
Simulation time 115328808 ps
CPU time 1.1 seconds
Started May 02 01:50:18 PM PDT 24
Finished May 02 01:50:19 PM PDT 24
Peak memory 204092 kb
Host smart-85876a1b-4524-4c30-860e-a6063b9bcbd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179180786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.4179180786
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.4200869508
Short name T487
Test name
Test status
Simulation time 1150165760 ps
CPU time 3.55 seconds
Started May 02 01:50:23 PM PDT 24
Finished May 02 01:50:28 PM PDT 24
Peak memory 227316 kb
Host smart-f585f7c5-64ff-4bd3-a354-e7565576c143
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200869508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.4200869508
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.621531644
Short name T230
Test name
Test status
Simulation time 4067246134 ps
CPU time 102.72 seconds
Started May 02 01:50:15 PM PDT 24
Finished May 02 01:51:59 PM PDT 24
Peak memory 1173320 kb
Host smart-20bbec6f-cba0-442d-a767-d44bcaa9673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621531644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.621531644
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.421643051
Short name T1085
Test name
Test status
Simulation time 527154076 ps
CPU time 17.39 seconds
Started May 02 01:50:21 PM PDT 24
Finished May 02 01:50:40 PM PDT 24
Peak memory 204140 kb
Host smart-8c68be39-04e2-4665-94b4-231f48c722d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421643051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.421643051
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.2283365412
Short name T937
Test name
Test status
Simulation time 1052199179 ps
CPU time 20.45 seconds
Started May 02 01:50:23 PM PDT 24
Finished May 02 01:50:44 PM PDT 24
Peak memory 348980 kb
Host smart-3acda316-8383-442c-9d7e-2ba2a387ad39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283365412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2283365412
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1666460888
Short name T457
Test name
Test status
Simulation time 77131465 ps
CPU time 0.65 seconds
Started May 02 01:50:14 PM PDT 24
Finished May 02 01:50:16 PM PDT 24
Peak memory 203844 kb
Host smart-b0110eed-9fb7-4acf-970f-bcda3f4e4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666460888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1666460888
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.497847134
Short name T1084
Test name
Test status
Simulation time 491360622 ps
CPU time 20.88 seconds
Started May 02 01:50:22 PM PDT 24
Finished May 02 01:50:44 PM PDT 24
Peak memory 236960 kb
Host smart-57bec785-683a-498c-82a8-fad910b162a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497847134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.497847134
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3458826831
Short name T258
Test name
Test status
Simulation time 2716549130 ps
CPU time 60.07 seconds
Started May 02 01:50:14 PM PDT 24
Finished May 02 01:51:16 PM PDT 24
Peak memory 296140 kb
Host smart-4b37b58e-e0ee-4d3c-92f2-46a32e7842eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458826831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3458826831
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.1389375177
Short name T449
Test name
Test status
Simulation time 11121535821 ps
CPU time 719.5 seconds
Started May 02 01:50:21 PM PDT 24
Finished May 02 02:02:22 PM PDT 24
Peak memory 2750612 kb
Host smart-9416dc55-922c-41f1-b26e-e863e3b0ae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389375177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.1389375177
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3641985531
Short name T535
Test name
Test status
Simulation time 1965695112 ps
CPU time 22.29 seconds
Started May 02 01:50:22 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 212284 kb
Host smart-c7877126-e938-464e-9c08-27db1ea6b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641985531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3641985531
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1311763233
Short name T316
Test name
Test status
Simulation time 924607967 ps
CPU time 4.83 seconds
Started May 02 01:50:22 PM PDT 24
Finished May 02 01:50:28 PM PDT 24
Peak memory 214676 kb
Host smart-e13f69df-182e-4e39-98f8-3a90d6eede0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311763233 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1311763233
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3878473743
Short name T703
Test name
Test status
Simulation time 10399283624 ps
CPU time 10.86 seconds
Started May 02 01:50:21 PM PDT 24
Finished May 02 01:50:34 PM PDT 24
Peak memory 244704 kb
Host smart-fd77f6f9-b909-49de-9d6a-3a4c34e12cc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878473743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3878473743
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1792058175
Short name T887
Test name
Test status
Simulation time 10101474168 ps
CPU time 66.78 seconds
Started May 02 01:50:22 PM PDT 24
Finished May 02 01:51:31 PM PDT 24
Peak memory 441712 kb
Host smart-1c133e69-13c6-47b1-a2e6-1b88f3f96fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792058175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1792058175
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2210324373
Short name T1311
Test name
Test status
Simulation time 455536980 ps
CPU time 2.5 seconds
Started May 02 01:50:22 PM PDT 24
Finished May 02 01:50:26 PM PDT 24
Peak memory 204220 kb
Host smart-f70d331a-c2be-4d3a-ad41-d0f04490ba0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210324373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2210324373
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1867205830
Short name T101
Test name
Test status
Simulation time 1257403794 ps
CPU time 5.87 seconds
Started May 02 01:50:25 PM PDT 24
Finished May 02 01:50:32 PM PDT 24
Peak memory 208012 kb
Host smart-63469125-759d-444d-81ec-7255123f1f33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867205830 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1867205830
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1404013637
Short name T1328
Test name
Test status
Simulation time 11864618755 ps
CPU time 11.49 seconds
Started May 02 01:50:21 PM PDT 24
Finished May 02 01:50:33 PM PDT 24
Peak memory 347900 kb
Host smart-f7cecf66-33a0-4b4f-abb8-871461a243ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404013637 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1404013637
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2520824214
Short name T1289
Test name
Test status
Simulation time 3696765053 ps
CPU time 11.69 seconds
Started May 02 01:50:21 PM PDT 24
Finished May 02 01:50:34 PM PDT 24
Peak memory 204240 kb
Host smart-ca084a53-a40d-4bcc-a33e-2d95a296e36e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520824214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2520824214
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1754618062
Short name T965
Test name
Test status
Simulation time 356096749 ps
CPU time 5.72 seconds
Started May 02 01:50:24 PM PDT 24
Finished May 02 01:50:31 PM PDT 24
Peak memory 204132 kb
Host smart-308fc9d9-ff48-49de-92f4-224205810f05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754618062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1754618062
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3604706427
Short name T772
Test name
Test status
Simulation time 25800365111 ps
CPU time 22.81 seconds
Started May 02 01:50:22 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 468196 kb
Host smart-b968c56a-cf82-4c00-928a-187aa109865c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604706427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3604706427
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.3676155400
Short name T889
Test name
Test status
Simulation time 9807767575 ps
CPU time 109.35 seconds
Started May 02 01:50:25 PM PDT 24
Finished May 02 01:52:15 PM PDT 24
Peak memory 1341832 kb
Host smart-6b9bba7c-2db2-4aa2-a1fe-205c8693a53e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676155400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.3676155400
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.4089353690
Short name T590
Test name
Test status
Simulation time 5189265630 ps
CPU time 6.2 seconds
Started May 02 01:50:26 PM PDT 24
Finished May 02 01:50:33 PM PDT 24
Peak memory 212480 kb
Host smart-5e235bf5-c204-4c94-9129-c56b6d10d852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089353690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.4089353690
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2509828747
Short name T336
Test name
Test status
Simulation time 28532119 ps
CPU time 0.64 seconds
Started May 02 01:42:31 PM PDT 24
Finished May 02 01:42:33 PM PDT 24
Peak memory 203916 kb
Host smart-1bd0d005-7d5c-491b-816f-b762246a2f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509828747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2509828747
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3163151019
Short name T827
Test name
Test status
Simulation time 104137733 ps
CPU time 1.96 seconds
Started May 02 01:42:30 PM PDT 24
Finished May 02 01:42:33 PM PDT 24
Peak memory 220624 kb
Host smart-661875a8-6654-4fbe-9f48-46cef2be11ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163151019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3163151019
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2608368114
Short name T1109
Test name
Test status
Simulation time 1213979124 ps
CPU time 5.9 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:37 PM PDT 24
Peak memory 270844 kb
Host smart-d2696389-623f-4b06-b628-34a0c630c909
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608368114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2608368114
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2334404
Short name T1058
Test name
Test status
Simulation time 2729096381 ps
CPU time 79.42 seconds
Started May 02 01:42:33 PM PDT 24
Finished May 02 01:43:53 PM PDT 24
Peak memory 412032 kb
Host smart-6889a02a-92e8-414d-931d-8cf7dd88d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2334404
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1512945868
Short name T1115
Test name
Test status
Simulation time 6743685485 ps
CPU time 49.71 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:43:21 PM PDT 24
Peak memory 548940 kb
Host smart-ba435eae-6b6f-4d5a-afd6-4f2045491dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512945868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1512945868
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2353646476
Short name T1228
Test name
Test status
Simulation time 98081946 ps
CPU time 1.04 seconds
Started May 02 01:42:30 PM PDT 24
Finished May 02 01:42:32 PM PDT 24
Peak memory 204064 kb
Host smart-ba1e1ade-95c5-44b8-baff-34e78cc3df9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353646476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2353646476
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2079555854
Short name T240
Test name
Test status
Simulation time 4738328385 ps
CPU time 152.18 seconds
Started May 02 01:42:28 PM PDT 24
Finished May 02 01:45:02 PM PDT 24
Peak memory 1334136 kb
Host smart-cb42c9d4-ee68-4903-b86c-244d2f1721e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079555854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2079555854
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2959486516
Short name T544
Test name
Test status
Simulation time 1854284613 ps
CPU time 19.5 seconds
Started May 02 01:42:27 PM PDT 24
Finished May 02 01:42:48 PM PDT 24
Peak memory 204216 kb
Host smart-049bec3f-18f0-42bd-8634-ee5c15d73bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959486516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2959486516
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1080611148
Short name T680
Test name
Test status
Simulation time 2366602558 ps
CPU time 23.83 seconds
Started May 02 01:42:31 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 347188 kb
Host smart-bb27801d-add9-4ed6-a4d7-750ccb388b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080611148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1080611148
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.1435943793
Short name T37
Test name
Test status
Simulation time 28364501 ps
CPU time 0.63 seconds
Started May 02 01:42:24 PM PDT 24
Finished May 02 01:42:26 PM PDT 24
Peak memory 203816 kb
Host smart-c74dc356-0340-4acf-a5c0-ae7f40f1c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435943793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1435943793
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2826110525
Short name T358
Test name
Test status
Simulation time 9034440556 ps
CPU time 38.8 seconds
Started May 02 01:42:30 PM PDT 24
Finished May 02 01:43:10 PM PDT 24
Peak memory 284660 kb
Host smart-46eef04a-3b2e-479a-815b-6bd4f512545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826110525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2826110525
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2310996152
Short name T405
Test name
Test status
Simulation time 1085165950 ps
CPU time 25.87 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 212392 kb
Host smart-86793837-c060-4fc8-9688-cea0b5080c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310996152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2310996152
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.326045993
Short name T276
Test name
Test status
Simulation time 1099483758 ps
CPU time 5.08 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:36 PM PDT 24
Peak memory 212440 kb
Host smart-6219e2a0-93df-4028-8b94-59121c060fac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326045993 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.326045993
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2003811941
Short name T495
Test name
Test status
Simulation time 10064289240 ps
CPU time 68.34 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:43:38 PM PDT 24
Peak memory 523088 kb
Host smart-42165e9b-0c27-4d49-b2a3-765762458623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003811941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2003811941
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3890901150
Short name T986
Test name
Test status
Simulation time 10068085425 ps
CPU time 103.42 seconds
Started May 02 01:42:33 PM PDT 24
Finished May 02 01:44:18 PM PDT 24
Peak memory 575396 kb
Host smart-0fb7d37c-0196-4ca3-992e-8fa49ee31e97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890901150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3890901150
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1346796265
Short name T1201
Test name
Test status
Simulation time 2748535476 ps
CPU time 2.68 seconds
Started May 02 01:42:28 PM PDT 24
Finished May 02 01:42:32 PM PDT 24
Peak memory 204236 kb
Host smart-8bdf8c96-a568-4fac-b585-388c2147a456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346796265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1346796265
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2081937429
Short name T828
Test name
Test status
Simulation time 810143122 ps
CPU time 4.18 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:34 PM PDT 24
Peak memory 204616 kb
Host smart-885c6df3-1914-41cd-abf8-25bfac250cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081937429 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2081937429
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1360735262
Short name T387
Test name
Test status
Simulation time 18789345407 ps
CPU time 35.28 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:43:06 PM PDT 24
Peak memory 921792 kb
Host smart-99f2a978-cb30-4278-8648-9ec841829662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360735262 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1360735262
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.816820295
Short name T399
Test name
Test status
Simulation time 5273081555 ps
CPU time 36.63 seconds
Started May 02 01:42:32 PM PDT 24
Finished May 02 01:43:10 PM PDT 24
Peak memory 204228 kb
Host smart-1809fdc4-2efa-4260-b296-2e402e35b157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816820295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.816820295
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2496792164
Short name T440
Test name
Test status
Simulation time 766106238 ps
CPU time 13.67 seconds
Started May 02 01:42:27 PM PDT 24
Finished May 02 01:42:41 PM PDT 24
Peak memory 206024 kb
Host smart-ffabbcd2-e7ab-43cc-8e4a-84be3bdc030b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496792164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2496792164
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1045573294
Short name T1213
Test name
Test status
Simulation time 19087115712 ps
CPU time 35.43 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:43:06 PM PDT 24
Peak memory 204172 kb
Host smart-96315ade-31ce-4af4-8324-f491f6ce7bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045573294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1045573294
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2755637881
Short name T874
Test name
Test status
Simulation time 38842151789 ps
CPU time 1195.9 seconds
Started May 02 01:42:28 PM PDT 24
Finished May 02 02:02:25 PM PDT 24
Peak memory 4724564 kb
Host smart-4af0c538-c80f-49bb-bdc1-f2288cdf127d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755637881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2755637881
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2053666806
Short name T811
Test name
Test status
Simulation time 4913319707 ps
CPU time 6.91 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:38 PM PDT 24
Peak memory 220476 kb
Host smart-f64038b4-4c19-444c-ae66-aeb73765df1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053666806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2053666806
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.2036555028
Short name T884
Test name
Test status
Simulation time 6616882905 ps
CPU time 7.43 seconds
Started May 02 01:42:30 PM PDT 24
Finished May 02 01:42:39 PM PDT 24
Peak memory 220300 kb
Host smart-af6c87f3-3adc-427c-a4d4-e4f8c7cb3d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036555028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.2036555028
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.200718962
Short name T273
Test name
Test status
Simulation time 20710592 ps
CPU time 0.69 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:42:40 PM PDT 24
Peak memory 203900 kb
Host smart-f6738031-4539-4d66-b99d-0da9392136df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200718962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.200718962
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3859292962
Short name T1330
Test name
Test status
Simulation time 235087197 ps
CPU time 1.48 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:42:41 PM PDT 24
Peak memory 212424 kb
Host smart-92b62e7e-378d-4bc2-bc9f-651c78365b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859292962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3859292962
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.4029383290
Short name T669
Test name
Test status
Simulation time 319071239 ps
CPU time 7.52 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:38 PM PDT 24
Peak memory 272772 kb
Host smart-868b0cb3-7b61-4d8d-b4b1-48786aac1c1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029383290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.4029383290
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3754849037
Short name T1097
Test name
Test status
Simulation time 9010442280 ps
CPU time 71.11 seconds
Started May 02 01:42:36 PM PDT 24
Finished May 02 01:43:48 PM PDT 24
Peak memory 747724 kb
Host smart-b16878f3-c926-4fa8-9783-95938712d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754849037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3754849037
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2288161435
Short name T99
Test name
Test status
Simulation time 17359273888 ps
CPU time 80.42 seconds
Started May 02 01:42:32 PM PDT 24
Finished May 02 01:43:54 PM PDT 24
Peak memory 453772 kb
Host smart-ec0500d2-f7ec-4378-99df-ab27845b216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288161435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2288161435
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.4111163127
Short name T344
Test name
Test status
Simulation time 334727617 ps
CPU time 0.88 seconds
Started May 02 01:42:32 PM PDT 24
Finished May 02 01:42:34 PM PDT 24
Peak memory 204020 kb
Host smart-6ee6e0b9-074f-462f-9f01-8089e180b64c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111163127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.4111163127
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2638452301
Short name T566
Test name
Test status
Simulation time 134778907 ps
CPU time 7.32 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:42:47 PM PDT 24
Peak memory 225748 kb
Host smart-73fb58ed-1782-4acc-b79e-2198ed538e2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638452301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2638452301
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.4170983857
Short name T1270
Test name
Test status
Simulation time 6991936376 ps
CPU time 74.47 seconds
Started May 02 01:42:27 PM PDT 24
Finished May 02 01:43:43 PM PDT 24
Peak memory 965048 kb
Host smart-8250cde3-08b4-4d28-b46d-05f283152ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170983857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.4170983857
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1803602005
Short name T512
Test name
Test status
Simulation time 314870197 ps
CPU time 12.48 seconds
Started May 02 01:42:35 PM PDT 24
Finished May 02 01:42:49 PM PDT 24
Peak memory 204096 kb
Host smart-d8f3be4d-959d-4767-b98e-c9db59e1f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803602005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1803602005
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3373935262
Short name T394
Test name
Test status
Simulation time 7378380892 ps
CPU time 89.27 seconds
Started May 02 01:42:37 PM PDT 24
Finished May 02 01:44:08 PM PDT 24
Peak memory 366104 kb
Host smart-7b59c1bd-f476-481d-b3de-1a4ead119c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373935262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3373935262
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.533544167
Short name T584
Test name
Test status
Simulation time 40504359 ps
CPU time 0.65 seconds
Started May 02 01:42:29 PM PDT 24
Finished May 02 01:42:31 PM PDT 24
Peak memory 203748 kb
Host smart-923b3161-d84e-49fe-a380-e0fb343f7a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533544167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.533544167
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.4218907411
Short name T963
Test name
Test status
Simulation time 669831528 ps
CPU time 2.48 seconds
Started May 02 01:42:39 PM PDT 24
Finished May 02 01:42:42 PM PDT 24
Peak memory 219240 kb
Host smart-c9999c55-2d94-4fc2-9bec-16af01f7f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218907411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.4218907411
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3582427142
Short name T311
Test name
Test status
Simulation time 1455247287 ps
CPU time 24.2 seconds
Started May 02 01:42:30 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 325352 kb
Host smart-76fc1b90-5928-424a-aa24-2ea8bb12d710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582427142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3582427142
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2339739584
Short name T888
Test name
Test status
Simulation time 598298475 ps
CPU time 11.04 seconds
Started May 02 01:42:35 PM PDT 24
Finished May 02 01:42:47 PM PDT 24
Peak memory 213860 kb
Host smart-a2d7962d-4a05-4c33-9539-bc2e475fa75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339739584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2339739584
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3424685521
Short name T771
Test name
Test status
Simulation time 517679797 ps
CPU time 2.67 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:42:42 PM PDT 24
Peak memory 204180 kb
Host smart-16735233-c7e1-45a2-9299-e5e334cd85d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424685521 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3424685521
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1748340325
Short name T1167
Test name
Test status
Simulation time 10152624436 ps
CPU time 12.01 seconds
Started May 02 01:42:37 PM PDT 24
Finished May 02 01:42:51 PM PDT 24
Peak memory 273652 kb
Host smart-0aacd691-2e0e-436c-8412-c2f190742361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748340325 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1748340325
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3720080118
Short name T719
Test name
Test status
Simulation time 10410213213 ps
CPU time 13.91 seconds
Started May 02 01:42:35 PM PDT 24
Finished May 02 01:42:50 PM PDT 24
Peak memory 287936 kb
Host smart-98119aae-0bf1-43ea-8ae7-624289d7d446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720080118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3720080118
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.2676963751
Short name T1187
Test name
Test status
Simulation time 886623779 ps
CPU time 2.47 seconds
Started May 02 01:42:35 PM PDT 24
Finished May 02 01:42:39 PM PDT 24
Peak memory 204188 kb
Host smart-50173860-1f44-4cf8-9951-15ce4ba6a160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676963751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.2676963751
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3912186858
Short name T1065
Test name
Test status
Simulation time 826407328 ps
CPU time 4.11 seconds
Started May 02 01:42:37 PM PDT 24
Finished May 02 01:42:42 PM PDT 24
Peak memory 204164 kb
Host smart-14adba9d-73d5-49bc-97b7-9a79659e4152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912186858 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3912186858
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.4057068909
Short name T928
Test name
Test status
Simulation time 15702763551 ps
CPU time 30.13 seconds
Started May 02 01:42:35 PM PDT 24
Finished May 02 01:43:07 PM PDT 24
Peak memory 673792 kb
Host smart-62361d3d-074a-4c31-a717-8e75826e89ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057068909 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.4057068909
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.4266100624
Short name T269
Test name
Test status
Simulation time 1256895892 ps
CPU time 8.14 seconds
Started May 02 01:42:40 PM PDT 24
Finished May 02 01:42:50 PM PDT 24
Peak memory 204060 kb
Host smart-c72f294a-b704-408c-93d2-b776b9f5697e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266100624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.4266100624
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.944195803
Short name T707
Test name
Test status
Simulation time 409995235 ps
CPU time 17.8 seconds
Started May 02 01:42:37 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 204132 kb
Host smart-2bdcf672-b465-424e-9eeb-fb04d760f86e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944195803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_rd.944195803
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1876232578
Short name T765
Test name
Test status
Simulation time 65027945644 ps
CPU time 2074.33 seconds
Started May 02 01:42:40 PM PDT 24
Finished May 02 02:17:17 PM PDT 24
Peak memory 11271556 kb
Host smart-b12aa8ab-f1c4-46c6-b23b-1047fbba5b93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876232578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1876232578
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2846213946
Short name T971
Test name
Test status
Simulation time 18431184265 ps
CPU time 113.77 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:44:33 PM PDT 24
Peak memory 979596 kb
Host smart-a0c04855-d30e-474a-a20d-113b748c6a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846213946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2846213946
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1525880222
Short name T438
Test name
Test status
Simulation time 3464104083 ps
CPU time 8.08 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:42:47 PM PDT 24
Peak memory 219988 kb
Host smart-1bd72693-02e5-4cdf-9e77-1d61c8d14202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525880222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1525880222
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.1669050549
Short name T18
Test name
Test status
Simulation time 4206586180 ps
CPU time 5.84 seconds
Started May 02 01:42:35 PM PDT 24
Finished May 02 01:42:42 PM PDT 24
Peak memory 213908 kb
Host smart-877aa204-f918-4f4f-b5ba-74de8115c255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669050549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.1669050549
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1784134259
Short name T1318
Test name
Test status
Simulation time 18633993 ps
CPU time 0.6 seconds
Started May 02 01:42:45 PM PDT 24
Finished May 02 01:42:46 PM PDT 24
Peak memory 203884 kb
Host smart-0edb4d8d-b17f-47cd-a72d-307cbab9fef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784134259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1784134259
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1735600595
Short name T1030
Test name
Test status
Simulation time 72827813 ps
CPU time 1.31 seconds
Started May 02 01:42:45 PM PDT 24
Finished May 02 01:42:47 PM PDT 24
Peak memory 212468 kb
Host smart-8b1fa2c3-d601-4cd9-aae5-e373c5eb56bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735600595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1735600595
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.29466333
Short name T84
Test name
Test status
Simulation time 372710532 ps
CPU time 18.81 seconds
Started May 02 01:42:36 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 276512 kb
Host smart-d64fa5c1-356c-4d2a-a26a-ca9b25116e65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.29466333
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1353972798
Short name T1116
Test name
Test status
Simulation time 1686825210 ps
CPU time 113.13 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:44:32 PM PDT 24
Peak memory 597152 kb
Host smart-43c2b23a-cfbf-4672-9297-d5cb8c854086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353972798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1353972798
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.555839323
Short name T322
Test name
Test status
Simulation time 2471647655 ps
CPU time 77.78 seconds
Started May 02 01:42:39 PM PDT 24
Finished May 02 01:43:58 PM PDT 24
Peak memory 726828 kb
Host smart-02fdaca1-df3c-4ac5-81b3-220b9edbf879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555839323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.555839323
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1897481006
Short name T284
Test name
Test status
Simulation time 166598584 ps
CPU time 1.15 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:42:41 PM PDT 24
Peak memory 204092 kb
Host smart-7aa45b44-7c4e-43ef-842e-0f391bd29f9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897481006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1897481006
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3543807832
Short name T1072
Test name
Test status
Simulation time 422245675 ps
CPU time 4.91 seconds
Started May 02 01:42:37 PM PDT 24
Finished May 02 01:42:43 PM PDT 24
Peak memory 204192 kb
Host smart-a0eed9c8-19dd-4f3b-8b95-b6bfba663c72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543807832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3543807832
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.595904130
Short name T903
Test name
Test status
Simulation time 15647748095 ps
CPU time 123.52 seconds
Started May 02 01:42:35 PM PDT 24
Finished May 02 01:44:39 PM PDT 24
Peak memory 1195012 kb
Host smart-a82b9b1c-a550-40c3-944b-b54ea4f180f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595904130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.595904130
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1530402428
Short name T575
Test name
Test status
Simulation time 651122380 ps
CPU time 2.65 seconds
Started May 02 01:42:47 PM PDT 24
Finished May 02 01:42:51 PM PDT 24
Peak memory 204200 kb
Host smart-204fefc3-5d19-4d15-992d-a0993eeaab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530402428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1530402428
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.2862939182
Short name T385
Test name
Test status
Simulation time 1091792123 ps
CPU time 12.58 seconds
Started May 02 01:42:48 PM PDT 24
Finished May 02 01:43:02 PM PDT 24
Peak memory 264256 kb
Host smart-ebb6418e-c193-4687-b26f-2fcc0a34faa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862939182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.2862939182
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.875248618
Short name T331
Test name
Test status
Simulation time 27637011 ps
CPU time 0.7 seconds
Started May 02 01:42:39 PM PDT 24
Finished May 02 01:42:40 PM PDT 24
Peak memory 203832 kb
Host smart-859aea36-d15b-4c6c-bfaa-e263d1f0c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875248618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.875248618
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.738846702
Short name T82
Test name
Test status
Simulation time 5164798915 ps
CPU time 30.64 seconds
Started May 02 01:42:45 PM PDT 24
Finished May 02 01:43:17 PM PDT 24
Peak memory 204304 kb
Host smart-f7d71ad8-248b-445e-999b-86c1f11fa455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738846702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.738846702
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1834304490
Short name T1277
Test name
Test status
Simulation time 1544484118 ps
CPU time 33.06 seconds
Started May 02 01:42:38 PM PDT 24
Finished May 02 01:43:12 PM PDT 24
Peak memory 345664 kb
Host smart-9664e347-bff4-4671-a58e-dfe17e7e63b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834304490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1834304490
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1915367303
Short name T201
Test name
Test status
Simulation time 34016219441 ps
CPU time 202.11 seconds
Started May 02 01:42:43 PM PDT 24
Finished May 02 01:46:06 PM PDT 24
Peak memory 814968 kb
Host smart-f4f44006-89ee-4d34-b4cb-c66d2dc5043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915367303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1915367303
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1140202444
Short name T368
Test name
Test status
Simulation time 2717623659 ps
CPU time 13.22 seconds
Started May 02 01:42:45 PM PDT 24
Finished May 02 01:43:00 PM PDT 24
Peak memory 215844 kb
Host smart-6cea0ad6-c835-4b43-b7d4-5b46e3e140f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140202444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1140202444
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3714293645
Short name T1173
Test name
Test status
Simulation time 951743737 ps
CPU time 4.23 seconds
Started May 02 01:42:45 PM PDT 24
Finished May 02 01:42:50 PM PDT 24
Peak memory 204156 kb
Host smart-7ae62a1d-921a-4ce7-88f1-9edf4fc47f76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714293645 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3714293645
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.622712623
Short name T436
Test name
Test status
Simulation time 10073614892 ps
CPU time 71.93 seconds
Started May 02 01:42:46 PM PDT 24
Finished May 02 01:43:59 PM PDT 24
Peak memory 473424 kb
Host smart-8660e95c-e049-41de-84f2-ac87bfb87c4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622712623 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.622712623
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1452929502
Short name T421
Test name
Test status
Simulation time 10123198289 ps
CPU time 27.1 seconds
Started May 02 01:42:47 PM PDT 24
Finished May 02 01:43:15 PM PDT 24
Peak memory 355768 kb
Host smart-d0b7386a-b90c-4dce-9357-5e231ccb7dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452929502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1452929502
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.533540181
Short name T638
Test name
Test status
Simulation time 235000900 ps
CPU time 1.76 seconds
Started May 02 01:42:45 PM PDT 24
Finished May 02 01:42:48 PM PDT 24
Peak memory 204120 kb
Host smart-fe6211ce-7667-41d1-84b6-9947f21f325d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533540181 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.533540181
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3511763262
Short name T366
Test name
Test status
Simulation time 746660983 ps
CPU time 3.93 seconds
Started May 02 01:42:45 PM PDT 24
Finished May 02 01:42:49 PM PDT 24
Peak memory 206356 kb
Host smart-45364793-f8ca-4532-965e-9da970d3c68b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511763262 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3511763262
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2298613855
Short name T396
Test name
Test status
Simulation time 2722921585 ps
CPU time 15.56 seconds
Started May 02 01:42:46 PM PDT 24
Finished May 02 01:43:02 PM PDT 24
Peak memory 649308 kb
Host smart-3c624514-dd32-4e97-ba5c-e169bf405ad2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298613855 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2298613855
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.4038821294
Short name T1312
Test name
Test status
Simulation time 1283992484 ps
CPU time 18.11 seconds
Started May 02 01:42:44 PM PDT 24
Finished May 02 01:43:03 PM PDT 24
Peak memory 204112 kb
Host smart-d6c135d5-6dd7-4a2e-be64-ace59aa6194e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038821294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.4038821294
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.176933246
Short name T1143
Test name
Test status
Simulation time 7298678194 ps
CPU time 19.22 seconds
Started May 02 01:42:43 PM PDT 24
Finished May 02 01:43:03 PM PDT 24
Peak memory 232484 kb
Host smart-f56ffdbb-7866-46d7-a6ad-d20b983a42cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176933246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.176933246
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1300498324
Short name T30
Test name
Test status
Simulation time 45942150094 ps
CPU time 427.28 seconds
Started May 02 01:42:47 PM PDT 24
Finished May 02 01:49:55 PM PDT 24
Peak memory 3876880 kb
Host smart-078885a7-d242-41f8-a826-8190094913be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300498324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1300498324
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.488394473
Short name T1191
Test name
Test status
Simulation time 16493491960 ps
CPU time 1766.99 seconds
Started May 02 01:42:46 PM PDT 24
Finished May 02 02:12:14 PM PDT 24
Peak memory 3300480 kb
Host smart-8ee8cc95-c36c-4ac4-b5a6-8432c5689a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488394473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_ta
rget_stretch.488394473
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1586838532
Short name T738
Test name
Test status
Simulation time 2602150959 ps
CPU time 5.92 seconds
Started May 02 01:42:43 PM PDT 24
Finished May 02 01:42:50 PM PDT 24
Peak memory 217268 kb
Host smart-868e0204-9be5-41fb-a6c0-9eef05fc06fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586838532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1586838532
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3970054629
Short name T536
Test name
Test status
Simulation time 18042358 ps
CPU time 0.6 seconds
Started May 02 01:42:59 PM PDT 24
Finished May 02 01:43:00 PM PDT 24
Peak memory 203904 kb
Host smart-17ba74ff-3f19-4ca2-bce7-a7971bfbf32d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970054629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3970054629
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.88984245
Short name T616
Test name
Test status
Simulation time 259032153 ps
CPU time 1.19 seconds
Started May 02 01:42:52 PM PDT 24
Finished May 02 01:42:54 PM PDT 24
Peak memory 212388 kb
Host smart-c56cfe1f-d891-49fb-a34c-4fef4ced83ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88984245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.88984245
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.4221973114
Short name T105
Test name
Test status
Simulation time 331975433 ps
CPU time 6.04 seconds
Started May 02 01:42:55 PM PDT 24
Finished May 02 01:43:02 PM PDT 24
Peak memory 274948 kb
Host smart-7c93eb88-1d57-47dd-ab52-1edbee627c1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221973114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.4221973114
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2768681951
Short name T46
Test name
Test status
Simulation time 2019835245 ps
CPU time 66.12 seconds
Started May 02 01:42:56 PM PDT 24
Finished May 02 01:44:03 PM PDT 24
Peak memory 684540 kb
Host smart-d7479014-19f5-4965-b4bb-661e10b267d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768681951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2768681951
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3249256155
Short name T582
Test name
Test status
Simulation time 8829607651 ps
CPU time 82.11 seconds
Started May 02 01:42:53 PM PDT 24
Finished May 02 01:44:16 PM PDT 24
Peak memory 755280 kb
Host smart-56ff8ae2-afa5-4d1f-947b-070cbf594512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249256155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3249256155
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2242287158
Short name T266
Test name
Test status
Simulation time 402528204 ps
CPU time 0.79 seconds
Started May 02 01:42:51 PM PDT 24
Finished May 02 01:42:53 PM PDT 24
Peak memory 203972 kb
Host smart-17e4955b-0908-4852-a7c5-bfcb7a4bc4c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242287158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2242287158
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1406989169
Short name T523
Test name
Test status
Simulation time 482878936 ps
CPU time 2.68 seconds
Started May 02 01:42:52 PM PDT 24
Finished May 02 01:42:56 PM PDT 24
Peak memory 204136 kb
Host smart-3cb2a2da-8330-4c5f-9c6b-246de5b4fbf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406989169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1406989169
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1357486333
Short name T111
Test name
Test status
Simulation time 14150781007 ps
CPU time 99.63 seconds
Started May 02 01:42:55 PM PDT 24
Finished May 02 01:44:35 PM PDT 24
Peak memory 1050788 kb
Host smart-765d9da3-6ea3-494e-bfdc-829a77f8c0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357486333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1357486333
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1098394089
Short name T929
Test name
Test status
Simulation time 1407955222 ps
CPU time 4.27 seconds
Started May 02 01:43:03 PM PDT 24
Finished May 02 01:43:08 PM PDT 24
Peak memory 204132 kb
Host smart-ad69c115-a304-4af3-aa5b-41be3b375a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098394089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1098394089
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3861824952
Short name T731
Test name
Test status
Simulation time 4276588433 ps
CPU time 111.24 seconds
Started May 02 01:43:05 PM PDT 24
Finished May 02 01:44:57 PM PDT 24
Peak memory 415976 kb
Host smart-1e97e6e7-afd1-4f1e-a4ac-1e2292181150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861824952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3861824952
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.463001380
Short name T453
Test name
Test status
Simulation time 30643598 ps
CPU time 0.67 seconds
Started May 02 01:42:53 PM PDT 24
Finished May 02 01:42:55 PM PDT 24
Peak memory 203852 kb
Host smart-36d9f165-4109-4961-83e9-c4b447302e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463001380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.463001380
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2620014328
Short name T792
Test name
Test status
Simulation time 2864537368 ps
CPU time 10.25 seconds
Started May 02 01:42:54 PM PDT 24
Finished May 02 01:43:05 PM PDT 24
Peak memory 204204 kb
Host smart-651d5a30-844f-42ce-b493-0cf3119a3589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620014328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2620014328
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.3079505228
Short name T930
Test name
Test status
Simulation time 1728671890 ps
CPU time 39.74 seconds
Started May 02 01:42:44 PM PDT 24
Finished May 02 01:43:24 PM PDT 24
Peak memory 265852 kb
Host smart-ce5611bb-8e26-42f0-a85b-c01c4d5e1d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079505228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3079505228
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2747389153
Short name T1128
Test name
Test status
Simulation time 40659286309 ps
CPU time 908.85 seconds
Started May 02 01:42:55 PM PDT 24
Finished May 02 01:58:05 PM PDT 24
Peak memory 2041536 kb
Host smart-e150f432-239f-49cc-be57-8f0d3e781847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747389153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2747389153
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.105159764
Short name T493
Test name
Test status
Simulation time 604347667 ps
CPU time 10.91 seconds
Started May 02 01:42:54 PM PDT 24
Finished May 02 01:43:06 PM PDT 24
Peak memory 220456 kb
Host smart-d5889500-cb85-4073-bf08-b6e7ad50082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105159764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.105159764
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1777196472
Short name T428
Test name
Test status
Simulation time 2870736780 ps
CPU time 3.2 seconds
Started May 02 01:42:52 PM PDT 24
Finished May 02 01:42:57 PM PDT 24
Peak memory 204244 kb
Host smart-d41cc34d-12ec-41c0-a4d5-b10a7ac73ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777196472 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1777196472
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2470400519
Short name T89
Test name
Test status
Simulation time 10137512469 ps
CPU time 15.92 seconds
Started May 02 01:42:54 PM PDT 24
Finished May 02 01:43:11 PM PDT 24
Peak memory 290416 kb
Host smart-00a3f3d3-ea63-451f-adaa-0924de505124
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470400519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2470400519
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.1473369243
Short name T328
Test name
Test status
Simulation time 10066647715 ps
CPU time 37.36 seconds
Started May 02 01:42:54 PM PDT 24
Finished May 02 01:43:32 PM PDT 24
Peak memory 423404 kb
Host smart-67698d12-1554-4a28-916c-9fe886854fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473369243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.1473369243
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1386128154
Short name T1238
Test name
Test status
Simulation time 541528144 ps
CPU time 2.7 seconds
Started May 02 01:42:51 PM PDT 24
Finished May 02 01:42:55 PM PDT 24
Peak memory 204084 kb
Host smart-55ada7c4-ce3c-4191-a072-436247bc2a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386128154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1386128154
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2480866331
Short name T373
Test name
Test status
Simulation time 2923926304 ps
CPU time 4.07 seconds
Started May 02 01:42:54 PM PDT 24
Finished May 02 01:43:00 PM PDT 24
Peak memory 204260 kb
Host smart-8085ea35-8be0-4159-b0dd-d987f782bbb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480866331 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2480866331
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1883595501
Short name T277
Test name
Test status
Simulation time 17942855103 ps
CPU time 429.52 seconds
Started May 02 01:42:56 PM PDT 24
Finished May 02 01:50:06 PM PDT 24
Peak memory 4250424 kb
Host smart-cd4a992b-950c-44d8-98ad-b48125ffe0b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883595501 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1883595501
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1620723131
Short name T108
Test name
Test status
Simulation time 897815979 ps
CPU time 12.65 seconds
Started May 02 01:42:52 PM PDT 24
Finished May 02 01:43:06 PM PDT 24
Peak memory 204180 kb
Host smart-e8d9a683-ea49-42e5-8873-ffa64e5d77dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620723131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1620723131
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.419188163
Short name T2
Test name
Test status
Simulation time 475169520 ps
CPU time 9.52 seconds
Started May 02 01:42:55 PM PDT 24
Finished May 02 01:43:06 PM PDT 24
Peak memory 204140 kb
Host smart-49168ad1-c87b-4bb3-a615-30957705f37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419188163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.419188163
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3020491105
Short name T1047
Test name
Test status
Simulation time 27723952161 ps
CPU time 21.84 seconds
Started May 02 01:42:55 PM PDT 24
Finished May 02 01:43:18 PM PDT 24
Peak memory 533584 kb
Host smart-30059c66-8833-43f9-8601-8cc5c0978094
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020491105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3020491105
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.635200820
Short name T610
Test name
Test status
Simulation time 5536940636 ps
CPU time 7.33 seconds
Started May 02 01:42:53 PM PDT 24
Finished May 02 01:43:02 PM PDT 24
Peak memory 353824 kb
Host smart-64acd17a-f9f3-497d-bc6a-65d970c72baa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635200820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_ta
rget_stretch.635200820
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2211317843
Short name T1315
Test name
Test status
Simulation time 2814322324 ps
CPU time 6.61 seconds
Started May 02 01:42:52 PM PDT 24
Finished May 02 01:42:59 PM PDT 24
Peak memory 218664 kb
Host smart-18beff10-e5f4-4915-9472-c5e0614aa0ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211317843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2211317843
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.882053193
Short name T774
Test name
Test status
Simulation time 21518662 ps
CPU time 0.59 seconds
Started May 02 01:43:09 PM PDT 24
Finished May 02 01:43:11 PM PDT 24
Peak memory 203792 kb
Host smart-4666f95a-eb9f-405b-8ebf-4d605512d798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882053193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.882053193
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1453670568
Short name T789
Test name
Test status
Simulation time 191549781 ps
CPU time 1.6 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:43:13 PM PDT 24
Peak memory 212388 kb
Host smart-a80c2763-e8fc-4db7-83cb-f4256d63f5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453670568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1453670568
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.259281979
Short name T456
Test name
Test status
Simulation time 995561088 ps
CPU time 5.33 seconds
Started May 02 01:43:00 PM PDT 24
Finished May 02 01:43:07 PM PDT 24
Peak memory 248096 kb
Host smart-d8928a66-364d-47f8-be7a-1a0fb6f01bbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259281979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.259281979
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3013026789
Short name T91
Test name
Test status
Simulation time 16165253422 ps
CPU time 41.35 seconds
Started May 02 01:43:00 PM PDT 24
Finished May 02 01:43:42 PM PDT 24
Peak memory 525672 kb
Host smart-ca48c425-2886-46c5-8702-cef0ce6c449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013026789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3013026789
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1120970805
Short name T110
Test name
Test status
Simulation time 14347341929 ps
CPU time 58.55 seconds
Started May 02 01:42:59 PM PDT 24
Finished May 02 01:43:59 PM PDT 24
Peak memory 703648 kb
Host smart-9115e1c2-42bb-41a6-9329-bf4ee4c8b9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120970805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1120970805
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.358927921
Short name T1203
Test name
Test status
Simulation time 141138584 ps
CPU time 1.09 seconds
Started May 02 01:43:00 PM PDT 24
Finished May 02 01:43:03 PM PDT 24
Peak memory 204132 kb
Host smart-5ceea5af-a6dc-4457-9cac-200a0820c462
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358927921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.358927921
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2966212845
Short name T728
Test name
Test status
Simulation time 122727439 ps
CPU time 3.04 seconds
Started May 02 01:43:06 PM PDT 24
Finished May 02 01:43:10 PM PDT 24
Peak memory 204108 kb
Host smart-705f3f3e-a0a1-4bc7-8643-80bb567208cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966212845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2966212845
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3270857477
Short name T726
Test name
Test status
Simulation time 7717363096 ps
CPU time 291.71 seconds
Started May 02 01:43:05 PM PDT 24
Finished May 02 01:47:57 PM PDT 24
Peak memory 1143708 kb
Host smart-bb36c312-e638-4ee1-8831-895073e5e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270857477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3270857477
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1065982837
Short name T782
Test name
Test status
Simulation time 1396414879 ps
CPU time 4.53 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:43:16 PM PDT 24
Peak memory 204108 kb
Host smart-f7e05941-74ef-4d4f-ac15-8504968225d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065982837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1065982837
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2768854960
Short name T696
Test name
Test status
Simulation time 3656249311 ps
CPU time 29.41 seconds
Started May 02 01:43:08 PM PDT 24
Finished May 02 01:43:38 PM PDT 24
Peak memory 371672 kb
Host smart-345195a0-6a37-463f-b627-8139f586f0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768854960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2768854960
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3795475416
Short name T775
Test name
Test status
Simulation time 46516213 ps
CPU time 0.65 seconds
Started May 02 01:42:59 PM PDT 24
Finished May 02 01:43:01 PM PDT 24
Peak memory 203748 kb
Host smart-1d498479-fa23-4e68-b24c-4990095f3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795475416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3795475416
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.549987674
Short name T280
Test name
Test status
Simulation time 6257860080 ps
CPU time 31.07 seconds
Started May 02 01:42:59 PM PDT 24
Finished May 02 01:43:31 PM PDT 24
Peak memory 213512 kb
Host smart-99109ccc-3a5c-42dc-8d01-bd1617a5baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549987674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.549987674
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.439457748
Short name T3
Test name
Test status
Simulation time 1371006955 ps
CPU time 22.82 seconds
Started May 02 01:42:59 PM PDT 24
Finished May 02 01:43:23 PM PDT 24
Peak memory 363636 kb
Host smart-5b459e7f-d451-4d2a-9e84-02e3e3683197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439457748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.439457748
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1724889782
Short name T181
Test name
Test status
Simulation time 10468100688 ps
CPU time 455.98 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:50:48 PM PDT 24
Peak memory 1376240 kb
Host smart-207a14a0-85ce-4b51-b180-f049053af75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724889782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1724889782
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.901744679
Short name T734
Test name
Test status
Simulation time 614411933 ps
CPU time 11.27 seconds
Started May 02 01:43:01 PM PDT 24
Finished May 02 01:43:13 PM PDT 24
Peak memory 215920 kb
Host smart-0638f383-f7d6-49e7-ac5b-3dbe36e5cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901744679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.901744679
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.3099657290
Short name T1209
Test name
Test status
Simulation time 732229237 ps
CPU time 3.51 seconds
Started May 02 01:43:17 PM PDT 24
Finished May 02 01:43:22 PM PDT 24
Peak memory 204152 kb
Host smart-17231195-2b14-4f10-af34-d3bcb4b2c0b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099657290 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.3099657290
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.721810160
Short name T1156
Test name
Test status
Simulation time 10025509127 ps
CPU time 76.44 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:44:27 PM PDT 24
Peak memory 500372 kb
Host smart-a987b13f-92b8-4e95-b57e-cb7b990cdeee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721810160 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.721810160
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.3781119048
Short name T1032
Test name
Test status
Simulation time 10114293038 ps
CPU time 32.03 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:43:43 PM PDT 24
Peak memory 405944 kb
Host smart-00d2f94e-1ac0-4b9c-beb2-1669d7fb30cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781119048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.3781119048
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.637748843
Short name T1121
Test name
Test status
Simulation time 2804133107 ps
CPU time 1.76 seconds
Started May 02 01:43:11 PM PDT 24
Finished May 02 01:43:15 PM PDT 24
Peak memory 204184 kb
Host smart-a3deb4a5-bc49-4b65-9029-47a8d9626bfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637748843 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_hrst.637748843
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2881944950
Short name T652
Test name
Test status
Simulation time 3396040538 ps
CPU time 4.89 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:43:16 PM PDT 24
Peak memory 218024 kb
Host smart-066e7ff6-74c9-479b-9949-c675620b40f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881944950 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2881944950
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3197491959
Short name T1086
Test name
Test status
Simulation time 21773340546 ps
CPU time 427.09 seconds
Started May 02 01:43:11 PM PDT 24
Finished May 02 01:50:20 PM PDT 24
Peak memory 5078328 kb
Host smart-bd18302c-9802-4d64-881a-6c3be54a1ba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197491959 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3197491959
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3323564526
Short name T325
Test name
Test status
Simulation time 1428169218 ps
CPU time 23.14 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:43:34 PM PDT 24
Peak memory 204188 kb
Host smart-f07c71a6-d610-4264-b7ac-98b4335852b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323564526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3323564526
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.3732171831
Short name T251
Test name
Test status
Simulation time 1253811286 ps
CPU time 21.57 seconds
Started May 02 01:43:11 PM PDT 24
Finished May 02 01:43:34 PM PDT 24
Peak memory 220576 kb
Host smart-977d3eb6-ed3c-4b6d-84b1-474360e97049
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732171831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.3732171831
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.296721653
Short name T1202
Test name
Test status
Simulation time 41678374954 ps
CPU time 80.72 seconds
Started May 02 01:43:09 PM PDT 24
Finished May 02 01:44:31 PM PDT 24
Peak memory 1375608 kb
Host smart-f4229f9a-e83d-4cfc-935f-552e4c75220f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296721653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.296721653
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2630445841
Short name T1271
Test name
Test status
Simulation time 19447353429 ps
CPU time 284.44 seconds
Started May 02 01:43:10 PM PDT 24
Finished May 02 01:47:56 PM PDT 24
Peak memory 2326864 kb
Host smart-1f509e77-2cf0-4530-bc2c-0ce2cf793743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630445841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2630445841
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1990348732
Short name T1059
Test name
Test status
Simulation time 5727470126 ps
CPU time 6.31 seconds
Started May 02 01:43:09 PM PDT 24
Finished May 02 01:43:16 PM PDT 24
Peak memory 218476 kb
Host smart-4675687c-6eb8-4efd-943d-7df9ca9a84af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990348732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1990348732
Directory /workspace/9.i2c_target_timeout/latest
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