Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	780167	1			T1	3		T2	3		T3	40
all_values[1]	780167	1			T1	3		T2	3		T3	40
all_values[2]	780167	1			T1	3		T2	3		T3	40
all_values[3]	780167	1			T1	3		T2	3		T3	40
all_values[4]	780167	1			T1	3		T2	3		T3	40
all_values[5]	780167	1			T1	3		T2	3		T3	40
all_values[6]	780167	1			T1	3		T2	3		T3	40
all_values[7]	780167	1			T1	3		T2	3		T3	40
all_values[8]	780167	1			T1	3		T2	3		T3	40
all_values[9]	780167	1			T1	3		T2	3		T3	40
all_values[10]	780167	1			T1	3		T2	3		T3	40
all_values[11]	780167	1			T1	3		T2	3		T3	40
all_values[12]	780167	1			T1	3		T2	3		T3	40
all_values[13]	780167	1			T1	3		T2	3		T3	40
all_values[14]	780167	1			T1	3		T2	3		T3	40

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8381342

1

T1

38

T2

40

T3

524

auto[1]

3321163

1

T1

7

T2

5

T3

76

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9401012

1

T1

45

T2

45

T3

600

auto[1]

2301493

1

T49

144367

T46

50365

T35

101385

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	66320	1			T3	2		T4	3		T6	1
all_values[0]	auto[0]	auto[1]	15276	1			T49	789		T46	242		T35	812
all_values[0]	auto[1]	auto[0]	558806	1			T1	3		T2	3		T3	38
all_values[0]	auto[1]	auto[1]	139765	1			T49	8834		T46	3117		T35	5946
all_values[1]	auto[0]	auto[0]	626659	1			T1	3		T2	3		T3	40
all_values[1]	auto[0]	auto[1]	152754	1			T49	9620		T46	3356		T35	6752
all_values[1]	auto[1]	auto[0]	483	1			T187	3		T35	60		T104	42
all_values[1]	auto[1]	auto[1]	271	1			T49	6		T46	4		T35	5
all_values[2]	auto[0]	auto[0]	616228	1			T1	3		T2	3		T3	40
all_values[2]	auto[0]	auto[1]	163741	1			T49	9621		T46	3351		T35	6755
all_values[2]	auto[1]	auto[0]	2	1			T207	2		-	-		-	-
all_values[2]	auto[1]	auto[1]	196	1			T49	4		T46	9		T35	5
all_values[3]	auto[0]	auto[0]	618013	1			T1	3		T2	3		T3	40
all_values[3]	auto[0]	auto[1]	161950	1			T49	9619		T46	3353		T35	6753
all_values[3]	auto[1]	auto[1]	204	1			T49	6		T46	7		T35	5
all_values[4]	auto[0]	auto[0]	616959	1			T1	3		T2	3		T3	40
all_values[4]	auto[0]	auto[1]	162991	1			T49	9623		T46	3355		T35	6756
all_values[4]	auto[1]	auto[0]	13	1			T68	2		T214	1		T215	2
all_values[4]	auto[1]	auto[1]	204	1			T49	3		T46	5		T35	4
all_values[5]	auto[0]	auto[0]	618015	1			T1	3		T2	3		T3	40
all_values[5]	auto[0]	auto[1]	161926	1			T49	9618		T46	3356		T35	6754
all_values[5]	auto[1]	auto[1]	226	1			T49	6		T46	4		T35	5
all_values[6]	auto[0]	auto[0]	165364	1			T1	3		T2	3		T3	40
all_values[6]	auto[0]	auto[1]	22072	1			T49	49		T46	499		T35	1688
all_values[6]	auto[1]	auto[0]	480117	1			T4	12		T8	7		T10	7
all_values[6]	auto[1]	auto[1]	112614	1			T49	9577		T46	2860		T35	5071
all_values[7]	auto[0]	auto[0]	619803	1			T1	3		T2	3		T3	40
all_values[7]	auto[0]	auto[1]	133255	1			T49	9215		T46	3158		T35	6479
all_values[7]	auto[1]	auto[0]	22363	1			T4	41		T8	35		T10	30
all_values[7]	auto[1]	auto[1]	4746	1			T49	410		T46	194		T35	278
all_values[8]	auto[0]	auto[0]	138926	1			T1	3		T2	3		T3	40
all_values[8]	auto[0]	auto[1]	19782	1			T49	56		T46	44		T35	1676
all_values[8]	auto[1]	auto[0]	477330	1			T4	22		T6	1		T8	14
all_values[8]	auto[1]	auto[1]	144129	1			T49	9569		T46	3315		T35	5084
all_values[9]	auto[0]	auto[0]	153575	1			T1	2		T2	2		T3	40
all_values[9]	auto[0]	auto[1]	24556	1			T49	163		T46	157		T35	1749
all_values[9]	auto[1]	auto[0]	462034	1			T1	1		T2	1		T4	17
all_values[9]	auto[1]	auto[1]	140002	1			T49	9463		T46	3203		T35	5011
all_values[10]	auto[0]	auto[0]	626414	1			T1	3		T2	3		T3	40
all_values[10]	auto[0]	auto[1]	153571	1			T49	9623		T46	3347		T35	6754
all_values[10]	auto[1]	auto[1]	182	1			T49	3		T46	5		T35	3
all_values[11]	auto[0]	auto[0]	2872	1			T2	2		T3	2		T4	3
all_values[11]	auto[0]	auto[1]	418	1			T49	26		T46	29		T35	19
all_values[11]	auto[1]	auto[0]	661857	1			T1	3		T2	1		T3	38
all_values[11]	auto[1]	auto[1]	115020	1			T49	9600		T46	3323		T35	6741
all_values[12]	auto[0]	auto[0]	624718	1			T1	3		T2	3		T3	40
all_values[12]	auto[0]	auto[1]	155251	1			T49	9621		T46	3353		T35	6758
all_values[12]	auto[1]	auto[1]	198	1			T49	3		T46	7		T35	2
all_values[13]	auto[0]	auto[0]	627154	1			T1	3		T2	3		T3	40
all_values[13]	auto[0]	auto[1]	152808	1			T49	9616		T46	3355		T35	6759
all_values[13]	auto[1]	auto[0]	2	1			T216	1		T217	1		-	-
all_values[13]	auto[1]	auto[1]	203	1			T49	2		T46	4		T35	1
all_values[14]	auto[0]	auto[0]	616985	1			T1	3		T2	3		T3	40
all_values[14]	auto[0]	auto[1]	162986	1			T49	9619		T46	3348		T35	6758
all_values[14]	auto[1]	auto[1]	196	1			T49	3		T46	5		T35	2